Bus fault cause determination method and electronic device

Abstract

The application discloses a bus fault reason determination method and electronic equipment, and relates to the technical field of computers, and comprises the following steps: if a target bus in a controller fails, determining a source pin corresponding to the target bus; determining a target pin corresponding to the source pin from a reserved pin; configuring the target pin based on configuration information of the target bus; configuring an interrupt mode of the source pin as an edge-triggered interrupt mode; when the source pin triggers an interrupt, reading a level signal of the source pin, setting an output level signal of the target pin to be consistent with the level signal of the corresponding source pin; and determining a fault reason of the target bus by collecting the output level signal of the target pin through a reserved terminal corresponding to the target pin by using a logic analyzer. The level signal of the source pin is copied to the target pin, and the logic analyzer is connected to the reserved terminal corresponding to the target pin, so that the technical effect of improving the fault reason determination efficiency is achieved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method for determining the cause of bus failures and electronic devices. Background Technology

[0002] In embedded system development and debugging, capturing and analyzing bus data in the embedded system using a logic analyzer is a crucial technique. Related technologies involve directly connecting the signal lines corresponding to the faulty bus to the logic analyzer's channels, setting the trigger conditions and sampling rate for the logic analyzer to capture faulty bus data, and configuring a faulty bus data analyzer within the logic analyzer to acquire and analyze the faulty bus data, thereby determining the cause of the faulty bus.

[0003] However, this method requires disassembling the embedded system and relies on soldering hardware circuits to connect the signal lines corresponding to the fault bus to a logic analyzer to determine the cause of the fault, which is inefficient. Summary of the Invention

[0004] This application provides a method and electronic device for determining the cause of bus failures, so as to at least solve the problem of low efficiency in determining the cause of failures in related technologies.

[0005] This application provides a method for determining the cause of a bus fault, including:

[0006] In the event of a target bus failure in the controller, determine the source pin corresponding to the target bus;

[0007] The target pin corresponding to the source pin is determined from the reserved pins of the controller, wherein each reserved pin corresponds to a reserved terminal;

[0008] Obtain the configuration information of the target bus;

[0009] Based on the configuration information of the target bus, configure the target pins accordingly;

[0010] Configure the interrupt mode of the source pin to edge-triggered interrupt mode;

[0011] Based on the interrupt handling model, when the source pin triggers an interrupt, the level signal of the source pin is read, and the output level signal of the target pin is set to be consistent with the level signal of the corresponding source pin.

[0012] The output level signal of the target pin is collected using a logic analyzer to determine the cause of the target bus fault. The logic analyzer is then connected to the reserved terminal corresponding to the target pin.

[0013] This application also provides a bus fault cause determination device, including:

[0014] The first determining module is used to determine the source pin corresponding to the target bus in the event of a target bus failure in the controller.

[0015] The second determining module is used to determine the target pin corresponding to the source pin from the reserved pins of the controller, wherein each reserved pin corresponds to a reserved terminal;

[0016] The acquisition module is used to acquire configuration information of the target bus;

[0017] The first configuration module is used to configure the target pins accordingly based on the configuration information of the target bus.

[0018] The second configuration module is used to configure the interrupt mode of the source pin as edge-triggered interrupt mode;

[0019] The read module is used based on the interrupt handling model. When the source pin triggers an interrupt, it reads the level signal of the source pin and sets the output level signal of the target pin to be consistent with the level signal of the corresponding source pin.

[0020] The third determination module is used to collect the output level signal of the target pin using a logic analyzer to determine the cause of the target bus fault. The logic analyzer is connected to the reserved terminal corresponding to the target pin.

[0021] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the bus fault cause determination methods described above when executing the computer program.

[0022] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described methods for determining the cause of a bus fault.

[0023] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described methods for determining the cause of a bus fault.

[0024] This application addresses the following issues in the case of a target bus failure in a controller: determining the source pin corresponding to the target bus; identifying the target pin corresponding to the source pin from the controller's reserved pins, where each reserved pin corresponds to a reserved terminal; acquiring the target bus's configuration information; configuring the target pin accordingly based on the target bus's configuration information; configuring the source pin's interrupt mode to edge-triggered interrupt mode; based on the interrupt handling model, when the source pin triggers an interrupt, reading the source pin's level signal and setting the target pin's output level signal to match the corresponding source pin's level signal; and using a logic analyzer to collect the target pin's output level signal to determine the cause of the target bus failure. The logic analyzer is connected to the reserved terminal corresponding to the target pin. By copying the source pin's level signal to the target pin, the logic analyzer can collect the target pin's output level signal through the reserved terminal corresponding to the target pin. Based on the target pin's output level signal, the cause of the target bus failure can be determined without disassembling the controller or soldering hardware circuitry. Therefore, this solves the technical problem of low efficiency in fault cause determination methods in related technologies, achieving a significant improvement in the efficiency of fault cause determination. Attached Figure Description

[0025] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This application provides a schematic diagram of the structure of a bus fault cause determination system.

[0027] Figure 2 A flowchart illustrating a method for determining the cause of a bus fault provided in an embodiment of this application;

[0028] Figure 3 A flowchart illustrating yet another method for determining the cause of a bus fault provided in an embodiment of this application;

[0029] Figure 4 This is a schematic diagram illustrating the process of copying the level signal of a clock signal pin according to an embodiment of this application.

[0030] Figure 5 A schematic diagram illustrating the determination of timing deviations provided in an embodiment of this application;

[0031] Figure 6 This is a schematic diagram of a bus fault cause determination device provided in an embodiment of this application;

[0032] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0034] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0035] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] In the development, debugging, and maintenance of embedded systems, accurately capturing bus data is crucial for a deep understanding of system operation mechanisms, troubleshooting, and performance optimization. Logic analyzers, with their powerful digital signal acquisition and analysis capabilities, have become the mainstream tool for capturing and analyzing bus data.

[0037] In related technologies, by directly connecting the signal line corresponding to the fault bus to the channel of the logic analyzer, setting the trigger conditions and sampling rate for the logic analyzer to capture fault bus data, and configuring a fault bus data analyzer in the logic analyzer, the acquisition and analysis of fault bus data can be realized to determine the cause of the fault bus failure.

[0038] For example, when the fault bus is an internal integrated circuit (I2C) bus, since the I2C bus consists of a serial clock line (SCL) and a serial data line (SDA), it is necessary to connect SCL and SDA to different independent channels of the logic analyzer, set the sampling rate of the logic analyzer to be at least 10 times the clock frequency of the I2C bus, configure the I2C protocol analyzer in the software of the logic analyzer, set the trigger according to specific conditions to capture I2C bus data, and then decode the data by the software to present detailed communication information and determine the cause of the I2C bus fault.

[0039] When the fault bus is an Improved Inter-Integrated Circuit (I3C) bus, in addition to connecting SCL and SDA to different independent channels of the logic analyzer, it may be necessary to connect the auxiliary control line to an independent channel of the logic analyzer. According to the I3C bus mode, the sampling rate of the logic analyzer is set, and the I3C protocol analyzer is configured in the software of the logic analyzer. The trigger is set based on the I3C protocol data packet content to capture I3C bus data. Then, the software decodes and presents detailed communication information according to the I3C frame format to determine the cause of the I3C bus fault.

[0040] When the fault bus is a Joint Test Action Group (JTAG) bus, because the JTAG bus consists of TestModeSelect (TMS) signal lines, TestClock (TCK) signal lines, TestDataInput (TDI) signal lines, and TestDataOutput (TDO) signal lines, it is necessary to connect the TMS, TCK, TDI, and TDO signal lines to different independent channels of the logic analyzer to ensure level matching. The sampling rate of the logic analyzer should be set to be more than 10 times the clock frequency of the JTAG bus. The JTAG protocol analyzer should be configured in the software of the logic analyzer to trigger the capture of JTAG bus data with specific test commands or TDI data mode settings. Then, the software decodes and presents detailed communication information according to the JTAG protocol to determine the cause of the JTAG bus fault.

[0041] However, current methods for determining the cause of bus faults require power-off and disassembly of the embedded system, relying on hardware wiring to connect the signal lines corresponding to the faulty bus to a logic analyzer to determine the cause of the fault, which is inefficient. Furthermore, this method cannot determine the cause of the fault in scenarios with a low probability of fault recurrence.

[0042] To address the aforementioned technical problems, embodiments of this application provide a method for determining the cause of a bus fault and an electronic device. The method includes: determining the source pin corresponding to the target bus in the event of a target bus fault in the controller; determining the target pin corresponding to the source pin from the controller's reserved pins, wherein each reserved pin corresponds to a reserved terminal; acquiring the configuration information of the target bus; configuring the target pin accordingly based on the target bus configuration information; configuring the interrupt mode of the source pin to an edge-triggered interrupt mode; based on the interrupt handling model, when the source pin triggers an interrupt, reading the level signal of the source pin and setting the output level signal of the target pin to be consistent with the level signal of the corresponding source pin; and using a logic analyzer to collect the output level signal of the target pin to determine the cause of the target bus fault, wherein the logic analyzer is connected to the reserved terminal corresponding to the target pin. The method provided by the above solution copies the level signal of the source pin to the target pin, so that the logic analyzer can collect the output level signal of the target pin through the reserved terminal corresponding to the target pin. Based on the output level signal of the target pin, the cause of the target bus fault is determined. The fault cause can be determined without disassembling the controller or soldering hardware circuits. Therefore, it can solve the technical problems of low efficiency in determining the fault cause in related technologies and the inability to determine the fault cause in scenarios with low fault recurrence probability. It achieves the technical effect of improving the efficiency of fault cause determination and accurately determining the fault cause in scenarios with low fault recurrence probability.

[0043] The specific application environment architecture or specific hardware architecture on which the bus fault cause determination method depends is described here.

[0044] The bus fault cause determination method and electronic device provided in this application are applicable to determining the cause of bus faults. Figure 1The diagram shows the structure of the bus fault cause determination system upon which this application is based. This system includes a controller and a logic analyzer. The controller is used to determine the source pin corresponding to the target bus in the event of a target bus fault; determine the target pin corresponding to the source pin from the controller's reserved pins, where each reserved pin corresponds to a reserved terminal; acquire the target bus's configuration information; configure the target pin accordingly based on the target bus's configuration information; configure the source pin's interrupt mode to an edge-triggered interrupt mode; and based on the interrupt handling model, when the source pin triggers an interrupt, read the source pin's level signal and set the target pin's output level signal to be consistent with the corresponding source pin's level signal. The logic analyzer is used to collect the target pin's output level signal to determine the cause of the target bus fault. The logic analyzer is connected to the reserved terminal corresponding to the target pin.

[0045] Embodiments of this application provide a method for determining the cause of a bus fault, applied to the aforementioned bus fault cause determination system. Figure 2 This is a flowchart illustrating the method for determining the cause of bus faults provided in an embodiment of this application, as shown below. Figure 2 As shown, the method for determining the cause of this bus fault includes the following steps:

[0046] Step S201: In the event of a target bus failure in the controller, determine the source pin corresponding to the target bus.

[0047] The controller is the Baseboard Management Controller (BMC). The BMC's functions are typically implemented using an AST chip. The BMC is an embedded system. The target bus can be I2C, I3C, JTAG, etc.

[0048] It should be noted that each signal line in the bus corresponds to a general purpose input / output (GPIO) pin. For example, the SCL pin of the I3C bus corresponds to the clock signal pin, and the SDA pin corresponds to the data signal pin.

[0049] The source pins corresponding to the target bus are the GPIO pins corresponding to the signal lines included in the target bus.

[0050] Step S202: Determine the target pin corresponding to the source pin from the reserved pins of the controller, wherein each reserved pin corresponds to a reserved terminal.

[0051] The controller's circuit board has multiple GPIO pins reserved as target pins corresponding to source pins, and provides non-intrusive signal access points for the logic analyzer through physical terminals connected to them.

[0052] Understandably, these reserved pins are reusable pins. In the event of different bus failures, they can be used as target pins corresponding to different source pins, which greatly improves the system's flexibility, maintainability, and economy. This avoids the waste of resources that would otherwise be required to reserve pins separately for each bus and improves the efficiency of fault cause determination.

[0053] Step S203: Obtain the configuration information of the target bus.

[0054] Step S204: Configure the target pins accordingly based on the configuration information of the target bus.

[0055] By configuring the target pins according to the configuration information based on the target bus, the timing reference and level standard of signal replication are ensured.

[0056] Step S205: Configure the interrupt mode of the source pin to edge-triggered interrupt mode.

[0057] Among them, the edge-triggered interrupt mode triggers the interrupt on the rising and falling edges of the level signal on the source pin.

[0058] By configuring the interrupt mode of the source pin as an edge-triggered interrupt module, level transitions can be captured in real time to trigger an interrupt, achieving signal-without-delay perception.

[0059] Step S206: Based on the interrupt handling model, when the source pin triggers an interrupt, the level signal of the source pin is read, and the output level signal of the target pin is set to be consistent with the level signal of the corresponding source pin.

[0060] The interrupt handling model is based on the Interrupt Service Routine (ISR).

[0061] When an interrupt is triggered by the source pin, the voltage level of the source pin is obtained by reading the register corresponding to the source pin. This register can be a GPIO input register, such as the GPIO_IN register. By writing to the GPIO output register of the target pin, the output voltage level of the target pin is set to match the voltage level of the corresponding source pin, ensuring synchronous replication of the voltage levels. This GPIO output register can be, for example, the GPIO_OUT register.

[0062] The level signal of the source pin can be either the input level signal of the source pin or the output level signal of the source pin.

[0063] Step S207: Use a logic analyzer to collect the output level signal of the target pin, determine the cause of the target bus fault, and connect the logic analyzer to the reserved terminal corresponding to the target pin.

[0064] The logic analyzer acquires the output level signal of the target pin through the reserved terminal corresponding to the target pin, and determines the cause of the target bus fault based on the output level signal of the target pin.

[0065] The sampling rate of the logic analyzer can be set to 10 times the clock frequency of the target bus (e.g., a logic analyzer with a clock frequency of 12.5MHz would have a sampling rate of 125MHz). This ensures that every level transition is captured completely.

[0066] Understandably, after determining the cause of the target bus failure, the configuration of the target pins is restored to its initial state.

[0067] The bus fault cause determination method provided in this application, through a pure software approach in the BMC system, copies the level signals of the GPIO pins corresponding to buses such as I2C / I3C / JTAG to reserved GPIO pins. The reserved terminals are then used to connect a logic analyzer to monitor bus data and determine the cause of bus faults. This method achieves accurate copying of level signals without increasing hardware costs or interfering with the original bus communication. It solves the problems of limited hardware modification and poor level signal synchronization during bus debugging in BMC scenarios in related technologies, significantly improving the flexibility and reliability of link monitoring.

[0068] Embodiments of this application provide a method for determining the cause of a bus fault, applied to the aforementioned bus fault cause determination system. Figure 3 This is a flowchart illustrating the method for determining the cause of bus faults provided in an embodiment of this application, as shown below. Figure 3 As shown, the method for determining the cause of this bus fault includes the following steps:

[0069] Step S301: In the event of a target bus failure in the controller, determine the source pin corresponding to the target bus. For details, please refer to [link to relevant documentation]. Figure 2 Step S201 of the illustrated embodiment will not be described again here.

[0070] Step S302: Determine the target pin corresponding to the source pin from the reserved pins of the controller, wherein each reserved pin corresponds to a reserved terminal.

[0071] Specifically, step S302 includes:

[0072] Step S3021: Based on the reserved pins of the controller, determine the free pins among the reserved pins.

[0073] Step S3022: Determine whether the idle pins include at least one adjacent pin combination, wherein the number of adjacent pins included in the adjacent pin combination is the same as the number of source pins.

[0074] Step S3023: If the idle pins include at least one adjacent pin combination, then determine one of the adjacent pin combinations as the target pin combination, and the target pins in the target pin combination correspond one-to-one with the source pins.

[0075] Specifically, a target pin combination is randomly selected from at least one adjacent pin combination included in the idle pins.

[0076] Step S303: Obtain the configuration information of the target bus. For details, please refer to [link to relevant documentation]. Figure 2 Step S203 of the illustrated embodiment will not be described again here.

[0077] Step S304: Configure the target pins accordingly based on the target bus configuration information. For details, please refer to [link to relevant documentation]. Figure 2 Step S204 of the illustrated embodiment will not be described again here.

[0078] Step S305: Configure the interrupt mode of the source pin to edge-triggered interrupt mode. For details, please refer to [link to relevant documentation]. Figure 2 Step S205 of the illustrated embodiment will not be described again here.

[0079] Step S306: Based on the interrupt handling model, when an interrupt is triggered by the source pin, the level signal of the source pin is read, and the output level signal of the target pin is set to be consistent with the level signal of the corresponding source pin. For details, please refer to [link to relevant documentation]. Figure 2 Step S206 of the illustrated embodiment will not be described again here.

[0080] Step S307: Use a logic analyzer to acquire the output level signal of the target pin to determine the cause of the target bus fault. Connect the logic analyzer to the reserved terminal corresponding to the target pin. For details, please refer to [link to details]. Figure 2 Step S207 of the illustrated embodiment will not be described again here.

[0081] The bus fault cause determination method provided in this application can intelligently complete the mapping from source pins to target pins by automatically determining the idle pins from the reserved pins of the controller and further determining whether there is a combination of adjacent pins that meets the quantity requirements, thereby reducing manual intervention and improving configuration efficiency.

[0082] By selecting "adjacent pin combinations" as target pins, it is helpful to maintain the timing consistency between signals. The logic analyzer probes can be connected to the adjacent terminals corresponding to this set of adjacent pin combinations, which greatly reduces the risk of wiring errors and operational complexity.

[0083] In some optional implementations, the above-mentioned bus fault cause determination method further includes:

[0084] Step a1: If the free pins do not include at least one adjacent pin combination, then determine the target pin corresponding to the source pin from the free pins based on the source pin.

[0085] Specifically, based on the source pin, the target pin corresponding to the source pin is randomly determined from the idle pins.

[0086] The bus fault cause determination method provided in this application provides a mitigation strategy when no adjacent pin combination is included in the idle pins, ensuring that the signal replication function can be enabled under any circumstances, and ensuring the robustness and availability of the signal replication function under limited resources.

[0087] In some optional implementations, the configuration information includes the current bus operating mode, the current bus communication rate, the electrical configuration of the source pin, the level range of the source pin, and the idle level signal of the source pin. Step S304 above includes:

[0088] Step b1: Configure the operating mode of the target pin based on the current bus operating mode.

[0089] The operating modes include high-speed mode and low-speed mode. It can be understood that the operating mode of the target pin is set to be the same as the current bus operating mode.

[0090] It should be noted that the configuration information of the target bus is obtained by reading the target bus controller register (such as the I3C control register).

[0091] Step b2: Configure the communication rate of the target pin based on the current bus communication rate.

[0092] The communication rate can be 100kHz, 1MHz, or 12.5MHz. It is understood that the communication rate of the target pin is set to be the same as the current bus communication rate.

[0093] Step b3: Configure the electrical configuration of the target pin to be the same as the electrical configuration of the corresponding source pin.

[0094] The electrical configuration includes open-drain output mode, push-pull output mode, and internal pull-up resistor enable state.

[0095] It should be noted that the output mode of the target pin can also be directly configured as a push-pull output mode to adapt to the input impedance (≥1MΩ) and signal range (0-3.3V / 0-5V) of the logic analyzer, ensuring that the replicated level signal can be stably acquired. The internal pull-up resistor of the target pin can also be enabled to avoid level drift caused by external circuit interference.

[0096] Step b4: Configure the level range of the target pin to be consistent with the level range of the corresponding source pin.

[0097] It should be noted that the target pin also needs to be configured with a drive capability of ≥2mA to meet the input requirements of the logic analyzer.

[0098] For example, if the source pin supports 3.3V, then configure the target pin to support 3.3V.

[0099] Step b5: Configure the initial output level signal of the target pin to be consistent with the idle level signal of the corresponding source pin.

[0100] For example, if the target bus is an I3C bus, since the source pins corresponding to SDA and SCL are both high when the I3C bus is idle, the initial output level signal of the target pin corresponding to the source pin is configured to be high. This avoids false triggering of the logic analyzer caused by inconsistent initial states.

[0101] The bus fault cause determination method provided in this application embodiment achieves electrical compatibility and timing consistency between the copied signal and the original bus signal by finely configuring the target pin parameters, fundamentally ensuring the reliability and measurement accuracy of the signal copying function.

[0102] In some optional implementations, the above-mentioned bus fault cause determination method further includes:

[0103] Step c1: If the source pin is the clock signal pin corresponding to the clock line, read the register data corresponding to the clock line.

[0104] Since the interrupt mode of the source pin is edge-triggered interrupt mode, the source pin will frequently trigger interrupts when it is the clock signal pin corresponding to the clock line. In order to ensure the synchronous replication of the level signal, the target pin corresponding to the clock signal pin can be configured to output a square wave based on the clock frequency of the clock signal on the clock line, which greatly reduces the overhead of the BMC's central processing unit.

[0105] Step c2: If the register data corresponding to the clock line includes the clock frequency of the clock signal, then obtain the clock frequency of the clock signal.

[0106] It is understandable that when the source pin is the clock signal pin corresponding to the clock line, if the register data corresponding to the clock line includes the clock frequency of the clock signal, then there is no need to set the interrupt mode of the clock signal pin to edge-triggered interrupt mode. You can directly configure the target pin corresponding to the clock signal pin to output a square wave based on the clock frequency of the clock model.

[0107] Step c3: If the register data corresponding to the clock line does not include the clock frequency of the clock signal, then obtain the number of interrupts triggered by the source pin per unit time; based on the number of interrupts triggered by the source pin per unit time, determine the clock frequency of the clock signal.

[0108] The unit of time can be 1ms. A timer is used to count the number of interrupts triggered by the source pin within a unit of time, and the clock frequency of the clock signal is calculated.

[0109] Specifically, the clock frequency of the clock signal = number of interrupts triggered by the source pin / 2 / unit time, because one clock cycle includes two interrupts, one rising edge and one falling edge.

[0110] For example, if the source pin triggers 2000 interrupts within 1ms, then the clock frequency of the clock signal = 2000 / 2 / 0.001s = 1MHz.

[0111] Understandably, once the clock frequency of the clock signal is determined, there is no need to set the interrupt mode of the clock signal pin to edge-triggered interrupt mode. Instead, the target pin corresponding to the clock signal pin can be directly configured to output a square wave based on the clock frequency of the clock signal.

[0112] Step c4: Control the target pin corresponding to the source pin to output a square wave based on the clock frequency of the clock signal.

[0113] Figure 4 This is a schematic diagram illustrating the process of copying the level signal of a clock signal pin according to an embodiment of this application, as shown below. Figure 4 As shown, there are three ways to copy the level signal of a clock signal pin. One method is to determine if the clock signal pin has triggered an interrupt. If it has, the level signal of the clock signal pin is read, and the output level signal of the target pin corresponding to the clock signal pin is set to match the level signal of the clock signal pin. Another method is to obtain the clock frequency if the register data corresponding to the clock line includes the clock frequency, and control the target pin corresponding to the clock signal pin to output a square wave based on the clock frequency. A third method is to obtain the number of interrupts triggered by the clock signal pin per unit time, determine the clock frequency based on the number of interrupts triggered per unit time, and control the target pin corresponding to the clock signal pin to output a square wave based on the clock frequency.

[0114] The bus fault cause determination method provided in this application ensures the reliability of clock frequency acquisition by offering two clock frequency acquisition paths: register reading and interrupt statistics. Compared to the method of copying the level signal at each interrupt, the method in this embodiment of directly outputting a square wave based on the clock frequency of the clock signal at the target pin greatly reduces the overhead of the central processing unit.

[0115] In some optional implementations, the above-mentioned bus fault cause determination method further includes:

[0116] Step d1: If the clock frequency of the clock signal is less than the first frequency threshold, the log printing function of the interrupt handling model is maintained. The log printing function is used to log the level signal of the source pin.

[0117] It should be noted that the central processing model has functions such as log printing, secondary verification of level signal delay, and level reading and copying.

[0118] The level read and copy function is used to read the level signal of the source pin when the source pin triggers an interrupt, and set the output level signal of the target pin to be consistent with the level signal of the corresponding source pin.

[0119] Under normal circumstances, functions such as log printing, level signal delay secondary verification, and level reading and copying are enabled.

[0120] The first frequency threshold can be 100kHz. This log printing function can output the level signal of the source pin via a Universal Asynchronous Receiver / Transmitter (UART) for easy monitoring by debugging personnel. While outputting the level signal of the source pin via the UART, the controller can also perform low-priority tasks (such as data backup), balancing functionality and performance.

[0121] It is understandable that a clock frequency less than the first frequency threshold indicates that the target bus is in a low-speed mode.

[0122] Step d2: If the clock frequency of the clock signal is not less than the first frequency threshold and is less than the second frequency threshold, then the log printing function is turned off.

[0123] The second frequency threshold can be 1MHz. It is understood that if the clock frequency of the clock signal is not less than the first frequency threshold but less than the second frequency threshold, the log printing function will be disabled, while the central processing model's level signal delay secondary verification function, level reading and copying function, etc., will remain enabled.

[0124] Step d3: If the clock frequency of the clock signal is not less than the second frequency threshold, then disable the log printing function and the level signal delay secondary verification function of the interrupt handling model.

[0125] It is understandable that if the clock frequency of the clock signal is not less than the second frequency threshold, it indicates that the target bus is in high-speed mode. The log printing function and the level signal delay secondary verification function of the interrupt handling model are disabled, while the level reading and copying functions are retained.

[0126] It should be noted that, if the clock frequency of the clock signal is not less than the second frequency threshold, it is also necessary to use a Nested Vectored Interrupt Controller (NVIC) to shield low-priority interrupts (such as timer interrupts) in the BMC, ensuring that edge-triggered interrupts of the source pin are executed first, and reducing the copying delay of the level signal.

[0127] The level signal delay secondary verification function is used to perform a delay secondary verification on the level signal of the source pin.

[0128] The bus fault cause determination method provided in this application significantly reduces interrupt latency and ensures the reliability of signal replication under stringent timing requirements by disabling log printing and debouncing verification functions in high-speed mode. In low-speed mode, complete log recording provides developers with abundant debugging data, and the retention of debouncing verification functions ensures the accuracy and stability of signals in low-speed environments.

[0129] In some optional implementations, the above bus fault cause determination method further includes, before setting the output level signal of the target pin to be consistent with the level signal of the corresponding source pin:

[0130] Step e1 involves performing a second-order delay verification on the level signal of the source pin.

[0131] Specifically, after the source pin triggers an interrupt, the first level signal of the source pin is read; after a preset delay, the second level signal of the source pin is read again; if the first level signal and the second level signal are consistent, it is determined that the level signal of the source pin has passed the delay-based double verification, and the output level signal of the target pin corresponding to the source pin is set to be consistent with the first level signal or the second level signal.

[0132] Step e2: If the level signal of the source pin passes the second delay verification, then the output level signal of the target pin is set to be consistent with the level signal of the corresponding source pin.

[0133] The bus fault cause determination method provided in this application embodiment effectively filters out transient electromagnetic interference through a delayed secondary verification mechanism, ensuring the accuracy and reliability of signal replication and improving the credibility of fault cause diagnosis results.

[0134] In some optional implementations, the above-mentioned bus fault cause determination method further includes:

[0135] Step f1: Configure the interrupt priority of the source pin to the highest level.

[0136] The bus fault cause determination method provided in this application configuration sets the interrupt priority of the source pin to the highest level (higher than UART, Serial Peripheral Interface (SPI) and other peripheral interrupts), ensuring that the interrupt response time is ≤50ns and avoiding delays in level signal replication.

[0137] In some optional implementations, the above-mentioned bus fault cause determination method further includes:

[0138] Step g1: During the testing phase of the interrupt handling model, the interrupt handling model is run to read the level signal of the test source pin when an interrupt is triggered by the test source pin corresponding to the test bus. The output level signal of the test target pin corresponding to the test source pin is set to be consistent with the level signal of the test source pin. Reserved pins include the test target pin. The level signals of the test source pin and the output level signals of the test target pin are collected using measuring instruments. The timing deviation between the level signal of the test source pin and the output level signal of the corresponding test target pin is determined. If the timing deviation is greater than a preset deviation threshold, the interrupt handling model is optimized.

[0139] The measuring instrument can be an oscilloscope or a logic analyzer.

[0140] Understandably, once the interrupt handling model passes the test, it can be used to execute the following steps: when an interrupt is triggered by a source pin, read the level signal of the source pin and set the output level signal of the target pin to be consistent with the level signal of the corresponding source pin; perform a second-order delay verification on the level signal of the source pin; and if the level signal of the source pin passes the second-order delay verification, set the output level signal of the target pin corresponding to the source pin to be consistent with the level signal of the source pin.

[0141] Understandably, during the testing phase of the interrupt handling model, a test bus fault is set, the test source pin corresponding to the test bus is determined, the test target pin corresponding to the test source pin is determined from the reserved pins of the controller, the test target pin is configured accordingly based on the configuration information of the test bus, and the interrupt mode of the test source pin is configured as edge-triggered interrupt mode.

[0142] Timing deviation is the time difference between a level transition at the test source pin and a level transition at the test target pin. The preset deviation threshold is set by a technician; for example, the preset deviation threshold could be 100ns (to meet the timing requirements of a 12.5MHz bus).

[0143] Understandably, if the timing deviation exceeds a preset deviation threshold, the interrupt handling model is optimized. After optimization, the interrupt handling model is returned to execution. This involves reading the level signal of the test source pin when an interrupt is triggered by the test source pin corresponding to the test bus, setting the output level signal of the test target pin corresponding to the test source pin to be consistent with the level signal of the test source pin (reserved pins include the test target pin); using measuring instruments to acquire the level signals of the test source pin and the output level signals of the test target pin; determining the timing deviation between the level signal of the test source pin and the corresponding output level signal of the test target pin; and if the timing deviation exceeds a preset deviation threshold, optimizing the interrupt handling model until the timing deviation is no greater than the preset deviation threshold.

[0144] It should be noted that optimizing the interrupt handling model can include optimizing the code length corresponding to the interrupt handling model to reduce the total execution time of the interrupt handling model, ensuring that the total execution time of the interrupt handling model is ≤50ns, that is, ensuring that the synchronization delay of the level signal is ≤50ns, thus laying the foundation for accurate replication.

[0145] Figure 5 This is a schematic diagram illustrating the determination of timing bias in an embodiment of this application, as shown below. Figure 5 As shown, by determining the time T0 when the level signal of the test source pin changes, and the time T1 when the level signal of the test target pin changes, the timing deviation t = T1 - T0 is determined based on the time when the level signal of the test source pin changes and the time when the level signal of the test target pin changes.

[0146] Step g2: During the testing phase of the interrupt handling model, electromagnetic interference is injected into the power supply of the controller. The interrupt handling model is then run to read the level signal of the test source pin under electromagnetic interference when an interrupt is triggered by the test source pin corresponding to the test bus. A second delay verification is performed on the level signal of the test source pin under electromagnetic interference. If the second delay verification of the level signal of the test source pin passes, the output level signal of the test target pin corresponding to the test source pin is set to be consistent with the level signal of the test source pin under electromagnetic interference. The level signal of the test source pin under electromagnetic interference and the output level signal of the test target pin are collected using measuring instruments. The consistency between the level signal of the test source pin under electromagnetic interference and the output level signal of the corresponding test target pin is determined. If the consistency is lower than a preset consistency threshold, the interrupt handling model is optimized.

[0147] Among them, electromagnetic interference can be ripple interference of 100mV / 1MHz to simulate the actual electromagnetic environment.

[0148] The preset consistency threshold can be 99.9%. That is, the false copy rate needs to be ≤0.1%.

[0149] Understandably, if the consistency is lower than the preset consistency threshold, the interrupt handling model is optimized. After optimization, the process returns to injecting electromagnetic interference into the controller's power supply and running the interrupt handling model. This allows for reading the level signal of the test source pin under electromagnetic interference when an interrupt is triggered by the test source pin corresponding to the test bus. A second delay verification is performed on the level signal of the test source pin under electromagnetic interference. If the second delay verification of the test source pin's level signal passes, the output level signal of the target pin corresponding to the test source pin is set to be consistent with the level signal of the test source pin under electromagnetic interference. Measuring instruments are used to collect the level signal of the test source pin under electromagnetic interference and the output level signal of the test target pin. The consistency between the level signal of the test source pin under electromagnetic interference and the corresponding output level signal of the test target pin is determined. If the consistency is lower than the preset consistency threshold, the interrupt handling model is optimized until the consistency is not lower than the preset consistency threshold.

[0150] It should be noted that during the testing phase of the interrupt handling model, the number of times the interference level signal of the test source pin was not filtered and the number of times the interference level signal of the test source pin was filtered are counted. Based on the number of times the interference level signal of the test source pin was not filtered and the number of times the interference level signal of the test source pin was filtered, the probability of the interference level signal being filtered is determined. If the probability of the interference level signal being filtered is not greater than a preset probability threshold, the interrupt handling model is optimized to ensure that transient jitter can be effectively filtered.

[0151] Furthermore, during the testing phase of the interrupt handling model, 1000 data frames were transmitted using the test bus at different communication rates. The interrupt handling model was run, and the output level signals of the target pins were collected using a logic analyzer to verify the timing integrity of the start signal, stop signal, and data bits, ensuring that no signals were missed or misaligned. If the verification failed, the interrupt handling model was optimized.

[0152] It should be noted that during the testing phase of the interrupt handling model, the CPU utilization rate during its operation is monitored in real time to ensure that the CPU utilization rate of tasks related to level signal replication is ≤5%, so as not to interfere with the core business of BMC (such as I3C bus data processing, sensor data acquisition, etc.). Specifically, the CPU utilization rate during the operation of the interrupt handling model can be monitored through the BMC's performance monitoring unit.

[0153] If the CPU utilization rate of tasks related to level signal replication is greater than 5%, the interrupt handling model should be optimized.

[0154] It should be noted that during the testing phase of the interrupt handling model, a monitoring status reporting function is added to the BMC's main program. This function is used to save the signal replication status during the testing phase to the log via UART, allowing debugging personnel to monitor the system's operation in real time and optimize parameters promptly. The signal replication status includes timing deviation, consistency, the probability of interference level signals being filtered, and CPU utilization.

[0155] The bus fault cause determination method provided in this application ensures the synchronization of signal replication by measuring and optimizing the replication delay using an oscilloscope during the testing phase of the interrupt handling model. By verifying the effectiveness of the delay secondary verification function and the probability of filtering interference level signals (i.e., fault tolerance counting) during the testing phase of the interrupt handling model, it ensures that the interrupt handling module can effectively filter transient electromagnetic interference ≤10ns, with a false replication rate ≤0.1%, ensuring the purity of the replicated signal and improving the reliability of the logic analyzer's analysis results.

[0156] By verifying the timing integrity of the replicated signals at different rates, the interrupt handling model logic is optimized to ensure the integrity and stability of signal replication at various rates. The CPU utilization rate for tasks related to control level signal replication is ≤5%, ensuring no interference with core BMC system tasks (such as data processing and peripheral control), and guaranteeing stable operation of the BMC system.

[0157] The bus fault cause determination method provided in this application provides a clear parameter configuration interface (such as interrupt priority and debouncing delay) and status reporting function, which allows debugging personnel to quickly complete deployment (within 30 minutes), monitor the replication status in real time, and facilitate subsequent maintenance and optimization.

[0158] In some optional implementations, step S302 above includes:

[0159] Step h1: Based on the reserved pins of the controller, determine the free pins among the reserved pins.

[0160] Step h2: Obtain the status of the idle pin.

[0161] Step h3: If all idle pins are in a normal state, determine whether the idle pins include at least one adjacent pin combination. The number of adjacent pins included in the adjacent pin combination is the same as the number of source pins. If the idle pins include at least one adjacent pin combination, determine one of the adjacent pin combinations as the target pin combination. The target pins in the target pin combination correspond one-to-one with the source pins.

[0162] Step h4: If at least one idle pin is in an abnormal state, an alarm message for the abnormal idle pin is reported; determine whether the normal idle pins include at least one adjacent pin combination, and the number of adjacent pins included in the adjacent pin combination is the same as the number of source pins; if the normal idle pins include at least one adjacent pin combination, determine one of the adjacent pin combinations as the target pin combination, and the target pins in the target pin combination correspond one-to-one with the source pins.

[0163] The bus fault cause determination method provided in this application embodiment detects and isolates reserved pins in abnormal states, thereby preventing duplicate signal errors caused by pin hardware failures from the source and ensuring the accuracy and reliability of fault cause diagnosis results.

[0164] The bus fault cause determination method provided in this application can not only be used in embedded system debugging scenarios, but also extended to debugging scenarios such as industrial control and IoT gateways, solving the signal acquisition problem in such scenarios where hardware modification is limited and interference is severe.

[0165] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0166] Embodiments of this application also provide a bus fault cause determination device, such as... Figure 6 As shown, the bus fault cause determination device includes:

[0167] The first determining module 601 is used to determine the source pin corresponding to the target bus in the event of a target bus failure in the controller.

[0168] The second determining module 602 is used to determine the target pin corresponding to the source pin from the reserved pins of the controller, wherein each reserved pin corresponds to a reserved terminal.

[0169] The acquisition module 603 is used to acquire the configuration information of the target bus.

[0170] The first configuration module 604 is used to configure the target pins accordingly based on the configuration information of the target bus.

[0171] The second configuration module 605 is used to configure the interrupt mode of the source pin as edge-triggered interrupt mode.

[0172] The reading module 606 is used to read the level signal of the source pin when the source pin triggers an interrupt based on the interrupt handling model, and set the output level signal of the target pin to be consistent with the level signal of the corresponding source pin.

[0173] The third determination module 607 is used to collect the output level signal of the target pin using a logic analyzer to determine the cause of the target bus fault. The logic analyzer is connected to the reserved terminal corresponding to the target pin.

[0174] In some alternative implementations, the second determining module 602 includes:

[0175] The first determining unit is used to determine the free pins among the reserved pins based on the reserved pins of the controller.

[0176] The determination unit is used to determine whether the idle pins include at least one adjacent pin combination, wherein the number of adjacent pins included in the adjacent pin combination is the same as the number of source pins.

[0177] The second determining unit is used to determine one of the adjacent pin combinations as the target pin combination if the idle pins include at least one adjacent pin combination, wherein the target pins in the target pin combination correspond one-to-one with the source pins.

[0178] In some optional embodiments, the bus fault cause determination device further includes:

[0179] The third determining unit is used to determine the target pin corresponding to the source pin from the free pins based on the source pin if the free pins do not include at least one adjacent pin combination.

[0180] In some alternative implementations, the first configuration module 604 includes:

[0181] The first configuration unit is used to configure the operating mode of the target pin based on the current bus operating mode.

[0182] The second configuration unit is used to configure the communication rate of the target pin based on the current bus communication rate.

[0183] The third configuration unit is used to configure the electrical configuration of the target pin to be the same as the electrical configuration of the corresponding source pin.

[0184] The fourth configuration unit is used to configure the level range of the target pin to be consistent with the level range of the corresponding source pin.

[0185] The fifth configuration unit is used to configure the initial output level signal of the target pin to be consistent with the idle level signal of the corresponding source pin.

[0186] In some optional embodiments, the bus fault cause determination device further includes:

[0187] The read unit is used to read the register data corresponding to the clock line when the source pin is the clock signal pin corresponding to the clock line.

[0188] The first acquisition unit is used to acquire the clock frequency of the clock signal if the register data corresponding to the clock line includes the clock frequency of the clock signal.

[0189] The second acquisition unit is used to acquire the number of interrupts triggered by the source pin per unit time if the register data corresponding to the clock line does not include the clock frequency of the clock signal; and to determine the clock frequency of the clock signal based on the number of interrupts triggered by the source pin per unit time.

[0190] The control unit is used to control the target pin corresponding to the source pin to output a square wave based on the clock frequency of the clock signal.

[0191] In some optional embodiments, the bus fault cause determination device further includes:

[0192] The enable unit is used to maintain the log printing function of the interrupt handling model if the clock frequency of the clock signal is less than a first frequency threshold. The log printing function is used to log the level signal of the source pin.

[0193] The first shutdown unit is used to disable the log printing function if the clock frequency of the clock signal is not less than a first frequency threshold and is less than a second frequency threshold.

[0194] The second shutdown unit is used to disable the log printing function and the level signal delay secondary verification function of the interrupt handling model if the clock frequency of the clock signal is not less than the second frequency threshold.

[0195] The level signal delay secondary verification function is used to perform a delay secondary verification on the level signal of the source pin.

[0196] In some optional implementations, the bus fault cause determination apparatus further includes, before setting the output level signal of the target pin to match the level signal of the corresponding source pin:

[0197] The verification unit is used to perform a delayed secondary verification of the level signal of the source pin.

[0198] The setting unit is used to set the output level signal of the target pin to be consistent with the level signal of the corresponding source pin if the level signal of the source pin passes the second delay verification.

[0199] In some optional embodiments, the bus fault cause determination device further includes:

[0200] The sixth configuration unit is used to configure the interrupt priority of the source pin to the highest level.

[0201] In some optional embodiments, the bus fault cause determination device further includes:

[0202] The first optimization unit is used to run the interrupt handling model during the testing phase of the interrupt handling model. When an interrupt is triggered by the test source pin corresponding to the test bus, it reads the level signal of the test source pin and sets the output level signal of the test target pin corresponding to the test source pin to be consistent with the level signal of the test source pin. The reserved pins include the test target pin. The unit uses measuring instruments to collect the level signal of the test source pin and the output level signal of the test target pin. It determines the timing deviation between the level signal of the test source pin and the output level signal of the corresponding test target pin. If the timing deviation is greater than a preset deviation threshold, the interrupt handling model is optimized.

[0203] The second optimization unit is used during the testing phase of the interrupt handling model to inject electromagnetic interference into the power supply of the controller and run the interrupt handling model. When an interrupt is triggered by the test source pin corresponding to the test bus, the unit reads the level signal of the test source pin under electromagnetic interference and performs a delayed secondary verification on the level signal. If the delayed secondary verification of the level signal of the test source pin passes, the output level signal of the corresponding test target pin is set to be consistent with the level signal of the test source pin under electromagnetic interference. Measuring instruments are used to collect the level signal of the test source pin under electromagnetic interference and the output level signal of the test target pin. The consistency between the level signal of the test source pin under electromagnetic interference and the corresponding output level signal of the test target pin is determined. If the consistency is lower than a preset consistency threshold, the interrupt handling model is optimized.

[0204] For a description of the features in the embodiment corresponding to the bus fault cause determination device, please refer to the relevant description of the embodiment corresponding to the bus fault cause determination method, which will not be repeated here.

[0205] Embodiments of this application also provide an electronic device, such as... Figure 7 As shown, it includes a processor 701 and a memory 702, in which a computer program is stored. The processor 701 is configured to run the computer program to perform the steps in any of the above-described bus fault cause determination method embodiments.

[0206] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the bus fault cause determination method when it is run.

[0207] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0208] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the bus fault cause determination method embodiments described above.

[0209] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described bus fault cause determination method embodiments.

[0210] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0211] The above provides a detailed description of a bus fault cause determination method and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for determining the cause of a bus fault, characterized in that, include: In the event of a target bus failure in the controller, determine the source pin corresponding to the target bus; The target pin corresponding to the source pin is determined from the reserved pins of the controller, wherein each reserved pin corresponds to a reserved terminal; Obtain the configuration information of the target bus; Based on the configuration information of the target bus, the target pins are configured accordingly; Configure the interrupt mode of the source pin to edge-triggered interrupt mode; Based on the interrupt handling model, when the source pin triggers an interrupt, the level signal of the source pin is read, and the output level signal of the target pin is set to be consistent with the level signal of the corresponding source pin. The output level signal of the target pin is acquired using a logic analyzer to determine the cause of the fault in the target bus. The logic analyzer is connected to the reserved terminal corresponding to the target pin. Determining the target pin corresponding to the source pin from the reserved pins of the controller includes: Based on the reserved pins of the controller, determine the idle pins among the reserved pins; Determine whether the idle pins include at least one adjacent pin combination, wherein the number of adjacent pins included in the adjacent pin combination is the same as the number of source pins; If the idle pins include at least one adjacent pin combination, then one of the adjacent pin combinations is determined as the target pin combination, and the target pins in the target pin combination correspond one-to-one with the source pins; The method further includes: If the idle pins do not include at least one adjacent pin combination, then the target pin corresponding to the source pin is determined from the idle pins based on the source pin.

2. The method according to claim 1, characterized in that, The configuration information includes the current bus operating mode, the current bus communication rate, the electrical configuration of the source pin, the level range of the source pin, and the idle level signal of the source pin; The configuration of the target pins based on the configuration information of the target bus includes: Configure the operating mode of the target pin based on the current bus operating mode; Configure the communication rate of the target pin based on the current bus communication rate; The electrical configuration of the target pin is the same as the electrical configuration of the corresponding source pin; Configure the voltage level range of the target pin to be consistent with the voltage level range of the corresponding source pin; Configure the initial output level signal of the target pin to be consistent with the idle level signal of the corresponding source pin.

3. The method according to claim 1, characterized in that, The method further includes: If the source pin is the clock signal pin corresponding to the clock line, read the register data corresponding to the clock line; If the register data corresponding to the clock line includes the clock frequency of the clock signal, then obtain the clock frequency of the clock signal; If the register data corresponding to the clock line does not include the clock frequency of the clock signal, then obtain the number of interrupts triggered by the source pin per unit time; based on the number of interrupts triggered by the source pin per unit time, determine the clock frequency of the clock signal; The target pin corresponding to the source pin is controlled to output a square wave based on the clock frequency of the clock signal.

4. The method according to claim 3, characterized in that, The method further includes: If the clock frequency of the clock signal is less than the first frequency threshold, the log printing function of the interrupt handling model is enabled. The log printing function is used to log the level signal of the source pin. If the clock frequency of the clock signal is not less than the first frequency threshold and is less than the second frequency threshold, then the log printing function is turned off. If the clock frequency of the clock signal is not less than the second frequency threshold, then the log printing function and the level signal delay secondary verification function of the interrupt handling model are disabled. The level signal delay secondary verification function is used to perform a delay secondary verification on the level signal of the source pin.

5. The method according to claim 1, characterized in that, Before setting the output level signal of the target pin to be consistent with the level signal of the corresponding source pin, the method further includes: The level signal of the source pin is subjected to a second verification after a delay; If the level signal of the source pin passes the second delay verification, the output level signal of the target pin is set to be consistent with the level signal of the corresponding source pin.

6. The method according to claim 1, characterized in that, The method further includes: Configure the interrupt priority of the source pin to the highest level.

7. The method according to claim 1, characterized in that, The method further includes: During the testing phase of the interrupt handling model, the interrupt handling model is run to read the level signal of the test source pin when an interrupt is triggered by the test source pin corresponding to the test bus, and set the output level signal of the test target pin corresponding to the test source pin to be consistent with the level signal of the test source pin. The reserved pin includes the test target pin. The level signal of the test source pin and the output level signal of the test target pin are collected using a measuring instrument. The timing deviation between the level signal of the test source pin and the corresponding output level signal of the test target pin is determined. If the timing deviation is greater than a preset deviation threshold, the interrupt handling model is optimized. During the testing phase of the interrupt handling model, electromagnetic interference is injected into the power supply of the controller, and the interrupt handling model is run. When an interrupt is triggered by the test source pin corresponding to the test bus, the level signal of the test source pin under electromagnetic interference is read, and a second delay verification is performed on the level signal of the test source pin under electromagnetic interference. If the second delay verification of the level signal of the test source pin passes, the output level signal of the test target pin corresponding to the test source pin is set to be consistent with the level signal of the test source pin under electromagnetic interference. Measuring instruments are used to collect the level signal of the test source pin under electromagnetic interference and the output level signal of the test target pin; the consistency between the level signal of the test source pin under electromagnetic interference and the corresponding output level signal of the test target pin is determined; if the consistency is lower than a preset consistency threshold, the interrupt handling model is optimized.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the bus fault cause determination method as described in any one of claims 1 to 7 when executing the computer program.

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