Decoder, decoding method, memory system, and memory controller

Abstract

The embodiment of the invention discloses a decoder, a decoding method, a memory system, a memory controller and a computer readable storage medium. The decoder comprises a data processing circuit and a data output circuit. The data processing circuitry is configured to: perform a current check calculation using a current column of a check matrix and a current sub-matrix of a current flag matrix; wherein the check matrix comprises n columns, and n is an integer greater than 1; the current flag matrix comprises n sub-matrixes, and the current sub-matrix is related to the current data block of the flipped code word; the code word comprises n data blocks, each data block comprises k code elements, and k is a positive integer; the current sub-matrix comprises k current flag bits, and the current flag bits are used for indicating whether corresponding code elements in the current data block are overturned or not; performing current increment check calculation on the result of the current check calculation and the previous syndrome to generate a current syndrome; the data output circuit is configured to output the flipped codeword based on the current syndrome satisfying the verification condition.

Description

Technical Field

[0001] This disclosure relates to the field of memory, and includes, but is not limited to, a decoder, a decoding method, a memory system, and a memory controller. Background Technology

[0002] Memory controllers and one or more memories can be integrated into various types of storage devices, such as solid-state drives (SSDs), universal flash storage (UFS), and embedded multi-media cards (eMMC). As memory integration and bit density increase, the bit error rate of storage devices also increases, making data reliability issues increasingly prominent.

[0003] To enhance data reliability, Error Correcting Code (ECC) technology has been used to detect and correct errors during data transmission. ECC typically uses the BCH (Blockchain Chip) algorithm and the Low Density Parity Check (LDPC) algorithm for data encoding and decoding. LDPC offers stronger error correction capabilities compared to BCH. However, LDPC is more complex, resulting in longer data decoding times. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a decoder is provided, the decoder including a data processing circuit and a data output circuit coupled to the data processing circuit;

[0005] The data processing circuit is configured as follows:

[0006] The current check calculation is performed using the current column of the check matrix and the current submatrix of the current flag matrix; wherein the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are associated with the current data block of the flipped codeword; the codeword includes n data blocks, each of which includes k code elements, where k is a positive integer; the current submatrix includes k current flag bits, each of which indicates whether the corresponding code element in the current data block of the codeword has been flipped;

[0007] The result of the current check calculation is combined with the previous syndrome to perform the current incremental check calculation, generating the current syndrome.

[0008] The data output circuit is configured as follows:

[0009] Based on the fact that the current syntactic satisfies the verification condition, the reversed codeword is output.

[0010] In some embodiments, the data processing circuit is further configured to:

[0011] Since the current syndrome does not meet the verification condition, the next verification calculation is performed using the next column of the verification matrix and the next submatrix of the current flag matrix;

[0012] The result of the next check calculation is combined with the current syndrome to perform the next incremental check calculation, generating the next syndrome.

[0013] The data output circuit is configured as follows:

[0014] Based on the next syntactic satisfying the verification condition, the reversed codeword is output.

[0015] In some embodiments, the next syndrome is the nth syndrome; the decoder further includes a bit-flipping processing circuit coupled to the data processing circuit, the bit-flipping processing circuit being configured to:

[0016] Since the nth syndrome does not satisfy the verification condition, the codeword is flipped again;

[0017] Generate the next flag matrix associated with the codeword that has been flipped again.

[0018] In some embodiments, the data processing circuit is configured to:

[0019] The codeword is initially checked using the parity-check matrix to generate an initial syndrome.

[0020] The bit-flipping processing circuit is configured as follows:

[0021] Since the initial syndrome does not satisfy the verification condition, the codeword is flipped.

[0022] Generate the first flag matrix associated with the flipped codeword.

[0023] In some embodiments, the bit-flipping processing circuit is specifically configured as follows:

[0024] The initial flag bits corresponding to the flipped symbols in the initial flag matrix are set to flag logic values ​​to generate the first flag matrix or the next flag matrix.

[0025] In some embodiments, the decoding operation of the codeword includes multiple iterative stages; wherein, different iterative stages correspond to different flag matrices.

[0026] In some embodiments, the decoder further includes a codeword buffer circuit coupled to the data processing circuit, the codeword buffer circuit being configured to:

[0027] Cache the codeword or flip the codeword.

[0028] In some embodiments, the data processing circuit is specifically configured as follows:

[0029] Calculate the product of the current column of the check matrix and the current submatrix of the current flag matrix to generate the current sub-adjoint expression;

[0030] Perform an XOR operation on the previous syndrome and the current subsynonym to generate the current syndrome.

[0031] In some embodiments, the decoder further includes a judgment circuit coupled to the data processing circuit and the data output circuit respectively, the judgment circuit being configured to:

[0032] Determine whether the current syndrome satisfies the verification condition.

[0033] In some embodiments, the verification condition includes a syndrome of 0.

[0034] According to a second aspect of the present disclosure, a decoding method is provided, comprising:

[0035] The current check calculation is performed using the current column of the check matrix and the current submatrix of the current flag matrix; wherein the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are associated with the current data block of the flipped codeword; the codeword includes n data blocks, each of which includes k code elements, where k is a positive integer; the current submatrix includes k current flag bits, each of which indicates whether the corresponding code element in the current data block of the codeword has been flipped;

[0036] The result of the current check calculation is combined with the previous syndrome to perform the current incremental check calculation, generating the current syndrome.

[0037] Based on the fact that the current syntactic satisfies the verification condition, the reversed codeword is output.

[0038] In some embodiments, the decoding method further includes: performing a next check calculation using the next column of the check matrix and the next submatrix of the current flag matrix, based on the fact that the current syntactic does not satisfy the check condition;

[0039] The result of the next check calculation is combined with the current syndrome to perform the next incremental check calculation, generating the next syndrome.

[0040] Based on the next syntactic satisfying the verification condition, the reversed codeword is output.

[0041] In some embodiments, the next syndrome is the nth syndrome; the decoding method further includes:

[0042] Since the nth syndrome does not satisfy the verification condition, the codeword is flipped again;

[0043] Generate the next flag matrix associated with the codeword that has been flipped again.

[0044] In some embodiments, the decoding method further includes:

[0045] The codeword is initially checked using the parity-check matrix to generate an initial syndrome.

[0046] Since the initial syndrome does not satisfy the verification condition, the codeword is flipped.

[0047] Generate the first flag matrix associated with the flipped codeword.

[0048] In some embodiments, generating the first flag matrix or the next flag matrix associated with the flipped codeword includes:

[0049] The initial flag bits corresponding to the flipped symbols in the initial flag matrix are set to flag logic values ​​to generate the first flag matrix or the next flag matrix.

[0050] In some embodiments, the decoding method further includes: caching the codeword or flipping the codeword.

[0051] In some embodiments, performing the current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix includes:

[0052] Calculate the product of the current column of the check matrix and the current submatrix of the current flag matrix to generate the current sub-adjoint expression;

[0053] The step of performing the current incremental check calculation by combining the result of the current check calculation with the previous association includes:

[0054] Perform an XOR operation on the previous syndrome and the current subsynonym to generate the current syndrome.

[0055] In some embodiments, the decoding method further includes: determining whether the current syntactic satisfies the verification condition.

[0056] In some embodiments, the verification condition includes a syndrome of 0.

[0057] According to a third aspect of the present disclosure, a memory system is provided, comprising:

[0058] A memory configured to output read data;

[0059] The decoder described in any embodiment of the first aspect of this disclosure is coupled to the memory; the decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

[0060] In some embodiments, the memory system further includes:

[0061] An encoder configured to receive write data and perform an encoding operation on the write data;

[0062] The memory is also configured to receive the encoded write data.

[0063] According to a fourth aspect of the present disclosure, a memory controller is provided, comprising:

[0064] A memory interface configured to receive and read data;

[0065] The decoder described in any embodiment of the first aspect of this disclosure is coupled to the memory interface; the decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

[0066] According to a fifth aspect of the present disclosure, a computer-readable storage medium is provided, the computer-readable storage medium storing instructions that are executed by a processor to implement the decoding method as described in any embodiment of the second aspect of the present disclosure.

[0067] In this embodiment, the current check calculation can be performed using the current column of the check matrix and the current submatrix of the current flag matrix. The result of the current check calculation is then combined with the previous syndrome to perform the current incremental check calculation, generating the current syndrome. If the current syndrome satisfies the check condition, decoding is successful, and the flipped codeword is output. This allows for timely exit from decoding, reducing decoding time and avoiding unnecessary erroneous flips. Attached Figure Description

[0068] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0069] Figure 1This is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0070] Figure 2a This is a schematic diagram of a memory card according to an embodiment of the present disclosure.

[0071] Figure 2b This is a schematic diagram of a solid-state drive according to an embodiment of the present disclosure.

[0072] Figure 3 This is a schematic block diagram of a three-dimensional NAND memory according to an embodiment of the present disclosure.

[0073] Figure 4 This is a schematic cross-sectional view of a memory according to an embodiment of the present disclosure.

[0074] Figure 5 This is a schematic diagram of a memory including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure.

[0075] Figure 6 This is a schematic diagram of an LDPC iterative decoding process according to an embodiment of the present disclosure.

[0076] Figure 7 This is a schematic block diagram of a decoder according to an embodiment of the present disclosure.

[0077] Figure 8 This is a schematic diagram of a decoding process according to an embodiment of the present disclosure.

[0078] Figure 9 This is a schematic block diagram of another decoder shown according to an embodiment of the present disclosure.

[0079] Figure 10 This is a schematic diagram illustrating another LDPC iterative decoding process according to an embodiment of the present disclosure.

[0080] Figure 11 This is a schematic diagram illustrating the calculation of an initial adjoint according to an embodiment of the present disclosure.

[0081] Figure 12 This is a schematic diagram illustrating a computational increment syndrome according to an embodiment of the present disclosure.

[0082] Figure 13 This is a flowchart illustrating a decoding method according to an embodiment of the present disclosure.

[0083] Figure 14 This is a schematic block diagram of a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0084] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

[0085] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of the actual embodiments, nor well-known functions and structures, may be described herein.

[0086] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0087] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0088] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0089] Figure 1This is a schematic diagram illustrating an electronic device according to an embodiment of the present disclosure. The electronic device 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein. See also... Figure 1 As shown, the electronic device 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0090] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or eMMC, and SSDs or eMMC are used as data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0091] The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions regarding data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes regarding data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., according to specific communication protocols) Figure 1 The memory controller 106 communicates with the host device 108. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Development Equipment (IDE), FireWire, etc.

[0092] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., UFS package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (Personal Computer Memory Card), CF card, Smart Media (SM) card, memory stick, Multimedia Card (MMC, RS-MMC (Reduced-Size MMC), MMCmicro), SD card (SD, miniSD, microSD, SDHC (Reduced-Size MMC)), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0093] Figure 3 This is a schematic block diagram illustrating a three-dimensional NAND memory according to an embodiment of the present disclosure. The memory 300 may be... Figure 1 An example of memory 104 is provided. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0094] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal memory values. In one example, if each MLC stores two bits of data, the MLC can be programmed to write one of three possible nominal memory values ​​into the cell, while a fourth nominal memory value in addition to these three nominal memory values ​​can be used to indicate an erase state.

[0095] like Figure 3 As shown, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source end and a top select gate (TSG) 312 at its drain end. The BSG 310 and TSG 312 may be configured to activate the selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0096] like Figure 3 As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source line of unselected memory blocks on the same plane as the selected memory block can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, memory cells 306 coupled to the same word line 318 in memory block 304 may constitute at least one physical page 320. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 of the corresponding physical page 320 and gate lines coupling the control gates.

[0097] Figure 4 This is a schematic cross-sectional view of a memory according to an embodiment of the present disclosure. (Refer to...) Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 301.

[0098] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0099] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0100] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0101] Return to reference Figure 3The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0102] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a physical page of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0103] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0104] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0105] 3D NAND flash memory, as a storage medium that is more stable and faster than traditional disk storage, has been widely used in various storage devices. To meet the ever-increasing storage demands, the process size of 3D NAND flash memory is continuously shrinking, and the types of storage cells are evolving from SLC to MLC, TLC, and QLC. This has led to an increase in the bit error rate. The traditional Bit-Chip (BCH) algorithm is no longer sufficient to guarantee data reliability. The LDPC algorithm, as an error correction method with error correction capabilities approaching the Shannon limit, is gradually replacing BCH and becoming the next-generation error correction coding method.

[0106] LDPC decoding determines success by checking if the syndrome is zero. Specifically, an initial check is performed on the codeword using a parity-check matrix to generate an initial check syndrome. If the initial check syndrome is zero, decoding is successful, and the decoding process exits; otherwise, the codeword is flipped, and at least one round of iterative checking is performed until the generated syndrome is zero or the maximum number of iterations is reached. A codeword typically consists of multiple data blocks, each containing multiple bits. During iterative checking, the syndrome for each iteration can be calculated incrementally. This will be discussed in the following section. Figure 6 An illustrative example is provided.

[0107] Figure 6 This is a schematic flowchart illustrating an LDPC iterative verification process according to an embodiment of this disclosure. (Refer to...) Figure 6 As shown, if the initial parity expression or the parity expression of the previous iteration is not 0, then the flipped codeword enters the current / current iteration parity expression. The parity expression of the current / current iteration is equal to the initial parity expression or the parity expression of the previous iteration + S. U0 +S U1 +……+S Ui +……+S U(n-1) 1 ≤ i ≤ n-1, where n is an integer greater than 1. If the current round / layer iteration check is 0, decoding is successful, and decoding exits; otherwise, if the maximum number of iterations has not been reached, the codeword can be flipped again (e.g., at least one bit is flipped) and the next round of iteration check can begin. It is understandable that if the initial check syntactic is not 0, the current round / layer iteration check can be the first round / layer iteration check.

[0108] It should be noted that, Figure 6 S U0 S is the product of the first column of the verification matrix and the first submatrix 0 of the current round's flag matrix. U1 S is the product of the second column of the verification matrix and the second submatrix 1 of the current round's flag matrix, ..., S Ui S is the product of the (i+1)th column of the verification matrix and the (i+1)th submatrix i of the current round's flag matrix, ..., S U(n-1) This is the product of the nth column of the check matrix and the nth submatrix (n-1) of the current round flag matrix. Here, each submatrix in the current round flag matrix is ​​used to indicate whether the code elements of the corresponding data block have been flipped. For example, the first submatrix 0 is used to indicate whether the code elements of the first data block of the codeword have been flipped, ..., and the nth submatrix (n-1) is used to indicate whether the code elements of the nth data block of the codeword have been flipped.

[0109] Figure 6This demonstrates that calculating the adjoint in each iteration incrementally can reduce the complexity of LDPC decoding to some extent, especially in scenarios requiring the decoding of large amounts of data. However, this scheme only determines whether decoding was successful after one iteration / layer is completed, which may miss opportunities, leading to longer decoding times and unnecessary error flips.

[0110] Based on one or more of the above-mentioned technical problems, this disclosure provides a decoder.

[0111] Figure 7 This is a schematic block diagram of a decoder according to an embodiment of the present disclosure. (Refer to...) Figure 7 As shown, the decoder 600 includes a data processing circuit 604 and a data output circuit 610 coupled to the data processing circuit 604. The data processing circuit 604 is configured to: perform a current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix; wherein the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are associated with the current data block of the flipped codeword; the codeword includes n data blocks, each data block including k bits, where k is a positive integer; the current submatrix includes k current flag bits, each current flag bit indicating whether the corresponding bit in the current data block of the codeword has been flipped; perform a current incremental check calculation by combining the result of the current check calculation with the previous syndrome to generate the current syndrome; the data output circuit 610 is configured to: output the flipped codeword based on the current syndrome satisfying the check condition.

[0112] It should be noted that, in the embodiments of this disclosure, the codewords include, but are not limited to, quasi-cyclic (QC) LDPC codes. The parity check matrix of a quasi-cyclic (QC) LDPC code may include multiple sub-parity check matrices. Each sub-parity check matrix may be a zero matrix or a cyclic permutation matrix. The cyclic permutation matrix may be an identity matrix or a sub-parity check matrix obtained by performing a predetermined number of cyclic shifts on the identity matrix.

[0113] For example, a codeword may consist of 512 bits, which can be divided into four data blocks, each containing 128 bits. Accordingly, the current submatrix may include 128 current flag bits, each used to indicate whether a bit in the current data block has been flipped. For instance, if a bit in the current data block is flipped, the corresponding current flag bit in the current submatrix can be set to logic "1"; if other bits in the current data block are not flipped, the corresponding current flag bits in the current submatrix can be set to logic "0". Here, an example of n being 4 and k being 128 is used, but this does not constitute a limitation on the scope of this disclosure.

[0114] It is understood that the current iteration verification includes at least one incremental verification calculation. In this embodiment of the disclosure, the current verification calculation can be performed using the current column of the verification matrix and the current submatrix of the current flag matrix, and the result of the current verification calculation can be combined with the previous syndrome to perform the current incremental verification calculation, generating the current syndrome. If the current syndrome satisfies the verification condition, it indicates successful decoding, and the flipped codeword is output. In this way, decoding can be exited in a timely manner, reducing decoding time and avoiding unnecessary erroneous flips.

[0115] It should be noted that if the syndrome generated at the end of one round of iterative verification does not meet the verification conditions and the maximum number of iterations has not been reached, the codeword needs to be flipped to obtain the flipped codeword, and a new round of iterative verification should be performed on the flipped codeword. In practical applications, the code elements that need to be flipped (i.e., erroneous code elements) in the codeword of one round of iterative verification can be determined first, and the erroneous code elements can be flipped to obtain the flipped codeword.

[0116] In some embodiments, refer to Figure 7 As shown, the data processing circuit 604 is further configured to: perform the next check calculation using the next column of the check matrix and the next submatrix of the current flag matrix based on the fact that the current syndrome does not meet the check condition; perform the next incremental check calculation with the result of the next check calculation and the current syndrome to generate the next syndrome; the data output circuit 610 is configured to: output the flipped codeword based on the fact that the next syndrome meets the check condition.

[0117] In this embodiment of the disclosure, after the current incremental check calculation, if the current syndrome does not meet the check condition, the next column of the check matrix and the next submatrix of the current flag matrix can be used to perform the next check calculation. The result of the next check calculation is then combined with the current syndrome to perform the next incremental check calculation, generating the next syndrome. If the next syndrome meets the check condition, the decoding is successful, and the flipped codeword is output. In this way, decoding can be exited in a timely manner, reducing decoding time and avoiding unnecessary erroneous flips.

[0118] It should be noted that the current incremental check calculation and the next incremental check calculation are different stages of the current iterative check. If the syndrome generated by the initial iterative check does not meet the check condition, the codeword can be flipped at least once, and at least one round of iterative check can be performed accordingly. Each time a codeword is flipped and enters the iterative check, a flag matrix associated with the flipped codeword can be generated, and at least one column of the check matrix and at least one submatrix of the flag matrix are used to perform at least one incremental check calculation to obtain at least one incremental syndrome. When the incremental syndrome meets the check condition, decoding is exited promptly, which not only reduces decoding time but also avoids erroneous flips caused by redundant incremental check calculations. For example, Figure 6The proposed scheme requires n incremental verification calculations in each iteration to determine whether the decoding was successful. This process is time-consuming and may also involve redundancy in the incremental verification calculations.

[0119] Figure 8 This is a schematic diagram illustrating a decoding process according to an embodiment of the present disclosure. (Refer to...) Figure 8 As shown, in this embodiment of the present disclosure, the process of performing one round of iteration using the decoder 600 includes: multiplying the current column of the parity check matrix and the current submatrix of the current flag matrix to obtain the current sub-compound; adding the previous compound and the current sub-compound to obtain the current compound; if the current compound is 0, it indicates successful decoding, and the reversed codeword is output; otherwise, multiplying the next column of the parity check matrix and the next submatrix of the current flag matrix to obtain the next sub-compound; adding the current compound and the next sub-compound to obtain the next compound; if the next compound is 0, it indicates successful decoding, and the reversed codeword is output; otherwise, performing a similar incremental check until the obtained incremental compound is 0 or the current iteration ends.

[0120] In this embodiment of the disclosure, the verification condition includes the adjoint being 0. The verification condition is met if the calculated initial adjoint or incremental adjoint is 0; otherwise, the verification condition is not met if the calculated initial adjoint or incremental adjoint is not 0. The following will use the verification condition of the adjoint being equal to 0 as an example for illustrative explanation. The initial adjoint will be described in detail in the following embodiments and will not be repeated here.

[0121] In some embodiments, refer to Figure 7 As shown, the next syndrome is the nth syndrome; the decoder 600 also includes a bit-flipping processing circuit 606 coupled to the data processing circuit 604, the bit-flipping processing circuit 606 is configured to: flip the codeword again based on the fact that the nth syndrome does not meet the check condition; and generate the next flag matrix associated with the flipped codeword.

[0122] In this embodiment of the disclosure, if the next syndrome is the nth syndrome and the nth syndrome is not 0, it indicates that the current iteration check has failed, and the codeword needs to be flipped again. The next round of iteration check is then performed on the flipped codeword. When the codeword is flipped again to enter the next round of iteration check, a next flag matrix related to the flipped codeword can be generated, and at least one column of the check matrix and at least one submatrix of the next flag matrix are used to perform the check. Figure 8 A similar new round of iterative verification.

[0123] In some embodiments, the codeword decoding operation includes multiple iterative stages; wherein, different iterative stages correspond to different flag matrices. For example, LDPC decoding typically includes initial check and multiple rounds of iterative check. After the initial check or after each round of iterative check, if the generated initial syndrome or the syndrome of the current round of iterative check is not 0, the codeword needs to be flipped and a flag matrix associated with the flipped codeword needs to be generated. Since the position of the codeword is different each time it is flipped, the generated flag matrix is ​​different, that is, the flag matrix corresponding to different iterative stages is different.

[0124] In some embodiments, the data processing circuit 604 is configured to: perform an initial check on the codeword using a check matrix to generate an initial syndrome; the bit flipping processing circuit 606 is configured to: flip the codeword based on the initial syndrome not meeting the check condition; and generate a first flag matrix associated with the flipped codeword.

[0125] In this embodiment of the disclosure, conventional calculation methods can be used during the initial verification process. For example, S = HC T S represents the initial syndrome, H represents the parity check matrix, and C represents the codeword. If the initial syndrome S is not 0, the erroneous code elements in the codeword are flipped, and the first flag matrix associated with the flipped codeword is generated based on the position of the flipped erroneous code elements.

[0126] In some embodiments, the bit-flipping processing circuit 606 is specifically configured to set the initial flag bit corresponding to the flipped symbol in the initial flag matrix to a flag logic value to generate the first flag matrix or the next flag matrix.

[0127] For example, if the initial symptom is not 0, the erroneous codeword in the codeword is flipped, and the corresponding initial flag bit in the initial flag matrix is ​​set to the logical value "1" according to the position of the flipped erroneous codeword. The logical value "1" is used to indicate that the erroneous codeword has been flipped, thereby generating the first flag matrix.

[0128] For example, if the nth syntactic is not 0, the erroneous codeword in the codeword is flipped, and the corresponding initial flag bit in the initial flag matrix is ​​set to the logical value "1" according to the position of the flipped erroneous codeword. The logical value "1" is used to indicate that the erroneous codeword has been flipped, thereby generating the next flag matrix.

[0129] It should be noted that the number of initial submatrices in the initial flag matrix can be the same as the number of data blocks in the codeword, that is, the initial flag matrix includes n initial submatrices, and the number of initial flag bits in each initial submatric can be the same as the number of symbols in each data block, that is, each initial submatric includes k initial flag bits. In some embodiments, the initial flag matrix can be an all-zero matrix, where the initial flag bits corresponding to the unflipped symbols in the initial flag matrix are logic values ​​"0".

[0130] In this embodiment, the initial flag bits corresponding to the flipped code elements in the initial flag matrix are set as flag logic values ​​to generate a flag matrix for each iteration. A column of the check matrix and a submatrix of the flag matrix are used for check calculation. Since the number of bits in the flipped code elements in a codeword is usually much smaller than the number of bits in the unflipped code elements, each submatrix of the flag matrix contains fewer logic values ​​"1" and more logic values ​​"0". This simplifies the complexity of the iterative check calculation and speeds up the decoding process, thereby reducing decoding time.

[0131] In some embodiments, the decoder 600 further includes a codeword buffer circuit 602 coupled to the data processing circuit 604. The codeword buffer circuit 602 is configured to buffer codewords or inverted codewords. For example, when the original codeword to be decoded is input into the decoder 600, the codeword buffer circuit 602 can buffer the input original codeword to be decoded (i.e., the codeword). As another example, if the initial verification fails or one round of iterative verification fails, the codeword buffer circuit 602 can buffer the iteratively decoded codeword (i.e., the inverted codeword). The data processing circuit 604 can retrieve the input original codeword to be decoded from the codeword buffer circuit 602 to perform the initial verification, or retrieve the iteratively decoded codeword from the codeword buffer circuit 602 to perform the next round of iterative verification.

[0132] In some embodiments, the data processing circuit 604 is specifically configured to: calculate the product of the current column of the parity check matrix and the current submatrix of the current flag matrix to generate the current sub-compound; and perform an XOR operation on the previous compound and the current sub-compound to generate the current compound.

[0133] In this embodiment of the disclosure, the data processing circuit 604 may include a matrix multiplier and a matrix adder; wherein, the matrix multiplier is used to calculate the product of the current column of the check matrix and the current submatrix of the current flag matrix, which is implemented by AND operation and XOR operation; the matrix adder is used to calculate the sum of the previous adjoint and the current subadjoint, which is implemented by XOR operation.

[0134] In some embodiments, the decoder 600 further includes a judgment circuit 608 that is coupled to the data processing circuit 604 and the data output circuit 610 respectively. The judgment circuit 608 is configured to: determine whether the current symptom satisfies the verification condition.

[0135] In this embodiment of the present disclosure, the judgment circuit 608 can receive the current syndrome generated by the data processing circuit 604. If the current syndrome is 0, the judgment circuit 608 generates a first judgment result, and the data output circuit 610 outputs the reversed codeword cached in the codeword cache circuit 602 based on the first judgment result; if the current syndrome is not 0, the judgment circuit 608 generates a second judgment result, and the data processing circuit 604 performs the next check calculation and the next incremental check calculation based on the second judgment result. Figure 7 In this circuit, a logic value of "0" represents the first judgment result, and a logic value of "1" represents the second judgment result. Of course, the judgment circuit 608 can also be used to determine whether the initial syndrome or other incremental syndromes (e.g., the next syndrome) are 0.

[0136] It should be noted that if the initial syntactic is not 0 or the nth syntactic in each round of iteration is not 0, the bit flipping processing circuit 606 flips the codeword based on the second judgment result.

[0137] Figure 9 This is a schematic block diagram of another decoder 600 according to an embodiment of this disclosure. Besides Figure 7 In addition to the codeword buffer circuit 602, data processing circuit 604, bit flipping processing circuit 606, judgment circuit 608, and data output circuit 610 shown, the decoder 600 may also include a first selection circuit 601, a second selection circuit 603, a matrix buffer circuit 605, a flipped codeword generation circuit 607, and a delay circuit 609. Of course, the decoder 600 may also include other circuits known in the art.

[0138] The first selection circuit 601 is configured to output either the original codeword to be decoded or the iteratively decoded codeword based on a first control signal. For example, if the first control signal indicates that the current check is an initial check, the first selection circuit 601 outputs the original codeword to be decoded; if the first control signal indicates that the current check is an iterative check, the first selection circuit 601 outputs the iteratively decoded codeword. It is understood that the iteratively decoded codeword is different from the original codeword to be decoded; the iteratively decoded codeword can be a flipped codeword that is flipped at least once based on the original codeword to be decoded. The first selection circuit 601 includes, but is not limited to, a multiplexer.

[0139] The codeword buffer circuit 602 is coupled to the first selection circuit 601. The codeword buffer circuit 602 is configured to buffer the original codeword to be decoded or the iteratively decoded codeword, that is, the codeword output by the first selection circuit 601 can be buffered in the codeword buffer circuit 602.

[0140] The second selection circuit 603 is coupled to the codeword buffer circuit 602 and the bit-flipping processing circuit 606, respectively. The second selection circuit 603 is configured to output either the original codeword to be decoded or the current sub-matrix of the current flag matrix based on the second control signal. For example, if the second control signal indicates that the current check is the initial check, the second selection circuit 603 outputs the original codeword to be decoded; if the second control signal indicates that the current check is the current iteration check, the second selection circuit 603 outputs the current sub-matrix of the current flag matrix. The second selection circuit 603 includes, but is not limited to, a multiplexer. The following description uses the example of the second selection circuit 603 outputting the current sub-matrix of the current flag matrix as an example.

[0141] The data processing circuit 604 is coupled to the second selection circuit 603, the matrix buffer circuit 605, and the bit-flipping processing circuit 606. The data processing circuit 604 is configured to: perform a current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix; and perform a current incremental check calculation by combining the result of the current check calculation with the previous syndrome to generate the current syndrome. The check matrix can be buffered in the matrix buffer circuit 605. Each time an incremental check calculation needs to be performed, the data processing circuit 604 can retrieve a column of the check matrix from the matrix buffer circuit 605. Of course, during the initial check process, the data processing circuit 604 can retrieve the entire check matrix from the matrix buffer circuit 605, that is, retrieve n columns of the check matrix.

[0142] The judgment circuit 608 is coupled to the data processing circuit 604, the data output circuit 610, and the bit flipping processing circuit 606. The judgment circuit 608 is configured to determine whether the current syndrome is 0. If the current syndrome is 0, the data output circuit 610 outputs the iterative decoding codeword cached in the codeword buffer circuit 602, i.e., exits decoding; otherwise, the data processing circuit 604 performs the next check calculation and the next incremental check calculation to generate the next syndrome. This process continues until the obtained incremental syndrome is 0 or the current iteration ends.

[0143] The bit-flipping processing circuit 606 is configured to: flip the codeword again based on the fact that the nth syntactic does not meet the check condition; and generate the next flag matrix associated with the flipped codeword. Alternatively, the bit-flipping processing circuit 606 is also configured to: flip the codeword based on the fact that the initial syntactic does not meet the check condition; and generate the first flag matrix associated with the flipped codeword.

[0144] The flip codeword generation circuit 607 is coupled to the codeword buffer circuit 602 and the bit-flipping processing circuit 606, respectively. The flip codeword generation circuit 607 is configured to generate the next iteration decoded codeword based on the flipped codewords and the codewords buffered in the codeword buffer circuit 602. In one example, the flip codeword generation circuit 607 includes, but is not limited to, an XOR logic gate circuit.

[0145] The delay circuit 609 is coupled to the flip codeword generation circuit 607 and the first selection circuit 601, respectively. The delay circuit 609 is configured to delay the next iteration of the decoded codeword by a preset time. It should be noted that the calculation time of the data processing circuit 604 and the judgment circuit 608 is relatively long. If the next iteration of the decoded codeword is immediately input into the first selection circuit 601, it will cause excess data to be written back to the codeword buffer circuit 602, which may lead to unwanted decoding errors. Therefore, by delaying the next iteration of the decoded codeword by a preset time, data write-back can be avoided. Here, the preset time can be reasonably set according to the calculation delay of the data processing circuit 604, and this disclosure does not have any special limitations in this regard.

[0146] Figure 10 This is a schematic diagram of another LDPC iterative decoding process according to an embodiment of this disclosure, which will be described below in conjunction with... Figure 10 The process of performing one iteration of the decoder provided in the embodiments of this disclosure will be described by way of example.

[0147] In one iteration, the first check calculation is performed using the first column of the check matrix and the first submatrix 0 of the current flag matrix, generating the first sub-association S. U0 And the first sub-compound S U0 Perform the first incremental verification calculation with the initial verification companion or the companion of the previous iteration to generate the first companion; determine whether the first companion is 0; if the first companion is 0, the decoding is successful and the decoding exits.

[0148] If the first appendage is not zero, perform a second check calculation using the second column of the check matrix and the second submatrix 1 of the current flag matrix to generate the second subappendage S. U1 And the second sub-associative S U1 Perform a second incremental check calculation with the first syndrome to generate a second syndrome; determine if the second syndrome is 0; if the second syndrome is 0, decoding is successful and the decoding process ends. Continue in this manner until the obtained incremental syndrome is 0 (e.g., the (i+1)th syndrome), or the nth syndrome is still not 0 at the end of this iteration, then flip the codeword and enter the next iteration.

[0149] Figure 11 This is a schematic diagram illustrating the calculation of an initial adjoint according to an embodiment of the present disclosure. Figure 12 This is a schematic diagram illustrating the calculation of an incremental syndrome according to an embodiment of this disclosure. The following will be combined with... Figure 11 and Figure 12 The LDPC decoding provided in the embodiments of this disclosure will be described by way of example.

[0150] Reference Figure 11As shown, an initial check is performed on the codeword using a parity-check matrix to generate an initial synod. The parity-check matrix is ​​a 4x4 matrix. The codeword consists of four data blocks, denoted as a0, a1, a2, and a3. The initial synod includes four check expressions, denoted as s0, s1, s2, and s3. If all four check expressions are 0, decoding is successful, and decoding exits. If at least one of the four check expressions is not 0, at least one bit of the codeword in at least one data block is flipped, and a first flag matrix associated with the flipped codeword is generated, entering the first round of iterative verification. For example, flipping the codeword in the second data block results in a first flag matrix consisting of four sub-matrices, denoted as 0, 1, 0, and 0.

[0151] Reference Figure 12 As shown, the product of the first column of the parity check matrix and the first submatrix 0 is calculated and the first incremental parity check is performed with the initial parity expression to generate the first parity expression S0'; it is determined whether the first parity expression S0' is 0; if the first parity expression S0' is 0, the decoding is successful and the decoding is exited.

[0152] If the first companion equation S0' is not 0, calculate the product of the second column of the parity check matrix and the second submatrix 1, and perform the second incremental parity check calculation with the first companion equation S0' to generate the second companion equation S1'; determine whether the second companion equation S1' is 0; if the second companion equation S1' is 0, the decoding is successful and the decoding exits.

[0153] If the second companion equation S1' is not 0, calculate the product of the third column of the parity check matrix and the third submatrix 0, and perform the third incremental parity check calculation with the second companion equation S1' to generate the third companion equation S2'; determine whether the third companion equation S2' is 0; if the third companion equation S2' is 0, the decoding is successful and the decoding exits.

[0154] If the third companion equation S2' is not 0, calculate the product of the fourth column of the parity check matrix and the fourth submatrix 0, and perform the fourth incremental parity check calculation with the third companion equation S2' to generate the fourth companion equation S3'; determine whether the fourth companion equation S3' is 0; if the fourth companion equation S3' is 0, the decoding is successful and the decoding exits.

[0155] If the fourth synod S3' is not 0, then at least one bit of the codeword in at least one data block is flipped again, and a second flag matrix associated with the flipped codeword is generated, entering the second round of iterative verification. For details on the second round of iterative verification, please refer to the relevant descriptions in the above embodiments; for brevity, they will not be repeated here.

[0156] Based on the decoder described above, this disclosure provides a decoding method. Figure 13 This is a flowchart illustrating a decoding method according to an embodiment of the present disclosure. (Refer to...) Figure 13 As shown, the decoding method includes:

[0157] S701: Perform current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix; wherein, the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are associated with the current data block of the flipped codeword; the codeword includes n data blocks, each data block including k code elements, where k is a positive integer; the current submatrix includes k current flag bits, each current flag bit indicating whether the corresponding code element in the current data block of the codeword has been flipped;

[0158] S702: Perform the current incremental check calculation by combining the result of the current check calculation with the previous syndrome, and generate the current syndrome;

[0159] S703: Output the reversed codeword based on the current symptom satisfying the check condition.

[0160] In some embodiments, the above decoding method further includes: performing a next check calculation using the next column of the check matrix and the next submatrix of the current flag matrix based on the fact that the current syndrome does not meet the check condition; performing a next incremental check calculation with the result of the next check calculation and the current syndrome to generate a next syndrome; and outputting the reversed codeword based on the fact that the next syndrome meets the check condition.

[0161] In some embodiments, the next syndrome is the nth syndrome; the above decoding method further includes: flipping the codeword again based on the fact that the nth syndrome does not meet the verification condition; and generating the next flag matrix associated with the flipped codeword.

[0162] In some embodiments, the above decoding method further includes: performing an initial check on the codeword using a check matrix to generate an initial syntactic; flipping the codeword based on the initial syntactic not satisfying the check condition; and generating a first flag matrix associated with the flipped codeword.

[0163] In some embodiments, generating the first flag matrix or the next flag matrix associated with the flipped codeword includes setting the initial flag bit in the initial flag matrix corresponding to the flipped codeword to a flag logic value to generate the first flag matrix or the next flag matrix.

[0164] In some embodiments, the above decoding method further includes: caching codewords or flipping codewords.

[0165] In some embodiments, S701 includes: calculating the product of the current column of the parity check matrix and the current submatrix of the current flag matrix to generate the current sub-compound; S702 includes: performing an XOR operation on the previous compound and the current sub-compound to generate the current compound.

[0166] In some embodiments, the above decoding method further includes: determining whether the current syntactic satisfies the verification condition.

[0167] In some embodiments, the verification condition includes a syndrome of 0.

[0168] In this embodiment, the decoding method can be executed by the decoder in any of the foregoing embodiments, and the decoding method can also achieve the technical effects that the decoder in the foregoing embodiments can achieve, which will not be repeated here. Regarding the decoding methods in the above embodiments, the specific implementation methods of each step have been described in detail in the relevant decoder embodiments, and will not be elaborated upon here.

[0169] Based on the decoder described above, this disclosure also provides a memory system. The memory system includes a memory and a decoder coupled to the memory. The memory is configured to output read data; the decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

[0170] In some embodiments, the memory system further includes an encoder. The encoder is configured to receive write data and perform encoding operations on the write data; the memory is also configured to receive the encoded write data.

[0171] Based on the decoder described above, this disclosure also provides a memory controller, including:

[0172] The memory interface is configured to receive and read data.

[0173] The decoder is coupled to the memory interface; the decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

[0174] Figure 14 This is a schematic block diagram of a memory system according to an embodiment of the present disclosure. The following will be combined with… Figure 14 The memory system and memory controller provided in the embodiments of this disclosure will be described by way of example.

[0175] Reference Figure 14As shown, the memory system 800 includes a memory controller 810 and a memory 820. The memory controller 810 controls the memory 820 to perform read and write operations. Here, the memory controller 810 and the memory 820 can be coupled in any suitable manner. The memory controller 810 includes a processor (CPU) 813, a cache 815, an error correction circuit 814, a host I / F 811, and a memory I / F 812. In this embodiment, the memory 820 can be a non-volatile semiconductor memory for storing data, such as a NAND flash memory. The memory system 800 is connected to a host. The host I / F 811 outputs commands received from the host, valid data (write data), etc., to the internal bus 816, and sends valid data read from the memory 820 (read data), responses from the processor 813, etc., back to the host.

[0176] The processor 813 can instruct the memory I / F 812 to write valid data, parity data, and parity matrix to the memory 820 according to commands from the host. In addition, the control unit can instruct the memory I / F 812 to read valid data, parity data, and parity matrix from the memory according to commands from the host.

[0177] The error correction circuit 814 here includes an encoder 817 and the decoder 600 described above. The encoder 817 encodes the written valid data of a predetermined size to generate parity check data (e.g., low-density parity check code LDPC) and a corresponding parity check matrix. The parity check data and the corresponding parity check matrix generated by the encoder 817 can be stored in a memory. The decoder 600 uses the parity check data and the corresponding parity check matrix to decode. The decoder 600 here includes a decoder, and the parity check code and the corresponding parity check matrix during decoding can be obtained from the memory.

[0178] Based on the decoder described above, this disclosure also provides a computer-readable storage medium storing instructions that are executed by a processor to implement the decoding method of any of the above embodiments.

[0179] Here, implementing all or part of the decoding methods in the above embodiments can be accomplished by instructing relevant hardware through instructions. These instructions can be stored in a computer-readable storage medium, and when executed, they can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc or a compact disc read-only memory (CD-ROM), etc.; the storage medium can also include combinations of the above types of memory.

[0180] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0181] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0182] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A decoder, characterized in that, The decoder includes a data processing circuit and a data output circuit coupled to the data processing circuit; The data processing circuit is configured as follows: The current check calculation is performed using the current column of the check matrix and the current submatrix of the current flag matrix; wherein the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are associated with the current data block of the flipped codeword; the codeword includes n data blocks, each of which includes k code elements, where k is a positive integer; the current submatrix includes k current flag bits, each of which indicates whether the corresponding code element in the current data block of the codeword has been flipped; The result of the current check calculation is combined with the previous syndrome to perform the current incremental check calculation, generating the current syndrome. The data output circuit is configured as follows: Based on the fact that the current syntactic satisfies the verification condition, the reversed codeword is output.

2. The decoder according to claim 1, characterized in that, The data processing circuit is further configured to: Since the current syndrome does not meet the verification condition, the next verification calculation is performed using the next column of the verification matrix and the next submatrix of the current flag matrix; The result of the next check calculation is combined with the current syndrome to perform the next incremental check calculation, generating the next syndrome. The data output circuit is configured as follows: Based on the next syntactic satisfying the verification condition, the reversed codeword is output.

3. The decoder according to claim 2, characterized in that, The next syndrome is the nth syndrome; the decoder further includes a bit-flipping processing circuit coupled to the data processing circuit, the bit-flipping processing circuit being configured as follows: Since the nth syndrome does not satisfy the verification condition, the codeword is flipped again; Generate the next flag matrix associated with the codeword that has been flipped again.

4. The decoder according to claim 3, characterized in that, The data processing circuit is configured as follows: The codeword is initially checked using the parity-check matrix to generate an initial syndrome. The bit-flipping processing circuit is configured as follows: Since the initial syndrome does not satisfy the verification condition, the codeword is flipped. Generate the first flag matrix associated with the flipped codeword.

5. The decoder according to claim 3 or 4, characterized in that, The bit-flipping processing circuit is specifically configured as follows: The initial flag bits corresponding to the flipped symbols in the initial flag matrix are set to flag logic values ​​to generate the first flag matrix or the next flag matrix.

6. The decoder according to claim 5, characterized in that, The decoding operation of the codeword includes multiple iterative stages; wherein, the flag matrix corresponding to different iterative stages is different.

7. The decoder according to claim 3, characterized in that, The decoder further includes a codeword buffer circuit coupled to the data processing circuit, the codeword buffer circuit being configured as follows: Cache the codeword or flip the codeword.

8. The decoder according to claim 1, characterized in that, The data processing circuit is specifically configured as follows: Calculate the product of the current column of the check matrix and the current submatrix of the current flag matrix to generate the current sub-adjoint expression; Perform an XOR operation on the previous syndrome and the current subsynonym to generate the current syndrome.

9. The decoder according to claim 1, characterized in that, The decoder further includes a judgment circuit coupled to the data processing circuit and the data output circuit respectively, the judgment circuit being configured to: Determine whether the current syndrome satisfies the verification condition.

10. The decoder according to claim 1, characterized in that, The verification condition includes a syndrome of 0.

11. A decoding method, characterized in that, include: The current check calculation is performed using the current column of the check matrix and the current submatrix of the current flag matrix; wherein the check matrix includes n columns, where n is an integer greater than 1; the current flag matrix includes n submatrices, which are associated with the current data block of the flipped codeword; the codeword includes n data blocks, each of which includes k code elements, where k is a positive integer; the current submatrix includes k current flag bits, each of which indicates whether the corresponding code element in the current data block of the codeword has been flipped; The result of the current check calculation is combined with the previous syndrome to perform the current incremental check calculation, generating the current syndrome. Based on the fact that the current syntactic satisfies the verification condition, the reversed codeword is output.

12. The decoding method according to claim 11, characterized in that, The decoding method further includes: Since the current syndrome does not meet the verification condition, the next verification calculation is performed using the next column of the verification matrix and the next submatrix of the current flag matrix; The result of the next check calculation is combined with the current syndrome to perform the next incremental check calculation, generating the next syndrome. Based on the next syntactic satisfying the verification condition, the reversed codeword is output.

13. The decoding method according to claim 12, characterized in that, The next syndrome is the nth syndrome; the decoding method further includes: Since the nth syndrome does not satisfy the verification condition, the codeword is flipped again; Generate the next flag matrix associated with the codeword that has been flipped again.

14. The decoding method according to claim 12, characterized in that, The decoding method further includes: The codeword is initially checked using the parity-check matrix to generate an initial syndrome. Since the initial syndrome does not satisfy the verification condition, the codeword is flipped. Generate the first flag matrix associated with the flipped codeword.

15. The decoding method according to claim 13 or 14, characterized in that, The generation of the first flag matrix or the next flag matrix associated with the flipped codeword includes: The initial flag bits corresponding to the flipped symbols in the initial flag matrix are set to flag logic values ​​to generate the first flag matrix or the next flag matrix.

16. The decoding method according to claim 14, characterized in that, The decoding method further includes: Cache the codeword or flip the codeword.

17. The decoding method according to claim 11, characterized in that, The step of performing the current check calculation using the current column of the check matrix and the current submatrix of the current flag matrix includes: Calculate the product of the current column of the check matrix and the current submatrix of the current flag matrix to generate the current sub-adjoint expression; The step of performing the current incremental check calculation by combining the result of the current check calculation with the previous association includes: Perform an XOR operation on the previous syndrome and the current subsynonym to generate the current syndrome.

18. The decoding method according to claim 11, characterized in that, The decoding method further includes: Determine whether the current syndrome satisfies the verification condition.

19. The decoding method according to claim 11, characterized in that, The verification condition includes a syndrome of 0.

20. A memory system, characterized in that, include: A memory configured to output read data; The decoder as described in any one of claims 1 to 10, wherein the decoder is coupled to the memory; The decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

21. The memory system according to claim 20, characterized in that, The memory system also includes: An encoder configured to receive write data and perform an encoding operation on the write data; The memory is also configured to receive the encoded write data.

22. A memory controller, characterized in that, include: A memory interface configured to receive and read data; The decoder as described in any one of claims 1 to 10, wherein the decoder is coupled to the memory interface; The decoder is configured to perform a decoding operation on the codewords obtained by converting the read data.

23. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that are executed by a processor to implement the decoding method as described in any one of claims 11 to 19.

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