Predicting neural network performance for compiler configuration

Abstract

The invention relates to a neural network performance for predicting compiler configuration. Apparatuses, systems, and techniques are described for predicting performance information for software to be compiled and executed on one or more integrated circuits. In at least one embodiment, one or more neural networks may be used to generate performance information corresponding to one or more integrated circuits based at least in part on configuration parameters for configuring one or more compilers to compile software to be executed by the one or more integrated circuits.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence for various tasks. For example, at least one embodiment relates to a processor or computing system that uses neural network comparisons to perform various tasks. Background Technology

[0002] Artificial intelligence techniques are implemented to accomplish various tasks. For example, the architecture and parameter size of neural networks used to perform different tasks may consume significant amounts of memory, time, or computational resources. Neural networks can be compiled using different configuration parameters, thereby improving the amount of memory, time, or computational resources required to perform different tasks. Attached Figure Description

[0003] Figure 1 A logic block diagram of a software performance prediction system according to at least one embodiment is shown;

[0004] Figure 2 A logic block diagram of a model training system for predicting performance information of one or more neural networks compiled according to compiler configuration parameters, according to at least one embodiment, is shown.

[0005] Figure 3 A logical block diagram of a compiler configuration analysis system according to at least one embodiment is shown;

[0006] Figure 4 A method for predicting software performance on an integrated circuit based on configuration parameters for compiling a neural network, according to at least one embodiment, is illustrated.

[0007] Figure 5 A method for determining the performance of configuration parameters for compiling a neural network to be executed on an integrated circuit, according to at least one embodiment, is illustrated.

[0008] Figure 6A The logic according to at least one embodiment is shown;

[0009] Figure 6B The logic according to at least one embodiment is shown;

[0010] Figure 7 The training and deployment of a neural network according to at least one embodiment are illustrated;

[0011] Figure 8 An example data center system according to at least one embodiment is shown;

[0012] Figure 9A An example of an autonomous vehicle according to at least one embodiment is shown;

[0013] Figure 9BThe illustration shows an embodiment according to at least one of the embodiments. Figure 9A Examples of camera positions and field of view for autonomous vehicles;

[0014] Figure 9C This is an illustration based on at least one embodiment. Figure 9A A block diagram of an example system architecture for an autonomous vehicle;

[0015] Figure 9D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 9A A diagram of a system for communication between autonomous vehicles;

[0016] Figure 10 This is a block diagram illustrating a computer system according to at least one embodiment;

[0017] Figure 11 This is a block diagram illustrating a computer system according to at least one embodiment;

[0018] Figure 12 A computer system according to at least one embodiment is shown;

[0019] Figure 13 A computer system according to at least one embodiment is shown;

[0020] Figure 14A A computer system according to at least one embodiment is shown;

[0021] Figure 14B A computer system according to at least one embodiment is shown;

[0022] Figure 14C A computer system according to at least one embodiment is shown;

[0023] Figure 14D A computer system according to at least one embodiment is shown;

[0024] Figure 14E and Figure 14F A shared programming model according to at least one embodiment is shown;

[0025] Figure 15 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown;

[0026] Figures 16A-16B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0027] Figures 17A-17B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0028] Figure 18 A computer system according to at least one embodiment is shown;

[0029] Figure 19A A parallel processor according to at least one embodiment is shown;

[0030] Figure 19B A partitioning unit according to at least one embodiment is shown;

[0031] Figure 19C A processing cluster according to at least one embodiment is shown;

[0032] Figure 19D A graphics multiprocessor according to at least one embodiment is shown;

[0033] Figure 20 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0034] Figure 21 A graphics processor according to at least one embodiment is shown;

[0035] Figure 22 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0036] Figure 23 A deep learning application processor according to at least one embodiment is shown;

[0037] Figure 24 A block diagram of an example neuromorphic processor is shown according to at least one embodiment;

[0038] Figure 25 At least a portion of a graphics processor is shown according to at least one embodiment;

[0039] Figure 26 At least a portion of a graphics processor according to one or more embodiments is shown;

[0040] Figure 27 At least a portion of a graphics processor according to one or more embodiments is shown;

[0041] Figure 28 It is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0042] Figure 29 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0043] Figures 30A-30B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0044] Figure 31 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0045] Figure 32 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0046] Figure 33 A memory partitioning unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0047] Figure 34 A streaming multiprocessor according to at least one embodiment is illustrated;

[0048] Figure 35 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0049] Figure 36 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment;

[0050] Figure 37 Example illustrations include an advanced computing pipeline 3610A for processing imaging data according to at least one embodiment;

[0051] Figure 38A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment;

[0052] Figure 38B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment;

[0053] Figure 39A A data flow diagram of a process for training a machine learning model according to at least one embodiment is shown;

[0054] Figure 39B This is an example illustration of a client-server architecture for enhancing annotation tools using a pre-trained annotation model, according to at least one embodiment; and

[0055] Figure 40 Components of a system for accessing a large language model according to at least one embodiment are shown. Detailed Implementation

[0056] Figure 1A logical block diagram of a software performance prediction system according to at least one embodiment is shown. In at least one embodiment, software performance can vary considerably depending on the hardware device (e.g., an integrated circuit) executing the software. In at least one embodiment, the software can be compiled to transform, optimize, and / or translate the software's instructions into an executable form. In at least one embodiment, different configuration parameters of the compiler may affect software performance. In at least one embodiment, a large number of hardware devices with different capabilities and configurations, and a large number of possible values ​​and / or configurations of the compiler (e.g., depending on different configuration parameters), may result in a very large number of possible performance scenarios for the software to be compiled. In at least one embodiment, one or more trained neural networks 120 may be implemented as part of a software performance prediction system 110 to generate performance predictions (as described below). Figures 1 to 5 (Discussed in detail), which can determine or otherwise predict the performance information of the software specified in performance prediction request 102.

[0057] In at least one embodiment, the software performance prediction system 110 can be implemented as a standalone tool or as part of a larger deployment or development system, application, or service. In at least one embodiment, performance prediction requests 102 and performance predictions 104 can be received and sent via an interface. In at least one embodiment, the interface of the software performance prediction system 110 may include a command-line interface, a graphical user interface, and / or an application programming interface (API). In at least one embodiment, the software performance prediction system 110 can provide performance predictions 104 to indicate the impact of different configuration parameters on the software execution hardware. In at least one embodiment, the software performance prediction system 110 can perform simulation tests quickly and efficiently, avoiding costly and time-consuming tests required to deterministically search for or evaluate different compiler parameter configurations.

[0058] For example, in at least one embodiment, the trained neural network 120 may include (e.g., in a feature space) mappings and / or interpolations between various integrated circuit capabilities 132, different software applications, systems, or components to be compiled 134, and compiler parameter configurations 136. In at least one embodiment, the software performance prediction system 110 can predict the performance of newly developed software, new integrated circuits, and / or new compiler features without performing actual performance tests. In at least one embodiment, the software performance prediction system 110 can improve software performance by discovering the optimal compiler parameter configuration to achieve desired performance characteristics (e.g., latency, throughput, and / or resource utilization). In at least one embodiment, as described below... Figures 3 to 5As discussed in detail, performance prediction 164 can be included as part of a result set that indicates trade-offs between achieving different performance characteristics (e.g., lower latency or lower throughput, lower latency or lower cost, etc.). In at least one embodiment, the software performance prediction system 110 can generate visualizations or other graphs of different performance characteristics for different compiler parameter configurations. In at least one embodiment, different visualizations, graphs, or other results can significantly reduce software deployment time by providing information for selecting configuration parameters to achieve the desired performance characteristics.

[0059] Figure 2 A logical block diagram of a model training system for predicting performance information of one or more neural networks compiled according to compiler configuration parameters, according to at least one embodiment, is shown. In at least one embodiment, one or more neural networks can be trained to predict the performance of a specific type of software. For example, in at least one embodiment, one or more neural networks can be trained to predict the performance of a specific type of hardware.

[0060] In at least one embodiment, the neural network performance measurement system 210 may be a test bench, kit, tool, application, or service that can access a variety of different hardware devices for executing the neural network, such as execution hardware 214, which may include various machine learning hardware acceleration devices, including but not limited to graphics processing units (GPUs), central processing units (CPUs), and / or tensor processing units (TPUs). In at least one embodiment, execution hardware 214 may provide a variety of different hardware capabilities for executing the compiled neural network, including various raw performance capabilities such as the speed, size, or bandwidth of computing resources (e.g., CPUs, GPUs, interconnects, memory, I / O, and networks). In at least one embodiment, execution hardware configuration 204 may specify which hardware devices 214. In at least one embodiment, execution hardware configuration 204 may specify configurable characteristics of execution hardware 214, such as setting cache size, allocating ports or other communication channels, etc.

[0061] In at least one embodiment, the neural network performance measurement system 210 can acquire or identify different neural networks 202 to measure performance using execution hardware 214 having execution hardware configuration 204 and compiler parameter range 206. In at least one embodiment, the neural network 202 can be trained to perform similar or identical tasks (e.g., natural language processing tasks, computer vision tasks, data analysis tasks) and / or can be implemented using the same or similar architectures (e.g., feedforward neural networks, recurrent neural networks (RNNs), convolutional neural networks (CNNs), generative adversarial networks (GANs), and / or transformer neural networks). In at least one embodiment, the neural network 202 can be heterogeneous in terms of task and / or architecture.

[0062] In at least one embodiment, the neural network performance measurement system 210 may acquire a compiler parameter range 206. In at least one embodiment, the compiler parameter range 206 may include different possible values ​​that can be specified for the neural network. In at least one embodiment, the compiler may transform, translate, prepare, convert, and / or optimize instructions used to execute the neural network 202. In at least one embodiment, the compiler may include an optimizer, such as NVIDIA's TensorRT or TensorRTLLM.

[0063] In at least one embodiment, the neural network performance measurement system 210 can implement a compiler and text 212 that can compile different neural networks 202 using different values ​​outside the compiler parameter range 206 for execution on different hardware configurations 204 on execution hardware 214. In at least one embodiment, test data 208 can be used to test the compiled version of the neural network 202. In at least one embodiment, the test data 208 can include input data of different neural networks 202 with truth labels. In at least one embodiment, the test data 208 can be input to the compiled neural network 202 and performance information (e.g., various performance metrics for measuring different performance attributes, such as inference latency, inference throughput, and / or resource utilization for performing inference).

[0064] In at least one embodiment, performance result 220 may be a data store or other collection of different performance metrics or other measurements captured by different compiled neural networks 202, which are compiled and tested (as indicated by 212) and executed on execution hardware 214. In at least one embodiment, model training system 230 may train one or more neural networks to predict the performance of one or more neural networks based on inputs, which may include neural networks (e.g., neural network 202), execution hardware configuration, capabilities, or other descriptions (e.g., execution hardware configuration 204 and / or compiler parameter range 206). In at least one embodiment, performance result 220 may serve as a ground truth for performing supervised learning techniques to predict performance information. In at least one embodiment, model training system 230 may apply a variety of different training techniques, including but not limited to stochastic gradient descent and backpropagation, and various optimizations for stochastic gradient descent, Adagrad, Adam, AdaDelta, and RMSProp. In at least one embodiment, the model training system 230 can train individual models or individual models to predict different performance attributes given an input neural network, hardware configuration or other capabilities, and compiler configuration parameters, such that model A predicts performance attribute A, model B predicts performance attribute B, and model C predicts performance attribute C. In at least one embodiment, the trained neural network 240 can be a single model trained to predict multiple different performance attributes given an input neural network, hardware configuration or other capabilities, and compiler configuration parameters, such that model A predicts performance attributes A, B, and C. In at least one embodiment, the trained neural network 240 can be included in simulation, analysis, or other tools to predict performance information for different neural networks compiled with different configuration parameters to execute on different hardware configurations (e.g., compiler configuration analysis 310).

[0065] Figure 3A logical block diagram of a compiler configuration analysis system according to at least one embodiment is shown. In at least one embodiment, the compiler configuration analysis system 310 may be a standalone system or implemented as part of a large application, such as a tool for developing or deploying neural networks on a host system. In at least one embodiment, the compiler configuration analysis system 310 may implement an interface, such as a command-line interface, a graphical user interface, or one or more APIs that can be used to submit various requests and return various responses. In at least one embodiment, a request 302 for neural network performance may be received via the interface of the compiler configuration analysis system 310. In at least one embodiment, the neural network performance request 302 may specify one or more features for predicting performance. In at least one embodiment, the features of the request 302 may include one or more neural networks to be compiled. In at least one embodiment, one or more neural networks may be specified in the request 302 based on a model name or other identifier, which may allow the compiler configuration analysis system 310 to retrieve the neural networks identified in the request 302. In at least one embodiment, one or more neural networks may be specified in request 302 based on characteristics or features (e.g., number of layers (and layer type, such as hidden layers), neural network type (e.g., feedforward neural network, RNN, CNN, GAN and / or transformer neural network), and / or various components (or subcomponents) of the neural network, various types of gates, encoders, decoders, self-attention or other attention mechanisms, sparse or dense connections, filters, generators, discriminators, transformers and / or masks, etc.).

[0066] In at least one embodiment, request 302 may include one or more execution hardware capabilities of one or more integrated circuits, for which neural networks will be compiled and predict performance information. In at least one embodiment, the execution hardware capabilities may be provided by tools, agents, or other applications installed on a host system to allow the integrated circuits to capture execution hardware capabilities. In at least one embodiment, tools, agents, or other applications installed on the host system may read the capability information of the integrated circuits, test, probe, or otherwise discover the actual or potential hardware capabilities of one or more integrated circuits, and then report or specify these hardware capabilities. In at least one embodiment, execution hardware capabilities may be specified via command line or user interface by selecting one or more hardware devices as or including the integrated circuits (e.g., selecting a device via a menu or other prompt). In at least one embodiment, hardware capabilities may be described as various raw performance capabilities such as the speed, size, or bandwidth of computing resources (e.g., CPU, GPU, interconnect, memory, I / O, and network, etc.) and / or configurable aspects of the hardware (e.g., setting cache size, allocating ports or other communication channels, etc.). In at least one embodiment, hardware capabilities may include device architecture (e.g., the number of processor cores and the connectivity between processor cores).

[0067] In at least one embodiment, a compiler may be specified as part of request 302. In at least one embodiment, a compiler may be specified based on a name and / or version identifier. In at least one embodiment, a prompt or other menu may specify an available compiler (or compiler version). In at least one embodiment, examples of a compiler may include an optimizer, such as NVIDIA's TensorRT or TensorRT LLM. In at least some embodiments, a range of different configuration parameter values ​​to be considered and used for prediction may be specified in request 302. In at least some embodiments, examples of compiler configuration parameters may include various parameters that may indicate how the compiled neural network is executed on an integrated circuit. In at least one embodiment, examples of configuration parameters (which may include flags or other various mechanisms for specifying configuration parameter values, which may accept multiple different values) may include, but are not limited to, the following:

[0068] Low / high precision data types

[0069] Strongly typed or weakly typed

[0070] Quantitative analysis

[0071] Tensor data format

[0072] • Dynamic input shape

[0073] Deep learning acceleration

[0074] • Polygraphy (deep learning model debugger)

[0075] • Parallelism type (e.g., tensor parallelism or pipeline parallelism)

[0076] • Data execution (e.g., how to partition or chunk data during forward propagation)

[0077] In at least one embodiment, the compiler configuration analysis system 310 can implement compiler configuration search execution 320. In at least one embodiment, compiler configuration search execution 320 can implement different search strategies to select different combinations of compiler parameter configurations specified in the compiler parameter range in request 302. In at least one embodiment, a deterministic search technique can be implemented by the compiler configuration search execution, which can iteratively search through a subset or all possible ranges of compiler parameter configurations specified in request 302. In at least one embodiment, reinforcement learning techniques can use alternative models to represent a set of optimal configuration parameters (which can be determined based on a performance target specified as part of request 302 (although not shown)). In at least one embodiment, for each configuration under consideration, compiler configuration search execution 320 can generate inputs, such as a compiler configuration combining hardware configuration and neural network 322 (as can be determined based on the neural network and execution hardware capabilities specified in request 302), and apply a trained neural network 330 to generate a performance prediction 324. In at least one embodiment, performance prediction 324 can include one or more performance attributes. In at least one embodiment, performance prediction 324 can include, but is not limited to, performance attributes (not shown) selected or specified in request 302. In at least one embodiment, a set of default or predefined performance attributes may be provided as performance predictions 324. In at least one embodiment, the trained neural network 330 may be a single model (according to the above regarding...). Figure 2 (The techniques discussed are used for training). In at least one embodiment, the trained neural network 330 may be multiple different models predicting different performance attributes.

[0078] In at least one embodiment, compiler configuration search execution 320 may provide performance predictions and compiler configuration pairs 326 to result generation 340. In at least one embodiment, result generation 340 may prepare, format, or otherwise generate result 304 for return via an interface of compiler configuration analysis system 310. In at least one embodiment, result generation 340 may apply filters or rankings to the performance predictions, thereby limiting the compiler configuration parameter and performance pairs in result 304 to a subset of predicted performance. In at least one embodiment, result generation 340 may generate visualizations of result 304. For example, in at least one embodiment, a graph such as a Pareto front may be generated to illustrate the trade-offs between different performance attributes (e.g., latency and throughput) and the corresponding different compiler configurations providing those attributes.

[0079] Figure 4 A method for predicting software performance on an integrated circuit based on configuration parameters for compiling a neural network, according to at least one embodiment, is illustrated. In at least one embodiment, regarding... Figure 4 The described techniques can be implemented as part of tools, analyzers, services, development systems, deployment systems, or other applications that can be used to configure software compilation. In at least one embodiment, one or more integrated circuits and the software to be executed by the integrated circuits, as indicated at step 410, can be identified. In at least one embodiment, integrated circuits can be identified based on interfaces of tools, analyzers, services, development systems, deployment systems, or other applications that can be used to configure software compilation. For example, in at least one embodiment, integrated circuits can be identified by tools, agents, or other software components installed on a system hosting one or more integrated circuits, capable of reading capability information, testing, probing, or otherwise discovering the actual or potential hardware capabilities of one or more integrated circuits, and then via tools, analyzers, services, development systems, deployment systems, or implementations regarding... Figure 4 Other applications of the discussed technology may have interfaces that report or specify these hardware capabilities. In at least one embodiment, the interface for identifying the integrated circuit may be implemented as a command-line interface, a graphical user interface, and / or one or more APIs, which include requests for predicting the performance of software compiled and executed on the integrated circuit. In at least one embodiment, the integrated circuit may be described or specified based on corresponding hardware capabilities, which may include, but are not limited to, various raw performance capabilities such as the speed, size, or bandwidth of computing resources (e.g., CPU, GPU, interconnect, memory, I / O, and networking, etc.) and / or configurable aspects of the hardware (e.g., setting cache size, allocating ports or other communication channels, etc.).

[0080] In at least one embodiment, the tool, analyzer, service, development system, deployment system, or implementation regarding... Figure 4 The interfaces of other applications of the discussed techniques are used to identify the software to be executed. In at least one embodiment, the software may be provided as one or more code files or other instruction sets for identification. In at least one embodiment, the software may be described using one or more features or characteristics (e.g., tasks, architectures, stages, components, or various aspects of performing one or more tasks). In at least one embodiment, the software may include one or more neural networks implementing machine learning models. In at least one embodiment, various types of software for performing different types of data processing tasks (e.g., data stream processing, data encoding, data decoding, transaction processing, or event processing, etc.) can be identified.

[0081] In at least one embodiment, one or more neural networks can be used to generate performance information corresponding to the integrated circuit, at least in part, based on configuration parameters used to configure the compiler to compile software to be executed by the integrated circuit, as indicated at step 420. In at least one embodiment, it can be based on the above regarding Figure 1 and / or Figure 2 The techniques discussed use, for example, performance information captured by different software programs to train one or more neural networks, which configure and execute the hardware capabilities of an integrated circuit using different compiler parameters. In at least one embodiment, one or more features of the software and one or more features of the integrated circuit may be included in the input of the neural network trained to generate performance information. In at least one embodiment, one or more compiler configurations (e.g., in addition to the features of the integrated circuit and the software) for compiling the software to execute on the integrated circuit may also be included as input. In at least one embodiment, the input may be encoded as a single input vector that concatenates the features of the integrated circuit hardware capabilities with the software features and configuration parameters as parameters. In at least one embodiment, one or more neural networks may be trained to generate multiple performance attributes included in the performance information, including the throughput of the software in completing tasks (e.g., X tasks per unit time), latency (e.g., Y time required to complete a task), and / or resource utilization (e.g., processor utilization Z, memory utilization W, and / or I / O utilization V). In at least one embodiment, different neural networks can be trained to predict different performance attributes, which can be ensembled to generate performance information (e.g., neural network A for latency, neural network B for throughput, etc.). In at least one embodiment, execution can be repeated for different configuration parameters. Figure 4The techniques illustrated are used to plot or search a performance attribute space in one or more dimensions, thereby providing indications of different combinations of performance attributes that can be achieved with different configuration parameter values ​​of the compiler. In at least one embodiment, different visualization techniques or interface styles can be implemented to present performance information of software compiled using configuration parameters for execution on an integrated circuit.

[0082] Figure 5 A method for determining the performance of configuration parameters for compiling a neural network for execution on an integrated circuit, according to at least one embodiment, is illustrated. In at least some embodiments, according to the above description... Figure 1 and Figure 4 The techniques discussed, and the software for which their predictive performance can be considered, may be one or more neural networks. In at least one embodiment, to specify one or more neural networks, one or more code files, scripts, or other instructions specifying or describing the architecture of one or more neural networks may be used. In at least one embodiment, one or more neural networks may be trained to perform various artificial intelligence tasks, including computer vision tasks, natural language processing, audio processing, or various other types of data processing, forecasting, or prediction tasks. In at least one embodiment, one or more neural networks may be implemented as a Large Language Model (LLM), which may be specified according to code, scripts, or other instructions including various neural network-based components. In at least one embodiment, weight values ​​or other parameters may be included in or accessed by the software specifying one or more neural networks (e.g., one or more weight / parameter files for executing one or more neural networks specified in one or more code files).

[0083] For example, in at least one embodiment, a converter-based LLM may include one or more of the following components that can be specified:

[0084] • Input embeddings divide input (e.g., text) into one or more tokens, which can be converted into embeddings (e.g., vectors).

[0085] • Location encoding, which adds more location information about encoded inputs (such as tags).

[0086] • An encoder analyzes the input text and creates hidden states that capture the context and meaning of the input (e.g., text).

[0087] The self-attention mechanism weights the importance of different labels in the input sequence by calculating attention scores.

[0088] a feedforward neural network, which can be applied independently to each label, includes fully connected layers with non-linear activation functions.

[0089] • The decoder performs autoregressive generation by attending to previously generated tags.

[0090] Multi-head attention, which is performed using different learned attention weights, is used to capture different types of relationships and simultaneously focus on different parts of the input sequence.

[0091] • Layer normalization, which can be applied after components or layers, stabilizes the learning process and improves the ability to generalize across different inputs.

[0092] • The output layer, which can vary depending on the task, for example using linear projection followed by SoftMax activation, generates the probability distribution for the next label.

[0093] In at least one embodiment, regarding Figure 5 The described techniques can be implemented as part of tools, analyzers, services, development systems, deployment systems, or other applications that can be used to configure the compilation of software (e.g., one or more neural networks) based at least in part on determined performance of configuration parameters used to compile neural networks for execution on integrated circuits. In at least one embodiment, a command-line interface, a graphical user interface, or an API can be used to invoke or initiate the techniques for determining the performance of configuration parameters used to compile neural networks for execution on integrated circuits.

[0094] In at least one embodiment, the hardware capability of the integrated circuit to execute a neural network can be identified, as indicated at step 510. In at least one embodiment, the hardware capability can be specified or input via an interface to a tool, analyzer, service, development system, deployment system, or other application. In at least one embodiment, the hardware capability can be acquired by a tool, agent, or other software component installed on a system hosting one or more integrated circuits, which is capable of reading capability information, testing, probing, or otherwise discovering the actual or potential hardware capabilities of one or more integrated circuits, and then transmitting this information via an analyzer, service, development system, deployment system, or implementation. Figure 5 Other applications of the technologies discussed herein report or specify these hardware capabilities through their interfaces. In at least one embodiment, the hardware capabilities may be similar to those described above. Figure 1 and Figure 5 The hardware capabilities discussed may include the speed, size, or bandwidth of computing resources (e.g., CPU, GPU, interconnect, memory, I / O, and network) and / or various raw performance capabilities of hardware configurable aspects (e.g., setting cache size, allocating ports or other communication channels).

[0095] In at least one embodiment, a neural network to be executed can be identified, as indicated at step 520. In at least one embodiment, one or more neural networks can be identified by a description of one or more aspects of the neural network (e.g., hidden size, vocabulary size, and number of layers, etc.) received via an interface of a tool, analyzer, service, development system, deployment system, or other application. In at least one embodiment, one or more neural networks can be identified by one or more code files, data files, and / or other instructions specifying the submission of one or more neural networks via an interface of a tool, analyzer, service, development system, deployment system, or other application (e.g., as part of a request to analyze one or more neural networks for different potential configuration settings). In at least one embodiment, one or more neural networks can be identified based on a suggested set of different neural networks that can be selected for analysis (e.g., by accessing a model repository or other data store listing different neural networks that can be compiled and executed).

[0096] In at least one embodiment, the trained neural network can be used to predict the performance of different corresponding configurations of configuration parameters used to compile the neural network for execution on an integrated circuit with the identified hardware capabilities, as indicated at step 530. In at least one embodiment, the trained neural network can be configured according to the above description regarding... Figure 2 The discussed technique is trained to capture the performance of different neural networks compiled with different compiler parameters for different integrated circuits with different hardware capabilities, thereby predicting the performance of the neural network on integrated circuits with different configuration parameters. In at least one embodiment, a range (or a specific set) of compiler configuration parameters can be specified in the request to obtain performance predictions. In at least one embodiment, tools, analyzers, services, development systems, deployment systems, or other applications can determine a range (or a specific set) of compiler configuration parameters used for performance prediction (e.g., based on search techniques that explore the search space of configuration parameters). In at least one embodiment, the trained neural network can take an embedding or feature vector as input, which concatenates or otherwise includes the hardware capabilities of the integrated circuit, the neural network, and the compiler configuration parameters, and generate inference predicting the performance of one or more performance attributes (e.g., latency, throughput, and resource utilization).

[0097] In at least one embodiment, predicted performance for different corresponding configurations of the configuration parameters can be provided, as indicated at step 540. In at least one embodiment, visualizations, such as Pareto fronts or graphs illustrating the trade-offs between different parameter configurations and performance properties (e.g., as shown in the image), can be generated. Figure 3Other graphics (as shown). In at least one embodiment, the values ​​of the configuration parameters may be provided for display in text or other human-readable format (e.g., as part of the interface of the development tool). In at least one embodiment, the values ​​of the configuration parameters may be automatically included in the code file or in other compilation requests that use the values ​​of the configuration parameters to compile the neural network. In at least one embodiment, the values ​​may be repeated. Figure 5 The techniques shown are used to add or update visualizations or results provided (as indicated at step 540) to include more possible configurations of the configuration parameters and predicted performance.

[0098] logic

[0099] Figure 6A Logic 615, according to at least one embodiment, as described elsewhere herein, can be used in one or more devices to perform operations such as those discussed herein. In at least one embodiment, logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 615 is inference and / or training logic. Details regarding logic 615 will be incorporated herein by reference. Figure 6A and / or Figure 6B Provided. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic for providing the functionality or operation described herein, wherein the logic may be collectively or individually embodied as circuitry forming part of a larger system (e.g., an integrated circuit (IC), a system-on-a-chip (SoC), or one or more processors (e.g., a CPU, a GPU)).

[0100] In at least one embodiment, logic 615 may include, but is not limited to, code and / or data storage 601 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, logic 615 may include or be coupled to code and / or data storage 601 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 601 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters using aspects of one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 601 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0101] In at least one embodiment, any portion of the code and / or data storage 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 601 may be a cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 601 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0102] In at least one embodiment, logic 615 may include, but is not limited to, code and / or data storage 605 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, code and / or data storage 605 stores weight parameters and / or input / output data for each layer of the neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, logic 615 may include or be coupled to code and / or data storage 605 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, an arithmetic logic unit (ALU)).

[0103] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 605 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 605 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0104] In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be separate storage structures. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be the same storage structure. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 601 and code and / or data storage 605 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0105] In at least one embodiment, logic 615 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 610 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on training and / or inference code (e.g., graph code) or as instructed thereto, the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 620, which are functions of input / output and / or weight parameter data stored in code and / or data storage 601 and / or code and / or data storage 605. In at least one embodiment, activations stored in activation storage 620 are generated based on linear algebra and / or matrix-based mathematics performed by ALU 610 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data storage 605 and / or code and / or data storage 601 are used as operands, and other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, may be stored in code and / or data storage 605 or code and / or data storage 601 or other on-chip or off-chip storage.

[0106] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 610, while in another embodiment, one or more ALUs 610 may be external to the processor or other hardware logic device or the circuitry that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 610 may be included within an execution unit of a processor, or otherwise included in an ALU bank accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 601, code and / or data storage 605, and activation storage 620 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 620 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0107] In at least one embodiment, the active memory 620 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 620 may be entirely or partially located within or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 620 is internal to or external to the processor, for example, or including DRAM, SRAM, flash memory, or certain other memory types, may depend on the available on-chip versus off-chip memory, the latency requirements for performing training and / or inference functions, the batch size of the data used in inference and / or training the neural network, or some combination of these factors.

[0108] In at least one embodiment, Figure 6A The logic 615 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM The inference processing unit (IPU) or from Intel. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6A The logic 615 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”)

[0109] Figure 6B A logic 615 according to at least one embodiment is illustrated. In at least one embodiment, logic 615 is inference and / or training logic. In at least one embodiment, logic 615 may include, but is not limited to, hardware logic, wherein computational resources, along with weight values ​​or other information corresponding to one or more layers of neurons within a neural network, are used dedicatedly or otherwise exclusively. In at least one embodiment, Figure 6B The logic 615 shown can be used in conjunction with application-specific integrated circuits (ASICs), such as those from Google. Processing unit, from Graphcore TM The inference processing unit (IPU) or from Intel. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6BThe logic 615 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, logic 615 includes, but is not limited to, code and / or data storage 601 and code and / or data storage 605, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 6B In at least one embodiment shown, each of code and / or data storage 601 and code and / or data storage 605 is associated with dedicated computing resources (e.g., computing hardware 602 and computing hardware 606). In at least one embodiment, each of computing hardware 602 and computing hardware 606 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on the information stored in code and / or data storage 601 and code and / or data storage 605, respectively, with the results stored in active storage 620.

[0110] In at least one embodiment, each of the code and / or data storage 601 and 605 and the corresponding computing hardware 602 and 606 corresponds to a different layer of the neural network, such that an activation obtained from one storage / computation pair 601 / 602 of the code and / or data storage 601 and computing hardware 602 is provided as input to the next storage / computation pair 605 / 606 of the code and / or data storage 605 and computing hardware 606, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 601 / 602 and 605 / 606 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) may be included in logic 615 after or in parallel with the storage / computation pairs 601 / 602 and 605 / 606.

[0111] Neural network training and deployment

[0112] Figure 7Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 706 is trained using a training dataset 702. In at least one embodiment, the training framework 704 is the PyTorch framework, while in other embodiments, the training framework 704 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 704 trains the untrained neural network 706 and allows it to be trained using the processing resources described herein to generate a trained neural network 708. In at least one embodiment, weights may be selected randomly or through pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0113] In at least one embodiment, supervised learning is used to train an untrained neural network 706, wherein the training dataset 702 includes inputs paired with desired outputs for input, or wherein the training dataset 702 includes inputs with known outputs and the outputs of the neural network 706 are manually graded. In at least one embodiment, the untrained neural network 706 is trained in a supervised manner and processes inputs from the training dataset 702, comparing the resulting outputs with a set of expected or desired outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 706. In at least one embodiment, a training framework 704 adjusts the weights controlling the untrained neural network 706. In at least one embodiment, the training framework 704 includes tools for monitoring the degree to which the untrained neural network 706 converges to a model (such as a trained neural network 708) suitable for generating correct answers (such as results 714) based on input data (such as a new dataset 712). In at least one embodiment, the training framework 704 repeatedly trains the untrained neural network 706 while adjusting the weights to refine the output of the untrained neural network 706 using a loss function and tuning algorithms such as stochastic gradient descent. In at least one embodiment, the training framework 704 trains the untrained neural network 706 until the untrained neural network 706 reaches the desired accuracy. In at least one embodiment, the trained neural network 708 can then be deployed to implement any number of machine learning operations.

[0114] In at least one embodiment, unsupervised learning is used to train an untrained neural network 706, wherein the untrained neural network 706 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 702 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 706 can learn groupings within the training dataset 702 and can determine how each input relates to the untrained dataset 702. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 708, which is capable of performing operations useful for reducing the dimensionality of a new dataset 712. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 712 that deviate from the normal patterns of the new dataset 712.

[0115] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 702. In at least one embodiment, the training framework 704 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 708 to adapt to a new dataset 712 without forgetting the knowledge injected into the trained neural network 708 during initial training.

[0116] In at least one embodiment, the training framework 704 is a framework processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is, for example, a toolkit developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes or uses logic 615 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0117] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations, such as human visual simulation, speech recognition, natural language processing, recommender systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0118] In at least one embodiment, OpenVINO supports neural network models for a variety of tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0119] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes the neural network model for execution on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's input (e.g., adjusting the size of the model's input), modifying the size of the model's input (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalizing, standardizing, quantizing (e.g., converting the model's weights from a first representation such as floating-point to a second representation such as integer), and / or variants thereof.

[0120] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to infer input data. In at least one embodiment, the inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0121] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computational processes and / or systems utilizing one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or portions of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., executing a first set of layers on a first device (e.g., a GPU) and a second set of layers on a second device (e.g., a CPU)).

[0122] In at least one embodiment, OpenVINO includes various functionalities similar to those associated with CUDA programming models, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0123] Data Center

[0124] Figure 8 An exemplary data center 800 in which at least one embodiment can be used is shown. In at least one embodiment, the data center 800 includes a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

[0125] In at least one embodiment, such as Figure 8As shown, the data center infrastructure layer 810 may include a resource coordinator 812, grouped computing resources 814, and node computing resources (“nodes CR”) 816(1)-816(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 816(1)-816(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 818(1)-818(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 816(1)-816(N) may be servers having one or more of the aforementioned computing resources.

[0126] In at least one embodiment, the grouped computing resources 814 may include individual groups of node CRs housed within one or more racks (not shown), or a plurality of racks housed within data centers (also not shown) in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resources 814 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0127] In at least one embodiment, resource coordinator 812 may be configured or otherwise control one or more nodes CR816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource coordinator 812 may include a Software Design Infrastructure (“SDI”) management entity for data center 800. In at least one embodiment, resource coordinator 812 may include hardware, software, or some combination thereof.

[0128] In at least one embodiment, such as Figure 8As shown, framework layer 820 includes a job scheduler 822, a configuration manager 824, a resource manager 826, and a distributed file system 828. In at least one embodiment, framework layer 820 may include a framework of software 832 supporting software layer 830 and / or one or more applications 842 supporting application layer 840. In at least one embodiment, software 832 or application 842 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 820 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark, which can leverage distributed file system 828 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 822 may include a Spark driver for facilitating the scheduling of workloads supported by various layers of the data center 800. In at least one embodiment, the configuration manager 824 may be able to configure different layers, such as the software layer 830 and the framework layer 820, which includes Spark and a distributed file system 828 for supporting large-scale data processing. In at least one embodiment, the resource manager 826 may be able to manage clustered or grouped computing resources mapped to or allocated to support the distributed file system 828 and the job scheduler 822. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 814 at the data center infrastructure layer 810. In at least one embodiment, the resource manager 826 may coordinate with the resource coordinator 812 to manage these mapped or allocated computing resources.

[0129] In at least one embodiment, the software 832 included in the software layer 830 may include software used by at least portions of nodes CR816(1)-816(N), grouped computing resources 814, and / or the distributed file system 828 of the framework layer 820. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0130] In at least one embodiment, one or more applications 842 included in application layer 840 may include one or more types of applications used by at least portions of nodes CR816(1)-816(N), grouped computing resources 814, and / or the distributed file system 828 of framework layer 820. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0131] In at least one embodiment, any of the configuration manager 824, resource manager 826, and resource coordinator 812 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 800 and can prevent underutilization and / or poor performance of the data center.

[0132] In at least one embodiment, data center 800 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 800. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 800 by using weight parameters calculated through one or more training techniques described herein.

[0133] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0134] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6BDetails regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in data center 800 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0135] In at least one embodiment, Figure 6A , Figure 6B , Figure 7 and / or Figure 8 At least one of the embodiments may include or cause one or more processors, circuits, or systems, according to the above regarding Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0136] Autonomous vehicles

[0137] Figure 9A An example of an autonomous vehicle 900 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 900 (which may alternatively be referred to herein as "vehicle 900") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle accommodating one or more passengers. In at least one embodiment, vehicle 900 may be a semi-tractor-trailer truck for hauling goods. In at least one embodiment, vehicle 900 may be an aircraft, robotic vehicle, or other type of vehicle.

[0138] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of that standard). In at least one embodiment, vehicle 900 may be able to have one or more functions according to levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 900 may be able to have conditional automation (level 3), high automation (level 4), and / or full automation (level 5), depending on the embodiment.

[0139] In at least one embodiment, vehicle 900 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 900 may include, but is not limited to, propulsion system 950, such as an internal combustion engine, a hybrid powertrain, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 950 may be connected to the drivetrain of vehicle 900, which may include, but is not limited to, a transmission, for enabling propulsion of vehicle 900. In at least one embodiment, propulsion system 950 may be controlled in response to receiving a signal from throttle / accelerator 952.

[0140] In at least one embodiment, when the propulsion system 950 is operating (e.g., when the vehicle 900 is in motion), the steering system 954 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 900 (e.g., along a desired path or route). In at least one embodiment, the steering system 954 may receive signals from the steering actuator 956. In at least one embodiment, for fully automated (Level 5) functionality, the steering wheel may be optional. In at least one embodiment, the brake sensor system 946 may be used to operate the vehicle brakes in response to signals received from the brake actuator 948 and / or brake sensors.

[0141] In at least one embodiment, one or more controllers 936 may include, but are not limited to, one or more systems-on-a-chip (“SoC”). Figure 9A A controller 936 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 900. For example, in at least one embodiment, one or more controllers 936 may send signals to operate vehicle braking via brake actuator 948, to operate steering system 954 via one or more steering actuators 956, and to operate propulsion system 950 via one or more throttle / accelerator 952. In at least one embodiment, one or more controllers 936 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 900. In at least one embodiment, one or more controllers 936 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0142] In at least one embodiment, one or more controllers 936 provide signals for controlling one or more components and / or systems of vehicle 900 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from, for example, but not limited to, the following sensors: one or more Global Navigation Satellite System (“GNSS”) sensors 958 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 960, one or more ultrasonic sensors 962, one or more LIDAR sensors 964, one or more inertial measurement unit (IMU) sensors 966 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 996, one or more stereo cameras 968, one or more wide-angle cameras 970 (e.g., fisheye cameras), one or more infrared cameras 972, one or more surround cameras 974 (e.g., 360-degree cameras), remote cameras ( Figure 9A (not shown in the image), medium-range camera ( Figure 9A (not shown), one or more speed sensors 944 (e.g., for measuring the speed of vehicle 900), one or more vibration sensors 942, one or more steering sensors 940, one or more brake sensors (e.g., as part of brake sensor system 946) and / or other sensor types.

[0143] In at least one embodiment, one or more controllers 936 may receive input (e.g., represented by input data) from the instrument panel 932 of the vehicle 900 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 934, a voice signaler, a speaker, and / or via other components of the vehicle 900. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 9A The HMI display 934 may display information such as location data (e.g., the location of vehicle 900, for example, on a map), direction, the location of other vehicles (e.g., occupying a grid), information about objects, and the state of objects perceived by one or more controllers 936. For example, in at least one embodiment, the HMI display 934 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers that have been, are being, or will be made (e.g., changing lanes now, reaching exit 34B within two miles, etc.).

[0144] In at least one embodiment, vehicle 900 further includes a network interface 924 that can communicate via one or more networks using one or more wireless antennas 926 and / or one or more modems. For example, in at least one embodiment, network interface 924 may be able to communicate via Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 926 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0145] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in vehicle 900 for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0146] In at least one embodiment, Figure 9A Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0147] Figure 9B The illustration shows an embodiment according to at least one of the embodiments. Figure 9A Examples of camera positions and fields of view for an autonomous vehicle 900. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 900.

[0148] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 900. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-to-clear-to-clear (“RCCC”) color filter array, a red-to-clear-to-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with an array of RCCC, RCCB and / or RBGC color filters, may be used to improve photosensitivity.

[0149] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0150] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (3D-printed) assembly, to remove stray light and reflected light from within the vehicle 900 (e.g., reflected light from the dashboard reflected in the windshield mirror), which may interfere with the camera's image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated into four pillars at each corner of the cabin.

[0151] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including portions of the environment in front of the vehicle 900 can be used for surround view to help identify the path and obstacles ahead, and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path, with the help of one or more controllers 936 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions such as traffic sign recognition.

[0152] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor”) color imager. In at least one embodiment, a wide-angle camera 970 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 9B Only one wide-angle camera 970 is shown, but in other embodiments, the vehicle 900 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 998 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 998 can also be used for object detection and classification, as well as basic object tracking.

[0153] In at least one embodiment, any number of stereo cameras 968 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 968 may include an integrated control unit comprising a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of the environment of the vehicle 900, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 968 may include, but are not limited to, a compact stereo vision sensor that may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 900 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 968 may be used in addition to or instead of those described herein.

[0154] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including portions of the environment on the sides of the vehicle 900 can be used for surround view, providing information for creating and updating an occupied grid, and generating a side-impact collision warning. For example, in at least one embodiment, a surround camera 974 (e.g., such as...) Figure 9B The four surround cameras shown can be positioned on the vehicle 900. In at least one embodiment, one or more surround cameras 974 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of the vehicle 900. In at least one embodiment, the vehicle 900 can use three surround cameras 974 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., forward-facing cameras) as a fourth surround-view camera.

[0155] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including portions of the environment behind the vehicle 900 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras also suitable as one or more forward-facing cameras (e.g., long-range camera 998 and / or one or more mid-range cameras 976, one or more stereo cameras 968, one or more infrared cameras 972, etc.), as described herein.

[0156] In at least one embodiment, Figure 9B Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0157] Figure 9C This illustrates at least one embodiment. Figure 9A A block diagram of an exemplary system architecture for an autonomous vehicle 900. In at least one embodiment, Figure 9CEach component, feature, and system of vehicle 900 is shown as connected via bus 902. In at least one embodiment, bus 902 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 900 used to assist in the control of various features and functions of vehicle 900, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 902 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 902 can be read to locate steering wheel angle, ground speed, engine rotation speed (“RPM”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 902 may be an ASIL B compliant CAN bus.

[0158] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or in place of CAN. In at least one embodiment, any number of buses forming bus 902 may be present, including but not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 902 may communicate with any component of vehicle 900, and two or more buses in bus 902 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chip (“SoC”) 904 (e.g., SoC 904(A) and SoC 904(B)), each of one or more controllers 936, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 900) and may be connected to a common bus, such as a CAN bus.

[0159] In at least one embodiment, vehicle 900 may include one or more controllers 936, such as those described herein. Figure 9A As described above. In at least one embodiment, controller 936 can be used for a wide variety of functions. In at least one embodiment, controller 936 can be coupled to any of various other components and systems of vehicle 900 and can be used to control vehicle 900, artificial intelligence of vehicle 900, infotainment and / or other functions of vehicle 900.

[0160] In at least one embodiment, vehicle 900 may include any number of SoCs 904. In at least one embodiment, each of the SoCs 904 may include, but is not limited to, a central processing unit (“one or more CPUs”) 906, a graphics processing unit (“one or more GPUs”) 908, one or more processors 910, one or more caches 912, one or more accelerators 914, one or more data storage 916, and / or other components and features not shown. In at least one embodiment, one or more SoCs 904 can be used to control vehicle 900 on a wide variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 904 may be combined with a high-definition (“HD”) map 922 in a system (e.g., the system of vehicle 900), which can be accessed via a network interface 924 from one or more servers (…). Figure 9C (Not shown in the image) Get map refresh and / or update.

[0161] In at least one embodiment, one or more CPU 906s may comprise a CPU cluster or CPU complex (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPU 906s may comprise multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPU 906s may comprise eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPU 906s may comprise four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2 megabytes (MB) L2 cache). In at least one embodiment, one or more CPU 906s (e.g., CCPLEX) may be configured to support simultaneous cluster operation, which allows any combination of clusters of one or more CPU 906s to be active at any given time.

[0162] In at least one embodiment, one or more CPUs 906 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware blocks to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; power gating of each core independently; clock gating of each core cluster independently when all cores are clock-gated or power-gated; and / or power gating of each core cluster independently when all cores are power-gated. In at least one embodiment, one or more CPUs 906 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state to input for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein the work is offloaded to the microcode.

[0163] In at least one embodiment, one or more GPUs 908 may include an integrated GPU (which may alternatively be referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 908 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 908 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 908 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 908 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 908 may use one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 908 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0164] In at least one embodiment, one or more GPU 908s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPU 908s may be fabricated on a FinFET (“FinFET”) circuit. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a scheduler (e.g., a thread bundle scheduler), or a sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for employing a mixture of computation and addressing operations to provide efficient execution of workloads. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0165] In at least one embodiment, one or more GPUs 908 may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem, used in some examples to provide a peak memory bandwidth of approximately 900GB / s. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”), such as fifth-generation graphics double data rate type synchronous random access memory (“GDDR5”), may also be used.

[0166] In at least one embodiment, one or more GPUs 908 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 908 to directly access the page tables of one or more CPUs 906. In at least one embodiment, when the memory management unit (“MMU”) of one or more GPUs 908 experiences a miss, an address translation request can be sent to one or more CPUs 906. In response, in at least one embodiment, two CPUs of one or more CPUs 906 can look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 908. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 906 and one or more GPUs 908, thereby simplifying the programming of one or more GPUs 908 and porting applications to one or more GPUs 908.

[0167] In at least one embodiment, one or more GPUs 908 may include any number of access counters that can track the frequency with which one or more GPUs 908 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of sharing memory ranges among processors.

[0168] In at least one embodiment, one or more SoCs 904 may include any number of caches 912, including those described herein. For example, in at least one embodiment, one or more caches 912 may include a Level 3 (“L3”) cache that can be used for both one or more CPUs 906 and one or more GPUs 908 (e.g., connected to one or more CPUs 906 and one or more GPUs 908). In at least one embodiment, one or more caches 912 may include a write-back cache that can track the state of each row, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, depending on the embodiment, the L3 cache may include 4 MB of memory or more.

[0169] In at least one embodiment, one or more SoCs 904 may include one or more accelerators 914 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 904 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 908 and offload some tasks from one or more GPUs 908 (e.g., to free up more cycles from one or more GPUs 908 to perform other tasks). In at least one embodiment, one or more accelerators 914 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0170] In at least one embodiment, one or more accelerators 914 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, and post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, rapidly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for protection and / or safety-related events.

[0171] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 908, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 908 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 908 and / or one or more accelerators 914.

[0172] In at least one embodiment, one or more accelerators 914 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, a PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 938, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, a PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0173] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, depending on the embodiment, the RISC core may use any of a variety of protocols. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0174] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPU 906s. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0175] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly perform programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0176] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Therefore, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general computer vision algorithms, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or different portions of an image. In at least one embodiment, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory for enhancing overall system security.

[0177] In at least one embodiment, one or more accelerators 914 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 914. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0178] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0179] In at least one embodiment, one or more SoCs 904 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to rapidly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0180] In at least one embodiment, one or more accelerators 914 may have broad applications for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 900, PVA may be designed to run classical computer vision algorithms, as they can be efficient in object detection and integer mathematical operations.

[0181] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure reconstruction from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0182] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, for example, the PVA is used to perform time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0183] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks, whose output is a measurement of confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence values. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 966 related to vehicle 900 orientation, distance, and object 3D position estimates obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 964 or one or more RADAR sensors 960).

[0184] In at least one embodiment, one or more SoCs 904 may include one or more data stores 916 (e.g., memory). In at least one embodiment, one or more data stores 916 may be on-chip memory of one or more SoCs 904, which may store neural networks to be executed on one or more GPUs 908 and / or DLAs. In at least one embodiment, one or more data stores 916 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data stores 916 may include one or more L2 or L3 caches.

[0185] In at least one embodiment, one or more SoCs 904 may include any number of processors 910 (e.g., embedded processors). In at least one embodiment, one or more processors 910 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security execution. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 904 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 904s, and / or power state management of one or more SoCs 904s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 904s may use the ring oscillator to detect the temperature of one or more CPUs 906s, one or more GPUs 908s, and / or one or more accelerators 914s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 904s into a lower power state and / or place the vehicle 900 into a driver safe parking mode (e.g., bring the vehicle 900 to a safe stop).

[0186] In at least one embodiment, one or more processors 910 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor having dedicated RAM.

[0187] In at least one embodiment, one or more processors 910 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, support for peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0188] In at least one embodiment, one or more processors 910 may further include a secure cluster engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 910 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 910 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0189] In at least one embodiment, one or more processors 910 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video playback applications to generate the final image for video post-processing functions required by the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 970, one or more surround cameras 974, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 904, the neural network being configured to recognize in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0190] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion in the video, denoising appropriately weights spatial information to reduce the weight of information provided by adjacent frames. In at least one embodiment, in the case where the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0191] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereoscopic shot frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 908 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 908 are powered and active for 3D rendering, the video image compositor can be used to offload one or more GPUs 908 to improve performance and responsiveness.

[0192] In at least one embodiment, one or more SoCs of SoC 904 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 904 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0193] In at least one embodiment, one or more SoCs 904 may further include extensive peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs 904 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 964, one or more RADAR sensors 960, etc., which may be connected via Ethernet channels), data from bus 902 (e.g., vehicle 900 speed, steering wheel position, etc.), data from one or more GNSS sensors 958 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs 904 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to free one or more CPUs 906 from routine data management tasks.

[0194] In at least one embodiment, one or more SoCs 904 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for a flexible, reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 904 can be faster, more reliable, and even more energy- and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 914, when combined with one or more CPUs 906, one or more GPUs 908, and one or more data storage 916, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0195] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0196] The embodiments described herein allow for the simultaneous and / or sequential execution of multiple neural networks and allow for the combination of results to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPU 920s) may include text and word recognition, thereby allowing the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of signs, and passing this semantic understanding to a path planning module running on a CPU complex.

[0197] In at least one embodiment, multiple neural networks can run simultaneously for driving levels 3, 4, or 5. For example, in at least one embodiment, a warning sign stating "Caution: flashing lights indicate icy conditions," along with the lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which informs the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within a DLA and / or on one or more GPUs 908.

[0198] In at least one embodiment, the CNN for face recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 900. In at least one embodiment, a normally open sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in safe mode, it can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 904 provide protection against theft and / or carjacking.

[0199] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 996 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 904 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, such as those identified by one or more GNSS sensors 958. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 962, to execute emergency vehicle safety routines, such as slowing the vehicle, pulling the vehicle to the side of the road, stopping, and / or idling the vehicle until the emergency vehicle passes.

[0200] In at least one embodiment, vehicle 900 may include one or more CPUs 918 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 904 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 918 may include, for example, an x86 processor. One or more CPUs 918 may be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 904, and / or monitoring the status and health of one or more controllers 936 and / or the on-chip infotainment system (“infotainment SoC”) 930. In at least one embodiment, one or more SoCs 904 include one or more interconnects, and the interconnects may include peripheral component interconnects fast (PCIe).

[0201] In at least one embodiment, the vehicle 900 may include one or more GPUs 920 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to one or more SoCs 904 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, the one or more GPUs 920 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of the vehicle 900 (e.g., sensor data).

[0202] In at least one embodiment, vehicle 900 may further include a network interface 924, which may include, but is not limited to, one or more wireless antennas 926 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 924 may be used to enable wireless connectivity to Internet cloud services (e.g., with servers and / or other network devices), with other vehicles, and / or with computing devices (e.g., passenger client devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 900 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 900 with information about vehicles near vehicle 900 (e.g., vehicles in front, to the side, and / or behind vehicle 900). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 900.

[0203] In at least one embodiment, network interface 924 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 936 to communicate over a wireless network. In at least one embodiment, network interface 924 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0204] In at least one embodiment, the vehicle 900 may further include one or more data storage 928, which may include, but is not limited to, off-chip (e.g., one or more off-chip SoC 904) storage. In at least one embodiment, the one or more data storage 928 may include, but is not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0205] In at least one embodiment, the vehicle 900 may further include one or more GNSS sensors 958 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 958 may be used, including, for example, but not limited to, GPS sensors using a USB connector with an Ethernet-to-serial interface (e.g., RS-232) bridge.

[0206] In at least one embodiment, vehicle 900 may further include one or more RADAR sensors 960. In at least one embodiment, one or more RADAR sensors 960 may be used by vehicle 900 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 960 may use a CAN bus and / or bus 902 (e.g., for transmitting data generated by one or more RADAR sensors 960) to control and access object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more RADAR sensors 960 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the RADAR sensors 960 are pulse Doppler RADAR sensors.

[0207] In at least one embodiment, one or more RADAR sensors 960 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 960 can help distinguish between static and moving objects and can be used by the ADAS system 938 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 960 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, employing six antennas, the four central antennas can create a focused beammap designed to record the environment surrounding the vehicle 900 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling them to quickly detect vehicles entering or leaving the lane of vehicle 900.

[0208] In at least one embodiment, as an example, a mid-range RADAR system may include a range of up to 160m (front) or 80m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 960 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 938 for blind spot detection and / or lane change assistance.

[0209] In at least one embodiment, the vehicle 900 may further include one or more ultrasonic sensors 962. In at least one embodiment, one or more ultrasonic sensors 962, which may be positioned at the front, rear, and / or sides of the vehicle 900, may be used for parking assistance and / or creating and updating occupancy grids. In at least one embodiment, a wide variety of ultrasonic sensors 962 may be used, and different ultrasonic sensors 962 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 962 may operate at the ASIL B functional safety level.

[0210] In at least one embodiment, vehicle 900 may include one or more LiDAR sensors 964. In at least one embodiment, one or more LiDAR sensors 964 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LiDAR sensors 964 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 900 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 964 that can use Ethernet channels (e.g., to provide data to a Gigabit Ethernet switch).

[0211] In at least one embodiment, one or more LiDAR sensors 964 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 964 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such embodiments, one or more LiDAR sensors 964 may include small devices that can be embedded in the front, rear, side, and / or corner locations of a vehicle 900. In at least one embodiment, one or more LiDAR sensors 964, in such embodiments, may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-mounted LiDAR sensors 964 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0212] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the area around vehicle 900 up to approximately 200m. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the propagation time of the laser pulse and the reflected light on each pixel, which in turn corresponds to the range from vehicle 900 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of vehicle 900. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0213] In at least one embodiment, the vehicle 900 may further include one or more IMU sensors 966. In at least one embodiment, the one or more IMU sensors 966 may be located at the center of the rear axle of the vehicle 900. In at least one embodiment, the one or more IMU sensors 966 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, the one or more IMU sensors 966 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, the one or more IMU sensors 966 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0214] In at least one embodiment, one or more IMU sensors 966 can be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 966 enable vehicle 900 to estimate its heading by directly observing and correlating velocity changes from GPS to one or more IMU sensors 966, without requiring input from magnetic sensors. In at least one embodiment, one or more IMU sensors 966 and one or more GNSS sensors 958 can be combined in a single integrated unit.

[0215] In at least one embodiment, vehicle 900 may include one or more microphones 996 placed inside and / or around vehicle 900. In at least one embodiment, one or more microphones 996 may be used for emergency vehicle detection and identification.

[0216] In at least one embodiment, vehicle 900 may further include any number of camera types, including one or more stereo cameras 968, one or more wide-angle cameras 970, one or more infrared cameras 972, one or more surround cameras 974, one or more long-range cameras 998, one or more mid-range cameras 976, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 900. In at least one embodiment, the type of camera used depends on vehicle 900. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 900. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 900 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, by way of example but not limited to, gigabit multimedia serial link (“GMSL”) and / or gigabit Ethernet communication. In at least one embodiment, previously referenced herein... Figure 9A and Figure 9B Each camera is described in more detail.

[0217] In at least one embodiment, the vehicle 900 may further include one or more vibration sensors 942. In at least one embodiment, the one or more vibration sensors 942 may measure vibrations of components of the vehicle 900 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 942 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0218] In at least one embodiment, vehicle 900 may include ADAS system 938. In at least one embodiment, ADAS system 938 may include, but is not limited to, SoC in some examples. In at least one embodiment, ADAS system 938 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) system, cooperative adaptive cruise control (“CACC”) system, forward collision warning (“FCW”) system, automatic emergency braking (“AEB”) system, lane departure warning (“LDW”) system, lane keeping assist (“LKA”) system, blind spot warning (“BSW”) system, rear cross traffic warning (“RCTW”) system, collision warning (“CW”) system, lane centering (“LC”) system and / or other systems, features and / or functions.

[0219] In at least one embodiment, the ACC system may use one or more RADAR sensors 960, one or more LIDAR sensors 964, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 900 and automatically adjusts the speed of vehicle 900 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 900 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0220] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via a wireless link or through a network connection (e.g., via the Internet) via network interface 924 and / or one or more wireless antennas 926. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately ahead (e.g., a vehicle immediately in front of vehicle 900 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 900, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0221] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 960, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual, haptic, and / or rapid braking pulses.

[0222] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply braking if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system can automatically apply braking to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or collision proximity braking.

[0223] In at least one embodiment, when vehicle 900 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is not activated when the driver indicates intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 900 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 900.

[0224] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of the car. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses turn signals. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback such as a display, speaker, and / or vibration components.

[0225] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when the vehicle 900 detects an object outside the range of the rear camera while reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0226] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, vehicle 900 decides for itself whether to follow the result of the main computer or auxiliary computer (e.g., a first or second controller in controller 936). For example, in at least one embodiment, ADAS system 938 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, output from ADAS system 938 may be provided to a supervisory MCU. In at least one embodiment, if output from the main computer and output from the auxiliary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0227] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU, indicating the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0228] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU may learn when the FCW system is recognizing a metallic object that is not actually dangerous, such as a drain grille or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 904s.

[0229] In at least one embodiment, the ADAS system 938 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and the not-quite-same software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can have greater confidence that the overall results are correct, and the vulnerability in the software or hardware on the host computer will not lead to a major error.

[0230] In at least one embodiment, the output of the ADAS system 938 can be fed into the perception block and / or the dynamic driving task block of the main computer. For example, in at least one embodiment, if the ADAS system 938 indicates a forward collision warning due to an object directly ahead, the perception block can use the information when the object is identified. In at least one embodiment, as described herein, the assistance computer can have its own neural network, which is trained to reduce the risk of false alarms.

[0231] In at least one embodiment, vehicle 900 may further include an infotainment SoC 930 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 930 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 930 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 900. For example, the infotainment SoC 930 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 934, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 930 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 900, such as information from ADAS system 938, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0232] In at least one embodiment, the infotainment SoC 930 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 930 may communicate with other devices, systems, and / or components of the vehicle 900 via bus 902. In at least one embodiment, the infotainment SoC 930 may be coupled to a supervisory MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of one or more main controllers 936 (e.g., the main computer and / or backup computer of the vehicle 900). In at least one embodiment, the infotainment SoC 930 may place the vehicle 900 into a driver-to-safe parking mode, as described herein.

[0233] In at least one embodiment, vehicle 900 may further include instrument panel 932 (e.g., digital instrument panel, electronic instrument panel, digital instrument cluster, etc.). In at least one embodiment, instrument panel 932 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 932 may include, but is not limited to, any number and combination of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 930 and instrument panel 932. In at least one embodiment, instrument panel 932 may be included as part of infotainment SoC 930, or vice versa.

[0234] In at least one embodiment, Figure 9C Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0235] Figure 9D It is based on at least one embodiment in one or more cloud-based servers and Figure 9AA diagram of a system for communication between autonomous vehicles 900. In at least one embodiment, the system may include, but is not limited to, one or more servers 978, one or more networks 990, and any number and type of vehicles, including vehicle 900. In at least one embodiment, one or more servers 978 may include, but is not limited to, multiple GPUs 984(A)-984(H) (collectively referred to herein as GPU 984), PCIe switches 982(A)-982(D) (collectively referred to herein as PCIe switch 982), and / or CPUs 980(A)-980(B) (collectively referred to herein as CPU 980). In at least one embodiment, GPU 984, CPU 980, and PCIe switch 982 may be interconnected with high-speed interconnects, such as, for example, but not limited to, NVLink interface 988 and / or PCIe connection 986 developed by NVIDIA. In at least one embodiment, GPU 984 is connected via NVLink and / or NVSwitch SoC, and GPU 984 and PCIe switch 982 are connected via PCIe interconnect. Although eight GPUs 984, two CPUs 980, and four PCIe switches 982 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 978 may include, but is not limited to, any number of GPUs 984, CPUs 980, and / or PCIe switches 982 in any combination. For example, in at least one embodiment, one or more servers 978 may each include eight, sixteen, thirty-two, and / or more GPUs 984.

[0236] In at least one embodiment, one or more servers 978 may receive image data representing an image from a vehicle via one or more networks 990, the image showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, one or more servers 978 may send updated neural network 992 and / or map information 994 to the vehicle via one or more networks 990, including but not limited to information about traffic and road conditions. In at least one embodiment, updates to map information 994 may include, but are not limited to, updates to HD map 922, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 992 and / or map information 994 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed at a data center (e.g., using one or more servers 978 and / or other servers).

[0237] In at least one embodiment, one or more servers 978 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 990, and / or the machine learning model may be used by one or more servers 978 to remotely monitor the vehicle).

[0238] In at least one embodiment, one or more servers 978 may receive data from the vehicle and apply the data to a state-of-the-art real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 978 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 984, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 978 may include a deep learning infrastructure in a data center powered by a CPU.

[0239] In at least one embodiment, the deep learning infrastructure of one or more servers 978 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in the vehicle 900. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 900, such as image sequences and / or objects located by the vehicle 900 in the image sequences (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by the vehicle 900, and if the results do not match and the deep learning infrastructure determines that the AI ​​in the vehicle 900 is malfunctioning, one or more servers 978 may send a signal to the vehicle 900 instructing the vehicle 900's fail-safe computer to take control, notify passengers, and complete a safe stopping operation.

[0240] In at least one embodiment, one or more servers 978 may include one or more GPUs 984 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, servers driven by CPUs, FPGAs, and other processors may be used for inference, such as in situations where performance is less critical. In at least one embodiment, one or more hardware structures 615 are used to execute one or more embodiments. This document incorporates... Figure 6A and / or Figure 6B Provide details about the hardware architecture of 615.

[0241] In at least one embodiment, Figure 9D Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0242] Computer System

[0243] Figure 10 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit for executing instructions. In at least one embodiment, according to this disclosure, such as in the embodiments described herein, computer system 1000 may include, but is not limited to, components such as processor 1002 for employing execution units (including logic) to execute algorithms for process data. In at least one embodiment, computer system 1000 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TMThe microprocessor can be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors can also be used. In at least one embodiment, the computer system 1000 can execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0244] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0245] In at least one embodiment, the computer system 1000 may include, but is not limited to, a processor 1002, which may include, but is not limited to, one or more execution units 1008 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 1000 is a single-processor desktop or server system, but in another embodiment, the computer system 1000 may be a multiprocessor system. In at least one embodiment, the processor 1002 may include, but is not limited to, for example, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 1002 may be coupled to a processor bus 1010, which can transmit data signals between the processor 1002 and other components in the computer system 1000.

[0246] In at least one embodiment, processor 1002 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to processor 1002. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 1006 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0247] In at least one embodiment, an execution unit 1008, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1002. In at least one embodiment, the processor 1002 may also include a microcode (“ucode”) read-only memory (“ROM”) storing microcode for certain macro instructions. In at least one embodiment, the execution unit 1008 may include logic for processing a packaged instruction set 1009. In at least one embodiment, by including the packaged instruction set 1009 in the instruction set of the general-purpose processor and the associated circuitry to be executed, operations used by numerous multimedia applications can be performed using packaged data in the processor 1002. In at least one embodiment, numerous multimedia applications can be accelerated and executed more efficiently by performing operations on packaged data using the full width of the processor's data bus, eliminating the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0248] In at least one embodiment, the execution unit 1008 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1000 may include, but is not limited to, memory 1020. In at least one embodiment, memory 1020 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1020 may store one or more instructions 1019 and / or data 1021 represented by data signals executable by processor 1002.

[0249] In at least one embodiment, the system logic chip may be coupled to processor bus 1010 and memory 1020. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1016, and processor 1002 may communicate with MCH 1016 via processor bus 1010. In at least one embodiment, MCH 1016 may provide a high-bandwidth memory path 1018 to memory 1020 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1016 may direct data signals between processor 1002, memory 1020, and other components in computer system 1000, and bridge data signals between processor bus 1010, memory 1020, and system I / O interface 1022. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1016 can be coupled to memory 1020 via high-bandwidth memory path 1018, and graphics / video card 1012 can be coupled to MCH 1016 via Accelerated Graphics Port (“AGP”) interconnect 1014.

[0250] In at least one embodiment, the computer system 1000 may use the system I / O interface 1022 as a proprietary hub interface bus to couple the MCH 1016 to the I / O controller hub (“ICH”) 1030. In at least one embodiment, the ICH 1030 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1020, chipset, and processor 1002. Examples may include, but are not limited to, an audio controller 1029, a firmware hub (“flash BIOS”) 1028, a wireless transceiver 1026, a data storage 1024, a conventional I / O controller 1023 including a user input and keyboard interface 1025, a serial expansion port 1027 (such as a Universal Serial Bus (“USB”) port), and a network controller 1034. In at least one embodiment, the data storage 1024 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0251] In at least one embodiment, Figure 10 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 10 An exemplary SoC can be shown. In at least one embodiment, Figure 10The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1000 are interconnected using a Computational Fast Link (CXL) interconnect.

[0252] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in computer system 1000 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0253] In at least one embodiment, Figure 10 Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0254] Figure 11 This is a block diagram illustrating an electronic device 1100 for utilizing processor 1110 according to at least one embodiment. In at least one embodiment, electronic device 1100 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0255] In at least one embodiment, the electronic device 1100 may, but is not limited to, a processor 1110 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1110 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 11 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 11 An exemplary SoC can be shown. In at least one embodiment, Figure 11The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 11 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0256] In at least one embodiment, Figure 11 It may include a display 1124, a touch screen 1125, a touchpad 1130, a near field communication unit (“NFC”) 1145, a sensor hub 1140, a thermal sensor 1146, a fast chipset (“EC”) 1135, a trusted platform module (“TPM”) 1138, a BIOS / firmware / flash (“BIOS, FW Flash”) 1122, a DSP 1160, a drive 1120 (such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1150, a Bluetooth unit 1152, a wireless wide area network unit (“WWAN”) 1156, a global positioning system (GPS) unit 1155, a camera (“USB 3.0 camera”) 1154 (such as a USB 3.0 camera) and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1115 implemented in, for example, the LPDDR3 standard. These components can each be implemented in any suitable way.

[0257] In at least one embodiment, other components may be communicatively coupled to processor 1110 via the components described herein. In at least one embodiment, accelerometer 1141, ambient light sensor (“ALS”) 1142, compass 1143, and gyroscope 1144 may be communicatively coupled to sensor hub 1140. In at least one embodiment, thermal sensor 1139, fan 1137, keyboard 1136, and touchpad 1130 may be communicatively coupled to EC 1135. In at least one embodiment, speaker 1163, earphone 1164, and microphone (“mic”) 1165 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1162, which in turn may be communicatively coupled to DSP 1160. In at least one embodiment, audio unit 1162 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1157 may be communicatively coupled to WWAN unit 1156. In at least one embodiment, components such as WLAN unit 1150, Bluetooth unit 1152, and WWAN unit 1156 may be implemented as next-generation form factors (“NGFF”).

[0258] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in electronic device 1100 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0259] In at least one embodiment, Figure 11 Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0260] Figure 12 A computer system 1200 according to at least one embodiment is shown. In at least one embodiment, the computer system 1200 is configured to implement various processes and methods described throughout this disclosure.

[0261] In at least one embodiment, the computer system 1200 includes, but is not limited to, at least one central processing unit (“CPU”) 1202 connected to a communication bus 1210 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1200 includes, but is not limited to, main memory 1204 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in the main memory 1204, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1222 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using the computer system 1200.

[0262] In at least one embodiment, the computer system 1200 includes, but is not limited to, an input device 1208, a parallel processing system 1212, and a display device 1206, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1208 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may reside on a single semiconductor platform to form the processing system.

[0263] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in computer system 1200 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0264] In at least one embodiment, Figure 12 Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0265] Figure 13 A computer system 1300 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1300 includes, but is not limited to, a computer 1310 and a USB flash drive 1320. In at least one embodiment, the computer 1310 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1310 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0266] In at least one embodiment, the USB flash drive 1320 includes, but is not limited to, a processing unit 1330, a USB interface 1340, and USB interface logic 1350. In at least one embodiment, the processing unit 1330 can be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1330 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1330 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1330 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1330 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0267] In at least one embodiment, the USB interface 1340 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1340 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1340 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1350 may include any amount and type of logic enabling the processing unit 1330 to interface with a device (e.g., computer 1310) via the USB connector 1340.

[0268] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in computer system 1300 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0269] In at least one embodiment, Figure 13 Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0270] Figure 14A An exemplary architecture is illustrated in which multiple GPUs 1410(1)-1410(N) are communicatively coupled to multiple multi-core processors 1405(1)-1405(M) via high-speed links 1440(1)-1440(N) (e.g., bus, point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1440(1)-1440(N) support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 1410(1)-1410(N) include, Figure 17A and Figure 17BThe disclosed one or more graphics cores (also simply referred to as "cores") 1700. In at least one embodiment, one or more graphics cores 1700 may be referred to as streaming multiprocessors ("SM"), streaming processors ("SP"), streaming processing units ("SPU"), compute units ("CU"), execution units ("EU"), and / or slices, wherein a slice in this context may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread bootstrap, or a scheduler).

[0271] Furthermore, in at least one embodiment, two or more GPUs 1410 are interconnected via high-speed links 1429(1)-1429(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1440(1)-1440(N). Similarly, two or more multi-core processors 1405 can be connected via a high-speed link 1428, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 14A This shows all communication between the various system components.

[0272] In at least one embodiment, each multi-core processor 1405 is communicatively coupled to processor memories 1401(1)-1401(M) via memory interconnects 1426(1)-1426(M), and each GPU 1410(1)-1410(N) is communicatively coupled to GPU memories 1420(1)-1420(N) via GPU memory interconnects 1450(1)-1450(N). In at least one embodiment, memory interconnects 1426 and 1450 may utilize similar or different memory access technologies. By way of example and not limitation, processor memories 1401(1)-1401(M) and GPU memories 1420 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In at least one embodiment, some portions of the processor memory 1401 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0273] As described herein, although the individual multi-core processors 1405 and GPUs 1410 can be physically coupled to specific memories 1401 and 1420 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the individual physical memories. For example, processor memories 1401(1)–1401(M) can each include 64 GB of system memory address space, and GPU memories 1420(1)–1420(N) can each include 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M = 2 and N = 4. Other values ​​for N and M are possible.

[0274] Figure 14B Additional details are shown regarding the interconnection between a multi-core processor 1407 and a graphics acceleration module 1446 according to one exemplary embodiment. In at least one embodiment, the graphics acceleration module 1446 may include one or more GPU chips integrated on a line card coupled to the processor 1407 via a high-speed link 1440 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1446 may alternatively be integrated on a package or chip having the processor 1407.

[0275] In at least one embodiment, the processor 1407 includes a plurality of cores 1460A-1460D (which may be referred to as “execution units”), each core having a translation back cover buffer (“TLB”) 1461A-1461D and one or more caches 1462A-1462D. In at least one embodiment, the cores 1460A-1460D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1462A-1462D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 1456 may be included in the caches 1462A-1462D and shared by the respective groups of cores 1460A-1460D. For example, one embodiment of the processor 1407 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1407 and the graphics acceleration module 1446 are connected to the system memory 1414, which may include... Figure 14A The processor memory 1401(1)-1401(M) is included.

[0276] In at least one embodiment, consistency of data and instructions stored in the various caches 1462A-1462D, 1456 and system memory 1414 is maintained via inter-core communication through the consistency bus 1464. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1464 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1464 to snoop on cache accesses.

[0277] In at least one embodiment, proxy circuitry 1425 communicatively couples graphics acceleration module 1446 to coherence bus 1464, thereby allowing graphics acceleration module 1446 to participate in cache coherence protocols as a peer of cores 1460A-1460D. Specifically, in at least one embodiment, interface 1435 provides connectivity to proxy circuitry 1425 via high-speed link 1440, and interface 1437 connects graphics acceleration module 1446 to high-speed link 1440.

[0278] In at least one embodiment, the accelerator integrated circuit 1436 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1431(1)-1431(N) of the graphics acceleration module 1446. In at least one embodiment, each of the graphics processing engines 1431(1)-1431(N) may include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1431(1)-1431(N) of the graphics acceleration module 1446 includes one or more graphics cores 1700, such as in combination Figure 17A and Figure 17B The discussion continues. In at least one embodiment, the graphics processing engines 1431(1)-1431(N) may alternatively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit (block transport) engines. In at least one embodiment, the graphics acceleration module 1446 may be a GPU having multiple graphics processing engines 1431(1)-1431(N), or the graphics processing engines 1431(1)-1431(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0279] In at least one embodiment, the accelerator integrated circuit 1436 includes a memory management unit (MMU) 1439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1414. In at least one embodiment, the MMU 1439 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1438 may store commands and data for efficient access by graphics processing engines 1431(1)-1431(N). In at least one embodiment, a fetch unit 1444 may be used to keep data stored in cache 1438 and graphics memory 1433(1)-1433(M) consistent with core caches 1462A-1462D, 1456 and system memory 1414. As previously stated, this can represent cache 1438 and memory 1433(1)-1433(M) being implemented via proxy circuit 1425 (e.g., sending updates related to the modification / access of cache lines on processor caches 1462A-1462D, 1456 to cache 1438 and receiving updates from cache 1438).

[0280] In at least one embodiment, a set of registers 1445 stores context data of threads executed by graphics processing engines 1431(1)-1431(N), and context management circuitry 1448 manages the thread context. For example, context management circuitry 1448 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1448 can store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1447 receives and processes interrupts received from system devices.

[0281] In at least one embodiment, MMU 1439 translates virtual / effective addresses from graphics processing engine 1431 into real / physical addresses in system memory 1414. In at least one embodiment, accelerator integrated circuit 1436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1446 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1446 may be dedicated to a single application executing on processor 1407, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1431(1)-1431(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0282] In at least one embodiment, the accelerator integrated circuit 1436 acts as a bridge to the system of the graphics acceleration module 1446 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1436 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1431(1)-1431(N).

[0283] In at least one embodiment, since the hardware resources of the graphics processing engines 1431(1)-1431(N) are explicitly mapped to the real address space seen by the host processor 1407, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1436 is the physical separation of the graphics processing engines 1431(1)-1431(N), making them appear as independent units to the system.

[0284] In at least one embodiment, one or more graphics memories 1433(1)-1433(M) are coupled to each graphics processing engine 1431(1)-1431(N), where N = M. In at least one embodiment, the graphics memories 1433(1)-1433(M) store instructions and data being processed by each graphics processing engine 1431(1)-1431(N). In at least one embodiment, the graphics memories 1433(1)-1433(M) may be volatile memories, such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0285] In at least one embodiment, to reduce data traffic on the high-speed link 1440, a biasing technique can be used to ensure that the data stored in the graphics memory 1433(1)-1433(M) is the data most frequently used by the graphics processing engine 1431(1)-1431(N), and preferably data that is not used (or at least not frequently used) by the cores 1460A-1460D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by the graphics processing engine 1431(1)-1431(N)) in the caches 1462A-1462D, 1456 and system memory 1414.

[0286] Figure 14C Another exemplary embodiment is shown, wherein the accelerator integrated circuit 1436 is integrated within the processor 1407. In this embodiment, the graphics processing engines 1431(1)-1431(N) communicate directly with the accelerator integrated circuit 1436 via a high-speed link 1440 through interfaces 1437 and 1435 (again, which can be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1436 can perform operations related to... Figure 14B The described operation is similar, but due to its close proximity to the coherence bus 1464 and caches 1462A-1462D, 1456, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1436 and a programming model controlled by the graphics acceleration module 1446.

[0287] In at least one embodiment, graphics processing engines 1431(1)-1431(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1431(1)-1431(N), thereby providing virtualization within a VM / partition.

[0288] In at least one embodiment, graphics processing engines 1431(1)-1431(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1431(1)-1431(N) to allow access by each operating system. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1431(1)-1431(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1431(1)-1431(N) to provide access to each process or application.

[0289] In at least one embodiment, the graphics acceleration module 1446 or the individual graphics processing engine 1431(1)-1431(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1414 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1431(1)-1431(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0290] Figure 14D An exemplary accelerator integration slice 1490 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1436. In at least one embodiment, the application is an effective address space 1482 in system memory 1414, which stores process element 1483. In at least one embodiment, process element 1483 is stored in response to a GPU call 1481 from an application 1480 executing on processor 1407. In at least one embodiment, process element 1483 includes the process state of the corresponding application 1480. In at least one embodiment, a job descriptor (WD) 1484 included in process element 1483 may be a single job requested by the application, or may include a pointer to a job queue. In at least one embodiment, WD 1484 is a pointer to a job request queue in the effective address space 1482 of the application.

[0291] In at least one embodiment, the graphics acceleration module 1446 and / or the respective graphics processing engines 1431(1)-1431(N) may be shared by all processes or subsets of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1484 to the graphics acceleration module 1446 to begin operations in a virtualized environment.

[0292] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1446 or an individual graphics processing engine 1431. In at least one embodiment, when the graphics acceleration module 1446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1436 for the owned partition; when the graphics acceleration module 1446 is assigned, the operating system initializes the accelerator integrated circuit 1436 for the owned process.

[0293] In at least one embodiment, during operation, the WD acquisition unit 1491 in the accelerator integration slice 1490 acquires the next WD 1484, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1446. In at least one embodiment, data from the WD 1484 may be stored in register 1445 and used by MMU 1439, interrupt management circuitry 1447, and / or context management circuitry 1448, as shown. For example, one embodiment of MMU 1439 includes segment / page walk circuitry for accessing segment / page tables 1486 within the OS virtual address space 1485. In at least one embodiment, interrupt management circuitry 1447 may process interrupt events 1492 received from the graphics acceleration module 1446. In at least one embodiment, when performing graphics operations, a valid address 1493 generated by graphics processing engines 1431(1)-1431(N) is translated into a real address by MMU 1439.

[0294] In at least one embodiment, register 1445 is copied for each graphics processing engine 1431(1)-1431(N) and / or graphics acceleration module 1446, and register 1445 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1490. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0295] Table 1 - Registers initialized by the management program

[0296]

[0297] Table 2 shows exemplary registers that can be initialized by the operating system.

[0298] Table 2 - Registers for Operating System Initialization

[0299]

[0300] In at least one embodiment, each WD 1484 is specific to a particular graphics acceleration module 1446 and / or graphics processing engine 1431(1)-1431(N). In at least one embodiment, it includes all the information required for the graphics processing engine 1431(1)-1431(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0301] Figure 14E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1498, in which a list of process elements 1499 is stored. In at least one embodiment, the hypervisor real address space 1498 can be accessed via a hypervisor 1496, which virtualizes the graphics acceleration module engine for operating system 1495.

[0302] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1446. In at least one embodiment, there are two programming models in which the graphics acceleration module 1446 is shared by multiple processes and partitions, namely time-slice sharing and graphics-oriented sharing.

[0303] In at least one embodiment, in this model, the hypervisor 1496 owns the graphics acceleration module 1446 and makes its functionality available to all operating systems 1495. In at least one embodiment, for the graphics acceleration module 1446 to support virtualization through the hypervisor 1496, the graphics acceleration module 1446 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1446 must provide a context saving and recovery mechanism, (2) the graphics acceleration module 1446 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1446 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, the fairness of the graphics acceleration module 1446 among processes must be ensured.

[0304] In at least one embodiment, application 1480 needs to make a system call to operating system 1495 using the graphics acceleration module type, working descriptor (WD), permission mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1446 and can take the form of graphics acceleration module 1446 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1446.

[0305] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1436 (not shown) and the graphics acceleration module 1446 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1496 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1483. In at least one embodiment, CSRP is one of the registers 1445 that includes the effective address of a region in the application's effective address space 1482 for the graphics acceleration module 1446 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0306] Upon receiving a system call, the operating system 1495 can verify that the application 1480 has been registered and granted permission to use the graphics acceleration module 1446. Then, in at least one embodiment, the operating system 1495 uses the information shown in Table 3 to invoke the hypervisor 1496.

[0307] Table 3 - Operating System to Hypervisor Call Parameters

[0308]

[0309] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1496 verifies that the operating system 1495 has been registered and granted permission to use the graphics acceleration module 1446. Then, in at least one embodiment, the hypervisor 1496 adds the process element 1483 to a linked list of process elements of the corresponding graphics acceleration module 1446 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0310] Table 4 - Process Element Information

[0311]

[0312]

[0313] In at least one embodiment, the hypervisor initializes multiple accelerator integration slice 1490 registers 1445.

[0314] like Figure 14F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1401(1)-1401(N) and GPU memories 1420(1)-1420(N). In this implementation, operations performed on GPUs 1410(1)-1410(N) utilize the same virtual / effective memory address space to access processor memories 1401(1)-1401(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1401(1), a second portion to second processor memory 1401(N), a third portion to GPU memory 1420(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1401 and GPU memories 1420, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0315] In at least one embodiment, the bias / coherence management circuitry 1494A-1494E within one or more MMUs 1439A-1439E ensures cache coherence between one or more host processors (e.g., 1405) and the cache of the GPU 1410, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 14FSeveral instances of bias / coherence management circuitry 1494A-1494E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 1405 and / or within the accelerator integrated circuit 1436.

[0316] One embodiment allows GPU memory 1420 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability of GPU memory 1420 to be accessed as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1405 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1420 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1410. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation can play a role in determining the effectiveness of GPU offloading.

[0317] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising 1 or 2 bits of memory pages attached per GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1410, the bias table can be implemented over one or more stolen memory ranges of GPU memory 1420. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0318] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1420 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1410 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1420. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to processor 1405 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1405 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request for a page pointing to the GPU bias can be forwarded to GPU 1410. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed by a software-based mechanism, a hardware-assisted software mechanism, or, in a limited set of cases, by a purely hardware-based mechanism.

[0319] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn invokes the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrating from the host processor 1405 bias to the GPU bias, but not for the reverse migration.

[0320] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1405 cannot cache. In at least one embodiment, to access these pages, the processor 1405 may request access from the GPU 1410, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1405 and the GPU 1410, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU rather than those needed by the host processor 1405, and vice versa.

[0321] One or more hardware structures 615 are used to execute one or more embodiments. This document may combine... Figure 6A and / or Figure 6B Provide details about one or more hardware structures 615.

[0322] Figure 15Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which can be manufactured using one or more IP cores. In addition to those illustrated, at least one embodiment may also include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0323] Figure 15 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1500 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1500 includes one or more application processors 1505 (e.g., CPUs), at least one graphics processor 1510, and may additionally include an image processor 1515 and / or a video processor 1520, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1500 includes peripheral or bus logic, which includes a USB controller 1525, a UART controller 1530, an SPI / SDIO controller 1535, and an I... 2 S / I 2 C controller 1540. In at least one embodiment, integrated circuit 1500 may include a display device 1545 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1550 and a Mobile Industrial Processor Interface (MIPI) display interface 1555. In at least one embodiment, storage may be provided by a flash memory subsystem 1560, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1565 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1570.

[0324] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in integrated circuit 1500 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0325] In at least one embodiment, Figure 15 Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0326] Figures 16A-16BExemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be fabricated using one or more IP cores. In addition to those illustrated, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0327] Figures 16A-16B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 16A An exemplary graphics processor 1610 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 16B An additional exemplary graphics processor 1640 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 16A The graphics processor 1610 is a low-power graphics processor core. In at least one embodiment, Figure 16B The graphics processor 1640 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1610, 1640 may be... Figure 15 A variant of the 1510 graphics processor.

[0328] In at least one embodiment, the graphics processor 1610 includes a vertex processor 1605 and one or more fragment processors 1615A-1615N (e.g., 1615A, 1615B, 1615C, 1615D to 1615N-1 and 1615N). In at least one embodiment, the graphics processor 1610 may execute different shader programs via separate logic, such that the vertex processor 1605 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1615A-1615N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1605 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1615A-1615N use the primitive and vertex data generated by the vertex processor 1605 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1615A-1615N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0329] In at least one embodiment, the graphics processor 1610 additionally includes one or more memory management units (MMUs) 1620A-1620B, one or more caches 1625A-1625B, and one or more circuit interconnects 1630A-1630B. In at least one embodiment, the one or more MMUs 1620A-1620B provide virtual-to-physical address mapping for the graphics processor 1610 (including for the vertex processor 1605 and / or fragment processors 1615A-1615N), and may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1625A-1625B. In at least one embodiment, the one or more MMUs 1620A-1620B may be synchronized with other MMUs within the system, including with... Figure 15 One or more application processors 1505, graphics processors 1515, and / or video processors 1520 are associated with one or more MMUs, such that each processor 1505-1520 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1630A-1630B enable the graphics processor 1610 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0330] In at least one embodiment, the graphics processor 1640 includes, as shown below: Figure 16B The one or more shader cores 1655A-1655N (e.g., 1655A, 1655B, 1655C, 1655D, 1655E, 1655F to 1655N-1 and 1655N) shown provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1640 includes an inter-core task manager 1645, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1655A-1655N and a tile unit 1658 to accelerate tile-based rendering operations, wherein rendering operations of the scene are subdivided in the image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0331] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6BDetails regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in graphics processor 1610 and / or 1640 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0332] In at least one embodiment, Figure 16A and / or Figure 16B Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0333] Figures 17A-17B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figures 17A-17B The shown or combined Figures 17A-17B The described components are integrated into a single system, such as a graphics processing unit (GPU), a system-on-a-chip (SoC), or other types of processors. In at least one embodiment, Figure 17A It shows that it can be included in Figure 15 The graphics core 1700 within the graphics processor 1510, and in at least one embodiment, may be as follows: Figure 16B The Unified Shader Core 1655A-1655N is shown. Figure 17B A highly parallel general-purpose graphics processing unit (“GPGPU”) suitable for deployment on a multi-chip module is illustrated in at least one embodiment; it may also be referred to as “graphics processing unit” 1730. In at least one embodiment, graphics processing unit 1730 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1500 includes a graphics core 1700, for example, forming an integrated circuit and / or forming a SoC, wherein such integrated circuit and / or such SoC performs the operations described herein.

[0334] In at least one embodiment, the graphics core 1700 includes a shared instruction cache 1702, texture units 1718, and cache / shared memory 1720 (e.g., including L1, L2, L3, last-level cache, or other caches), which are shared for execution resources within the graphics core 1700. In at least one embodiment, the graphics core 1700 may include multiple slices 1701A-1701N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1700. In at least one embodiment, each slice 1701A-1701N refers to the graphics core 1700. In at least one embodiment, slices 1701A-1701N have sub-slices that are part of slices 1701A-1701N. In at least one embodiment, slices 1701A-1701N are independent of other slices or dependent on other slices. In at least one embodiment, slices 1701A-1701N may include supporting logic including local instruction caches 1704A-1704N, thread schedulers (orderers) 1706A-1706N, thread dispatchers 1707A-1708N, and a set of registers 1710A-1710N. In at least one embodiment, slices 1701A-1701N may include a set of additional functional units (AFU 1712A-1712N), floating-point units (FPU 1714A-1714N), integer arithmetic logic units (ALU 1716A-1716N), address calculation units (ACU 1713A-1713N), double-precision floating-point units (DPFPU 1715A-1715N), and matrix processing units (MPU 1717A-1717N). In at least one embodiment, MPU 1717A-1717N is referred to as a matrix engine.

[0335] In at least one embodiment, each slice 1701A-1701N includes one or more engines for floating-point and integer vector operations, and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1701A-1701N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating-point (also known as "FP16"), 32-bit floating-point (also known as "FP32"), or 64-bit floating-point (also known as "FP64"). In at least one embodiment, one or more slices 1701A-1701N include 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, wherein the vector engines and math units are exposed via matrix expansion. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, such as 16 cores and ray tracing units or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of the processor. In at least one embodiment, the graphics core 1700 includes one or more matrix engines for calculating matrix operations, such as when calculating tensor operations.

[0336] In at least one embodiment, one or more slices 1701A-1701N include one or more ray tracing units for calculating ray tracing operations (e.g., 16 ray tracing units per slice 1701A-1701N). In at least one embodiment, the ray tracing units calculate ray traversal, triangle intersection, bounding box intersection, or other ray tracing operations.

[0337] In at least one embodiment, one or more slices 1701A-1701N include media slices that encode, decode, and / or transcode data; scale and / or format convert data; and / or perform video quality operations on video data.

[0338] In at least one embodiment, one or more slices 1701A-1701N are linked to an L2 cache and memory architecture, link connectors, a high-bandwidth memory (HBM) stack (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 1701A-1701N include multiple cores (e.g., 16 cores) paired with each core and multiple ray tracing units (e.g., 16). In at least one embodiment, one or more slices 1701A-1701N have one or more L1 caches. In at least one embodiment, one or more slices 1701A-1701N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) (e.g., corresponding to instructions) for storing data; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in the geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., shapes) and converting it into a raster image (e.g., a series of pixels, points, or lines, which, when displayed together, create an image represented by shapes); one or more hierarchical depth buffers (Hiz) for caching data; and / or one or more pixel back-ends. In at least one embodiment, slices 1701A-1701N include memory structures, such as L2 caches.

[0339] In at least one embodiment, the FPU 1714A-1714N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1715A-1715N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1716A-1716N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1717A-1717N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1717A-1717N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1712A-1712N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric function operations (e.g., sine, cosine, etc.).

[0340] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in graphics core 1700 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0341] In at least one embodiment, the graphics core 1700 includes an interconnect and link structure sublayer attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 1700 (e.g., eight) to be interconnected without glue using load / memory units (LSUs), data transfer units, and synchronization semantics across the multiple graphics processors 1700. In at least one embodiment, the interconnect includes standardized interconnects (e.g., PCIe) or some combination thereof.

[0342] In at least one embodiment, the graphics core 1700 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, wherein the individual dies may be interconnected (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the graphics core 1700 includes compute tiles, storage tiles (e.g., where storage tiles may be exclusively accessed by different tiles or different chipsets, such as Rambo tiles), base tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, wherein all tiles are packaged together in the graphics core 1700 as part of the GPU. In at least one embodiment, the graphics core 1700 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile may have eight graphics cores 1700, an L1 cache; and a base tile may have a host interface employing PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight links, and eight ports with an embedded switch. In at least one embodiment, the blocks are connected to face-to-face (F2F) chip bonding via fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, the graphics core 1700 includes a memory structure comprising memory and is a block accessible to the multiple blocks. In at least one embodiment, the graphics core 1700 stores, accesses, or loads its own hardware context in memory, wherein the hardware context is a set of data loaded from registers prior to process resumption, and wherein the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0343] In at least one embodiment, the graphics core 1700 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream into a parallel data stream, or a parallel data stream into a serial data stream.

[0344] In at least one embodiment, the graphics core 1700 includes a high-speed consistent unified architecture (GPU-to-GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected via an embedded switch, wherein the GPU-to-GPU bridge is controlled by a controller.

[0345] In at least one embodiment, the graphics core 1700 executes an API, wherein the API abstracts the hardware of the graphics core 1700 and utilizes an instruction access library to perform mathematical operations (e.g., a mathematical kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communication, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0346] In at least one embodiment, Figure 17A Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0347] Figure 17B A general-purpose processing unit (GPGPU) 1730 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1730 can be directly linked to other instances of the GPGPU 1730 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1730 includes a host interface 1732 for establishing a connection to a host processor. In at least one embodiment, the host interface 1732 is a PCI Express interface. In at least one embodiment, the host interface 1732 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1730 receives commands from the host processor and uses a global scheduler 1734 (which may be referred to as a thread sequencer and / or asynchronous computing engine) to allocate the execution threads associated with those commands to a set of computing clusters 1736A-1736H. In at least one embodiment, the computing clusters 1736A-1736H share a cache memory 1738. In at least one embodiment, cache memory 1738 may be used as a higher-level cache than the cache memory within compute clusters 1736A-1736H. In at least one embodiment, compute clusters 1736A-1736H include slices, or referred to as "slices". In at least one embodiment, GPGPU 1730 is part of a SoC, such as part of integrated circuit 1500. Figure 15 ).

[0348] In at least one embodiment, the GPGPU 1730 includes memories 1744A-1744B coupled to the compute cluster 1736A-1736H via a set of memory controllers 1742A-1742B (e.g., one or more controllers of HBM2e). In at least one embodiment, memories 1744A-1744B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0349] In at least one embodiment, each of the computing clusters 1736A-1736H includes a set of graphics cores, such as Figure 17A The graphics core 1700 may include various types of integer and floating-point logic units that can perform computational operations over a range of precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1736A-1736H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0350] In at least one embodiment, multiple instances of GPGPU 1730 can be configured to operate as a compute cluster. In at least one embodiment, the communication used for synchronization and data exchange by compute clusters 1736A-1736H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 1730 communicate via host interface 1732. In at least one embodiment, GPGPU 1730 includes an I / O hub 1739 that couples GPGPU 1730 to GPU link 1740, which provides direct connectivity to other instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1730 reside in a separate data processing system and communicate via a network device accessible via host interface 1732. In at least one embodiment, in addition to or as an alternative to host interface 1732, GPU link 1740 may also be configured to implement a connection to the host processor.

[0351] In at least one embodiment, the GPGPU 1730 can be configured to train a neural network. In at least one embodiment, the GPGPU 1730 can be used within an inference platform. In at least one embodiment, when using the GPGPU 1730 for inference, the GPGPU 1730 may include fewer compute clusters 1736A-1736H compared to when using the GPGPU 1730 to train a neural network. In at least one embodiment, the memory technology associated with the memories 1744A-1744B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1730 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0352] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in the GPGPU 1730 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0353] In at least one embodiment, Figure 17B Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0354] Figure 18This is a block diagram illustrating a computing system 1800 according to at least one embodiment. In at least one embodiment, the computing system 1800 includes a processing subsystem 1801 having one or more processors 1802 and system memory 1804 communicating via interconnect paths that may include a memory hub 1805. In at least one embodiment, the memory hub 1805 may be a separate component within a chipset assembly or may be integrated within one or more processors 1802. In at least one embodiment, the memory hub 1805 is coupled to an I / O subsystem 1811 via a communication link 1806. In at least one embodiment, the I / O subsystem 1811 includes an I / O hub 1807 that enables the computing system 1800 to receive input from one or more input devices 1808. In at least one embodiment, the I / O hub 1807 enables a display controller to provide output to one or more display devices 1810A, the display controller being included in one or more processors 1802. In at least one embodiment, one or more display devices 1810A coupled to the I / O hub 1807 may include local, internal, or embedded display devices.

[0355] In at least one embodiment, the processing subsystem 1801 includes one or more parallel processors 1812 coupled to a memory hub 1805 via a bus or other communication link 1813. In at least one embodiment, the communication link 1813 may use one of any number of standards based on a communication link technology or protocol (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 1812 form a computationally concentrated parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as integrated many-core (MIC) processors. In at least one embodiment, some or all of the parallel processors 1812 form a graphics processing subsystem that can output pixels to one or more display devices 1810A coupled via an I / O hub 1807. In at least one embodiment, one or more parallel processors 1812 may also include a display controller and a display interface (not shown) for implementing direct connection to one or more display devices 1810B. In at least one embodiment, the parallel processor 1812 includes one or more cores, such as the graphics core 1700 discussed herein.

[0356] In at least one embodiment, system storage unit 1814 may be connected to I / O hub 1807 to provide a storage mechanism for computing system 1800. In at least one embodiment, I / O switch 1816 may be used to provide an interface mechanism for enabling connectivity between I / O hub 1807 and other components, such as network adapter 1818 and / or wireless network adapter 1819 integrated into the platform, and various other devices that may be added via one or more additional devices 1820. In at least one embodiment, network adapter 1818 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1819 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless devices.

[0357] In at least one embodiment, the computing system 1800 may include other components, not explicitly shown, that may also be connected to the I / O hub 1807, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnect can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect or interconnect protocols). Figure 18 The communication paths of each component.

[0358] In at least one embodiment, one or more parallel processors 1812 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU), such as a graphics core 1700. In at least one embodiment, one or more parallel processors 1812 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1800 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1812, a memory hub 1805, one or more processors 1802, and an I / O hub 1807 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1800 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1800 may be integrated into a multi-chip module (MCM), which may interconnect with other MCMs to a modular computing system.

[0359] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in computing system 1800 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0360] In at least one embodiment, Figure 18 Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0361] processor

[0362] Figure 19A A parallel processor 1900 according to at least one embodiment is illustrated. In at least one embodiment, the various components of the parallel processor 1900 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 1900 is according to an exemplary embodiment. Figure 18 Variations of the one or more parallel processors 1812 shown. In at least one embodiment, the parallel processor 1900 includes one or more graphics cores 1700.

[0363] In at least one embodiment, the parallel processor 1900 includes a parallel processing unit 1902. In at least one embodiment, the parallel processing unit 1902 includes an I / O unit 1904 that enables communication with other devices, including other instances of the parallel processing unit 1902. In at least one embodiment, the I / O unit 1904 can be directly connected to other devices. In at least one embodiment, the I / O unit 1904 is connected to other devices via a hub or switch interface (e.g., a memory hub 1905). In at least one embodiment, the connection between the memory hub 1905 and the I / O unit 1904 forms a communication link 1913. In at least one embodiment, the I / O unit 1904 is connected to a host interface 1906 and a memory crossbar switch 1916, wherein the host interface 1906 receives commands for performing processing operations, and the memory crossbar switch 1916 receives commands for performing memory operations.

[0364] In at least one embodiment, when host interface 1906 receives a command buffer via I / O unit 1904, host interface 1906 can route work operations for executing those commands to front-end 1908. In at least one embodiment, front-end 1908 is coupled to scheduler 1910 (which may be referred to as sequencer), which is configured to assign commands or other work items to processing cluster array 1912. In at least one embodiment, scheduler 1910 ensures that processing cluster array 1912 is correctly configured and in an active state before assigning tasks to clusters in processing cluster array 1912. In at least one embodiment, scheduler 1910 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1910 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing cluster array 1912. In at least one embodiment, host software can demonstrate workloads for scheduling on processing cluster array 1912 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing cluster array 1912 by the scheduler 1910 logic within the microcontroller, which includes the scheduler 1910.

[0365] In at least one embodiment, the processing cluster array 1912 may include up to "N" processing clusters (e.g., clusters 1914A, 1914B to 1914N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other diagrams). In at least one embodiment, each cluster 1914A-1914N of the processing cluster array 1912 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1910 may use various scheduling and / or work allocation algorithms to allocate work to clusters 1914A-1914N in the processing cluster array 1912, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1910, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 1912. In at least one embodiment, different clusters 1914A-1914N in the processing cluster array 1912 may be assigned to process different types of programs or to perform different types of computations.

[0366] In at least one embodiment, the processing cluster array 1912 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 1912 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 1912 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0367] In at least one embodiment, the processing cluster array 1912 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1912 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1912 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1902 may transfer data from system memory via I / O unit 1904 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1922) and then written back to system memory.

[0368] In at least one embodiment, when the parallel processing unit 1902 is used to perform graphics processing, the scheduler 1910 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among multiple clusters 1914A-1914N in the processing cluster array 1912. In at least one embodiment, portions of the processing cluster array 1912 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 1914A-1914N can be stored in a buffer to allow intermediate data to be transferred between the clusters 1914A-1914N for further processing.

[0369] In at least one embodiment, the processing cluster array 1912 may receive processing tasks to be executed via a scheduler 1910, which receives commands defining the processing tasks from a front end 1908. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 1910 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 1908. In at least one embodiment, the front end 1908 may be configured to ensure that the processing cluster array 1912 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0370] In at least one embodiment, each of one or more instances of the parallel processing unit 1902 may be coupled to the parallel processor memory 1922. In at least one embodiment, the parallel processor memory 1922 may be accessed via a memory crossbar switch 1916, which may receive memory requests from the processing cluster array 1912 and the I / O unit 1904. In at least one embodiment, the memory crossbar switch 1916 may be accessed via a memory interface 1918. In at least one embodiment, the memory interface 1918 may include a plurality of partition units (e.g., partition units 1920A, 1920B to 1920N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 1922. In at least one embodiment, the number of partition units 1920A-1920N is configured to be equal to the number of memory units, such that the first partition unit 1920A has a corresponding first memory unit 1924A, the second partition unit 1920B has a corresponding second memory unit 1924B, and the Nth partition unit 1920N has a corresponding Nth memory unit 1924N. In at least one embodiment, the number of partition units 1920A-1920N may not be equal to the number of memory units.

[0371] In at least one embodiment, memory cells 1924A-1924N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 1924A-1924N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, and HDM3. In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across memory cells 1924A-1924N, allowing partitioning cells 1920A-1920N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 1922. In at least one embodiment, local instances of the parallel processor memory 1922 may be excluded to facilitate a unified memory design that utilizes system memory and local cache memory.

[0372] In at least one embodiment, any of clusters 1914A-1914N in the processing cluster array 1912 can process data to be written to any memory cell 1924A-1924N within the parallel processor memory 1922. In at least one embodiment, the memory crossbar switch 1916 can be configured to transfer the output of each cluster 1914A-1914N to any partition cell 1920A-1920N or another cluster 1914A-1914N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 1914A-1914N can communicate with the memory interface 1918 via the memory crossbar switch 1916 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar switch 1916 has a connection to a memory interface 1918 for communicating with I / O unit 1904, and a connection to a local instance of parallel processor memory 1922, enabling processing units within different processing clusters 1914A-1914N to communicate with system memory or other memory not local to parallel processing unit 1902. In at least one embodiment, the memory crossbar switch 1916 can use virtual channels to separate traffic flows between clusters 1914A-1914N and partition units 1920A-1920N.

[0373] In at least one embodiment, multiple instances of the parallel processing unit 1902 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 1902 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1902 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system including one or more instances of the parallel processing unit 1902 or the parallel processor 1900 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0374] Figure 19B This is a block diagram of a partitioning unit 1920 according to at least one embodiment. In at least one embodiment, the partitioning unit 1920 is... Figure 19A This is an example of one of the partitioning units 1920A-1920N. In at least one embodiment, the partitioning unit 1920 includes an L2 cache 1921, a frame buffer interface 1925, and a ROP 1926 (raster operation unit). In at least one embodiment, the L2 cache 1921 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 1916 and the ROP 1926. In at least one embodiment, the L2 cache 1921 outputs read misses and urgent write-back requests to the frame buffer interface 1925 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 1925. In at least one embodiment, the frame buffer interface 1925 communicates with memory cells in the parallel processor memory (such as...). Figure 19A It is coupled to one of the memory cells 1924A-1924N (e.g., within the parallel processor memory 1922).

[0375] In at least one embodiment, ROP 1926 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1926 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 1926 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 1926 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data per tile.

[0376] In at least one embodiment, ROP 1926 is included within each processing cluster (e.g., Figure 19A Clusters 1914A-1914N are used instead of partition units 1920. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted via a memory crossbar switch 1916. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...) Figure 18 Displayed on one or more display devices 1810, routed by processor 1802 for further processing, or by... Figure 19A One of the processing entities within the parallel processor 1900 is routed for further processing.

[0377] Figure 19C This is a block diagram of a processing cluster 1914 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 19A An instance of one of the processing clusters 1914A-1914N. In at least one embodiment, processing cluster 1914 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issuing technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, Single Instruction Multiple Threading (SIMT) technology is used to support the parallel execution of a large number of typically synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0378] In at least one embodiment, the operation of the processing cluster 1914 can be controlled via a pipeline manager 1932 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1932... Figure 19AThe scheduler 1910 receives instructions and manages the execution of these instructions via the graphics multiprocessor 1934 and / or texture unit 1936. In at least one embodiment, the graphics multiprocessor 1934 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 1914 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 1914 may include one or more instances of the graphics multiprocessor 1934. In at least one embodiment, the graphics multiprocessor 1934 can process data, and the data crossover switch 1940 can be used to allocate the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1932 can facilitate the allocation of processed data by specifying the destination of the processed data to be allocated via the data crossover switch 1940.

[0379] In at least one embodiment, each graphics multiprocessor 1934 within the processing cluster 1914 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0380] In at least one embodiment, instructions sent to the processing cluster 1914 constitute threads. In at least one embodiment, a group of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group can be assigned to a different processing engine within the graphics multiprocessor 1934. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1934. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1934. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 1934, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 1934.

[0381] In at least one embodiment, the graphics multiprocessor 1934 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1934 may forgo the internal cache and use a cache memory within the processing cluster 1914 (e.g., L1 cache 1948). In at least one embodiment, each graphics multiprocessor 1934 may also access partition units (e.g., Figure 19A The L2 cache is located within partition units 1920A-1920N, which are shared among all processing clusters 1914 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1934 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 1902 can be used as global memory. In at least one embodiment, the processing cluster 1914 includes multiple instances of the graphics multiprocessor 1934, which can share common instructions and data that can be stored in the L1 cache 1948.

[0382] In at least one embodiment, each processing cluster 1914 may include a memory management unit (“MMU”) 1945 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1945 may reside in Figure 19A The memory interface 1918 is located within the MMU 1945. In at least one embodiment, the MMU 1945 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1945 may include an address translation lookahead buffer (TLB) or a cache that may reside within the graphics multiprocessor 1934, L1 cache 1948, or processing cluster 1914. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0383] In at least one embodiment, the processing cluster 1914 can be configured such that each graphics multiprocessor 1934 is coupled to a texture unit 1936 to perform a texture mapping operation that determines texture sample locations, reads texture data, and filters texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1934, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 1934 outputs a processed task to a data crossbar switch 1940 to provide the processed task to another processing cluster 1914 for further processing, or stores the processed task in an L2 cache, local parallel processor memory, or in system memory via a memory crossbar switch 1916. In at least one embodiment, a preROP 1942 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1934 and direct the data to a ROP unit, which can be associated with a partitioning unit (e.g., [missing information]). Figure 19A The PreROP 1942 unit is located together with the partition units 1920A-1920N. In at least one embodiment, the PreROP 1942 unit can perform optimizations for color mixing, organizing pixel color data, and performing address translation.

[0384] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in graphics processing cluster 1914 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0385] In at least one embodiment, Figure 19A , Figure 19B and / or Figure 19C Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0386] Figure 19DA graphics multiprocessor 1934 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 1934 is coupled to a pipeline manager 1932 of a processing cluster 1914. In at least one embodiment, the graphics multiprocessor 1934 has an execution pipeline including, but not limited to, an instruction cache 1952, an instruction unit 1954, an address mapping unit 1956, a register file 1958, one or more general-purpose graphics processing unit (GPGPU) cores 1962, and one or more load / store units 1966, wherein one or more load / store units 1966 can perform load / store operations to load / store instructions corresponding to the execution operations. In at least one embodiment, the GPGPU cores 1962 and the load / store units 1966 are coupled to a cache memory 1972 and a shared memory 1970 via a memory and cache interconnect 1968. In at least one embodiment, the GPGPU cores 1962 are part of a SoC, such as... Figure 15 Part of the integrated circuit 1500.

[0387] In at least one embodiment, instruction cache 1952 receives a stream of instructions to be executed from pipeline manager 1932. In at least one embodiment, instructions are cached in instruction cache 1952 and dispatched for execution by instruction unit 1954. In at least one embodiment, instruction unit 1954 may dispatch instructions as thread groups (e.g., thread bundles, wavefronts, waves), wherein each thread in the thread group is assigned to a different execution unit within GPGPU core 1962. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 1956 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 1966.

[0388] In at least one embodiment, register file 1958 provides a set of registers for the functional units of graphics multiprocessor 1934. In at least one embodiment, register file 1958 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 1934 (e.g., GPGPU core 1962, load / store unit 1966). In at least one embodiment, register file 1958 is partitioned between each functional unit, such that a dedicated portion of register file 1958 is allocated to each functional unit. In at least one embodiment, register file 1958 is partitioned between different thread bundles (which may be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 1934.

[0389] In at least one embodiment, each GPGPU core 1962 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1934. In at least one embodiment, the architectures of the various GPGPU cores 1962 may be similar or different. In at least one embodiment, a first portion of the GPGPU core 1962 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-1908 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 1934 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1962 may also include fixed-function or special-function logic.

[0390] In at least one embodiment, the GPGPU core 1962 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 1962 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0391] In at least one embodiment, the memory and cache interconnect 1968 is an interconnect network connecting each functional unit of the graphics multiprocessor 1934 to the register file 1958 and the shared memory 1970. In at least one embodiment, the memory and cache interconnect 1968 is a cross-switch interconnect that allows the load / store unit 1966 to perform load and store operations between the shared memory 1970 and the register file 1958. In at least one embodiment, the register file 1958 can operate at the same frequency as the GPGPU core 1962, resulting in very low latency for data transfer between the GPGPU core 1962 and the register file 1958. In at least one embodiment, the shared memory 1970 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 1934. In at least one embodiment, the cache memory 1972 can be used, for example, as a data cache for caching texture data communicated between functional units and texture units 1936. In at least one embodiment, the shared memory 1970 can also be used as a program-managed cache. In at least one embodiment, in addition to the data automatically cached in cache memory 1972, the thread executing on GPGPU core 1962 can also programmatically store data in shared memory.

[0392] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the SoC includes a parallel processor or a GPGPU, as described herein, wherein the parallel processor or the GPGPU is executed on the SoC. In at least one embodiment, the GPU may be integrated with the core in a package or on a chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions included in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0393] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6BDetails regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in graphics multiprocessor 1934 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0394] In at least one embodiment, Figure 19D Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0395] Figure 20 A multi-GPU computing system 2000 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 2000 may include a processor 2002 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2006A-D via a host interface switch 2004. In at least one embodiment, the host interface switch 2004 is a PCI Express switch device that couples the processor 2002 to a PCI Express bus, through which the processor 2002 can communicate with the GPGPUs 2006A-D. In at least one embodiment, the GPGPUs 2006A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 2016. In at least one embodiment, the GPU-to-GPU links 2016 are connected to each of the GPGPUs 2006A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2016 enable direct communication between each GPGPU 2006A-D without communication via the host interface bus 2004 to which the processor 2002 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 2016, the host interface bus 2004 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 2000 via one or more network devices. While in at least one embodiment, the GPGPU 2006A-D is connected to the processor 2002 via the host interface switch 2004, in at least one embodiment, the processor 2002 includes direct support for the P2P GPU link 2016 and can be directly connected to the GPGPU 2006A-D. In at least one embodiment, the GPGPU 2006A-D is part of the SoC (such as...). Figure 15 (Part of the integrated circuit 1500), in which the GPGPU 2006A-D performs the operations described herein.

[0396] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in a multi-GPU computing system 2000 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0397] In at least one embodiment, the multi-GPU computing system 2000 includes one or more graphics cores 1700.

[0398] In at least one embodiment, Figure 20 Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0399] Figure 21 This is a block diagram of a graphics processor 2100 according to at least one embodiment. In at least one embodiment, the graphics processor 2100 includes a ring interconnect 2102, a pipeline front end 2104, a media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, the ring interconnect 2102 couples the graphics processor 2100 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2100 is one of many processors integrated within a multi-core processing system. In at least one embodiment, the graphics processor 2100 includes a graphics core 1700.

[0400] In at least one embodiment, the graphics processor 2100 receives multiple batches of commands via a ring interconnect 2102. In at least one embodiment, the input commands are interpreted by a command streamer 2103 in a pipeline front-end 2104. In at least one embodiment, the graphics processor 2100 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2103 provides the commands to the geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, the command streamer 2103 provides the commands to a video front-end 2134, which is coupled to a media engine 2137. In at least one embodiment, the media engine 2137 includes a video quality engine (VQE) 2130 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2133 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2136 and the media engine 2137 each generate an execution thread for thread execution resources provided by at least one graphics core 2180.

[0401] In at least one embodiment, the graphics processor 2100 includes scalable thread execution resources featuring graphics cores 2180A-2180N (which may be modular and sometimes referred to as core slices), each graphics core having multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2100 may have any number of graphics cores 2180A. In at least one embodiment, the graphics processor 2100 includes graphics cores 2180A having at least a first sub-core 2150A and a second sub-core 2160A. In at least one embodiment, the graphics processor 2100 is a low-power processor with a single sub-core (e.g., 2150A). In at least one embodiment, the graphics processor 2100 includes multiple graphics cores 2180A-2180N, each graphics core including a set of first sub-cores 2150A-2150N and a set of second sub-cores 2160A-2160N. In at least one embodiment, each of the first sub-cores 2150A-2150N includes at least a first set of execution units 2152A-2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each of the second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each sub-core 2150A-2150N, 2160A-2160N shares a set of shared resources 2170A-2170N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic. In at least one embodiment, the graphics processor 2100 includes load / store units in the pipeline front end 2104.

[0402] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, logic 615 may be used in graphics processor 2100 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0403] In at least one embodiment, Figure 21 Embodiments may include or cause one or more processors, circuits, or systems, according to the above description. Figures 1-5 The various embodiments discussed are used to predict software performance on an integrated circuit based on configuration parameters used to compile a neural network.

[0404] Figure 22 This is a block diagram illustrating a microarchitecture for a processor 2200 according to at least one embodiment, the processor 2200 including logic circuitry for executing instructions. In at least one embodiment, the processor 2200 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2200 may include registers for storing packaged data, such as 64-bit wide MMX data in a microprocessor implemented using Intel's MMX technology from Santa Clara, California. TM Registers. In at least one embodiment, an MMX register available in both integer and floating-point forms can operate with packed data elements accompanying Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (beyond) (commonly referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 2200 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0405] In at least one embodiment, processor 2200 includes an ordered front end (“front end”) 2201 for fetching instructions to be executed and preparing instructions for later use in the processor pipeline. In at least one embodiment, front end 2201 may include several units. In at least one embodiment, instruction prefetcher 2226 fetches instructions from memory and feeds the instructions to instruction decoder 2228, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2228 decodes the received instructions into one or more machine-executable so-called “micro-operations” or “micro-instructions” (also referred to as “micro ops”, “uops”, or “μ-ops”). In at least one embodiment, instruction decoder 2228 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2230 may assemble the decoded micro-operations into an ordered sequence or trace of programs in micro-operation queue 2234 for execution. In at least one embodiment, when the trace cache 2230 encounters a complex instruction, the microcode ROM 2232 provides the micro-operations required to complete the operation.

[0406] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2228 may access the microcode ROM 2232 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-operations for processing at the instruction decoder 2228. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2232. In at least one embodiment, the tracking cache 2230 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2232 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2232 has completed the serialization of the micro-operations of the instruction, the machine front end 2201 may resume fetching micro-operations from the tracking cache 2230.

[0407] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2203 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as the instruction stream moves down the pipeline and is scheduled for execution. In at least one embodiment, the out-of-order execution engine 2203 includes, but is not limited to, an allocator / register renamer 2240, a memory micro-operation queue 2242, an integer / floating-point micro-operation queue 2244, a memory scheduler 2246, a fast scheduler 2202, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2204, and a simple floating-point scheduler (“simple FP scheduler”) 2206. In at least one embodiment, the fast scheduler 2202, the slow / general-purpose floating-point scheduler 2204, and the simple floating-point scheduler 2206 are also collectively referred to herein as “micro-operation schedulers 2202, 2204, 2206”. In at least one embodiment, the allocator / register renamer 2240 allocates the machine buffers and resources required for each micro-operation to execute. In at least one embodiment, the allocator / register renamer 2240 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2240 also allocates entries for each micro-operation in one of two micro-operation queues, preceding the memory scheduler 2246 and micro-operation schedulers 2202, 2204, 2206, with memory micro-operation queue 2242 for memory operations and integer / floating-point micro-operation queue 2244 for non-memory operations. In at least one embodiment, the micro-operation schedulers 2202, 2204, 2206 determine when a micro-operation is ready to be executed based on the readiness of their dependent input register operand sources and the availability of execution resources required for the micro-operation to complete its operation. In at least one embodiment, the fast scheduler 2202 may schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2204 and the simple floating-point scheduler 2206 may schedule once per master processor clock cycle. In at least one embodiment, micro-operation schedulers 2202, 2204, and 2206 arbitrate dispatch ports to schedule micro-operations for execution.

[0408] In at least one embodiment, execution block 2211 includes, but is not limited to, integer register file / bypass network 2208, floating-point register file / bypass network (“FP register file / bypass network”) 2210, address generation units (“AGU”) 2212 and 2214, fast arithmetic logic units (ALU) (“fast ALU”) 2216 and 2218, slow arithmetic logic unit (“slow ALU”) 2220, floating-point ALU (“FP”) 2222, and floating-point move unit (“FP move”) 2224. In at least one embodiment, integer register file / bypass network 2208 and floating-point register file / bypass network 2210 are also referred to herein as “register files 2208, 2210”. In at least one embodiment, AGUs 2212 and 2214, fast ALUs 2216 and 2218, slow ALU 2220, floating-point ALU 2222, and floating-point movement unit 2224 are also referred to herein as "execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224". In at least one embodiment, execution block 2211 may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0409] In at least one embodiment, register networks 2208, 2210 may be arranged between micro-operation schedulers 2202, 2204, 2206 and execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224. In at least one embodiment, integer register file / bypass network 2208 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2210 performs floating-point operations. In at least one embodiment, each of register networks 2208, 2210 may include, but is not limited to, a bypass network that can bypass a recently completed result that has not yet been written to a register file or forward it to a new relevant micro-operation. In at least one embodiment, register networks 2208, 2210 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2208 may include, but is not limited to, two separate register files, one for low-order 32-bit data and the other for high-order 32-bit data. In at least one embodiment, the floating-point register file / bypass network 2210 may include, but is not limited to, 128-bit wide entries, since floating-point instructions typically have operands with widths ranging from 64 to 128 bits.

[0410] In at least one embodiment, execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224 can execute instructions. In at least one embodiment, register networks 2208 and 2210 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2200 can be, but is not limited to, any number of execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224, and combinations thereof. In at least one embodiment, floating-point ALU 2222 and floating-point move unit 2224 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2222 can be, but is not limited to, a 64-bit multiplication-64-bit floating-point divider for performing division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2216 and 2218. In at least one embodiment, fast ALUs 2216 and 2218 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2220, because slow ALU 2220 can include, but is not limited to, integer execution hardware for long-delay type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by ALUs 2212 and 2214. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2222 and the floating-point moving unit 2224 can be implemented to support a range of operands with various bit widths, such as supporting 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0411] In at least one embodiment, micro-operation schedulers 2202, 2204, and 2206 dispatch dependent operations before the parent load has completed execution. In at least one embodiment, since micro-operations can be speculatively scheduled and executed within processor 2200, processor 2200 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily prevents the scheduler from accessing the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, replaying dependent operations may be necessary and may allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0412] In at least one embodiment, "register" can refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register can be one that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuitry. Rather, in at least one embodiment, a register can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0413] In at least one embodiment, processor 2200 or each core of processor 2200 includes one or more prefetchers, one or more fetchers, one or more predecoders, one or more decoders for decoding data (e.g., instructions), one or more instruction queues for processing instructions (e.g., instructions corresponding to operations or API calls), one or more micro-operation (μOP) caches for storing μOPs, one or more micro-operation (μOP) queues, an ordered execution engine, one or more load buffers, one or more store buffers, one or more reorder buffers, one or more fill buffers, an out-of-order execution engine, one or more ports, one or more shift and / or shift units, one or more fused multiply-accumulate (FMA) units, one or more load and store units (“LSU”) for performing load / store operations corresponding to loaded / stored data (e.g., instructions) to perform operations (e.g., performing APIs, API calls), one or more matrix multiply-accumulate (MMA) units, and / or one or more shuffle units for performing any functions further described with respect to processor 2200. In at least one embodiment, the processor 2200 can access, use, implement, or execute instructions corresponding to the API call.

[0414] In at least one embodiment, processor 2200 includes one or more hyperpath interconnects (UPIs), such as point-to-point processor interconnects; one or more PCIe connections; one or more accelerators for accelerating computation or operation; and / or one or more memory controllers. In at least one embodiment, processor 2200 includes a shared last-level cache (LLC) coupled to one or more memory controllers, which enables shared memory access across processor cores.

[0415] In at least one embodiment, the processor 2200 or its core has a mesh structure, wherein the processor core, on-chip cache, memory controller, and I / O controller are organized into rows and columns, connected at each intersection by wires and switches to allow for bends. In at least one embodiment, the processor 2200 has one or more higher memory bandwidths (HMBs, e.g., HMBe) for storing data or caching data in, for example, Double Data Rate 5 Synchronous Dynamic Random Access Memory (DDR5 SDRAM). In at least one embodiment, one or more components of the processor 2200 are interconnected using Compute Expression Link (CXL) interconnects. In at least one embodiment, the memory controller uses a Least Recently Used (LRU) method to determine the contents stored in the cache. In at least one embodiment, the processor 2200 includes one or more PCIe instances (e.g., PCIe 5.0).

[0416] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, part or all of logic 615 may be incorporated into execution block 2211 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2211. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2211 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0417] In at least one embodiment, Figure 22 Implementations include one or more processors, circuits, or systems for enabling one or more neural networks to identify one or more locations in a graphics rendering scene where one or more objects are placed.

[0418] Figure 23A deep learning application processor 2300 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2300 uses instructions that, if executed by the deep learning application processor 2300, cause the deep learning application processor 2300 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2300 is an application-specific integrated circuit (ASIC). In at least one embodiment, as a result of executing one or more instructions or both, the application processor 2300 performs matrix multiplication operations or is "hardwired" into hardware. In at least one embodiment, the deep learning application processor 2300 includes, but is not limited to, a processing cluster 2310(1)-2310(12), an inter-chip link (“ICL”) 2320(1)-2320(12), an inter-chip controller (“ICC”) 2330(1)-2330(2), a second-generation high-bandwidth memory (“HBM2”) 2340(1)-2340(4), a memory controller (“Mem Ctrlr”) 2342(1)-2342(4), a high-bandwidth memory physical layer (“HBM PHY”) 2344(1)-2344(4), a management controller central processing unit (“management controller CPU”) 2350, a serial peripheral interface, internal integrated circuits, and a general purpose input / output block (“SPI, I…”). 2 C, GPIO”)2360, Peripheral Component Interconnect Fast Controller and Direct Memory Access Block (“PCIe Controller and DMA”)2370, and Sixteen-Channel Peripheral Component Interconnect Fast Port (“PCI Express x 16”)2380.

[0419] In at least one embodiment, processing cluster 2310 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques (including those described herein). In at least one embodiment, each processing cluster 2310 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2300 can include any number and type of processing cluster 2300. In at least one embodiment, the inter-chip link 2320 is bidirectional. In at least one embodiment, the inter-chip link 2320 and the inter-chip controller 2330 enable multiple deep learning application processors 2300 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2300 can include any number (including zero) and type of ICL 2320 and ICC 2330.

[0420] In at least one embodiment, the HBM2 2340 provides a total of 32GB of memory. In at least one embodiment, the HBM2 2340(i) is associated with both the memory controller 2342(i) and the HBM PHY 2344(i), where “i” is any integer. In at least one embodiment, any number of HBM2 2340s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2342 and HBM PHY 2344. In at least one embodiment, any number and type of blocks implementing any number and type of communication standards in any technically feasible manner can replace SPI, I... 2 C. GPIO 2360, PCIe controller and DMA 2370 and / or PCIe 2380.

[0421] Logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding logic 615 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the deep learning application processor 2300. In at least one embodiment, the deep learning application processor 2300 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2300. In at least one embodiment, the processor 2300 may be used to perform one or more neural network use cases described herein.

[0422] In at least one embodiment, Figure 23 Embodiments may include or cause one or more processors, ci...

Claims

1. A processor, comprising: One or more circuits are used to generate performance information corresponding to one or more integrated circuits using one or more neural networks, at least in part based on configuration parameters used to configure one or more compilers to compile software to be executed by one or more integrated circuits.

2. The processor of claim 1, wherein the one or more neural networks accept the configuration parameters, one or more features of the software, and one or more features of the one or more integrated circuits as input.

3. The processor of claim 1, wherein the performance information includes predictions of different configurations of the configuration parameters, and wherein one or more circuits further provide the performance information as a result in response to a request for the performance information.

4. The processor of claim 3, wherein the results are provided as a visualization illustrating trade-offs between different configurations of the configuration parameters regarding two or more performance attributes.

5. The processor of claim 1, wherein the one or more neural networks are trained using performance results captured by different software, the software being compiled and tested on different hardware configurations using different configurations of the configuration parameters.

6. The processor of claim 1, wherein the software is one or more trained neural networks.

7. The processor of claim 6, wherein the compiler is an optimizer for executing the one or more trained neural networks on the one or more integrated circuits.

8. A method comprising: One or more neural networks are used to generate performance information corresponding to the one or more integrated circuits, based at least in part on configuration parameters used to configure one or more compilers to compile software to be executed by one or more integrated circuits.

9. The method of claim 8, wherein the one or more neural networks accept the configuration parameters, one or more features of the software, and one or more features of the one or more integrated circuits as input.

10. The method of claim 8, wherein the performance information includes predictions of different configurations of the configuration parameters, and wherein the method further comprises: The performance information is provided as a result in response to a request for the performance information.

11. The method of claim 10, wherein the result is provided as a visualization illustrating trade-offs between different configurations of the configuration parameters regarding two or more performance attributes.

12. The method of claim 8, wherein the one or more neural networks are trained using performance results captured by different software, the software being compiled and tested on different hardware configurations using different configurations of the configuration parameters.

13. The method of claim 8, wherein the software is one or more trained neural networks.

14. The method of claim 13, wherein the compiler is an optimizer for executing the one or more trained neural networks on the one or more integrated circuits.

15. A system comprising: One or more processors, the one or more processors being used to generate performance information corresponding to the one or more integrated circuits using one or more neural networks, at least in part based on configuration parameters for configuring one or more compilers to compile software to be executed by one or more integrated circuits; as well as One or more memories, the one or more memories being used to store parameters associated with the one or more neural networks.

16. The system of claim 15, wherein the one or more neural networks accept the configuration parameters, one or more features of the software, and one or more features of the one or more integrated circuits as input.

17. The system of claim 15, wherein the performance information includes predictions of different configurations of the configuration parameters, and wherein one or more processors further provide the performance information as a result in response to a request for the performance information.

18. The system of claim 17, wherein the results are provided as a visualization illustrating trade-offs between different configurations of the configuration parameters regarding two or more performance attributes.

19. The system of claim 15, wherein the one or more neural networks are trained using performance results captured by different software, the software being compiled and tested on different hardware configurations using different configurations of the configuration parameters.

20. The system of claim 15, wherein the software is one or more trained neural networks.

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