Processor heterogeneous system, inter-processor data access method and related products

Abstract

The invention provides a processor heterogeneous system, an inter-processor data access method and a related product. The system comprises a CPU (Central Processing Unit) and a target processor, the target processor is a processor different from the CPU in type; a target performance function is packaged in a drive program of the target processor, the target performance function comprises a first function, and the first function is used for synchronizing data in a target cache corresponding to a lock page memory of the CPU into the lock page memory under the condition that the target processor reads data from the memory of the CPU; the method comprises the following steps: under the condition that data to be read by a target processor is written into a target cache, calling a target performance function to synchronize the data to be read by the target processor in the target cache into a lock page memory; and copying the data to be read by the target processor from the lock page memory to the memory of the target processor. According to the method and the device, the problem that error data are read when other processors access the memory of the CPU in an architecture that the CPU does not support cache consistency can be solved.

Description

Technical Field

[0001] This application relates to the field of processor technology, and more specifically, to a processor heterogeneous system, an inter-processor data access method, and related products. Background Technology

[0002] In a processor heterogeneous system with a CPU (Central Processing Unit) (i.e., a processor system consisting of a CPU and other types of processors), since each processor has its own memory, if the CPU does not support cache coherency when accessing data between processors by requesting page-locked memory, it may cause other processors in the processor heterogeneous system to read incorrect data when accessing the CPU's memory.

[0003] For example, in a CPU+GPU (Graphics Processing Unit) heterogeneous system, the CPU has its own memory, and the GPU has its own video memory. When the CPU needs the GPU to perform calculations, data transfer between the CPU and GPU is involved. Taking data copying as an example: the CPU first allocates a block of memory, copies the data that the GPU needs to process into that memory, then allocates a block of video memory, and finally calls the GPU's copy command. Through the GPU's DMA (Direct Memory Access) controller, the data is moved from memory to video memory. This process involves allocating CPU memory. In many CPUs, to improve efficiency, a paged memory allocation method is generally used. That is, when allocating memory, the system pins the actual physical memory for mapping. However, this method relies on the CPU to ensure cache coherency. In a non-cache-coherent CPU architecture (i.e., an architecture where the CPU does not support cache coherency), a situation may occur where the CPU writes data to the paged memory (at this time, the data is actually written to the cache and has not yet reached memory), and then notifies the GPU to read it, but the GPU reads incorrect data. The reason for this situation is that in a non-cache-coherent CPU architecture, when the CPU operates on memory, it first writes the data to the cache. However, the data in the cache is not synchronized to the memory. The GPU reads the data directly from the memory via DMA (DMA reads data without going through the cache). As a result, the data read is different from the data that is actually written to the cache and needs to be read, leading to a data read error. Summary of the Invention

[0004] The purpose of this application is to provide a processor heterogeneous system, an inter-processor data access method, and related products to solve the problem that in an architecture where the CPU does not support cache coherency, other processors in the processor heterogeneous system may read incorrect data when accessing the CPU's memory.

[0005] This application provides a method for inter-processor data access in a heterogeneous processor system, the heterogeneous processor system including a CPU and a target processor; the target processor is a processor of a different type than the CPU; the driver of the target processor encapsulates a target function, the target function including a first function, the first function being used to synchronize data in a target cache corresponding to the CPU's paged memory to the paged memory when the target processor reads data from the CPU's memory; the method is applied to the target processor, the method including: when the data to be read by the target processor is written to the target cache, calling the target function to synchronize the data to be read by the target processor in the target cache to the paged memory; and copying the data to be read by the target processor from the paged memory to the memory of the target processor.

[0006] In the above implementation scheme of this application, by encapsulating a target function in the target processor's driver, when the CPU writes data to be read by the target processor into the target cache corresponding to the paged memory, the target function synchronizes the data in the target cache to the paged memory, and then copies the data to be read by the target processor from the paged memory to the target processor's memory. Thus, in a non-cache-coherent CPU architecture, the target processor can synchronize data not synchronized to the paged memory to the paged memory by calling the encapsulated target function, thereby ensuring the accuracy of the copied data to be read by the target processor and avoiding the problem of other processors in a heterogeneous processor system reading incorrect data when accessing the CPU's memory.

[0007] Optionally, the target function further includes a second function, which is used to control the CPU's cache to be in an invalid state when the CPU reads data from memory; the method further includes: writing data to be read by the CPU into the CPU's memory; and calling the target function to invalidate the CPU's cache.

[0008] In a non-cache-coherent CPU architecture, when the target processor transfers data to the CPU, it writes the data to be read by the CPU into the locked page memory. However, because the CPU does not support cache coherence, the data in the target cache corresponding to the locked page memory is not updated, and the CPU will encounter errors when reading data from the target cache. With the above implementation, after the target processor writes the data to be read by the CPU into the locked page memory, it invalidates the CPU's cache by calling a target function. This way, when the CPU subsequently tries to read the data, it will have to read the data from the locked page memory because the target cache is invalid, thus avoiding errors in data reads.

[0009] Optionally, the target function includes a first input parameter; the first input parameter includes a cache refresh direction, wherein the cache refresh direction is: the target processor reads data from the CPU's memory, or the target processor writes data to the CPU's memory for the CPU to read; the method further includes: before calling the target function to synchronize the data to be read by the target processor in the target cache to the locked page memory, or before calling the target function to invalidate the CPU's cache, controlling the target function to call the function to be executed according to the first input parameter; the function to be executed is the first function or the second function.

[0010] In the above implementation, by setting the first output parameter to include the cache refresh direction, the current usage scenario can be determined based on the input first output parameter including the cache refresh direction, thereby enabling the execution of the required function and realizing different processing in two directions, thus solving the CPU cache consistency problem.

[0011] Optionally, the target function includes a second input parameter; the second input parameter includes a handle to the paged memory; the method further includes: before calling the target function to synchronize the data to be read by the target processor in the target cache to the paged memory, or before calling the target function to invalidate the CPU cache, controlling the target function to determine the DMA address of the paged memory based on the handle of the paged memory; Correspondingly, calling the target function to synchronize the data to be read by the target processor in the target cache to the locked page memory includes: synchronizing the data to be read by the target processor in the target cache to the memory corresponding to the DMA address through the first function; Correspondingly, writing data to be read by the CPU into the CPU's memory includes: writing the data to be read by the CPU into the memory corresponding to the DMA address.

[0012] In the above implementation, by setting a second input parameter that includes the handle of the page lock memory, the DMA address of the page lock memory can be determined based on the handle of the page lock memory. This enables the target processor to accurately copy data to be read from the page lock memory on the CPU side, or to accurately write data to the page lock memory on the CPU side.

[0013] Optionally, the target function is encapsulated with a user-space call function; the user-space call function is used to provide user space for calling the target function.

[0014] In the above implementation, by encapsulating the target function into a user-space call function (such as an ioctl operation function), the user space can call the target function through this user-space call function, thus making it easier for users to use.

[0015] This application also provides a method for inter-processor data access in a processor heterogeneous system, the processor heterogeneous system including a CPU and a target processor; the target processor is a processor of a different type from the CPU; the driver of the target processor encapsulates a target function, the target function including a first function, the first function being used to synchronize data in a target cache corresponding to the paged memory of the CPU to the paged memory when the target processor reads data from the memory of the CPU; the method is applied to the CPU, the method including: writing data to be read by the target processor into the target cache, so that the target processor can call the target function to synchronize the data to be read by the target processor in the target cache to the paged memory, and copying the data to be read by the target processor from the paged memory to the memory of the target processor.

[0016] In the above implementation scheme of this application, when the CPU writes data to be read by the target processor into the target cache corresponding to the paged memory, the target processor can synchronize the data in the target cache to the paged memory through the encapsulated target function in the driver, and then copy the data to be read by the target processor from the paged memory to the target processor's memory. In this way, under a non-cache-coherent CPU architecture, the target processor can realize the synchronization of data that has not been synchronized to the paged memory to the paged memory by calling the encapsulated target function, thereby ensuring the accuracy of the copied data to be read by the target processor and avoiding the problem of other processors in a heterogeneous processor system reading incorrect data when accessing the CPU's memory.

[0017] Optionally, the target function further includes a second function, which is used to control the CPU's cache to be in an invalid state when the CPU reads data from memory; the method further includes: reading the data to be read by the CPU from the CPU's memory when the CPU's cache is in an invalid state.

[0018] As mentioned earlier, in a non-cache-coherent CPU architecture, when the target processor transmits data to the CPU, it writes the data to be read by the CPU into the locked page memory. However, since the CPU does not support cache coherence, the data in the target cache corresponding to the locked page memory will not be updated, leading to errors when the CPU reads data from the target cache. With the implementation described above, the target processor can invalidate the CPU's target cache by calling a target function. The CPU then reads the data to be read from the CPU's memory while the target cache is invalid, thus reducing the probability of CPU data read errors.

[0019] This application also provides a processor heterogeneous system, including: a CPU and a target processor; the target processor is a processor of a different type from the CPU; the driver of the target processor encapsulates a target function, the target function including a first function, the first function being used to synchronize data in the target cache corresponding to the paged memory of the CPU to the paged memory when the target processor reads data from the memory of the CPU.

[0020] In the above implementation scheme of this application, by encapsulating the target function in the driver of the target processor, and by using the target function to synchronize the data in the target cache corresponding to the CPU's paged memory to the paged memory when the target processor reads data from the CPU's memory, in a non-cache-coherent CPU architecture, the target processor can realize the synchronization of data that has not been synchronized to the paged memory to the paged memory by calling the encapsulated target function, thereby ensuring the accuracy of the copied data to be read by the target processor and avoiding the problem of other processors in the heterogeneous processor system reading incorrect data when accessing the CPU's memory.

[0021] Optionally, the target function further includes a second function, which is used to control the CPU's cache to be in an invalid state when the CPU reads data from memory.

[0022] As mentioned earlier, in a non-cache-coherent CPU architecture, when the target processor transfers data to the CPU, it writes the data to be read by the CPU into the locked page memory. However, since the CPU does not support cache coherence, the data in the target cache corresponding to the locked page memory will not be updated, and errors will occur when the CPU reads data from the target cache. In the above implementation, by setting the target function to include a second function, the second function is used to control the CPU cache to be in an invalid state when the CPU reads data from memory. This allows the target processor to write the data to be read by the CPU into the locked page memory, and by executing the second function of the target function, the CPU will no longer read data from the target cache, but from the locked page memory, thus ensuring the correctness of the data read by the CPU.

[0023] Optionally, the target function includes a first input parameter; the first input parameter includes a cache refresh direction, wherein the cache refresh direction is: the target processor reads data from the CPU's memory, or the target processor writes data to the CPU's memory for the CPU to read; when the cache refresh direction is that the target processor reads data from the CPU's memory, the target function executes the first function; when the cache refresh direction is that the target processor writes data to the CPU's memory for the CPU to read, the target function executes the second function.

[0024] In the above implementation, by setting the first output parameter to include the cache refresh direction, the current usage scenario can be determined based on the input first output parameter including the cache refresh direction, thereby enabling the execution of the required function and realizing different processing in two directions, thus solving the CPU cache consistency problem.

[0025] Optionally, the target function includes a second input parameter; the second input parameter includes a handle to the page-locked memory; the handle to the page-locked memory is used to determine the DMA address of the page-locked memory.

[0026] In the above implementation, by setting a second input parameter that includes the handle of the page lock memory, the DMA address of the page lock memory can be determined based on the handle of the page lock memory. This enables the target processor to accurately copy data to be read from the page lock memory on the CPU side, or to accurately write data to the page lock memory on the CPU side.

[0027] Optionally, the target function is encapsulated with a user-space call function; the user-space call function is used to provide user space for calling the target function.

[0028] In the above implementation, by encapsulating the target function into a user space call function, the user space can call the target function through the user space call function, thus making it easier for users to use.

[0029] This application also provides an electronic component, including any of the processor heterogeneous systems described above.

[0030] This application also provides an electronic device, including a processor and a memory, wherein the processor is configured to execute one or more programs stored in the memory to implement any of the methods described above. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This application provides a schematic diagram of the basic structure of a processor heterogeneous system. Figure 2 A schematic diagram of the interaction flow of an inter-processor data access method in a processor heterogeneous system provided in this application embodiment; Figure 3 An interactive schematic diagram provided for an embodiment of this application, in which the target function includes a second function; Figure 4 This application provides a schematic diagram illustrating the process of a GPU accessing data from a CPU in a traditional processor heterogeneous system. Figure 5 This is a schematic diagram illustrating the process of a GPU accessing CPU data in a processor heterogeneous system using the processor described in this application, provided as an embodiment of this application. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0034] To address the issue that in architectures where the CPU does not support cache coherency, other processors in a heterogeneous processor system may read incorrect data when accessing the CPU's memory, this application provides a heterogeneous processor system and an inter-processor data access method applied to the heterogeneous processor system.

[0035] See also Figure 1 As shown, Figure 1 This is a basic structural diagram of the processor heterogeneous system provided in this application embodiment, including: a CPU, CPU memory, a target processor, and target processor memory. The target processor is a processor of a different type than the CPU, such as a GPU, GPGPU (General-Purpose Computing on Graphics Processing Units), NPU (Neural Network Processing Unit), ISP (Image Signal Processor), DPU (Display Processing Unit), VPU (Video Processing Unit), DSP (Digital Signal Processor), etc. In this application embodiment, when the target processor is a GPU or GPGPU, the target processor memory can be video memory.

[0036] In this embodiment of the application, the target function can be encapsulated in the driver of the target processor.

[0037] In this embodiment, the target function may include a first function, which is used to synchronize data in the target cache corresponding to the CPU's paged memory to the paged memory when the target processor reads data from the CPU's memory. Thus, in a non-cache-coherent CPU architecture, the target processor can synchronize data not synchronized to the paged memory to the paged memory by calling the encapsulated target function, thereby ensuring the accuracy of the copied data to be read by the target processor and avoiding the problem of other processors in a heterogeneous system reading incorrect data when accessing the CPU's memory.

[0038] Furthermore, considering that in a non-cache-coherent CPU architecture, when the target processor transfers data to the CPU, the target processor writes the data to be read by the CPU into the locked page memory. However, since the CPU does not support cache coherence, the data in the target cache corresponding to the locked page memory will not be updated, and the CPU will encounter errors when reading data from the target cache.

[0039] In some optional embodiments of this application, the target function may further include a second function. The second function is used to control the CPU's cache to be in an invalid state when the CPU reads data from memory. This allows the target processor to write data to be read by the CPU into the CPU's locked page memory, and by executing the second function of the target function, prevent the CPU from reading data from the target cache, instead reading data from the locked page memory, thereby ensuring the correctness of the data read by the CPU.

[0040] In some optional embodiments of this application, the target function may include a first input parameter. The first input parameter includes a cache refresh direction, which is either the target processor reading data from the CPU's memory or the target processor writing data to the CPU's memory for the CPU to read.

[0041] When the cache refresh direction is for the target processor to read data from the CPU's memory, the target function executes the first function; when the cache refresh direction is for the target processor to write data to the CPU's memory for the CPU to read, the target function executes the second function.

[0042] In this optional implementation, the two cache refresh directions can be represented by two different parameter values. For example, parameter value 1 can be used to indicate that the cache refresh direction is when the target processor reads data from the CPU's memory, and parameter value 0 can be used to indicate that the cache refresh direction is when the target processor writes data to the CPU's memory for the CPU to read.

[0043] In this way, the current usage scenario can be determined based on the first output parameter, including the cache refresh direction, so as to execute the required function, realize different processing in two directions, and solve the CPU cache coherency problem.

[0044] In some optional embodiments of this application, the target function may further include a second input parameter. The second input parameter may include a handle to the paged memory, thereby allowing the DMA address of the paged memory to be determined via the handle.

[0045] It is understood that in the embodiments of this application, the target processor may be a DMA controller that writes data to the CPU's memory and reads data from the CPU's memory.

[0046] Once the DMA address of the paged memory is determined: If the target processor needs to read data from the CPU's paged memory (for ease of distinction and description, the data that the target processor needs to read from the CPU's paged memory will be referred to as the data to be read by the target processor), the DMA controller can read (copy) the data to be read by the target processor from the determined DMA address into the target processor's memory. If the target processor needs to write data to the CPU's paged memory (for ease of distinction and description, the data that the target processor writes to the CPU's paged memory will be referred to as the data to be read by the CPU), the DMA controller can write the data to be read by the CPU into the DMA address in the CPU's memory. For example, the DMA controller can copy the data to be read by the CPU stored in the target processor's memory to the DMA address in the CPU's memory.

[0047] By inputting the second input parameter, the DMA address of the page-locked memory can be determined based on the handle of the page-locked memory. This enables the target processor to accurately copy data to be read from the page-locked memory on the CPU side, or to accurately write data from the page-locked memory on the CPU side to be read by the CPU, thereby improving the accuracy of data reading and writing.

[0048] In the embodiments of this application, when calling the target function to execute the first function or the second function, the first function or the second function can be implemented by calling different interfaces in the system respectively.

[0049] In some optional embodiments of this application, the target function may be encapsulated in a user-space call function. The user-space call function provides a way for the user space to invoke the target function. By encapsulating the target function in a user-space call function, the user space can invoke the target function through this function, thus facilitating user access.

[0050] For example, user-space call functions can be, but are not limited to, ioctl operation functions.

[0051] In the above optional implementation, the user space call function can be located in the user space of the target processor, thereby facilitating user use.

[0052] Based on the aforementioned processor heterogeneous systems, see [link to relevant documentation]. Figure 2 As shown, Figure 2 This application illustrates a schematic diagram of the interaction flow of the inter-processor data access method in a processor heterogeneous system, including: S201: The CPU writes the data to be read by the target processor into the target cache.

[0053] In this embodiment, before writing the data to be read by the target processor into the target cache, the CPU can first perform a memory allocation operation based on the page-locked memory mechanism to obtain the page-locked memory and the corresponding target cache, and then write the data to be read by the target processor into the target cache.

[0054] S202: The target processor calls the target function to synchronize the data to be read by the target processor in the target cache to the locked page memory.

[0055] In some optional embodiments of this application, the target function may include a second input parameter, which includes a handle to the paged memory. In this case, the target processor can control the target function to determine the DMA address of the paged memory based on the handle, and then synchronize the data to be read by the target processor from the target cache to the memory corresponding to the DMA address through the first function.

[0056] S203: Copy the data to be read by the target processor from the locked memory to the target processor's memory.

[0057] In some optional embodiments of this application, the target processor may copy the data to be read by the target processor from the locked memory to the target processor's memory through the DMA controller.

[0058] Correspondingly, when the target function includes a second function, see also [the relevant documentation]. Figure 3 The interactive diagram shown includes: S301: The target processor writes data to be read by the CPU into the CPU's memory.

[0059] When the target function can include a second input parameter, the target processor can control the target function to determine the DMA address of the paged memory based on the handle of the paged memory, and then write the data to be read by the CPU into the memory corresponding to the DMA address.

[0060] In some optional embodiments of this application, the target processor may use a DMA controller to copy data to be read by the CPU from the target processor's memory to the CPU's memory.

[0061] S302: Call the target function to execute the second function, invalidating the CPU cache.

[0062] It is understandable that when the CPU cache is invalid, the CPU cannot read data from the cache.

[0063] S303: The CPU reads the data to be read from the CPU's memory.

[0064] To accommodate the two scenarios described above, in some optional embodiments of this application, as mentioned above, the target function may include a first input parameter.

[0065] Therefore, before the target processor calls the target function to synchronize the data to be read by the target processor in the target cache to the locked page memory, or before calling the target function to invalidate the CPU cache, the target processor can control the target function to call the function to be executed according to the first input parameter.

[0066] Specifically, if the cache refresh direction included in the first input parameter is that the target processor reads data from the CPU's memory, the function to be executed is the first function; if the cache refresh direction included in the first input parameter is that the target processor writes data to the CPU's memory for the CPU to read, the function to be executed is the second function.

[0067] In some optional embodiments of this application, the target function is encapsulated with a user space call function, which is used to provide user space to call the target function.

[0068] It should be understood that, for the sake of brevity, some of the content described in the system embodiments will not be repeated in this method embodiment.

[0069] The processor heterogeneous system and inter-processor data access method provided in this application encapsulate a target function in the target processor's driver. When the CPU writes data to be read by the target processor into the target cache corresponding to the paged memory, the target function synchronizes the data in the target cache to the paged memory. Then, the data to be read by the target processor is copied from the paged memory to the target processor's memory. In this way, under a non-cache-coherent CPU architecture, the target processor can synchronize data not synchronized to the paged memory to the paged memory by calling the encapsulated target function. This ensures the accuracy of the copied data to be read by the target processor and avoids the problem of other processors in the processor heterogeneous system reading incorrect data when accessing the CPU's memory.

[0070] To facilitate understanding of the solutions in the embodiments of this application, the following example illustrates the process of the GPU accessing CPU data in a CPU+GPU heterogeneous processor system (since GPU memory is called video memory, unless otherwise specified in this example, memory refers to CPU memory by default), and where the CPU does not support cache coherence. First see Figure 4 As shown, Figure 4This illustrates the process by which the GPU accesses data from the CPU in a traditional heterogeneous processor system, including: First, in user space, the cudaMallocHost (a command for allocating paged memory) command is called to request memory A, and at the same time, the cudaMalloc (a command for allocating memory on the GPU) command is called to request video memory B.

[0071] Then, the system instructs the execution of copying the data to be read by the GPU (i.e., the aforementioned data to be read by the target processor) to memory A. It's important to note that if the CPU supports cache coherency, under the cache coherency mechanism, the CPU will automatically copy the data to be read by the GPU to memory A after writing it to the target cache. However, if the CPU does not support cache coherency, although user space instructs the copying of the data to be read by the GPU to memory A, in actual execution, the CPU only writes the data to be read by the GPU to the target cache corresponding to memory A. The data in the target cache is not synchronized to memory A; in this case, memory A still actually stores the original data.

[0072] Then, the cudaMemcpy interface (an interface that provides one-step data transfer) is called to trigger the operation of copying data from memory A to video memory B.

[0073] At this point, in the kernel space, the cudaMemcpy interface generates copy instructions for the GPU, and sends the copy instructions to the GPU by calling the kernel interface through the ioctl operation function.

[0074] Finally, at the hardware level, the GPU performs a DMA operation through the DMA controller to copy the data in memory A to video memory B.

[0075] Obviously, if the CPU does not support cache coherency during this process, the data actually read by the GPU is the original data in memory A, not the data to be read by the GPU.

[0076] Therefore, in this example solution, the target function is implemented in the GPU driver. The input parameters of this target function include: the handle to the paged memory and the cache refresh direction (memory operations are divided into two categories: one is CPU writes followed by GPU reads, in which case the cache needs to be refreshed, i.e., the cache content is synchronized to memory; the other is GPU writes followed by CPU reads, in which case invalid cache is required (even if the memory is in an invalid state), so that the CPU will skip the cache and read data from memory). The implementation logic of the target function is as follows: first, based on the handle to the paged memory, the DMA map information (i.e., DMA address, etc.) of the actual memory is found; then, based on the cache refresh direction, the system's DMA cache synchronization interface is called to perform cache synchronization operations on the paged memory.

[0077] The target function is encapsulated in an ioctl operation function, allowing it to be called from user space. This ioctl operation function is then further encapsulated in the GPU's user space for user access.

[0078] At this time, you can refer to Figure 5 As shown, Figure 5 This paper illustrates the process by which a GPU accesses CPU data in a processor heterogeneous system employing the present application, including: First, just like in the traditional way, the cudaMallocHost command is called in user space to allocate memory A, and the cudaMalloc command is called at the same time to allocate video memory B.

[0079] Then, instruct the execution of the operation to copy the data to be read by the GPU to memory A.

[0080] The difference is that at this time, the user-space cache refresh interface (i.e., the ioctl operation function) will be called, passing in the handle of the locked page memory and the cache refresh direction.

[0081] After receiving the user's ioctl call, the kernel mode executes the target function added in the kernel mode. First, it finds the DMA address of the locked page memory based on the handle of the locked page memory. Then, according to the passed cache refresh direction, it calls the corresponding system interface to perform cache synchronization processing (that is, synchronize the data to be read by the GPU in the target cache to memory A).

[0082] Then, after the user-space cache refresh interface returns a result indicating successful cache synchronization, the cudaMemcpy interface is called to trigger the operation of copying the data in memory A to video memory B.

[0083] At this point, in the kernel space, the cudaMemcpy interface generates copy instructions for the GPU, and sends the copy instructions to the GPU by calling the kernel interface through the ioctl operation function.

[0084] Finally, at the hardware level, the GPU performs a DMA operation through the DMA controller to copy the data in memory A to video memory B.

[0085] In this way, by implementing the target function in the GPU driver, an active cache refresh mechanism is added. Under the existing GPU usage architecture, the cache can be actively synchronized after user-space memory copying and other operations, ensuring that the GPU receives the correct data to be read by the GPU, so that the GPU can run normally.

[0086] Based on the same inventive concept, embodiments of this application also provide an electronic component, which may include the processor heterogeneous system provided in embodiments of this application.

[0087] In the embodiments of this application, electronic components refer to components that can be manufactured and sold independently, and that can cooperate with other electronic components to form larger electronic components or complete electronic devices. For example, they may include, but are not limited to, the circuit boards, processor modules, motherboards, etc., of the processor heterogeneous system provided in the embodiments of this application, but this is not a limitation.

[0088] Based on the same inventive concept, embodiments of this application also provide an electronic device, which may include the aforementioned electronic components.

[0089] In the embodiments of this application, the electronic device may also include more components. For example, it may also have an internal communication bus for communication between the CPU and the target processor; or it may also have an external communication interface, such as a USB (Universal Serial Bus) interface, a CAN (Controller Area Network) bus interface, etc.; or it may also have an information display component such as a display screen, but this is not a limitation.

[0090] In the embodiments of this application, the electronic device may be, but is not limited to, a mobile terminal (such as a smartphone, laptop, PDA, smart wearable device, etc.), a fixed terminal (such as a desktop host, desktop smart monitor, smart TV, etc.), or a non-terminal device (such as a server, etc.).

[0091] In the various embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly indicating the number, specific order, or primary and secondary relationship of the indicated technical features.

[0092] In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0093] In the embodiments provided in this application, and / or include three cases, for example, A and / or B include: A and B, A but not B, and B but not A.

[0094] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments.

[0095] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for inter-processor data access in a heterogeneous processor system, characterized in that, The processor heterogeneous system includes a CPU and a target processor; the target processor is a processor of a different type from the CPU; the driver for the target processor encapsulates a target function, which includes a first function, which is used to synchronize data in the target cache corresponding to the paged memory of the CPU to the paged memory when the target processor reads data from the memory of the CPU; The method is applied to the target processor, and the method includes: When the data to be read by the target processor is written into the target cache, the target function is called to synchronize the data to be read by the target processor in the target cache to the locked memory; The data to be read by the target processor is copied from the locked memory to the target processor's memory.

2. The inter-processor data access method in a heterogeneous processor system as described in claim 1, characterized in that, The target function further includes a second function, which is used to control the CPU's cache to be in an invalid state when the CPU reads data from memory; the method further includes: Write data to be read by the CPU into the CPU's memory; Calling the target function invalidates the CPU cache.

3. The inter-processor data access method in a heterogeneous processor system as described in claim 2, characterized in that, The target function includes a first input parameter; the first input parameter includes a cache refresh direction, wherein the cache refresh direction is: the target processor reads data from the CPU's memory, or the target processor writes data to the CPU's memory for the CPU to read; the method further includes: Before calling the target function to synchronize the data to be read by the target processor in the target cache to the locked page memory, or before calling the target function to invalidate the CPU cache, the target function is controlled to call the function to be executed according to the first input parameter; the function to be executed is the first function or the second function.

4. The inter-processor data access method in a heterogeneous processor system as described in claim 2, characterized in that, The target function includes a second input parameter; the second input parameter includes a handle to the locked memory; the method further includes: Before calling the target function to synchronize the data to be read by the target processor in the target cache to the paged memory, or before calling the target function to invalidate the CPU cache, the target function is controlled to determine the direct memory access (DMA) address of the paged memory based on the handle of the paged memory. Correspondingly, calling the target function to synchronize the data to be read by the target processor in the target cache to the locked page memory includes: synchronizing the data to be read by the target processor in the target cache to the memory corresponding to the DMA address through the first function; Correspondingly, writing data to be read by the CPU into the CPU's memory includes: writing the data to be read by the CPU into the memory corresponding to the DMA address.

5. The inter-processor data access method in a heterogeneous processor system as described in any one of claims 1-4, characterized in that, The target function is encapsulated with a user-space call function; the user-space call function is used to provide user space with the ability to call the target function.

6. A method for inter-processor data access in a heterogeneous processor system, characterized in that, The processor heterogeneous system includes a CPU and a target processor; the target processor is a processor of a different type from the CPU; the driver for the target processor encapsulates a target function, which includes a first function, which is used to synchronize data in the target cache corresponding to the paged memory of the CPU to the paged memory when the target processor reads data from the memory of the CPU; The method is applied to the CPU, and the method includes: The data to be read by the target processor is written into the target cache, so that the target processor can call the target function to synchronize the data to be read by the target processor in the target cache to the paged memory, and copy the data to be read by the target processor from the paged memory to the memory of the target processor.

7. The inter-processor data access method in a heterogeneous processor system as described in claim 6, characterized in that, The target function further includes a second function, which is used to control the CPU's cache to be in an invalid state when the CPU reads data from memory; the method further includes: If the CPU's cache is invalid, read the data to be read by the CPU from the CPU's memory.

8. A processor heterogeneous system, characterized in that, include: CPU and target processor; the target processor is a processor of a different type from the CPU; The driver program for the target processor encapsulates a target function, which includes a first function. The first function is used to synchronize the data in the target cache corresponding to the paged memory of the CPU to the paged memory when the target processor reads data from the memory of the CPU.

9. The processor heterogeneous system as described in claim 8, characterized in that, The target function also includes a second function, which is used to control the CPU's cache to be in an invalid state when the CPU reads data from memory.

10. The processor heterogeneous system as described in claim 9, characterized in that, The target function includes a first input parameter; the first input parameter includes a cache refresh direction, wherein the cache refresh direction is: the target processor reads data from the CPU's memory, or the target processor writes data to the CPU's memory for the CPU to read; When the cache refresh direction is that the target processor reads data from the CPU's memory, the target function executes the first function; when the cache refresh direction is that the target processor writes data to the CPU's memory for the CPU to read, the target function executes the second function.

11. The processor heterogeneous system as described in claim 9, characterized in that, The target function includes a second input parameter; the second input parameter includes a handle to the paged memory; the handle to the paged memory is used to determine the direct memory access (DMA) address of the paged memory.

12. The processor heterogeneous system as described in any one of claims 8-11, characterized in that, The target function is encapsulated with a user-space call function; the user-space call function is used to provide user space with the ability to call the target function.

13. An electronic component, characterized in that, Including the processor heterogeneous system as described in any one of claims 8-12.

14. An electronic device, characterized in that, Includes the electronic components as described in claim 13.

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