Bus control unit, processing device, system-on-chip, bus control method, and computer storage medium

Abstract

The embodiment of the invention provides a bus control unit, a processing device, a system on chip, a bus control method and a computer storage medium. The bus control unit comprises a compression execution unit which adopts a compression algorithm to compress the sparse data to obtain compressed data and compression attribute information; the compression control unit is used for generating a data signal carrying the compression attribute information and the compression data according to an instruction format of a communication bus and sending the data signal through the communication bus, and the compression attribute information is used for decompressing the compression data to obtain the sparse data.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to a bus control unit, a processing device, a system-on-a-chip, a bus control method, and a computer storage medium. Background Technology

[0002] The sparsity of parameter data in neural networks refers to the presence of a large number of zero or near-zero values ​​in the weight matrix or eigenvectors. Data sparsity is widespread in machine learning, for example, in sparse feature data in graph neural networks or pruned networks. This sparsity can be utilized in conjunction with model pruning and quantization techniques to further reduce model size and accelerate the inference process.

[0003] For example, during forward and backward propagation, only the terms corresponding to non-zero weights are calculated, which can reduce a large number of multiplication operations and thus accelerate the training process. Alternatively, algorithmic implementations such as sparse matrix multiplication for sparse data can further improve computational efficiency.

[0004] For example, during the training or inference process of a neural network, when caching sparse data, the sparsity of the data can reduce the memory usage of the neural network.

[0005] To further improve the parallel processing of sparse data in neural networks across different processing devices, it is desirable to provide a reliable bus control scheme that efficiently transmits sparse data between different processing devices via a communication bus. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a bus control unit, a processing device, a system-on-a-chip, a bus control method, and a computer storage medium to solve the above problems.

[0007] According to a first aspect of the present invention, a bus control unit is provided, comprising: a compression execution unit, which uses a compression algorithm to compress sparse data to obtain compressed data and compression attribute information; and a compression control unit, which generates a data signal carrying the compression attribute information and the compressed data according to the instruction format of a communication bus, and transmits the data signal via the communication bus, wherein the compression attribute information is used to decompress the compressed data to obtain the sparse data.

[0008] According to a second aspect of the present invention, a processing apparatus is provided, comprising: a bus control unit as described in the first aspect.

[0009] According to a third aspect of the present invention, a system-on-a-chip is provided, comprising: a processing device according to the second aspect; and a communication bus through which different processing devices communicate.

[0010] According to a fourth aspect of the present invention, a bus control method is provided, comprising: compressing sparse data using a compression algorithm to obtain compressed data and compression attribute information; generating a data signal carrying the compression attribute information and the compressed data according to the instruction format of a communication bus, wherein the compression attribute information is used to decompress the compressed data to obtain the sparse data; and transmitting the data signal via the communication bus.

[0011] According to a fifth aspect of the present invention, a bus control unit is provided, comprising: a processor, a memory, an internal bus interface, and an internal bus, wherein the processor, the memory, and the internal bus interface communicate with each other via the internal bus; the memory is used to store at least one executable instruction, the executable instruction causing the processor to perform the method as described in the fourth aspect.

[0012] According to a sixth aspect of the present invention, a computer storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in the fourth aspect.

[0013] In the embodiment of the present invention, the compression execution unit compresses sparse data to obtain compressed data and compression attribute information. The compression control unit can encapsulate the compressed data and compression attribute information into the instruction format of the communication bus, thereby reusing the instruction format of the communication bus to transmit the compressed data and compression attribute information. This enables the bus control unit on the receiving side to decompress the compressed data according to the compression attribute information, improving the transmission efficiency of the communication bus and helping to reduce or avoid caching of sparse data, thereby improving the computing efficiency of the processing device. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0015] Figure 1 Here are some example schematic block diagrams of on-chip systems.

[0016] Figure 2 This is a schematic structural block diagram of a bus control unit according to some embodiments of the present invention.

[0017] Figure 3 for Figure 2 A schematic diagram of some examples of compression algorithms in the embodiments.

[0018] Figure 4 for Figure 2 A schematic block diagram of a bus control unit, representing some examples of embodiments.

[0019] Figure 5 for Figure 2 A schematic block diagram of a bus control unit, representing some examples of embodiments.

[0020] Figure 6 This is a flowchart illustrating the steps of a bus control method according to other embodiments of the present invention.

[0021] Figure 7 This is a schematic diagram of the bus control unit according to other embodiments of the present invention. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0023] The specific implementation of the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0024] To improve the parallel processing of sparse data in neural networks across different processing devices, it is desirable to provide a reliable bus control scheme that efficiently transmits sparse data between different processing devices via communication buses such as the Advanced Dextensible Interface (AXI) bus.

[0025] Figure 1 Here are some example schematic block diagrams of on-chip systems. Figure 1 The system-on-chip 100 includes N processing devices 110 (i.e., processing devices 0 to N-1) acting as AXI master devices and M processing devices 130 (i.e., processing devices 0 to M-1) acting as AXI slave devices. The processing devices can be used for computational processing (e.g., PE) and storage processing (e.g., memory). Any processing device 110 can perform bus communication with any processing device 130 via an AXI bus 120.

[0026] In some examples, the AXI bus protocol is based on burst-based transfers. For instance, some AXI bus protocols define read address channels, read data channels, write address channels, and write data channels. The address channel carries control messages to describe the attributes of the data being transferred. Data transfer is implemented using the write channel to transfer data from the "master device" to the "slave device." The "slave device" uses the write response channel to complete a write transfer. The read channel is used to transfer data from the "slave device" to the "master device."

[0027] AXI is a data transmission protocol based on a VALID / READY (i.e., enable / ready to receive) handshake mechanism. The source end uses VALID to indicate that the address / control signals and data are valid, and the destination end uses READY to indicate that it can accept information.

[0028] Specifically, in the read / write address channel, each read and write transfer has its own address channel, which carries the address control information for that transfer. In the read data channel, the read data carries the read data and read response signals, including a data bus (8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024 bits) and a read response signal indicating the completion of the read transfer. In the write data channel, the data is considered buffered; the "master" can initiate a new write transfer without waiting for the "slave" to acknowledge the previous write transfer. The write channel includes a data bus (8 / 16…1024 bits) and byte lines (used to indicate the validity of 8-bit data signals).

[0029] The signals for each channel are defined as follows:

[0030] global signals

[0031] signal name signal source Signal Description ACLK Clock source Global clock signal ARESETn Reset source Global reset signal, active low

[0032] Write address channel signal

[0033]

[0034]

[0035] Write data channel signal

[0036] signal name signal source Signal Description wid main equipment ID tag for one-time write transfer wdata main equipment Write data wuser main equipment Extended signal wvalid main equipment The enable signal indicates that the write operation was successful. wready From the equipment The receive ready signal indicates that write data can be received.

[0037] Read address channel signal

[0038]

[0039] Read data channel signal

[0040]

[0041]

[0042] Figure 2 This is a schematic structural block diagram of a bus control unit according to some embodiments of the present invention. The bus control unit 200 includes a compression execution unit 210 and a compression control unit 220.

[0043] Specifically, the compression execution unit 210 uses a compression algorithm to compress sparse data to obtain compressed data and compression attribute information.

[0044] For example, sparse data can be parameter data for neural networks such as graph neural networks or pruned neural networks. Sparse data can be data containing repeating zero characters or other repeating characters. The bus control unit can obtain parameter data from functional units in the processing device, which are used to perform calculations on the parameter data of neural networks such as graph neural networks or pruned neural networks.

[0045] For example, in some cases, the compression algorithm is the Run-Length Encoding (RLE) algorithm, and the compression attribute information is a sequence of descriptive characters, in which descriptive characters are used to describe repeating characters in sparse data.

[0046] In addition, the compression control unit 220 generates a data signal carrying compression attribute information and compressed data according to the instruction format of the communication bus. The compression attribute information is used to decompress the compressed data to obtain sparse data.

[0047] For example, encoded attribute information is transmitted via signals from the wuser / ruser port of the AXI bus. As another example, the bus control unit can support at least uncompressed and compressed modes. Uncompressed mode is used to transmit dense data (i.e., non-sparse data) between different processing devices, while compressed mode is used to transmit sparse data between different processing devices.

[0048] In the embodiment of the present invention, the compression execution unit compresses sparse data to obtain compressed data and compression attribute information. The compression control unit can encapsulate the compressed data and compression attribute information into the instruction format of the communication bus, thereby reusing the instruction format of the communication bus to transmit the compressed data and compression attribute information. This enables the bus control unit on the receiving side to decompress the compressed data according to the compression attribute information, improving the transmission efficiency of the communication bus and helping to reduce or avoid caching of sparse data, thereby improving the computing efficiency of the processing device.

[0049] In some examples, the compression control unit is specifically used to: generate a first data signal carrying write compressed data and write compressed attribute information according to the write instruction format of the communication bus, and send the first data signal to the downstream bus control unit via the communication bus. That is, by compressing sparse data, the instruction format is reused to transmit the compression result of sparse data to the downstream bus control unit, thereby improving the efficiency of write data transmission between the local processing device and the downstream processing device.

[0050] In other examples, the bus control unit includes a decompression control unit and a decompression execution unit. The decompression control unit parses the data signal according to the instruction format of the communication bus to obtain compressed data and compression attribute information. The decompression execution unit decompresses the compressed data based on the compression attribute information to obtain sparse data. In other words, by compressing sparse data to obtain compressed data and compression attribute information, the decompression control unit can decompress the compressed data based on the compression attribute information, improving the transmission efficiency of the communication bus, reducing or avoiding the caching of sparse data, and thus improving the computational efficiency of the processing device.

[0051] like Figure 3 As shown, sparse data is compressed by the bus control unit 200 in the master device 110 to obtain compressed data, which is then transmitted to the bus control unit 200 in the slave device 120 via the AXI bus 130. Alternatively, sparse data is compressed by the bus control unit 200 in the slave device 120 to obtain compressed data, which is then transmitted to the bus control unit 200 in the master device 110 via the AXI bus 130. Embodiments of the present invention implement compression processing independent of the processing architecture because compression within the bus control unit of the AXI bus does not affect the logic of the functional units.

[0052] In some specific examples, sparse data can be:

[0053] 7 7 7 5 0 0 0 4 4 0 0 0 0 0 2 2 2 2 0 0 0 0 0 0 4 0 0 9 0 0 0 0

[0054] The sparse data consists of 32*4 bytes. After compression using the first compression algorithm, the resulting compressed data is:

[0055] 7 5 0 4 0 2 0 4 0 9 0

[0056] The compression attribute information of the compressed data is as follows:

[0057] 3 1 3 2 5 4 6 1 2 1 4

[0058] In this context, the compression mode of the first compression algorithm (e.g., vanilla run-length encoding) indicates the number of repetitions of the corresponding byte in the compressed data for each byte in the compression attribute information. Accordingly, the compression ratio = [11 * 4 bytes (compressed data) + 11 bytes (wuser)] / 32 * 4 bytes (original data) = 44.1%.

[0059] Alternatively, after compression using the second compression algorithm, the resulting compressed data is:

[0060] 7 7 7 5 3 4 4 5 2 2 2 2 6 4 2 9 4

[0061] The compression attribute information of the compressed data is as follows:

[0062] 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 1

[0063] The compression mode (zero encoding) of the first compression algorithm indicates whether each byte in the compression attribute information corresponds to a zero byte in the compressed data. If the corresponding byte is non-zero, then the byte is zero; if the corresponding byte is zero, then the byte indicates the number of repetitions of zero bytes. Accordingly, the compression ratio = [17 * 4 bytes (compressed data) + (17 bits / 8 (wuser))] / 32 * 4 bytes (original data) = 54.7% (zero encoding).

[0064] In some embodiments, such as Figure 4 The processing device containing the bus control unit shown serves as the master device of the communication bus and includes a write operation unit 430. The write operation unit 430 includes a compression execution unit 433 and a compression control unit, which includes a compression instruction unit 431 and a write data unit 432.

[0065] Without loss of generality, the write instruction format includes a write extension signal and a write data signal. Specifically, the compression control unit is used to: generate a write extension signal carrying write compression attribute information and a write data signal carrying write compressed data, and send the write extension signal and write data signal in parallel to the downstream bus control unit via the communication bus. In some examples, the write extension signal can be the wuser signal in the write compressed data channel. It should be understood that the write extension signal carries the write compression attribute information of the write compressed data, and the write data signal carries the write compressed data. In bus protocols such as AXI, the instruction format of the write extension signal and the write data signal is fully reused to transmit compressed sparse data to the downstream bus control unit.

[0066] In some examples, the compression execution unit 433 receives a compression control instruction and a write data instruction including sparse data, and compresses the sparse data (e.g., write data) in the write data instruction according to the compression control instruction to obtain write compressed data and write compression attribute information. In some examples, the compression instruction unit 431 may receive a compression control instruction (enc_cmd) and transmit the compression control instruction from the write operation unit 430 to the compression execution unit 433.

[0067] Furthermore, the compression execution unit 433 transmits the write compressed data to the write data unit 432, and the write data unit 432 generates a write data signal (e.g., wdata) carrying the write compressed data. The compression execution unit 433 transmits write compression attribute information to the compression instruction unit 431, and the compression instruction unit 431 generates a write extension signal (e.g., wuser) carrying the write compression attribute information. For example, the compression instruction unit 431 responds to a compression control command and waits for the compression execution unit 433 to send the write compression attribute information. After obtaining the write compression attribute information, it generates the write extension signal.

[0068] Furthermore, such as Figure 5 The processing device of the bus control unit shown can be used as a slave device of the communication bus, including a write operation unit 530. The write operation unit 530 includes a decompression execution unit 533 and a decompression control unit, which includes a decompression instruction unit 531 and a write data unit 532.

[0069] Without loss of generality, the decompression control unit is specifically used to parse the write data signal and write extension signal according to the write instruction format of the communication bus to obtain the write compressed data and write compression attribute information. The decompression execution unit is specifically used to decompress the write compressed data and write compression attribute information to obtain sparse data. In other words, by parsing the write data signal and write extension signal received from the upstream bus control unit to obtain the write compressed data and write compression attribute information, the write data signal and write extension signal in the instruction format are reused, improving the transmission efficiency of write data between the local processing device and the upstream processing device.

[0070] In some examples, the decompression instruction unit 531 parses the write extension signal according to the instruction format to obtain write compression attribute information, and parses the write data signal according to the instruction format to obtain write compressed data. For example, the decompression instruction unit 531 can obtain the write extension signal from the upstream bus control unit, and also obtain the write data signal from the upstream bus control unit.

[0071] Further, the decompression execution unit 533 obtains write compression attribute information and write compression data from the decompression instruction unit 531. The decompression execution unit 533 decompresses the write compression data according to the write compression attribute information to obtain sparse data. The write data unit 532 responds to the write instruction signal and writes the sparse data into the registers of the local processing device or the local memory.

[0072] It should be understood that the write data unit 432 may send an enable signal (e.g., wvalid) to the decompression execution unit 533, and the decompression execution unit 533 may send a receive ready signal (e.g., wready) to the write data unit 432, such that when both the enable signal and the receive ready signal are valid, a write data signal (e.g., wdata) carrying the write compressed data is triggered to be transmitted between the write data unit 432 and the decompression execution unit 533.

[0073] Furthermore, the bus control unit may also include an address instruction unit 410, which can receive a receive ready signal from the address channel from the downstream bus control unit and send a ready signal to the compression execution unit 433, so that the compression execution unit 433 responds to the receive ready signal and performs compression on the sparse data in the write data instruction according to the compression control instruction.

[0074] Furthermore, the address instruction unit 410 can receive address instructions (e.g., ax_addr) and send an address signal carrying the write address to the downstream bus control unit. The address instruction unit 410 can also send an enable signal (e.g., axvalid) to the address instruction unit 510, and the address instruction unit 510 sends a receive ready signal (e.g., axready) to the address instruction unit 410, such that when both the enable signal and the receive ready signal are valid, the address signal (e.g., axaddr) and the write indication signal are triggered for transmission between the address instruction unit 510 and the address instruction unit 410.

[0075] The bus control unit in the processing device, acting as the master device, may further include a parameter instruction unit 420. The parameter instruction unit 420 receives bus control instructions (e.g., axcmd), parses the bus control instructions to obtain various transmission transaction parameters, and generates data parameter signals carrying different transmission transaction parameters. For example, transmission transaction parameters include the transmission transaction type (e.g., burst type in the AXI bus protocol), the upper limit of the data length transmitted in the transmission transaction (e.g., the upper limit of the number of bytes in a burst transmission in the AXI bus protocol), and the actual data length transmitted in the transmission transaction (e.g., the actual number of bytes in a burst transmission in the AXI bus protocol). Accordingly, the parameter instruction unit 420 may also send various data parameter signals to downstream bus control units. The bus control instructions may also represent read indication signals and write indication signals.

[0076] Furthermore, the compression instruction unit 431 generates the data length for writing compressed data based on compression attribute information (e.g., enc_info), and sends the data length for writing compressed data (e.g., via axcmd_cmpr) to the parameter instruction unit 420. The parameter instruction unit 420 writes the data length for writing compressed data into the data parameter signal corresponding to each data item. Without loss of generality, the bus control unit also includes a parameter instruction unit that adds the data length of compressed data to the data length field describing sparse data, generates a data parameter signal, and sends the data parameter signal and the data signal in parallel to the downstream bus control unit. It should be understood that adding the data length of compressed data to the data length field describing sparse data, instead of the data length of the sparse data itself, facilitates the parsing of the data signal based on the data length of the compressed data. In bus protocols such as AXI, this further improves the reliability of compressed data parsing while transmitting compressed data of sparse data using the instruction format of the multiplexed data parameter signal.

[0077] The bus control unit in the processing device of the slave device may also include an address instruction unit 510. The address instruction unit 510 can receive the address signal in the address channel from the upstream bus control unit and send a decompression request signal to the decompression execution unit 533 in response to the address signal, so that the decompression execution unit 533 responds to the decompression request signal and decompresses the write compressed data in the write data signal according to the write compression attribute information.

[0078] In addition, the address instruction unit 510 can also send a receive ready signal to the address instruction unit 410 and receive an enable signal sent by the address instruction unit 410, so that the address instruction unit 410 and the address instruction unit 510 trigger the transmission of the address signal and the write instruction signal when both the enable signal and the receive ready signal are valid.

[0079] The bus control unit may also include a parameter instruction unit 520, which receives data parameter signals carrying different transmission transaction parameters sent by the upstream bus control unit. For example, transmission transaction parameters include the transmission transaction type, the upper limit of the data length transmitted in the transmission transaction, and the actual data length transmitted in the transmission transaction. Furthermore, the decompression instruction unit 531 can obtain the data length of the written compressed data from the parameter instruction unit 520 and parse the written compressed data from the write data signal based on the data length. Without loss of generality, the parameter instruction unit is also used to: parse the data reference signal to obtain the data length of the compressed data. The decompression control unit is also used to: parse the data signal based on the data length to obtain the compressed data, thereby improving the reliability of parsing the compressed data.

[0080] In other embodiments, the bus control unit in the processing apparatus of the slave device includes a compression unit 540, which includes a compression execution unit 543 and a compression control unit. The compression control unit includes a compression instruction unit 541 and a data read unit 542. Generally, the compression control unit can obtain sparse data from the upstream bus control unit, generate a second data signal carrying compressed data and compressed attribute information according to the read instruction format of the communication bus, and send the second data signal to the downstream bus control unit via the communication bus. That is, by compressing the sparse data and multiplexing the instruction format to transmit the compressed result of the sparse data to the downstream bus control unit, the efficiency of data transmission between the local processing device and the downstream processing device is improved.

[0081] The bus control unit in the processing device, acting as the master device, includes a read operation unit 440. The read operation unit 440 includes a decompression execution unit 443 and a decompression control unit. The decompression control unit includes a decompression instruction unit 441 and a read data unit 442. Generally speaking, the decompression control unit is specifically used to: parse the read data signal and the read extension signal according to the read instruction format of the communication bus to obtain read compressed data and read compressed attribute information (e.g., decoding info). The decompression execution unit is specifically used to decompress the read compressed data and read compressed attribute information to obtain sparse data (e.g., read data). In other words, by parsing the read data signal (e.g., rdata) and the read extension signal (e.g., rdata) received from the downstream bus control unit to obtain read compressed data and read compressed attribute information, the read data signal and read extension signal in the instruction format are reused, improving the transmission efficiency of read data between the local processing device and the downstream processing device.

[0082] For example, the decompression instruction unit 441 generates a write extension signal carrying read compression attribute information in response to a compression control instruction, and then sends the read extension signal to the compression instruction unit 541. The read data unit 542 obtains the read indication signal, parses the read indication signal according to the read instruction format of the communication bus, and reads sparse data from the registers or local memory of the local processing device. The compression instruction unit 541 reads the extension signal from the upstream processing device and parses the read extension signal to obtain the read compression attribute information.

[0083] The compression execution unit 543 obtains read compression attribute information from the compression instruction unit 541 and sparse data from the read data unit 542. It compresses the sparse data according to the read compression attribute information to obtain read compressed data.

[0084] The compression execution unit 543 generates a read data signal carrying the read compressed data and sends the read data signal to the read data unit 442, so that the read data unit 442 can parse the read data signal to obtain the read compressed data.

[0085] The decompression execution unit 443 obtains read compression attribute information from the decompression instruction unit 441 and read compressed data from the read data unit 442. It then decompresses the read compressed data according to the read compression attribute information to obtain sparse data.

[0086] It should be understood that the decompression instruction unit 441 can parse the read extension signal according to the read instruction format of the communication bus to obtain the read compression attribute information. The read data unit 442 can parse the read data signal according to the read instruction format of the communication bus to obtain the read compressed data.

[0087] The decompression execution unit 443 decompresses the read compressed data and read compressed attribute information to obtain sparse data, and then generates a read response signal carrying the sparse data for the read indication signal, which is fed back to the functional unit of the local processing device.

[0088] It should be understood that the read data unit 442 can send an enable signal (e.g., rvalid) to the compression execution unit 543, and the compression execution unit 543 can send a receive ready signal (e.g., rready) to the read data unit 442, so that the read data unit 442 and the compression execution unit 543 trigger the transmission of the read data signal (e.g., rdata) when both the enable signal and the receive ready signal are valid.

[0089] Without loss of generality, the parameter instruction unit in the bus control unit of the processing device, which is the master device, is also used to: parse the data reference signal to obtain the data length of the compressed data. The decompression control unit is also used to: parse the data signal according to the data length to obtain the compressed data, thereby improving the reliability of parsing the compressed data.

[0090] The following will combine Figure 6 Bus control methods according to other embodiments of the present invention are described. Figure 6 Bus control methods include:

[0091] S610: Uses a compression algorithm to compress sparse data to obtain compressed data and compressed attribute information.

[0092] S620: Generate a data signal carrying the compression attribute information and the compressed data according to the instruction format of the communication bus, wherein the compression attribute information is used to decompress the compressed data to obtain the sparse data.

[0093] S630: Transmit the data signal via the communication bus.

[0094] In the embodiment of the present invention, the compression execution unit compresses sparse data to obtain compressed data and compression attribute information. The compression control unit can encapsulate the compressed data and compression attribute information into the instruction format of the communication bus, thereby reusing the instruction format of the communication bus to transmit the compressed data and compression attribute information. This enables the bus control unit on the receiving side to decompress the compressed data according to the compression attribute information, improving the transmission efficiency of the communication bus and helping to reduce or avoid caching of sparse data, thereby improving the computing efficiency of the processing device.

[0095] In other embodiments, generating a data signal carrying the compression attribute information and the compressed data according to the instruction format of the communication bus includes: generating a first data signal carrying write compressed data and write compression attribute information according to the write instruction format of the communication bus, and sending the first data signal to a downstream bus control unit via the communication bus.

[0096] In other embodiments, the write instruction format includes a write extension signal and a write data signal. Generating a first data signal carrying write compressed data and write compression attribute information according to the write instruction format of the communication bus includes: generating a write extension signal carrying the write compression attribute information, and generating a write data signal carrying the write compressed data. Sending the first data signal to a downstream bus control unit via the communication bus includes: sending the write extension signal and the write data signal in parallel to the downstream bus control unit via the communication bus.

[0097] In other embodiments, the bus control method further includes: adding the data length of the compressed data to a data length field describing the sparse data, generating a data parameter signal, and sending the data parameter signal and the data signal in parallel to the downstream bus control unit.

[0098] In other embodiments, generating a data signal carrying the compression attribute information and the compressed data according to the instruction format of the communication bus includes: generating a second data signal carrying read compressed data and read compression attribute information according to the read instruction format of the communication bus, and sending the second data signal to a downstream bus control unit via the communication bus.

[0099] In other embodiments, the bus control method further includes: parsing data signals according to the instruction format of the communication bus to obtain compressed data and compression attribute information; and decompressing the compressed data according to the compression attribute information to obtain sparse data.

[0100] In other embodiments, according to the instruction format of the communication bus, data signals are parsed to obtain compressed data and compression attribute information, including: parsing read data signals and read extended signals according to the read instruction format of the communication bus to obtain read compressed data and read compression attribute information. Based on the compression attribute information, the compressed data is decompressed to obtain sparse data, including: decompressing the read compressed data and the read compression attribute information to obtain sparse data.

[0101] In other embodiments, according to the instruction format of the communication bus, data signals are parsed to obtain compressed data and compression attribute information, including: according to the write instruction format of the communication bus, write data signals and write extension signals are parsed respectively to obtain write compressed data and write compression attribute information. Based on the compression attribute information, the compressed data is decompressed to obtain sparse data, including: decompressing the write compressed data and the write compression attribute information to obtain sparse data.

[0102] In other embodiments, the bus control method further includes: parsing the data reference signal to obtain the data length of the compressed data; and parsing the data signal according to the data length to obtain the compressed data.

[0103] In other embodiments, the compression algorithm is a run-length encoding algorithm, and the compression attribute information is a descriptive character sequence, wherein the descriptive characters in the descriptive character sequence are used to describe the repeating characters in the sparse data.

[0104] The specific implementation of each step in the bus control method can be found in the description of the corresponding unit in the above-described embodiment of the bus control unit, which also has corresponding beneficial effects, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the bus control method described above can be referred to the description of the corresponding unit in the embodiment of the bus control unit, and will not be repeated here.

[0105] Reference Figure 7The diagram shows a structural schematic of a bus control unit according to another embodiment of the present invention. The specific implementation of the bus control unit is not limited by the specific embodiments of the present invention.

[0106] like Figure 7 As shown, the bus control unit may include: a processor 702 for executing program 710, an internal bus interface 704, a memory 706, and an internal bus 708.

[0107] The processor, internal bus interface, and memory communicate with each other through the internal bus.

[0108] An internal bus interface is used to communicate with other bus control units or servers.

[0109] The processor is used to execute programs, specifically the relevant steps in the above method embodiments.

[0110] Specifically, the program may include program code, which includes computer operation instructions.

[0111] The processor may be a CPU, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. The one or more processors included in a smart device may be processors of the same type, such as one or more CPUs; or they may be processors of different types, such as one or more CPUs and one or more ASICs.

[0112] Memory is used to store programs. Memory may include high-speed RAM, and may also include non-volatile memory, such as at least one disk drive.

[0113] The program may include multiple computer instructions, and specifically, the program may use multiple computer instructions to cause the processor to execute the bus control method described in any of the foregoing method embodiments.

[0114] The specific implementation of each step in the program can be found in the corresponding descriptions of the steps, modules, or units in the above method embodiments, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described device, equipment, or module can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0115] This invention also provides a computer storage medium storing a computer program thereon, which, when executed by a processor, implements the method described in any of the foregoing method embodiments. The computer storage medium includes, but is not limited to, compact disc read-only memory (CD-ROM), random access memory (RAM), floppy disk, hard disk, or magneto-optical disk.

[0116] This invention also provides a computer program product, including computer instructions that instruct a computing device to execute the bus control method in the above-described plurality of method embodiments.

[0117] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of the present invention can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0118] The methods described above according to embodiments of the present invention can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and subsequently stored in a local recording medium, downloaded via a network. Thus, the methods described herein can be stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA)). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., random access memory (RAM), read-only memory (ROM), flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0119] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments of the present invention.

[0120] The above embodiments are only used to illustrate the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A bus control unit, comprising: The compression execution unit uses a compression algorithm to compress sparse data, obtaining compressed data and compression attribute information; The compression control unit generates a data signal carrying the compression attribute information and the compressed data according to the instruction format of the communication bus, and sends the data signal via the communication bus, wherein the compression attribute information is used to decompress the compressed data to obtain the sparse data.

2. The bus control unit according to claim 1, wherein, The compression control unit is specifically used for: According to the write instruction format of the communication bus, a first data signal carrying write compressed data and write compressed attribute information is generated, and the first data signal is sent to the downstream bus control unit via the communication bus.

3. The bus control unit according to claim 2, wherein, The write instruction format includes write extension signals and write data signals; The compression control unit is specifically used to: generate a write extension signal carrying the write compression attribute information, and generate a write data signal carrying the write compression data, and send the write extension signal and the write data signal in parallel to the downstream bus control unit via the communication bus.

4. The bus control unit according to claim 1, wherein, The bus control unit further includes a parameter instruction unit, which adds the data length of the compressed data to the data length field describing the sparse data, generates a data parameter signal, and sends the data parameter signal and the data signal in parallel to the downstream bus control unit.

5. The bus control unit according to claim 1, wherein, The compression control unit is specifically used to: generate a second data signal carrying read compression data and read compression attribute information according to the read instruction format of the communication bus, and send the second data signal to the downstream bus control unit via the communication bus.

6. The bus control unit according to claim 1, wherein, The bus control unit also includes: The decompression control unit parses the data signals according to the instruction format of the communication bus to obtain compressed data and compression attribute information; The decompression execution unit decompresses the compressed data according to the compression attribute information to obtain sparse data.

7. The bus control unit according to claim 6, wherein, The decompression control unit is specifically used to: parse the read data signal and the read extension signal according to the read command format of the communication bus to obtain the read compressed data and read compressed attribute information; The decompression execution unit is specifically used to: decompress the read compressed data and the read compressed attribute information to obtain sparse data.

8. The bus control unit according to claim 6, wherein, The decompression control unit is specifically used to: parse the write data signal and the write extension signal according to the write instruction format of the communication bus, and obtain the write compressed data and write compressed attribute information; The decompression execution unit is specifically used to: decompress the write compressed data and the write compressed attribute information to obtain sparse data.

9. The bus control unit according to claim 1, wherein, The parameter instruction unit is also used to: parse the data reference signal to obtain the data length of the compressed data; The decompression control unit is further configured to: parse the data signal according to the data length to obtain the compressed data.

10. The bus control unit according to claim 1, wherein, The compression algorithm is a run-length encoding algorithm, and the compression attribute information is a descriptive character sequence. The descriptive characters in the descriptive character sequence are used to describe the repeated characters in the sparse data.

11. A processing apparatus, comprising: The bus control unit according to any one of claims 1-10.

12. A system-on-a-chip, comprising: The processing apparatus according to claim 11; A communication bus is used for communication between different processing devices.

13. A bus control method, comprising: A compression algorithm is used to compress sparse data to obtain compressed data and compressed attribute information; According to the instruction format of the communication bus, a data signal carrying the compression attribute information and the compressed data is generated, wherein the compression attribute information is used to decompress the compressed data to obtain the sparse data; The data signal is transmitted via the communication bus.

14. The method according to claim 13, wherein, The method further includes: Based on the instruction format of the communication bus, the data signal is parsed to obtain compressed data and compression attribute information; Based on the compression attribute information, the compressed data is decompressed to obtain sparse data.

15. A bus control unit, comprising: The processor, memory, internal bus interface, and internal bus are connected, and the processor, memory, and internal bus interface communicate with each other through the internal bus. The memory is used to store at least one executable instruction that causes the processor to perform the method according to claim 13 or 14.

16. A computer storage medium having a computer program stored thereon, which, when executed by a processor, implements the method according to claim 13 or 14.

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