Multi-objective optimization method for thermal vibration stress and return loss of TSV interconnection structure

Abstract

The invention belongs to the field of electronic packaging reliability, and provides a TSV interconnection structure thermal vibration stress and return loss multi-objective optimization method. The method comprises the following steps: firstly, establishing a 3D-TSV laminated chip packaging interconnection structure simulation analysis model based on ANSYS and HFSS; carrying out thermal structure coupling analysis, random vibration loading analysis and return loss analysis; determining a parameter level of the TSV interconnection structure; 17 TSV interconnection structure parameter response surface test groups are designed, and a corresponding simulation model is established and analyzed; fitting a non-linear relation mapping relational expression between the TSV interconnection structure parameters and thermal structure coupling stress, random vibration stress and return loss according to response surface test data; and carrying out multi-objective optimization on the TSV interconnection structure by using an NSWOA optimization algorithm, calculating the weight of thermal structure coupling stress, random vibration stress and return loss by using an entropy weight theory, and sorting an optimal solution set by using a rank sum ratio synthesis method to obtain an optimal parameter level combination. And certain guidance is provided for the reliability design of the TSV interconnection structure.

Description

Technical Field

[0001] This invention relates to the field of electronic packaging technology, and in particular to a multi-objective optimization method for thermal shock stress and return loss of TSV interconnect structures. Background Technology

[0002] With the rapid development of information technology, the demand for high-performance, highly integrated, and low-power electronic systems is increasing. Three-dimensional through-silicon via (3D-TSV) technology, as one of the key technologies to achieve this goal, is particularly important. However, the complexity of the 3D-TSV stacked chip package interconnect structure means it may be subject to multi-physics coupling loading during use, posing numerous challenges in practical applications. The high-density integration of TSV technology leads to a sharp increase in internal chip power consumption, and the inefficient dissipation of heat can easily cause localized high temperatures and thermal stress concentration, thus affecting the stability and reliability of the TSV structure. During the use of TSV devices, random vibrations may cause fatigue damage to the TSV and its surrounding packaging materials, potentially leading to fracture and failure. With the continuous increase in data transmission rates, the requirements for signal integrity are also becoming increasingly stringent; therefore, return loss analysis of TSV interconnect junctions is also essential.

[0003] Response surface methodology (RSM) is a mathematical method that uses polynomial functions to approximate implicit limit state functions or input-output relationships of complex systems through a series of deterministic experiments. First proposed by Box et al., RSM has been widely applied in fields such as mechanics and electronics.

[0004] The Non-Dominated Sorting Whale Optimization Algorithm (NSWOA) is a multi-objective whale optimization algorithm based on non-dominated sorting, proposed by Pradeep Jangir and Narottam Jangir in 2017. NSWOA is developed from the Whale Optimization Algorithm (WOA) by incorporating multi-objective optimization theory. It introduces non-dominated sorting, crowding calculation, and an elite retention strategy, overcoming the limitation of traditional whale optimization algorithms in directly handling multi-objective optimization problems. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-objective optimization method for thermal stress and return loss in TSV interconnect structures. Its features include:

[0006] A simulation analysis model of the interconnect structure of 3D-TSV stacked chip packaging was established based on ANSYS and HFSS.

[0007] Thermal structural coupling analysis, random vibration loading analysis, and return loss analysis were performed to obtain the maximum stress and return loss of the TSV interconnect structure.

[0008] Determine the parameter levels of the TSV interconnect structure;

[0009] Seventeen combinations of TSV interconnect structure parameters were obtained using the Box-Behnken experimental design method. Corresponding simulation models were established and analyzed.

[0010] Data on thermal structural coupling stress, random vibration stress, and return loss under various parameter level combinations were obtained.

[0011] Based on the data, a nonlinear mapping relationship between the TSV interconnect structure parameters and the thermal structural coupling stress, random vibration stress, and return loss was fitted.

[0012] The NSWOA optimization algorithm is used to perform multi-objective optimization on the TSV interconnect structure. The entropy weight theory is used to calculate the weights of thermal structural coupling stress, random vibration stress and return loss, and the rank-sum ratio comprehensive method is used to sort the optimization solution set to obtain the optimal parameter level combination.

[0013] Optionally, when performing structural analysis on the finite element model of the 3D-TSV stacked chip, the boundary conditions are set to be full constraints in the X, Y and Z directions at the four corners of the bottom surface of the PCB.

[0014] Optionally, when performing random vibration analysis on the finite element model of the 3D-TSV stacked chip, the loading condition shall be selected as the US military standard MIL-STD NAVMAT P9492. Attached Figure Description

[0015] Figure 1 A simulation analysis model of the 3D-TSV stacked chip package interconnect structure is provided for an embodiment example of the present invention.

[0016] Figure 2 A thermal structural coupling stress distribution cloud map provided for an embodiment of the present invention.

[0017] Figure 3 Stress cloud diagram under random vibration loading conditions provided as an example of an embodiment of the present invention.

[0018] Figure 4 The return loss curves of the 1-10GHz TSV interconnect structure are provided as an example of an implementation of the present invention. Detailed Implementation

[0019] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer through the following description. It should be noted that the following examples are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0020] A simulation analysis model of the 3D-TSV stacked chip package interconnect structure was established based on ANSYS and HFSS, such as... Figure 1 As shown.

[0021] A stress-strain finite element analysis of the TSV interconnect structure under thermal-structural coupling conditions was performed using an indirect coupling method. First, a thermal analysis was conducted on the finite element model in the first stage to obtain the temperature field generated by the chip's own heat generation. Then, in the second stage, these temperature field results were applied as volume loads to the structural model for structural analysis, yielding the corresponding stress and strain. The stress result contour plot is shown below. Figure 2 As shown.

[0022] When performing random vibration finite element analysis on the 3D-TSV stacked chip finite element model, full constraints were applied at the four corners of the bottom surface of the PCB board. Modal analysis was first performed on the 3D-TSV stacked chip finite element model, followed by PSD spectrum analysis. The stress cloud diagram under random vibration loading conditions is shown below. Figure 3 As shown.

[0023] After establishing a return loss analysis model for the TSV interconnect structure in HFSS, simulation analysis was performed. First, waveport excitation was added to the TSV interconnect structure. Second, the material properties of the chip, microbumps, copper pillars, insulating layer, and filler layer in the model were defined. Finally, the scanning frequency range of the model was set to 1-10 GHz, and the variation law of return loss of the TSV interconnect structure within this frequency range was obtained through solution analysis. Figure 4 As shown.

[0024] The structural and material parameters of the TSV interconnect structure were selected as follows: copper pillar height, microbump height, and microbump material. Each factor was assigned three levels, and a three-factor, three-level response surface experiment was designed, as shown in Table 1.

[0025] Table 1 Factor Level Table

[0026]

[0027] Seventeen combinations of TSV interconnect structural parameters were obtained using the Box-Behnken experimental design method. Corresponding simulation models were established and analyzed. The thermal structural coupling stress, random vibration stress, and return loss data of each parameter combination are shown in Table 2.

[0028] Table 2. Stress and Return Loss Analysis Results under Thermal Loading

[0029]

[0030]

[0031] Choose the higher-order polynomial shown in equation (1) to fit the function between the dependent variable Y and the independent variable X.

[0032]

[0033] Using equation (1), the regression equation for the thermal structural coupling stress Y1 of the TSV interconnect structure with the copper pillar height A, the microbump height B, and the microbump material C is obtained, as shown in equation (2):

[0034] Y1=486.50603-6.59683×A-12.10785×B+16.816×C

[0035] +0.046634×A 2 +0.30658×B 2 -4.26338×C 2 (2)

[0036] -0.036615×A×B+4.45E-03×A×C-4.6E-03×B×C

[0037] Similarly, the regression equations for the random vibration stress Y2 and the return loss Y3 under high-frequency conditions of the TSV interconnect structure with the copper pillar height A, the microbump height B, and the microbump material C are shown in equations (3) and (4), respectively:

[0038] Y2=-6966.1875+255.5×A+281.55×B+2501.25×C

[0039] -1.0475×A 2 -7.24×B 2 -750.5×C 2 (3)

[0040] -0.165×A×B-6.175×A×C+33.9×B×C

[0041] Y3=1.28999-0.35053×A-0.38194×B+2.7375E-03×C

[0042] +1.86E-04×A 2 +7.18E-04×B 2 -5.25E-04×C 2 (4)

[0043] +8.23E-04×A×B-7.5E-06×A×C-1.5E-05×B×C

[0044] Using the NSWOA optimization algorithm, the number of initial variables is set to 3 (specifically, the height of the copper pillar x). 1 Micro-bump height x 2 Using micro-bump material x3, set three independent variables with constraints 75≤x1≤95, 20≤x2≤30, and 1≤x3≤3 (where x3 is an integer only). The objective function to be solved is 3. The population size is 100, the crossover probability is 0.8, the mutation probability is 0.1, and the maximum number of iterations is 400.

[0045] After solving the problem using the NSWOA algorithm, parameter level combinations with high thermal structural coupling stress, random vibration stress, and return loss were eliminated, resulting in 20 Pareto Front optimization solutions. The entropy and entropy weights of thermal structural coupling stress, random vibration stress, and return loss were calculated, yielding a weight of 31.773% for thermal structural coupling stress, 34.436% for random vibration stress, and 33.79% for return loss. The optimal parameter level combination was then sorted using the rank-sum ratio method: copper pillar height 76 μm, microbump height 22.477 μm, and microbump material 1.

[0046] The above are merely simple implementation examples of the present invention, and do not constitute the sole or limiting interpretation of the present invention. Any equivalent substitutions, modifications, or adjustments made by those skilled in the art to the technical solutions and content of the present invention, based on an understanding and adherence to the core ideas and basic technical solutions of the present invention, are considered reasonable extensions and applications of the present invention, and such modifications are all included within the protection scope of the present invention.

Claims

1. A multi-objective optimization method for thermal shock stress and return loss in a TSV interconnect structure, characterized in that, Specifically, the steps include the following: 1) A simulation analysis model of the interconnect structure of a 3D-TSV stacked chip package was established based on ANSYS and HFSS; 2) Perform thermal structural coupling analysis, random vibration loading analysis, and return loss analysis to obtain the maximum stress and return loss of the TSV interconnect structure; 3) Determine the parameter levels of the TSV interconnect structure; 4) Seventeen combinations of TSV interconnect structure parameters were obtained using the Box-Behnken experimental design method, and corresponding simulation models were established and analyzed. 5) Data on thermal structural coupling stress, random vibration stress, and return loss under various parameter level combinations; 6) Based on the data, fit the nonlinear relationship mapping formula between the TSV interconnect structure parameters and the thermal structural coupling stress, random vibration stress and return loss; 7) Using the NSWOA optimization algorithm, multi-objective optimization of the TSV interconnect structure is performed. The entropy weight theory is used to calculate the weights of thermal structural coupling stress, random vibration stress and return loss, and the rank-sum ratio comprehensive method is used to sort the optimization solution set to obtain the optimal parameter level combination.

2. The multi-objective optimization method for thermal shock stress and return loss of a TSV interconnect structure according to claim 1, characterized in that, In step 1), the 3D-TSV stacked chip package interconnect structure includes: stacked chip, copper pillar, microbump, insulating layer, filling layer, substrate, solder joint array and printed circuit board.

3. The multi-objective optimization method for thermal shock stress and return loss of a TSV interconnect structure according to claim 1, characterized in that, In step 2), the thermal structure coupling analysis uses a stacked chip as the heat source, with each chip layer consuming 0.25W, and the chip heat generation rate being 4.2517 × 10⁷ W / m². 3 .

4. The multi-objective optimization method for thermal shock stress and return loss of a TSV interconnect structure according to claim 1, characterized in that, In step 2), the method for analyzing the return loss is as follows: first, add wave port excitation to the TSV interconnect structure, then set the scanning frequency range of the model to 1-10GHz, and solve the analysis to obtain the variation law of the return loss of the TSV interconnect structure in this frequency range.

5. The multi-objective optimization method for thermal shock stress and return loss of a TSV interconnect structure according to claim 1, characterized in that, In step 3), the parameters of the TSV interconnect structure are: copper pillar height, microbump height, and microbump material, with each factor having 3 horizontal values.

6. The multi-objective optimization method for thermal shock stress and return loss of a TSV interconnect structure according to claim 1, characterized in that, In step 7), the NSWOA optimization algorithm sets the objective function to be solved to 3; the population size to be 100; the crossover probability to be 0.8; the mutation probability to be 0.1; and the maximum number of iterations to be 400.

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