Construction method and device of device performance determination model, equipment, medium and product

Abstract

The invention discloses a construction method and device of a device performance determination model, equipment, a medium and a product, and relates to the technical field of semiconductor device modeling. The method comprises the following steps: respectively responding to configuration operation on an input layer and an output layer of an initial model in an interactive interface, and displaying the input layer and the output layer in a model display area of the interactive interface; in response to a configuration operation on a hidden layer of the initial model in the interactive interface, displaying the hidden layer in a model display area of the interactive interface; in response to a selection operation on an activation function of the hidden layer in the interactive interface, displaying the activation function in a model display area of the interactive interface; and in response to a model loading operation, constructing and displaying an initial device performance determination model according to the number of neurons of the input layer and the output layer, the number of hidden layers of the initial model, the number of neurons of each hidden layer and the target activation function of the hidden layers. Through the technical scheme, the modeling efficiency can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device modeling technology, and in particular to a method, apparatus, device, medium, and product for constructing a device performance determination model. Background Technology

[0002] In the field of semiconductor devices, traditional modeling methods are primarily based on physical mechanisms. Early device modeling typically relied on rigorous semiconductor physics theories, such as drift-diffusion equations, band theory, and carrier transport models. These models effectively reveal the working principles of devices and are widely used in process scaling and circuit simulation. As device dimensions continue to shrink, researchers have introduced more complex physical mechanisms, such as quantum effects, interface traps, and short-channel effects, to improve model accuracy. Currently, these methods mostly exist at the research level in the form of script tools. Users train the model by setting parameters such as the number of network layers and activation functions, and then derive the model weights to replace or supplement the role of traditional compact models in circuit simulation.

[0003] However, as process nodes continue to evolve, traditional physical modeling has gradually revealed some disadvantages, such as high modeling complexity: nanoscale devices involve numerous physical effects, model formulas are becoming increasingly complex, and the number of parameters is enormous; long development cycle: each new process node often requires several years of modeling and verification, making it difficult to quickly respond to industry needs; limited applicability: traditional models are often optimized for specific device structures and materials, making it difficult to promote them to new devices (such as two-dimensional material devices); and limited simulation efficiency: high-precision numerical models have huge computational overhead in circuit-level simulations, making it difficult to meet the needs of large-scale design. Existing methods are often implemented using scripting tools or simple neural network automation tools, which brings several disadvantages in practical applications, such as: a high barrier to entry: device modeling engineers often lack in-depth knowledge of programming languages ​​and deep learning frameworks; cumbersome model configuration: users need to write and modify code to set parameters such as the number of network layers, neurons, and activation functions, lacking intuitive visualization tools; difficulty in understanding the structure: when the number of network layers is large, users find it difficult to intuitively judge the connection relationships between layers, relying only on textual information to understand the structure, which can easily lead to misjudgments; low parameter tuning efficiency: during network construction, each adjustment of the number of layers, neurons, or activation functions requires considering the connection relationships between preceding and subsequent layers, which can easily lead to inconsistencies or errors, affecting modeling efficiency; opaque structural complexity: in semiconductor device modeling, network complexity directly affects training convergence speed and physical consistency. Without visualization, model complexity is difficult to quantify and perceive, and engineers cannot quickly assess whether the network is "too deep" or "too wide"; lack of intuitive guidance for optimization: for multi-input, multi-output device models, the lack of graphical representation means that researchers find it difficult to grasp the mapping structure between inputs and outputs, which may lead to more reliance on repeated trials for model optimization, reducing efficiency. Therefore, the existing modeling methods result in low model building efficiency. Summary of the Invention

[0004] This invention provides a method, apparatus, device, medium, and product for constructing a device performance determination model to solve the problem of low modeling efficiency.

[0005] According to one aspect of the present invention, a method for constructing a device performance determination model is provided, comprising:

[0006] In response to configuration operations on the input and output layers of the initial model in the interactive interface, the number of neurons in the input and output layers is obtained and displayed in the model display area of ​​the interactive interface.

[0007] In response to the configuration operation of the hidden layers of the initial model in the interactive interface, the target number of hidden layers and the target number of neurons in each hidden layer of the initial model are obtained and displayed in the model display area;

[0008] In response to the selection operation of the activation function of the hidden layer in the interactive interface, the target activation function of the hidden layer is obtained and displayed in the model display area;

[0009] In response to the model loading operation, an initial device performance determination model is constructed and displayed in the model display area based on the number of neurons in the input layer and the output layer, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation function of the hidden layer.

[0010] According to another aspect of the present invention, an apparatus for constructing a device performance determination model is provided, comprising:

[0011] The first configuration module is used to respond to the configuration operations of the input layer and output layer of the initial model in the interactive interface, respectively, to obtain the number of neurons in the input layer and the output layer, and to display them in the model display area of ​​the interactive interface;

[0012] The second configuration module is used to respond to the configuration operation of the hidden layers of the initial model on the interactive interface, obtain the target number of hidden layers and the target number of neurons in each hidden layer of the initial model, and display them in the model display area;

[0013] A function selection module is used to obtain the target activation function of the hidden layer in response to the selection operation of the activation function of the hidden layer in the interactive interface, and display it in the model display area.

[0014] The model building module is used to respond to the model loading operation by constructing an initial device performance determination model based on the number of neurons in the input layer and the output layer, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation function of the hidden layer, and then displaying it in the model display area.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the method for constructing a device performance determination model according to any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the method for constructing a device performance determination model according to any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer program product is provided, comprising a computer program / instructions that, when executed by a processor, implement a method for constructing a device performance determination model as described in any embodiment of the present invention.

[0019] This invention provides a highly efficient device modeling method by responding to configuration operations on the input and output layers of an initial model in an interactive interface, obtaining the number of neurons in the input and output layers, and displaying this number in the model display area of ​​the interactive interface; responding to configuration operations on the hidden layers of the initial model in the interactive interface, obtaining the target number of hidden layers and the target number of neurons in each hidden layer, and displaying this number in the model display area; responding to the selection of activation functions for the hidden layers in the interactive interface, obtaining the target activation functions for the hidden layers, and displaying this function in the model display area; and responding to a model loading operation, constructing an initial device performance determination model based on the number of neurons in the input and output layers, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation functions of the hidden layers, and displaying this model in the model display area. This provides a highly efficient device modeling method, optimizes the modeling process, and allows device modeling engineers to perform semiconductor device modeling and simulation work more efficiently and accurately.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a method for constructing a device performance determination model provided in an embodiment of the present invention;

[0023] Figure 2 This is a flowchart of another method for constructing a device performance determination model provided in an embodiment of the present invention;

[0024] Figure 3 This is a topological structure diagram of a first model provided in an embodiment of the present invention;

[0025] Figure 4 This is a topological structure diagram of a second model provided in an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram of the training results of a current prediction model provided in an embodiment of the present invention;

[0027] Figure 6 This is a schematic diagram of the training results of a current prediction model provided in an embodiment of the present invention;

[0028] Figure 7 This is a schematic diagram of the training results of a charge prediction model provided in an embodiment of the present invention;

[0029] Figure 8 This is a schematic diagram of the training results of a charge prediction model provided in an embodiment of the present invention;

[0030] Figure 9 This is a schematic diagram of the training results of a charge prediction model provided in an embodiment of the present invention;

[0031] Figure 10 This is a schematic diagram of the training results of a charge prediction model provided in an embodiment of the present invention;

[0032] Figure 11 This is a schematic diagram of the training results of a charge prediction model provided in an embodiment of the present invention;

[0033] Figure 12 This is a schematic diagram of the training results of a charge prediction model provided in an embodiment of the present invention;

[0034] Figure 13 This is a schematic diagram of the training results of a charge prediction model provided in an embodiment of the present invention;

[0035] Figure 14 This is a schematic diagram of the training results of a charge prediction model provided in an embodiment of the present invention;

[0036] Figure 15 This is a schematic diagram of the structure of a device for constructing a device performance determination model provided in an embodiment of the present invention;

[0037] Figure 16 This is a schematic diagram of the structure of an electronic device that implements the device performance determination model construction method of the embodiments of the present invention. Detailed Implementation

[0038] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0039] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0040] Furthermore, it should be noted that the information collected in the technical solution of this invention is information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of related data all comply with the relevant laws, regulations and standards of relevant countries and regions, necessary confidentiality measures have been taken, and public order and good morals are not violated. Corresponding operation entry points are provided for users to choose to authorize or refuse.

[0041] Figure 1 This is a flowchart illustrating a method for constructing a device performance determination model according to an embodiment of the present invention. This embodiment is applicable to the construction of device performance determination models. The method can be executed by a device performance determination model construction device, which can be implemented in hardware and / or software. This device can be configured in an electronic device with corresponding data processing capabilities, such as a server. Figure 1 As shown, the method includes:

[0042] S110: Responding to the configuration operations of the input layer and output layer of the initial model in the interactive interface, respectively, the number of neurons in the input layer and output layer is obtained and displayed in the model display area of ​​the interactive interface.

[0043] The interactive interface is used to operate the neural network model. It allows users to design the neural network architecture through parameter settings, and the model structure updates in real time whenever parameters change. The initial model is a neural network framework with incomplete parameter configuration. Configuration operations are the specific actions users take on the interactive interface (such as entering numbers, selecting options, dragging components, etc.). The number of neurons in the input layer needs to match the dimensions of the data features, and the number of neurons in the output layer needs to match the task objective. The model display area is the visual area within the interactive interface that presents the model structure and parameters.

[0044] Specifically, the interactive interface is developed based on the PySide framework. This interface combines neural network structure design, parameter setting, and topology visualization, allowing users to intuitively design, adjust, and optimize neural network structures through a graphical interface, facilitating semiconductor device modeling. Responding to user configuration operations on the input and output layers of the initial model within the interactive interface, the number of neurons in the input and output layers is obtained and graphically displayed in the model display area of ​​the interactive interface. Users can freely adjust the dimensions of the input and output layers according to modeling needs, ensuring that the neural network structure can effectively map the nonlinear relationship between input and output. The dimensions of the input layer (input_dim) and the output layer (output_dim) can be set by adjusting the input control (QSpinBox) to ensure that the physical quantities of the input and output match the neural network design. For example, in semiconductor device modeling, the input layer is typically used to receive electrical parameters (such as Vgs, Vds), while the output layer corresponds to the physical output of the device (such as Qd, Qg).

[0045] S120. In response to the configuration operation of the hidden layers of the initial model in the interactive interface, obtain the target number of hidden layers and the target number of neurons in each hidden layer of the initial model, and display them in the model display area.

[0046] The target number of hidden layers is the total number of hidden layers determined after configuration via the interactive interface. The target number of neurons is the number of neurons in a single hidden layer, determined after configuration for each hidden layer.

[0047] Specifically, in response to the user's configuration operation on the hidden layers of the initial model in the interactive interface, the target number of hidden layers and the target number of neurons in each hidden layer are obtained based on the operation information of the configuration operation. These numbers are then graphically displayed in the model display area. For example, if the user selects 3 hidden layers (maximum 5 layers) in the interactive interface, and the operation information includes "3 hidden layers", then the initial model has 3 hidden layers. If the user selects 10 neurons in the first hidden layer in the interactive interface, and the operation information includes "10 neurons in the first hidden layer", then the target number of neurons in the first hidden layer is 10.

[0048] S130. In response to the selection operation of the activation function of the hidden layer in the interactive interface, the target activation function of the hidden layer is obtained and displayed in the model display area.

[0049] Activation functions are mathematical functions embedded in neurons within a neural network. Their role is to inject non-linearity into the model, enabling it to learn patterns in complex data. The target activation function is determined through selection on the interactive interface, ultimately defining the activation function for the hidden layer. Activation functions include Sigmoid, ReLU, and Tanh, among others.

[0050] Specifically, users can use an interactive interface (such as a visual configuration tool) to select an activation function from the available options for each hidden layer. The system can then respond to the selection of the activation function for the hidden layer in the interactive interface, obtain the target activation function for the hidden layer, and display the target activation function graphically in the model display area.

[0051] S140. In response to the model loading operation, construct an initial device performance determination model based on the number of neurons in the input and output layers, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation function of the hidden layers, and display it in the model display area.

[0052] The initial device performance determination model is a neural network model built based on configuration parameters used to evaluate device performance. These configuration parameters include the number of neurons in the input and output layers, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation function for the hidden layers.

[0053] Specifically, in response to the model loading operation, an initial device performance determination model is constructed based on the number of neurons in the input and output layers, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation function of the hidden layers. The model structure and parameters of this initial device performance determination model are then graphically displayed in the model display area of ​​the interactive interface. For example, nodes represent neurons, lines represent connections, and the parameters of each layer (number of layers, number of neurons, activation function type) are labeled, allowing users to intuitively see the model configuration results.

[0054] Optionally, it also includes: displaying a model name configuration control on the interactive interface, obtaining the model name in response to input on the model name configuration control; and saving the model parameters of the initial device performance determination model in JSON format based on the model name in response to clicking the save button on the interactive interface.

[0055] The model name configuration control is used to allow users to set the model name.

[0056] Specifically, the interactive interface displays a model name configuration control, allowing users to name their models. The system responds to input in the control by obtaining the model name; and responds to a click on the save button by saving the model name, storing the initial device performance parameters in JSON format. After designing the neural network model, users can save the model parameters (such as number of layers, number of neurons, activation function, etc.) as a file in JSON format. This facilitates quick reuse of previously designed network configurations, simplifying the modeling process, and the file can also be shared. By assigning different model names to different models, redundant design is avoided.

[0057] Optionally, it also includes: displaying zoom in or zoom out controls in the model display area of ​​the interactive interface, and responding to click operations on the zoom in or zoom out controls in the model display area to zoom in or zoom out the content displayed in the model display area.

[0058] The zoom-in control is used to enlarge the content, and the zoom-out control is used to shrink the content. The zoom-in control can be a "+" icon or a "zoom in" button in the model display area; the zoom-out control can be a "-" icon or a "zoom out" button in the model display area.

[0059] Specifically, in response to clicks on the zoom-in or zoom-out controls in the model display area, clicking the zoom-in control triggers a zoom-in effect, and clicking the zoom-out control triggers a zoom-out effect, thus enlarging or shrinking the content displayed in the model display area. This makes it easier for users to see model details or the overall structure, allowing for flexible adjustment of the model's visual display size and improving the user experience.

[0060] In this embodiment of the invention, users configure the input / output layers, hidden layer structure, number of neurons, and activation functions of the network through an interface. The system generates the corresponding network topology diagram in real time, achieving a clear correspondence between the model structure and its physical meaning. The graphical approach provides an intuitive display and interactive configuration of the network structure, simplifying the model design process, reducing parameter tuning error rates, and helping users understand the correspondence between the network structure and device characteristics, thereby improving modeling efficiency and the rationality of model configuration. Simultaneously, it supports saving and reusing network configurations, allowing for quick recall at different devices or modeling stages, improving modeling efficiency and realizing a shift from parametric design to visual modeling, enhancing the intuitiveness and engineering practicality of the model design.

[0061] Figure 2 This is a flowchart of a method for constructing a device performance determination model according to an embodiment of the present invention. Based on the above embodiments, this embodiment optimizes the step of "obtaining the number of neurons in the input and output layers in response to configuration operations on the input and output layers of the initial model at the interactive interface," providing an optional implementation scheme. For example... Figure 2 As shown, the method includes:

[0062] S210. Display the input layer configuration control and output layer configuration control of the initial model on the interactive interface. Respond to the input operation of the number of neurons in the input layer configuration control and the input operation of the number of neurons in the output layer configuration control, respectively, to obtain the number of the first neuron in the input layer and the number of the second neuron in the output layer.

[0063] The input layer configuration controls are used to set the parameters of the input layer in the model. The output layer configuration controls are used to set the parameters of the output layer in the model. The controls can take the form of numeric input boxes (where users can directly enter specific numbers), spin boxes with range limitations (adding "+" and "-" buttons to the numeric input box, allowing users to adjust the number of steps), drop-down selection boxes, etc. The number of neurons in the first layer represents the number of neurons in the input layer. The number of neurons in the second layer represents the number of neurons in the output layer. Input is performed by entering information into the input boxes on the interactive interface.

[0064] Specifically, the interactive interface displays input layer configuration controls and output layer configuration controls for the initial model. In response to inputting the number of neurons in the input layer configuration controls of the initial model via the interactive interface, the number of neurons in the first input layer is obtained; similarly, in response to inputting the number of neurons in the output layer configuration controls of the initial model via the interactive interface, the number of neurons in the second output layer is obtained. Thus, by selecting numbers via the interactive interface, the number of neurons in the input and output layers are set respectively, and the number of neurons in the first and second layers is determined after input.

[0065] S220. Display the input and output layers in real time in the model display area of ​​the interactive interface.

[0066] Specifically, the system will display changes in the input and output layers in real time and update the network topology.

[0067] S230. In response to the configuration operation of the hidden layers of the initial model in the interactive interface, obtain the target number of hidden layers and the target number of neurons in each hidden layer of the initial model, and display them in the model display area.

[0068] S240. In response to the selection operation of the activation function of the hidden layer in the interactive interface, the target activation function of the hidden layer is obtained and displayed in the model display area.

[0069] S250: In response to the model loading operation, based on the number of neurons in the input and output layers, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation function of the hidden layers, an initial device performance determination model is constructed and displayed in the model display area.

[0070] Optionally, in response to the configuration operation of the hidden layers of the initial model in the interactive interface, the target number of hidden layers and the target number of neurons in each hidden layer of the initial model are obtained and displayed in the model display area, including: displaying a hidden layer drop-down menu in the interactive interface; in response to the selection operation of the number of hidden layers in the hidden layer drop-down menu, obtaining the target number of hidden layers of the initial model; displaying a hidden layer configuration control in the interactive interface according to the target number of hidden layers; in response to the input operation of the number of neurons in the hidden layer configuration control, obtaining the target number of neurons in the hidden layers; displaying the target number of hidden layers and the target number of neurons in each hidden layer in the model display area, and updating the connection relationship between neurons in the input layer, hidden layer and output layer in the model display area in real time.

[0071] The hidden layer configuration controls are used to configure the parameters of the model's hidden layers. These controls are interactive components on the user interface (such as input boxes or drop-down menus), appearing after the target number of hidden layers is selected. For example, selecting 3 hidden layers will display 3 corresponding hidden layer configuration controls, allowing the user to input the number of neurons and activation function for each layer. The target number of neurons is the final number of neurons in a single hidden layer determined by inputting numbers into the hidden layer configuration controls. For example, inputting 6, 8, and 6 for 3 hidden layers corresponds to the target number of neurons in each layer. Connections refer to the signal transmission relationships between neurons in different layers of a neural network. Typically, neurons in adjacent layers are connected pairwise (e.g., each neuron in the input layer connects to all neurons in the first hidden layer). The model display area uses lines and other graphical methods to visually represent this connection structure.

[0072] Specifically, when a user adjusts the number of hidden layers, the interface automatically generates a corresponding number of input controls and binds appropriate update events as needed. For example, when adjusting the number of hidden layers, the system dynamically generates a corresponding number of QSpinBox and QComboBox controls so that the user can set the number of neurons and activation functions for each layer. Whenever parameters change (such as adjusting the number of layers or neurons), the system triggers the `draw_network()` function, which clears the current scene and redraws the neuron nodes and inter-layer connections. Using QGraphicsScene and QGraphicsView, each neuron node is drawn as a circle using QGraphicsEllipseItem, and connections between layers are drawn using QGraphicsLineItem. Each time parameters are adjusted, the interface refreshes these graphical elements to ensure real-time updates of the network topology. In the interactive interface, the parameter adjustment event and the drawing update process are decoupled, avoiding unnecessary redrawing on each adjustment.

[0073] Optionally, the initial model includes a first model and a second model;

[0074] Accordingly, in some embodiments, the following are also included:

[0075] 1) Determine multiple first sample voltage pairs for the sample device; the first sample voltage pair includes the sample drain-source voltage and the sample gate-source voltage;

[0076] The sample device is a semiconductor device used for model training. The first sample voltage pair is a combination of two sample voltage parameters. These parameters include the sample drain-source voltage and the sample gate-source voltage. The sample drain-source voltage is the voltage applied between the drain (D) and source (S) of the device, and can be denoted as... The sample gate-source voltage refers to the voltage applied between the gate (G) and source (S) of a device, and can be denoted as... .

[0077] Specifically, by controlling the voltage scanning range and step size, the key operating range of the device (such as the linear region, saturation region, and subthreshold region) is covered, thereby collecting multiple sample voltage pairs covering the entire operating range of the sample device to ensure that the sample data can support the model in learning the complete "voltage-current" relationship.

[0078] 2) The first model is trained using multiple first sample voltage pairs to obtain the current prediction model;

[0079] The first model is an untrained neural network. While its structure is fixed, its configuration parameters are initial and it cannot accurately predict current. The current prediction model, on the other hand, is a pre-trained model used to predict leakage current.

[0080] Specifically, multiple first sample voltage pairs are input into the first model one by one. The model learns the mapping relationship between the input first sample voltage pairs and the output leakage current, and continuously reduces the prediction error until the prediction error of the model for the first sample voltage pairs is small enough (such as the loss value is lower than a preset threshold). The training ends at this time. The model at this time is a current prediction model. The current prediction model can output a leakage current that conforms to the actual characteristics of the device based on the input drain-source voltage and gate-source voltage.

[0081] 3) Normalize multiple first sample voltage pairs to obtain multiple second sample voltage pairs;

[0082] The second sample voltage pair is a normalized sample voltage pair. Normalization is a mathematical transformation that maps the data to a uniform numerical range. The second sample voltage pair consists of a combination of two normalized sample voltage parameters: normalized sample drain-source voltage and normalized sample gate-source voltage.

[0083] Specifically, multiple first sample voltage pairs are normalized to obtain multiple second sample voltage pairs. This avoids bias towards parameters with larger numerical ranges during model training due to the different numerical ranges of voltage parameters. For example, if the range of sample drain-source voltage in the first sample voltage pair is 0-10V, and the original value of a sample drain-source voltage is 5V, and the range of sample gate-source voltage is 0-5V, and the original value of a sample gate-source voltage is 2.5V, meaning the minimum value of the sample drain-source voltage is 0V, the maximum value is 10V, and the minimum value of the sample gate-source voltage is 0V, and the maximum value is 5V, then normalization is used. Specifically, the original value of the sample drain-source voltage is subtracted from the minimum value of the sample drain-source voltage to obtain the first difference; the sample drain-source voltage is then normalized. The maximum value of the drain-source voltage is subtracted from the minimum value of the sample drain-source voltage to obtain the second difference; the first difference is divided by the second difference to obtain the normalized sample drain-source voltage; the original value of the sample gate-source voltage is subtracted from the minimum value of the sample gate-source voltage to obtain the third difference; the maximum value of the sample gate-source voltage is subtracted from the minimum value of the sample gate-source voltage to obtain the fourth difference; the third difference is divided by the fourth difference to obtain the normalized sample gate-source voltage, that is, the normalized sample drain-source voltage is 0.5V.

[0084] 4) The second model is trained using multiple second sample voltage pairs to obtain the charge prediction model;

[0085] The second model is an untrained neural network. The model parameters of the second initial network differ from those of the first initial network. The current prediction model is a trained model used to predict intermediate charge amounts. Intermediate charge amounts are intermediate quantities related to the charge distribution.

[0086] Specifically, multiple second sample voltage pairs are input into the second model one by one. The model learns the mapping relationship between the input second sample voltage pairs and the output intermediate charge, continuously reducing the prediction error until the prediction error of the model for the second sample voltage pairs is sufficiently small (e.g., the loss value is below a preset threshold). Training ends at this point, and the model is a charge prediction model. The charge prediction model can output an intermediate charge that conforms to the actual characteristics of the device based on the input normalized drain-source voltage and normalized gate-source voltage. The intermediate charge includes intermediate drain-source charge and intermediate gate-source charge. Thus, by outputting intermediate drain-source charge and intermediate gate-source charge that conform to the actual charge distribution law based on the normalized voltage pairs, it provides a foundation for subsequent derivation of the dynamic capacitance characteristics of the device.

[0087] 5) Based on the current prediction model and the charge prediction model, the performance determination model of the target device is obtained.

[0088] The current prediction model is a pre-trained model that takes drain-source voltage and gate-source voltage as input and outputs drain current, which can be used to characterize the static electrical characteristics of the device. The charge prediction model is also a pre-trained model that takes normalized drain-source voltage and normalized gate-source voltage as input and outputs intermediate drain-source charge and intermediate gate-source charge (which can be further used to derive capacitance), used to characterize the dynamic electrical characteristics of the device. The target device performance determination model is a combined model formed by integrating the current prediction model and the charge prediction model.

[0089] Specifically, the current prediction model and the charge prediction model are integrated into a comprehensive model that can fully evaluate the performance of semiconductor devices. Through the synergistic effect of the two models, both static and dynamic characteristics of the device are covered. The current prediction model provides static operating state support for the charge prediction model, while the charge prediction model supplements the dynamic characteristics not covered by the current model, thus solving the problem that a single model cannot comprehensively evaluate device performance.

[0090] This method involves determining multiple first sample voltage pairs for the sample device, including sample drain-source voltage and sample gate-source voltage. Using these first sample voltage pairs, a first model is trained to obtain a current prediction model. These first sample voltage pairs are then normalized to obtain multiple second sample voltage pairs. Using these second sample voltage pairs, a second model is trained to obtain a charge prediction model. Based on the current and charge prediction models, a target device performance determination model is obtained. The current prediction model focuses on the static voltage-current relationship, accurately fitting output and transfer characteristic curves to ensure the extraction accuracy of static parameters such as threshold voltage and saturation current. The charge prediction model focuses on the dynamic voltage-charge-capacitance relationship, achieving accurate capacitance prediction through partial derivative calculations. These two models have clearly defined roles, respectively tackling the modeling challenges of static and dynamic characteristics, ultimately enabling the target device performance determination model to achieve high accuracy in both static and dynamic dimensions. This provides a highly efficient device modeling method, optimizes the modeling process, and allows device modeling engineers to perform semiconductor device modeling and simulation work more efficiently and accurately.

[0091] Optionally, it also includes: displaying a hidden layer configuration control in the interactive interface, retraining the target device performance determination model in response to the adjustment of the activation function of the hidden layer configuration control; and displaying the convergence rate and device characteristic curve of the target device performance determination model in the result display area of ​​the interactive interface.

[0092] Among them, convergence rate is the speed at which the error decreases during model training, and convergence rate reflects training efficiency. Device characteristic curves are graphs that describe the changing trends of device performance-related indicators, such as curves showing performance changes with parameters.

[0093] Specifically, the hidden layer configuration control includes settings options related to the activation function. The hidden layer configuration control is displayed on the interactive interface. After adjusting the activation function of the model based on the hidden layer configuration control on the interactive interface (such as switching the activation function type), the system will retrain the target device performance determination model. After training is completed, the result display area of ​​the interface will display the convergence rate of the model and the device characteristic curve.

[0094] This invention transforms neural network construction from parameter setting to a visual operation. Users can intuitively view the connection relationships between the input layer (Vgs, Vds), hidden layer, and output layer (Qg, Qd), making model design more intuitive and consistent with physical understanding. The interface supports real-time drawing and structure adjustment, allowing users to quickly compare the effects of different layer numbers, activation functions, and other settings, improving parameter tuning and optimization efficiency. Through structural visualization, users can intuitively see the impact of network depth and complexity, making it easier to identify potential overfitting or structural inconsistencies, thereby optimizing model design and enhancing model stability. The automatically generated network topology diagram can be directly used for presentations or papers, with clear and standardized graphics that intuitively reflect model hierarchy and data flow, facilitating engineers in demonstrating modeling ideas and results. It supports saving and reusing network configurations, allowing for rapid recall at different devices or modeling stages, improving modeling efficiency.

[0095] Optionally, the first model includes a first input layer, at least one first hidden layer, and a first output layer; the second model has the same structure as the first model, but different model parameters.

[0096] The first model consists of two layers: a first input layer receiving input parameters (sample voltage pairs) and a second output layer containing two nodes corresponding to the sample drain-source voltage and the sample gate-source voltage, respectively. A first hidden layer learns the nonlinear relationship between the input and output parameters. Each hidden layer includes at least one node, and the specific data of each node can be configured as needed. Each hidden layer can also be configured with an activation function. The first output layer outputs the model's prediction result, which is the predicted leakage current. The first output layer has one node. The first model is a multi-layer neural network structure consisting of an input layer, a hidden layer, and an output layer. The second model has the same structure as the first model, also consisting of a multi-layer neural network structure with an input layer, a hidden layer, and an output layer. For example, the topology of the first model could be as follows: Figure 3As shown, the first model can include a first input layer, three first hidden layers, and a first output layer. The first model has 5 layers. The first input layer has 2 nodes. The three first hidden layers correspond to the 2nd, 3rd, and 4th layers respectively. The 2nd layer has 8 nodes, the 3rd layer has 9 nodes, and the 4th layer has 8 nodes. The 5th output layer has 1 node. The activation function for the 1st layer is sigmoid, the 2nd layer is ReLU, and the 3rd layer is sigmoid. The 4th and 5th layers have no activation function. The output layer has no activation function to ensure that the output current can vary within a continuous real number range.

[0097] Specifically, the second model includes a second input layer, at least one second hidden layer, and a second output layer. The second input layer receives input parameters, which are second sample voltage pairs. The second input layer has two nodes, corresponding to the normalized sample drain-source voltage and the normalized sample gate-source voltage, respectively. The second hidden layer learns the nonlinear relationship between the input and output parameters. Each second hidden layer includes at least one node, and the specific data of the nodes can be set according to requirements. Each second hidden layer can be configured with an activation function. The second output layer outputs the model's prediction results, namely, the predicted intermediate drain-source charge and the predicted intermediate gate-source charge. The second output layer has two nodes. For example, the topology of the second model can be as follows: Figure 4 As shown, the second model can include a second input layer, three second hidden layers, and a second output layer, for a total of five layers. The first layer is the second input layer with two nodes. The three second hidden layers correspond to layers 2, 3, and 4 respectively, each with ten nodes. The fifth layer is the second output layer with two nodes. The activation functions for layers 1, 2, and 3 are all sigmoid, while layers 4 and 5 have no activation function. This ensures that the models' fitting ability to their respective tasks is matched, while also ensuring the independence of the training process, ultimately resulting in models adapted for both current prediction and charge prediction.

[0098] Optionally, the sample drain-source voltages are the same in multiple first sample voltage pairs, but the sample gate-source voltages are different; or, the sample drain-source voltages are different in multiple first sample voltage pairs, but the sample gate-source voltages are the same.

[0099] Specifically, in multiple first sample voltage pairs, the sample drain-source voltages are the same, but the sample gate-source voltages are different. That is, the sample drain-source voltage is fixed, the sample gate-source voltage is scanned, and the leakage current is output, thereby obtaining the effect of gate-source voltage variation on leakage current under the same drain-source voltage. For example, fixing the sample drain-source voltage to a certain value: select multiple typical drain-source voltage points (e.g., a sample drain-source voltage of 0.1V for linear region testing, a sample drain-source voltage of 5V for saturation region testing, etc.), and scan the sample gate-source voltage: for each fixed sample drain-source voltage, control the sample gate-source voltage to start from 0V and gradually increase it to the maximum value of the sample gate-source voltage (e.g., 5V) according to a set step size (e.g., 0.05V). Record a set (sample drain-source voltage, sample gate-source voltage) as the first sample voltage pair at each step. The step size is determined by the data density and acquisition frequency. In multiple first sample pairs, the sample drain-source voltages are different, but the sample gate-source voltages are the same. That is, the sample gate-source voltage is fixed, the sample drain-source voltage is scanned, and the leakage current is output, thereby obtaining the effect of drain-source voltage variation on leakage current under the same gate-source voltage. By fixing one voltage parameter and scanning another, the key operating characteristics (output characteristics and transfer characteristics) of semiconductor devices can be covered, ensuring that the sample data can reflect the electrical behavior of the device under different bias conditions.

[0100] Optionally, a first model is trained using multiple first sample voltage pairs to obtain a current prediction model, including: inputting multiple first sample voltage pairs into the first model to obtain sample predicted current; determining a first training loss based on the sample predicted current and the true current corresponding to the first sample voltage pair; and training the first model using the first training loss to obtain a current prediction model.

[0101] Here, the sample predicted current is the predicted current output by the first model. The true current is the actual leakage current acquired synchronously with the first sample voltage pair. The first training loss is used to quantify the difference between the sample predicted current and the true current.

[0102] Specifically, multiple first sample voltage pairs are input into the first model to obtain the sample predicted current. Based on the sample predicted current and the corresponding true current for each first sample voltage pair, a first training loss is determined. For example, the sum of the squares of the differences between the sample predicted current and the true current is used as the first training loss. The larger the first training loss, the worse the model's prediction performance. The first model is then trained using the first training loss to obtain a current prediction model. For example, using the first training loss, the parameters (weights, biases) of each layer of the first model are adjusted through backpropagation (if the sample predicted current value is too small, the weights are adjusted to increase the output) to reduce the loss. This process is iterated repeatedly until the prediction error of the first model for the samples is sufficiently small. When the prediction error of the first model stabilizes at a low level and can accurately predict new voltage pairs, the training ends. At this point, the first model is the current prediction model. By optimizing the parameters, the model's predictions become increasingly accurate, ultimately resulting in a reliable current prediction model.

[0103] Optionally, multiple second sample voltage pairs are used to train the second model to obtain a charge prediction model, including: inputting multiple second sample voltage pairs into the second model to obtain the sample predicted charge; calculating the partial derivative of the sample predicted charge with respect to the second sample voltage pairs to obtain the sample predicted capacitance; determining the second training loss based on the sample predicted capacitance and the true capacitance corresponding to the second sample voltage pairs; and using the second training loss to iteratively train the second model to obtain the charge prediction model.

[0104] Here, the sample predicted charge is the predicted intermediate charge output by the second model. The sample predicted capacitance is the predicted capacitance calculated using partial derivatives. The true capacitance is the actual capacitance acquired synchronously with the second sample voltage pair. The second training loss is used to quantify the difference between the sample predicted capacitance and the true capacitance.

[0105] Specifically, multiple second sample voltage pairs are input into the second model one by one. Based on the initialized parameters, the second model outputs the sample predicted charge. Based on the partial derivative calculation formula, the partial derivative of the sample predicted charge (predicted intermediate drain-source charge and predicted intermediate gate-source charge) with respect to the second sample voltage pair (normalized sample drain-source voltage and normalized sample gate-source voltage) is calculated to obtain the sample predicted capacitance. Based on the sample predicted capacitance and the true capacitance corresponding to the second sample voltage pair, the second training loss is determined. Using the second training loss, the parameters (weights and biases) of the second model are adjusted through the backpropagation algorithm. This process is repeated until the loss value drops to a preset threshold, so that the sample predicted charge output by the model, after partial derivative calculation, is closer to the true capacitance. After training, the second model at this time is the charge prediction model. The charge prediction model can output the predicted intermediate charge that conforms to the actual charge distribution law based on the normalized voltage pair.

[0106] Optionally, the formula for calculating partial derivatives is:

[0107] ;

[0108] in, To predict the intermediate drain-source charge, To predict the intermediate gate-source charge, D represents the drain-source and G represents the gate-source. For the normalized sample drain-source voltage, For the normalized sample gate-source voltage, To predict the partial derivative of the intermediate gate-source charge with respect to the normalized sample drain-source voltage, i.e. The predicted capacitance representing the gate-source charge and drain-source voltage. To predict the partial derivative of the intermediate gate-source charge with respect to the normalized sample gate-source voltage, i.e. The predicted capacitance represents the relationship between gate-source charge and gate-source voltage. To predict the partial derivative of the intermediate drain-source charge with respect to the normalized sample drain-source voltage, i.e. The predicted capacitance represents the drain-source charge and drain-source voltage. To predict the partial derivative of the intermediate drain-source charge with respect to the normalized sample gate-source voltage, i.e. This represents the predicted capacitance of the drain-source charge and gate-source voltage.

[0109] Optionally, the second training loss formula is expressed as:

[0110] ;

[0111] Where Loss represents the second training loss. The predicted capacitance representing the gate-source charge and drain-source voltage. The predicted capacitance represents the relationship between gate-source charge and gate-source voltage. The predicted capacitance represents the drain-source charge and drain-source voltage. The predicted capacitance represents the drain-source charge and gate-source voltage. The true capacitance representing the drain-source charge and gate-source voltage. The true capacitance representing the drain-source charge and drain-source voltage. The true capacitance representing the gate-source charge and gate-source voltage. The true capacitance represents the relationship between gate-source charge and drain voltage. The second training loss is obtained by summing the errors of all capacitance elements, thus capturing the learning performance of the second model on the charge-capacitance relationship.

[0112] Optionally, the training results output by the current prediction model can be as follows: Figure 5 and Figure 6 As shown, Figure 5 This is a schematic diagram showing the output leakage current (Id) when the gate-source voltage is fixed and the drain-source voltage (Vds) is different. Figure 6 This is a schematic diagram showing the output leakage current when the drain-source voltage is fixed and the gate-source voltage (Vgs) is different.

[0113] Optionally, the training results obtained based on the predicted charge output by the charge prediction model can be as follows: Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 As shown, these correspond to the relationships between gate-source capacitance (Cgg) and gate-source voltage (Vg), gate-source capacitance (Cgg) and drain-source voltage (Vd), gate-source capacitance (Cgd) and gate-source voltage (Vg), gate-source capacitance (Cgd) and drain-source voltage (Vd), drain-source capacitance (Cdg) and gate-source voltage (Vg), drain-source capacitance (Cdg) and drain-source voltage (Vd), drain-source capacitance (Cdd) and gate-source voltage (Vg), and drain-source capacitance (Cdd) and drain-source voltage (Vd), respectively.

[0114] This approach directly optimizes current error through the first training loss, enabling the current prediction model to accurately capture output and transfer characteristics. Conversely, it directly optimizes capacitance error through the second training loss, ensuring that the predicted charge output by the charge prediction model, after partial derivative, matches the measured capacitance, thus guaranteeing accurate fitting of dynamic characteristics. The current prediction model provides static parameters (threshold voltage, drive current, etc.), while the charge prediction model provides dynamic parameters (switching delay, cutoff frequency, etc.) through capacitance. Combining these two approaches allows for a comprehensive evaluation of device performance in actual circuits, overcoming the limitation of traditional single models that can only evaluate partial characteristics. The high-precision current and capacitance prediction results can be directly used for semiconductor device design optimization and circuit simulation tool model calibration, accelerating the R&D cycle and ultimately achieving high-precision, high-efficiency modeling of the full performance of semiconductor devices.

[0115] Optionally, in some embodiments, the following may also be included:

[0116] 1) Obtain the target voltage pair of the target device.

[0117] The target device is the semiconductor device to be evaluated. The target voltage pair is the voltage pair of the target device.

[0118] Specifically, if it is necessary to evaluate the performance of a target device under a specific operating condition, then the target voltage pair for that operating condition is obtained. For example, if the target device needs to operate at a drain-source voltage of 5V and a gate-source voltage of 3V in practical applications, then the target voltage pair is obtained as drain-source voltage = 5V and gate-source voltage = 3V. Thus, based on the application requirements of the target device, the corresponding voltage parameters can be extracted from the actual circuit conditions as target voltage pairs, providing input data for subsequent model prediction of its performance.

[0119] 2) The target predicted current is obtained by inputting the target voltage to the current prediction model of the target device performance determination model.

[0120] The target predicted current is the predicted leakage current of the target device.

[0121] Specifically, the target voltage of the target device is input into the current prediction model in the target device performance determination model, and finally the leakage current prediction value of the target device under the voltage condition is obtained, that is, the target predicted current.

[0122] 3) Normalize the target voltage pairs to obtain the processed target voltage pairs.

[0123] The processed target voltage pairs are standard voltage pairs obtained through normalization.

[0124] 4) Input the processed target voltage into the charge prediction model of the target device performance determination model to obtain the target predicted charge.

[0125] The target predicted charge is the predicted intermediate charge value of the target device.

[0126] Specifically, the normalized target voltage is input into the charge prediction model of the target device performance determination model, and finally the intermediate quantity related to the charge distribution of the target device under the voltage condition is obtained, that is, the target predicted charge.

[0127] 5) Determine the performance of the target device based on the target predicted current and target predicted charge.

[0128] Specifically, by predicting the target current, key static parameters (such as the saturation region drive current) are extracted to determine the device's conduction capability and gate control accuracy. Capacitive parameters are derived from the predicted target charge, and dynamic indicators are extracted, such as the faster the device charges and discharges as the smaller the capacitance. This allows for an accurate evaluation of the static and dynamic performance of semiconductor devices.

[0129] This invention provides a method for efficiently, comprehensively, and accurately evaluating the performance of a target device. It involves obtaining a target voltage pair for the target device; inputting this target voltage pair into the current prediction model of the target device performance determination model to obtain the target predicted current; normalizing the target voltage pair to obtain a processed target voltage pair; inputting the processed target voltage pair into the charge prediction model of the target device performance determination model to obtain the target predicted charge; and determining the performance of the target device based on the target predicted current and target predicted charge. This approach enables efficient, comprehensive, and accurate performance evaluation of the target device, achieving a full-dimensional evaluation from static conductivity to dynamic response speed. It aligns with the physical characteristics of semiconductor devices and meets the needs of rapid device performance assessment in engineering applications. It eliminates the need for complex testing platforms or lengthy physical testing, thus improving the efficiency of device performance evaluation.

[0130] Figure 15 This is a schematic diagram of a device for constructing a device performance determination model according to an embodiment of the present invention. This embodiment is applicable to the construction of device performance determination models. The method can be executed by a device for constructing device performance determination models, which can be implemented in hardware and / or software. This device can be configured in an electronic device with corresponding data processing capabilities, such as a server. Figure 15 As shown, the device includes:

[0131] The first configuration module 310 is used to respond to the configuration operations of the input layer and output layer of the initial model in the interactive interface, respectively, to obtain the number of neurons in the input layer and output layer, and to display them in the model display area of ​​the interactive interface.

[0132] The second configuration module 320 is used to respond to the configuration operation of the hidden layers of the initial model in the interactive interface, obtain the target number of hidden layers and the target number of neurons in each hidden layer of the initial model, and display them in the model display area.

[0133] The function selection module 330 is used to respond to the selection operation of the activation function of the hidden layer in the interactive interface, obtain the target activation function of the hidden layer, and display it in the model display area;

[0134] The model building module 340 is used to respond to the model loading operation by building an initial device performance determination model based on the number of neurons in the input and output layers, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation function of the hidden layers, and then displaying it in the model display area.

[0135] In this embodiment of the invention, users configure the input / output layers, hidden layer structure, number of neurons, and activation functions of the network through an interface. The system generates the corresponding network topology diagram in real time, achieving a clear correspondence between the model structure and its physical meaning. The graphical approach provides an intuitive display and interactive configuration of the network structure, simplifying the model design process, reducing parameter tuning error rates, and helping users understand the correspondence between the network structure and device characteristics, thereby improving modeling efficiency and the rationality of model configuration. Simultaneously, it supports saving and reusing network configurations, allowing for quick recall at different devices or modeling stages, improving modeling efficiency and realizing a shift from parametric design to visual modeling, enhancing the intuitiveness and engineering practicality of the model design.

[0136] Optionally, the first configuration module 310 includes:

[0137] The first quantity acquisition unit is used to display the input layer configuration control and the output layer configuration control of the initial model on the interactive interface. It responds to the input operation of the number of neurons in the input layer configuration control and the input operation of the number of neurons in the output layer configuration control, respectively, to obtain the first neuron count of the input layer and the second neuron count of the output layer.

[0138] The first display unit is used to display the input and output layers in real time in the model display area of ​​the interactive interface.

[0139] Optionally, the second configuration module 320 includes:

[0140] The second quantity acquisition unit is used to display a hidden layer drop-down menu in the interactive interface, and in response to the selection operation of the number of hidden layers in the hidden layer drop-down menu, obtain the target number of hidden layers of the initial model.

[0141] The second display unit is used to display the hidden layer configuration controls on the interactive interface according to the target number of hidden layers;

[0142] The third quantity acquisition unit is used to obtain the target number of neurons in the hidden layer in response to the input operation of the number of neurons in the hidden layer configuration control;

[0143] The third display unit is used to display the number of target hidden layers and the number of target neurons in each hidden layer in the model display area, and to update the connection relationships between neurons in the input layer, hidden layer and output layer in the model display area in real time.

[0144] Optionally, the initial model includes a first model and a second model;

[0145] Correspondingly, the device also includes: a target device performance determination model determination module;

[0146] The target device performance determination model determination module includes:

[0147] The first sample voltage pair determination unit is used to determine multiple first sample voltage pairs of the sample device; the first sample voltage pair includes the sample drain-source voltage and the sample gate-source voltage.

[0148] The current prediction model determination unit is used to train the first model using multiple first sample voltage pairs to obtain the current prediction model.

[0149] The second sample voltage pair determination unit is used to normalize multiple first sample voltage pairs to obtain multiple second sample voltage pairs.

[0150] The charge prediction model determination unit is used to train the second model using multiple second sample voltage pairs to obtain the charge prediction model;

[0151] The target device performance determination model determination unit is used to obtain the target device performance determination model based on the current prediction model and the charge prediction model.

[0152] Optionally, the device may also include: a results display module;

[0153] The results display module includes:

[0154] The retraining unit is used to display hidden layer configuration controls in the interactive interface and retrain the target device performance determination model in response to the adjustment of the activation function of the hidden layer configuration controls.

[0155] The results display unit is used to display the convergence rate of the target device performance determination model and the device characteristic curves in the results display area of ​​the interactive interface.

[0156] Optionally, the device may also include: a file generation module;

[0157] The file generation module includes:

[0158] The name retrieval unit is used to display the model name configuration control on the interactive interface and obtain the model name in response to the input operation of the model name configuration control;

[0159] The file generation unit is used to display zoom-in or zoom-out controls in the model display area of ​​the interactive interface. In response to the click operation of the save button in the interactive interface, it saves the model parameters of the initial device performance determination model in JSON format according to the model name.

[0160] The device performance determination model construction apparatus provided in the embodiments of the present invention can execute the device performance determination model construction method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0161] According to embodiments of the present invention, the present invention also provides an electronic device, a readable storage medium, and a computer program product.

[0162] Figure 16 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0163] like Figure 16 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0164] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0165] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as methods for constructing device performance determination models.

[0166] In some embodiments, the method for constructing a device performance determination model can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the method for constructing the device performance determination model described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to execute the method for constructing the device performance determination model by any other suitable means (e.g., by means of firmware).

[0167] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0168] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0169] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0170] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0171] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0172] A computing system can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product within the cloud computing service system to address the shortcomings of traditional physical hosts and virtual private servers, such as high management difficulty and weak business scalability.

[0173] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0174] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for constructing a device performance determination model, characterized in that, The method includes: In response to configuration operations on the input and output layers of the initial model in the interactive interface, the number of neurons in the input and output layers is obtained and displayed in the model display area of ​​the interactive interface. In response to the configuration operation of the hidden layers of the initial model in the interactive interface, the target number of hidden layers and the target number of neurons in each hidden layer of the initial model are obtained and displayed in the model display area; In response to the selection operation of the activation function of the hidden layer in the interactive interface, the target activation function of the hidden layer is obtained and displayed in the model display area; In response to the model loading operation, an initial device performance determination model is constructed and displayed in the model display area based on the number of neurons in the input layer and the output layer, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation function of the hidden layer.

2. The method according to claim 1, characterized in that, The step of responding to configuration operations on the input and output layers of the initial model in the interactive interface, obtaining the number of neurons in the input and output layers, and displaying them in the model display area of ​​the interactive interface includes: The interactive interface displays the input layer configuration control and the output layer configuration control of the initial model. In response to the input operation of the number of neurons in the input layer configuration control and the input operation of the number of neurons in the output layer configuration control, the first number of neurons in the input layer and the second number of neurons in the output layer are obtained. The input layer and the output layer are displayed in real time in the model display area of ​​the interactive interface.

3. The method according to claim 1, characterized in that, The step of responding to the configuration operation of the hidden layers of the initial model on the interactive interface, obtaining the target number of hidden layers and the target number of neurons in each hidden layer of the initial model, and displaying them in the model display area includes: The interactive interface displays a hidden layer drop-down menu, and in response to the selection operation of the number of hidden layers in the hidden layer drop-down menu, the target number of hidden layers of the initial model is obtained; The hidden layer configuration control is displayed on the interactive interface according to the target number of hidden layers; In response to an input operation on the number of neurons in the hidden layer configuration control, the target number of neurons in the hidden layer is obtained; The model display area shows the number of target hidden layers and the number of target neurons in each hidden layer, and updates the connection relationships between neurons in the input layer, the hidden layer and the output layer in real time in the model display area.

4. The method according to claim 1, characterized in that, The initial model includes a first model and a second model; Accordingly, the method further includes: Determine multiple first sample voltage pairs for the sample device; the first sample voltage pair includes sample drain-source voltage and sample gate-source voltage; The first model is trained using the multiple first sample voltage pairs to obtain the current prediction model; The plurality of first sample voltage pairs are normalized to obtain a plurality of second sample voltage pairs; The second model is trained using the multiple second sample voltage pairs to obtain the charge prediction model; Based on the current prediction model and the charge prediction model, a target device performance determination model is obtained.

5. The method according to claim 4, characterized in that, The method further includes: The interactive interface displays a hidden layer configuration control, and in response to the adjustment of the activation function of the hidden layer configuration control, the target device performance determination model is retrained. The results display area of ​​the interactive interface shows the convergence rate of the target device performance determination model and the device characteristic curves.

6. The method according to claim 1, characterized in that, The method further includes: The interactive interface displays a model name configuration control, and the model name is obtained in response to the input operation of the model name configuration control; In response to a click on the save button in the interactive interface, the model parameters of the initial device performance determination model are saved in JSON format according to the model name.

7. The method according to claim 1, characterized in that, The method further includes: A zoom-in or zoom-out control is displayed in the model display area of ​​the interactive interface. In response to the click operation of the zoom-in or zoom-out control in the model display area, the content displayed in the model display area is zoomed in or zoomed out.

8. An apparatus for constructing a device performance determination model, characterized in that, The device includes: The first configuration module is used to respond to the configuration operations of the input layer and output layer of the initial model in the interactive interface, respectively, to obtain the number of neurons in the input layer and the output layer, and to display them in the model display area of ​​the interactive interface; The second configuration module is used to respond to the configuration operation of the hidden layers of the initial model on the interactive interface, obtain the target number of hidden layers and the target number of neurons in each hidden layer of the initial model, and display them in the model display area; A function selection module is used to obtain the target activation function of the hidden layer in response to the selection operation of the activation function of the hidden layer in the interactive interface, and display it in the model display area. The model building module is used to respond to the model loading operation by constructing an initial device performance determination model based on the number of neurons in the input layer and the output layer, the number of hidden layers in the initial model, the number of neurons in each hidden layer, and the target activation function of the hidden layer, and then displaying it in the model display area.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, which is then executed by the at least one processor to enable the at least one processor to perform the method for constructing the device performance determination model according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the method for constructing the device performance determination model according to any one of claims 1-7.

11. A computer program product comprising a computer program that, when executed by a processor, implements a method for constructing a device performance determination model according to any one of claims 1-7.

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