A signal pre-equalization circuit and electronic chip

Abstract

The application provides a signal pre-equalization circuit and an electronic chip, and relates to the technical field of memory interfaces. The circuit comprises a driver module, an equalization control module and a pre-equalization module. The input end of the driver module receives an input data signal, and the output end of the driver module is coupled to an output node. The input end of the equalization control module receives the input data signal, and the equalization control module is configured to generate a corresponding control pulse in response to a jump of the input data signal. The pre-equalization module is coupled between a power supply, the output node and a ground, and is controlled by the control pulse. In a pre-emphasis mode, the pre-equalization module injects or extracts a transient current to the output node during a jump of the input data signal in response to the control pulse. In a de-emphasis mode, the pre-equalization module is turned off during a jump of the input data signal in response to the control pulse, and provides a steady-state bias current to the output node when the input data signal is in a steady state, so as to reduce the amplitude of an output signal. The application has the advantages of high adjustment precision, low power consumption, small area and no influence on bandwidth.

Description

Technical Field

[0001] This application relates to the field of memory interface technology, and more specifically, to a signal pre-equalization circuit and electronic chip. Background Technology

[0002] In fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) interface chips, as speed and energy efficiency improve, the chip output power supply voltage drops to 1.1V. Due to the increasing speed of the transmitter (TX), the output signal is susceptible to attenuation caused by package parasitic inductance and long channel lengths, resulting in inter-symbol interference (ISI). Therefore, the transmitter needs to use pre-equalization techniques to improve the signal.

[0003] In high-speed links at double data rates, signal integrity is crucial for overall system performance. Therefore, high-speed signals must maintain good quality after packaging and long channels. However, DDR memory chip circuit traces are typically long with significant insertion loss, making high-speed signals highly susceptible to attenuation. The transmitter needs to provide strong signal pre-compensation capabilities and flexible compensation schemes for different channel traces. Furthermore, the transmitter requires optimal energy efficiency, posing a significant challenge to its pre-equalization design.

[0004] Traditional pre-emphasis techniques typically involve connecting a high-frequency enhancement path, consisting of an inverter and a capacitor in series, in parallel at the driver output. This approach has significant drawbacks: the capacitor occupies a large chip area, and its parasitic capacitance degrades the output bandwidth; furthermore, the acceleration time of the capacitive coupling is difficult to control precisely, easily causing signal overshoot and exacerbating channel reflections. Traditional de-emphasis techniques achieve this by driving a portion of the parallel driver units with the input data and its delayed inverted signal, respectively. The de-emphasis intensity is adjusted by changing the number of conducting driver units. This approach leads to a trade-off between adjustment accuracy and output load / power consumption: achieving high accuracy requires a large number of parallel units, increasing the output load and limiting bandwidth; and when transmitting low-frequency data, there is a significant DC power consumption path, resulting in low energy efficiency.

[0005] Therefore, existing pre-equalization techniques struggle to achieve a balance between multiple objectives, including high-precision adjustment, low power consumption, small area, and no impact on bandwidth. Summary of the Invention

[0006] The purpose of this application is to provide a signal pre-equalization circuit and electronic chip to solve the problem that existing pre-equalization technologies are unable to achieve a balance between multiple objectives such as high-precision adjustment, low power consumption, small area, and no impact on bandwidth.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0008] On one hand, embodiments of this application provide a signal pre-equalization circuit, the signal pre-equalization circuit comprising:

[0009] The driver module receives input data signals at its input terminal and its output terminal is coupled to the output node.

[0010] The equalization control module receives the input data signal at its input terminal and is configured to generate corresponding control pulses in response to the transition of the input data signal;

[0011] The pre-equalization module is coupled between the power supply, the output node, and ground, and is controlled by the control pulse;

[0012] The pre-equalization module can operate in a pre-emphasis mode or a deemphasis mode; in the pre-emphasis mode, the pre-equalization module responds to the control pulse and injects or extracts transient current into the output node during the transition of the input data signal.

[0013] In the de-emphasis mode, the pre-equalization module responds to the control pulse, is turned off during the transition of the input data signal, and provides a steady-state bias current to the output node when the input data signal is in a steady state, so as to reduce the amplitude of the output signal.

[0014] Optionally, the pre-equalization module includes a first controllable current path and a second controllable current path, wherein the first controllable current path is coupled between the power supply and the output node, and the second controllable current path is coupled between the output node and ground; wherein,

[0015] In the pre-emphasis mode, the first controllable current path is activated in response to the rising edge of the input data signal to inject transient current into the output node; the second controllable current path is activated in response to the falling edge of the input data signal to extract transient current from the output node.

[0016] In the de-emphasis mode, when the input data signal is at a steady-state high level, the second controllable current path is activated to draw steady-state current from the output node; when the input data signal is at a steady-state low level, the first controllable current path is activated to inject steady-state current into the output node.

[0017] Optionally, the first controllable current path includes a P-type switch, a first current source, and a first switching assembly. The drain of the P-type switch is coupled to the output node, the source of the P-type switch is coupled to the power supply through the first current source, and the gate of the P-type switch is coupled to the equalization control module through the first switching assembly.

[0018] The second controllable current path includes an N-type switch, a second current source, and a second switching assembly. The drain of the N-type switch is coupled to the output node, the source of the N-type switch is coupled to ground through the second current source, and the gate of the N-type switch is coupled to the equalization control module through the second switching assembly.

[0019] Optionally, the first switching assembly includes a first pre-emphasis enable switch and a first deemphasis enable switch, the second switching assembly includes a second pre-emphasis enable switch and a second deemphasis enable switch, and the equalization control module includes a first equalization control unit and a second equalization control unit.

[0020] One end of the first pre-emphasis enable switch and the first de-emphasis enable switch is connected to the gate of the P-type switch, and one end of the second pre-emphasis enable switch and the second de-emphasis enable switch is connected to the gate of the N-type switch; the other end of the first pre-emphasis enable switch and the second de-emphasis enable switch is connected to the output terminal of the first equalization control unit; the other end of the first de-emphasis enable switch and the second pre-emphasis enable switch is connected to the output terminal of the second equalization control unit.

[0021] In the pre-emphasis mode, the first pre-emphasis enable switch and the second pre-emphasis enable switch are synchronously turned on, and the first de-emphasis enable switch and the second de-emphasis enable switch are turned off.

[0022] In the de-emphasis mode, when the input data signal is at a steady-state high level, the second de-emphasis enable switch is turned on, and the first pre-emphasis enable switch, the second pre-emphasis enable switch, and the first de-emphasis enable switch are all turned off; when the input data signal is at a steady-state low level, the first de-emphasis enable switch is turned on, and the first pre-emphasis enable switch, the second pre-emphasis enable switch, and the second de-emphasis enable switch are all turned off.

[0023] Optionally, the equalization control module includes a first equalization control unit and a second equalization control unit. The input terminals of the first equalization control unit and the second equalization control unit both receive input data signals, and the output terminals of the first equalization control unit and the second equalization control unit are both coupled to the pre-equalization module.

[0024] The first equalization control unit and the second equalization control unit are configured to generate corresponding first control pulses and second control pulses in response to the transition of the input data signal.

[0025] Optionally, the first equalization control unit includes a first delay chain, a first inverter, and a first logic device. The first input terminal of the first logic device receives an input data signal. The first delay chain, the first inverter, and the second input terminal of the first logic device are connected in series. The first delay chain receives the input data signal. The output terminal of the first logic device is used to output the first control pulse.

[0026] The second equalization control unit includes a second delay chain, a second inverter, and a second logic device. The first input terminal of the second logic device is connected to the second delay chain, and the second input terminal of the second logic device is connected to the second inverter. The input terminals of the second delay chain and the second inverter receive the input data signal, and the output terminal of the second logic device is used to output the second control pulse.

[0027] The width of the first control pulse is determined by the delay time of the first delay chain, and the width of the second control pulse is determined by the delay time of the second delay chain.

[0028] Optionally, the first logic device is a NAND gate, and the second logic device is an AND gate; or,

[0029] Both the first logic device and the second logic device are selectors.

[0030] Optionally, the driver module includes a drive control unit and a plurality of drive units connected in parallel. The drive control unit is connected to a switching transistor in each of the drive units, and the input terminal of the drive control unit receives the input data signal and is configured to generate a corresponding drive signal in response to the transition of the input data signal.

[0031] Optionally, each drive unit includes a first switch and a second switch, and the drive control unit includes a third logic device, a fourth logic device and a third inverter. The first input terminal of the third logic device receives an input data signal, the second input terminal of the third logic device receives an enable control signal, and the output terminal of the third logic device is connected to the control terminal of the first switch.

[0032] The first input terminal of the fourth logic device receives an enable control signal, the second input terminal of the fourth logic device is connected to the third inverter, the input terminal of the third inverter receives the input data signal, and the output terminal of the fourth logic device is connected to the control terminal of the second switch.

[0033] On the other hand, this application also provides an electronic chip, which includes the above-described signal pre-equalization circuit.

[0034] Compared with the prior art, this application has the following advantages:

[0035] This application provides a signal pre-equalization circuit and electronic device. The signal pre-equalization circuit includes a driver module whose input terminal receives an input data signal and whose output terminal is coupled to an output node; an equalization control module whose input terminal receives the input data signal and is configured to generate a corresponding control pulse in response to the transition of the input data signal; and a pre-equalization module coupled between a power supply, an output node, and ground, and controlled by the control pulse. The pre-equalization module can operate in a pre-emphasis mode or a de-emphasis mode. In the pre-emphasis mode, the pre-equalization module, in response to the control pulse, injects or extracts transient current to the output node during the transition of the input data signal. In the de-emphasis mode, the pre-equalization module, in response to the control pulse, is turned off during the transition of the input data signal and provides a steady-state bias current to the output node when the input data signal is in a steady state, thereby reducing the amplitude of the output signal.

[0036] Because the signal pre-equalization circuit provided in this application includes only a few modules, it is easy to integrate, achieving the goal of small area. Furthermore, by using the same pre-equalization module in conjunction with configurable control logic, both pre-emphasis and de-emphasis modes can be implemented, allowing for flexible selection of the optimal equalization strategy based on channel characteristics. In addition, the pre-equalization module uses current injection / extraction to implement pre-emphasis and de-emphasis modes; the equalization strength can be achieved by precisely adjusting the current injection / extraction, thus enabling high-precision adjustment without affecting bandwidth.

[0037] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is an electrical schematic diagram of the signal pre-equalization circuit provided in an embodiment of this application.

[0040] Figure 2 This is a waveform comparison diagram showing the pre-emphasis mode with and without pre-emphasis mode provided in an embodiment of this application.

[0041] Figure 3 This is a waveform diagram of the pre-emphasis mode provided in this application.

[0042] Figure 4 This is a waveform diagram of the deemphasis mode provided in this application.

[0043] In the picture:

[0044] 110 - Equalization control module; 111 - First equalization control unit; 1111 - First delay chain; 1112 - First inverter; 1113 - First logic device; 112 - Second equalization control unit; 1121 - Second delay chain; 1122 - Second inverter; 1123 - Second logic device; 120 - Driver module; 121 - Third logic device; 122 - Fourth logic device; 123 - Third inverter; 130 - Pre-equalization module; 131 - First controllable current path; 132 - Second controllable current path; M1 - P-type switch; I1 - First current source; M2 - N-type switch; I2 - Second current source; K1 - First pre-emphasis enable switch; K2 - First de-emphasis enable switch; K3 - Second pre-emphasis enable switch; K4 - Second de-emphasis enable switch; M3 - First switch; M4 - Second switch; R1 - First resistor; R2 - Second resistor. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0047] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0048] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0049] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0050] As described in the background section, current pre-equalization techniques struggle to achieve a balance between multiple objectives, including high-precision adjustment, low power consumption, small area, and no impact on bandwidth.

[0051] In view of this, in order to solve the above problems, this application provides a signal pre-equalization circuit. For one implementation method, please refer to... Figure 1 The signal pre-equalization circuit includes a driver module 120, an equalization control module 110, and a pre-equalization module 130. The driver module 120 receives the input data signal at its input terminal and its output terminal is coupled to the output node. The equalization control module 110 receives the input data signal at its input terminal and is configured to generate corresponding control pulses in response to transitions in the input data signal. The pre-equalization module 130 is coupled between the power supply, the output node, and ground, and is controlled by the control pulses. The pre-equalization module 130 can operate in a pre-emphasis mode or a de-emphasis mode. In pre-emphasis mode, the pre-equalization module 130, in response to the control pulses, injects or extracts transient current into the output node during input data signal transitions. In de-emphasis mode, the pre-equalization module 130, in response to the control pulses, is turned off during input data signal transitions and provides a steady-state bias current to the output node when the input data signal is in a steady state, thereby reducing the amplitude of the output signal.

[0052] Understandably, in this application, both pre-emphasis and de-emphasis modes can be achieved through the same pre-equalization module 130 and configurable control logic. The optimal equalization strategy can be flexibly selected based on channel characteristics, achieving a unified architecture and flexible modes. Simultaneously, the use of current injection / extraction allows for precise control of the pulse width to achieve equalization intensity with high adjustment accuracy. Furthermore, this method can be implemented using a current source structure, minimizing the impact on the output node load and avoiding significant degradation of circuit bandwidth. Moreover, in pre-emphasis mode, the pre-equalization module 130 operates only for a brief period during signal transitions; in de-emphasis mode, although steady-state current exists, the current injection / extraction is adjustable, resulting in controllable overall power consumption. In addition, the entire signal pre-equalization circuit has fewer modules, making it easier to integrate and reducing the overall area.

[0053] The output node is used to connect to an external channel. As one implementation method, the pre-equalization module 130 operates in pre-emphasis mode or de-emphasis mode according to the working mode enable signal and the received control pulse, and adjusts the current of the output node.

[0054] As one implementation, the pre-equalization module 130 includes a first controllable current path 131 and a second controllable current path 132. The first controllable current path 131 is coupled between the power supply and the output node, and the second controllable current path 132 is coupled between the output node and ground. In pre-emphasis mode, the first controllable current path 131 is activated in response to the rising edge of the input data signal to inject transient current into the output node; the second controllable current path 132 is activated in response to the falling edge of the input data signal to draw transient current from the output node. In de-emphasis mode, when the input data signal is at a steady-state high level, the second controllable current path 132 is activated to draw steady-state current from the output node; when the input data signal is at a steady-state low level, the first controllable current path 131 is activated to inject steady-state current into the output node.

[0055] It should be noted that the pre-emphasis described in this application is a signal pre-equalization technique, the core of which lies in selectively enhancing the high-frequency components of the signal to compensate for the attenuation of the signal edges caused by the channel. In the circuit, a controllable current path coupled to the output node is controlled to inject or extract a transient, pulsed current into or from the node during the transition edge. This transient current is superimposed on the drive current provided by the driver module 120, significantly increasing the charging and discharging current of the output node during the transition. Figure 2 As shown, this method can accelerate the voltage change rate (dv / dt) of the output signal, making the signal edges steeper. When the input data signal is in a steady state, the controllable current path is turned off, which does not affect the DC level of the output node, thereby maintaining the integrity of the output signal amplitude and achieving the purpose of counteracting high-frequency loss of the channel and reducing inter-symbol interference.

[0056] De-emphasis is also a signal pre-equalization technique, the core of which lies in relatively attenuating the low-frequency components of the signal to reduce inter-symbol interference caused by the channel. In the circuit, a controllable current path connected in parallel with the output node of the driver module 120 provides a continuous, steady-state bias current to the node during steady-state conditions. Specifically, when the output is at a steady-state high level, the bias current is the current drawn from the output node, forming a shunt and pulling down the actual voltage value of the high-level output. When the output is at a steady-state low level, the bias current is the current injected into the output node, forming a pull-up and raising the actual voltage value of the low-level output. At the same time, during the transient period when the input data signal changes, the controllable current path is briefly turned off to ensure that the edge of the output signal is fully driven by the driver module 120, maintaining the steepness of the edge.

[0057] Through the above operations, the pre-equalization module 130 can actively compress the voltage swing of the output signal in steady state. This makes the signal amplitude smaller than the amplitude after a transition when continuously transmitting the same data bits (long "0" or long "1"). In this implementation, on the one hand, since the voltage swing of the output signal in steady state has been compressed, the total amplitude required for each transition in the next transition can be lower, thereby increasing the transition rate. For example, when the de-emphasis mode is not enabled, the high-level amplitude of the signal is 1V, and the low-level amplitude is -1V. Therefore, the total amplitude of each transition in the following transitions is 2V. However, when the de-emphasis mode is enabled, the high-level amplitude of the signal may be lowered to 0.8V, and the low-level amplitude may be raised to -0.8V, resulting in a total amplitude of 1.6V for each transition in the following transitions. This shortens the time required for signal transitions. Combined with the effect of accelerating the voltage change rate of the output signal in the pre-emphasis mode, the time required for signal transitions can be further shortened. On the other hand, the pre-equalization module 130 of this application makes the signal amplitude at the sampling time of the receiver determined more by the recent jump, thus suppressing the trailing interference caused by the preceding bit to the current bit.

[0058] It should also be noted that the "steady state" mentioned in this application is a concept relative to "transition." For example, for the rising edge of an input data signal, the signal transitions from a low level to a high level; while for the falling edge of an input data signal, the signal transitions from a high level to a low level. A stable high level means that after the signal transitions from a low level to a high level, it remains at a high level for a period of time. During this period, the input data signal is at a steady-state high level; a steady-state low level is the opposite.

[0059] Understandably, current can be injected into the output node through the first controllable current path 131, and current can be drawn from the output node through the second controllable current path 132. This allows for rapid signal transitions during pre-emphasis mode, thus accelerating the transition of the output signal. In de-emphasis mode, the voltage swing of the output signal VOUT in steady state can be compressed.

[0060] In one implementation, the first controllable current path 131 includes a P-type switch M1, a first current source I1, and a first switching assembly. The drain of the P-type switch M1 is coupled to the output node, the source of the P-type switch M1 is coupled to the power supply through the first current source I1, and the gate of the P-type switch M1 is coupled to the equalization control module 110 through the first switching assembly. The second controllable current path 132 includes an N-type switch M2, a second current source I2, and a second switching assembly. The drain of the N-type switch M2 is coupled to the output node, the source of the N-type switch M2 is coupled to ground through the second current source I2, and the gate of the N-type switch M2 is coupled to the equalization control module 110 through the second switching assembly.

[0061] The first switching assembly includes a first pre-emphasis enable switch K1 and a first deemphasis enable switch K2; the second switching assembly includes a second pre-emphasis enable switch K3 and a second deemphasis enable switch K4; the equalization control module 110 includes a first equalization control unit 111 and a second equalization control unit 112; one end of the first pre-emphasis enable switch K1 and the first deemphasis enable switch K2 is connected to the gate of the P-type switching transistor M1; one end of the second pre-emphasis enable switch K3 and the second deemphasis enable switch K4 is connected to the gate of the N-type switching transistor M2; the other end of the first pre-emphasis enable switch K1 and the second deemphasis enable switch K4 is connected to the output terminal of the first equalization control unit 111; the first deemphasis enable switch K2 and the second deemphasis enable switch K3 and the second deemphasis enable switch K4 are connected to the gate of the N-type switching transistor M2; the other end of the first pre-emphasis enable switch K1 and the second deemphasis enable switch K4 are connected to the output terminal of the first equalization control unit 111; the first deemphasis enable switch K3 and the second deemphasis enable switch K4 are connected to the gate of the N-type switching transistor M2; the first pre- ... first pre-emphasis enable switch K1 and the second deemphasis The other end of the second pre-emphasis enable switch K3 is connected to the output terminal of the second equalization control unit 112. In pre-emphasis mode, the first pre-emphasis enable switch K1 and the second pre-emphasis enable switch K3 are synchronously turned on, and the first de-emphasis enable switch K2 and the second de-emphasis enable switch K4 are turned off. In de-emphasis mode, when the input data signal is at a steady-state high level, the second de-emphasis enable switch K4 is turned on, and the first pre-emphasis enable switch K1, the second pre-emphasis enable switch K3, and the first de-emphasis enable switch K2 are all turned off. When the input data signal is at a steady-state low level, the first de-emphasis enable switch K2 is turned on, and the first pre-emphasis enable switch K1, the second pre-emphasis enable switch K3, and the second de-emphasis enable switch K4 are all turned off.

[0062] Based on this, it can be understood that the input terminal of the equalization control module 110 receives the input data signal and generates two control pulses ( Figure 1 The outputs of DP2 and DN2 are sent to the pre-equalization module 130. The pre-equalization module 130 operates in pre-emphasis mode or de-emphasis mode according to the operating mode enable signal and the received control pulses, adjusting the current of the output nodes. Specifically, the operating mode enable signal controls the on / off states of the first pre-emphasis enable switch K1, the first de-emphasis enable switch K2, the second pre-emphasis enable switch K3, and the second de-emphasis enable switch K4; the two control pulses control the on / off states of the P-type switch M1 and the N-type switch M2.

[0063] In one implementation, the equalization control module 110 includes a first equalization control unit 111 and a second equalization control unit 112. The input terminals of both the first and second equalization control units 111 and 112 receive input data signals, and their output terminals are both coupled to the pre-equalization module 130. The first and second equalization control units 111 and 112 are configured to generate corresponding first control pulse DP2 and second control pulse DN2 in response to changes in the input data signals. In conjunction with the pre-equalization module 130, it can be understood that the first control pulse DP2 is used to control the on / off state of the first controllable current path 131, and the second control pulse DN2 is used to control the on / off state of the second controllable current path 132.

[0064] The first equalization control unit 111 includes a first delay chain 1111, a first inverter 1112, and a first logic device 1113. The first input terminal of the first logic device 1113 receives an input data signal. The second input terminals of the first delay chain 1111, the first inverter 1112, and the first logic device 1113 are connected in series. The first delay chain 1111 receives the input data signal, and the output terminal of the first logic device 1113 is used to output a first control pulse DP2. The second equalization control unit 112 includes a second delay chain 1121, a second inverter 1112, and a second delay chain 1113. 22 and a second logic device 1123, the first input terminal of the second logic device 1123 is connected to the second delay chain 1121, the second input terminal of the second logic device 1123 is connected to the second inverter 1122, the input terminals of the second delay chain 1121 and the second inverter 1122 receive input data signals, and the output terminal of the second logic device 1123 is used to output the second control pulse DN2; the width of the first control pulse DP2 is determined by the delay time of the first delay chain 1111, and the width of the second control pulse DN2 is determined by the delay time of the second delay chain 1121.

[0065] In this application, the specific types of the first logic device 1113 and the second logic device 1123 are not limited, as long as they can perform the corresponding logic functions. For example, the first logic device 1113 is a NAND gate and the second logic device 1123 is an AND gate; or, the first logic device 1113 and the second logic device 1123 are both selectors.

[0066] Taking the first logic device 1113 as a NAND gate and the second logic device 1123 as an AND gate as an example, for the first equalization control unit 111, when the input data signal has a rising edge, the input data signal immediately becomes high, while the delay chain output DLP has not changed (it is still low), and becomes high after passing through the inverter.

[0067] The second equalization control unit 112 generates a signal to control the second controllable current path 132. For the second equalization control unit 112, when the input data signal experiences a falling edge, the input data signal immediately goes low, and the AND gate output immediately goes low. Simultaneously, the input data signal is inverted and goes high. This high level is delayed by a delay chain T before being transmitted to the other input of the AND gate, causing the AND gate output to return to high after a time T. This generates a low-level pulse with a width of T. By adjusting the delay times of the first delay chain 1111 and the second delay chain 1121, the pulse width of the pre-emphasis current can be precisely controlled, or the duration for which the second current source I2 is turned off in de-emphasis mode can be controlled, thereby achieving fine adjustment of the equalization intensity and reflection suppression.

[0068] In one implementation, the driver module 120 includes a drive control unit and multiple drive units connected in parallel. The drive control unit is connected to a switching transistor in each drive unit, and the input terminal of the drive control unit receives input data signals and is configured to generate corresponding drive signals in response to the transitions of the input data signals. Figure 1 (DP1 and DN1).

[0069] Each drive unit includes a first switch M3 and a second switch M4, as well as a first resistor R1 and a second resistor R2. The drive control unit includes a third logic device 121, a fourth logic device 122, and a third inverter 123. The first input terminal of the third logic device 121 receives an input data signal, the second input terminal of the third logic device 121 receives an enable control signal, and the output terminal of the third logic device 121 is connected to the control terminal of the first switch M3. The first input terminal of the fourth logic device 122 receives an enable control signal, the second input terminal of the fourth logic device 122 is connected to the third inverter 123, the input terminal of the third inverter 123 receives an input data signal, and the output terminal of the fourth logic device 122 is connected to the control terminal of the second switch M4.

[0070] Understandably, in each driving unit, the first switching transistor M3 acts as a pull-up transistor, and the second switching transistor M4 acts as a pull-down transistor, and each driving unit constitutes a driver with an inverter structure. The driving control unit is used to generate driving signals, the first driving signal DP1 and the second driving signal DN1, to control the gates of the first switching transistor M3 and the second switching transistor M4. In one embodiment, the driving control unit includes a third logic device 121, a fourth logic device 122, and a third inverter 123. For example, the first logic device 121 uses a NAND gate, and the fourth logic device 122 uses a NOT gate. This makes the gate circuit structures of the driving control unit and the equalization control module 110 similar (both use NAND gates and AND gates), thus facilitating integration and reducing the overall circuit area.

[0071] For the first equalization control unit, the input data signal D is sent to one input of a NAND gate, and the other input of the NAND gate receives the enable control signal EN. The output of the NAND gate is DP1, which is used to control the first switching transistor M3. For the second equalization control unit, the input data signal D is sent to a third inverter, and the output of the third inverter, along with the enable control signal EN, is sent to the input of an AND gate. The output of the AND gate is DN1, which is used to control the second switching transistor M4. When EN is active, DP1 and D are in phase, and DN1 and D are out of phase, and the driver operates normally. When EN is inactive, DP1 and DN1 are low, M3 and M4 are both off, and the driver is in a high-impedance state. By connecting multiple such drive units in parallel and controlling their respective EN signals, the strength adjustment of the driver itself (such as impedance matching) can be achieved.

[0072] It should be noted that the specific circuit structures, logic gate types, and control polarities of the switching transistors in the above figures and embodiments are merely examples. Those skilled in the art can make various modifications based on the concept of this application. For example, logic devices can be implemented using other types of gate circuit combinations to achieve the same function; switching components can be implemented using transmission gates, independent MOS switches, etc.; current sources can be implemented using diode-connected MOS transistors, precision current sources with operational amplifiers, etc.; delay chains can be implemented using digitally controlled adjustable delay units, analog RC delays, etc.

[0073] The signal pre-equalization circuit provided in this application is illustrated below with specific waveform diagrams:

[0074] Please combine Figure 3 and Figure 1The circuit is configured in pre-emphasis mode with pre-emphasis enabled. DP1 and DN1 are the input signals of the driver unit; DLP and DLN are the signals of the input data signal D after passing through the delay chain; DP2 is the logical AND-NOT signal of DLP and the input data signal D; DN2 is the logical AND signal of DLN and the input data signal D. When the input data signal D transitions from low to high, assuming the delay of the delay chain is T, DP2 generates a low-level pulse with a pulse width of T. Similarly, the DN2 signal is low at this time. Furthermore, in pre-emphasis mode, K1 and K3 are turned on, and K2 and K4 are turned off, enabling DP2 to open the pull-up current path. The first current source injects current into the output signal of the driver unit, thereby accelerating the rise of the output signal VOUT. When the input data signal D transitions from high to low, DN2 generates a high-level pulse with a pulse width of T, and similarly, the DP2 signal is high at this time. Furthermore, in pre-emphasis mode, K1 and K3 are turned on, while K2 and K4 are turned off, allowing the high-level pulse DN2 to open the pull-down current path. The second current source draws current from the output node, thereby accelerating the descent of the output signal. When the input signal is a long high or long low DC signal, DP2 is high and DN2 is low, keeping both the pull-up and pull-down current paths closed. Therefore, this circuit achieves the pre-emphasis effect. The intensity of the pre-emphasis can be adjusted by changing the current source or the delay chain time. Additionally, channel reflections can be eliminated in this mode by adjusting the delay chain time.

[0075] Please see Figure 4 and Figure 1 When the deemphasis enable is turned on, the circuit is configured in deemphasis mode. When the input data signal D is a steady-state high level, DP2 is high and DN2 is low. Simultaneously, K4 is turned on, and K1, K2, and K3 are turned off, keeping the pull-down current path open. At this time, a DC path exists between the drive unit and the pull-down current path, reducing the high-level amplitude of the drive unit's output. Similarly, when the input signal is a long low DC signal, DN2 is low, DP2 is high, K3 is turned on, and K1, K2, and K4 are turned off, keeping the pull-up current path open. At this time, a DC path exists between the drive unit and the pull-up current path, increasing the low-level amplitude of the drive unit's output. Therefore, this circuit achieves the deemphasis effect. The strength of the deemphasis can be adjusted by changing the current of the current mirror or the delay time of the delay chain.

[0076] Understandably, this application has at least the following advantages:

[0077] 1. Unified architecture and flexible modes: Through the same pre-equalization module and configurable control logic, both pre-emphasis and de-emphasis modes can be implemented, and the optimal equalization strategy can be flexibly selected according to the channel characteristics.

[0078] 2. High precision and low impact: Current injection / extraction is performed using a current source bias. The equalization intensity can be achieved by precisely adjusting the current source size or controlling the pulse width, resulting in high adjustment precision. The current mirror structure has a small area, minimizing its impact on the output node load and not significantly degrading the circuit bandwidth.

[0079] 3. High energy efficiency: In pre-emphasis mode, the current path only works for a short time during signal transition; in de-emphasis mode, although there is steady-state current, the current value can be precisely set and controlled by the current source, and the overall power consumption is controllable, which is better than the DC power consumption path of traditional solutions.

[0080] 4. Reflection suppression: By finely adjusting the width of the control pulse (i.e., the duration of the equalization effect), the channel characteristics can be matched, effectively avoiding signal overshoot caused by overcompensation, thereby suppressing channel reflection.

[0081] Furthermore, it should be noted that, in order to achieve the best pre-equalization effect, the delay T of the first delay chain and the second delay chain provided in this application is greater than the transition time required for the input data signal when the pre-equalization mode is not enabled, and less than one period of the data frequency, so that pre-equalization can be achieved throughout the entire transition process of the input data signal.

[0082] 5. Easy to integrate: The circuit mainly consists of MOS switches, current sources, digital logic gates, and adjustable delay chains, making it very suitable for implementation and integration in mainstream CMOS processes. Furthermore, it should be noted that when both the equalization control module and the drive control unit use gate circuits, both include NAND gates and AND gates, further facilitating integration.

[0083] Based on the above implementation, this application also provides an electronic chip, which includes the above-described signal pre-equalization circuit.

[0084] In summary, embodiments of this application provide a signal pre-equalization circuit and electronic device. The signal pre-equalization circuit includes a driver module whose input terminal receives an input data signal and whose output terminal is coupled to an output node; an equalization control module whose input terminal receives the input data signal and is configured to generate a corresponding control pulse in response to the transition of the input data signal; and a pre-equalization module coupled between a power supply, an output node, and ground, and controlled by the control pulse. The pre-equalization module can operate in a pre-emphasis mode or a de-emphasis mode. In the pre-emphasis mode, the pre-equalization module, in response to the control pulse, injects or extracts transient current into the output node during the transition of the input data signal. In the de-emphasis mode, the pre-equalization module, in response to the control pulse, is turned off during the transition of the input data signal and provides a steady-state bias current to the output node when the input data signal is in a steady state, thereby reducing the amplitude of the output signal.

[0085] Because the signal pre-equalization circuit provided in this application includes only a few modules, it is easy to integrate, achieving the goal of small area. Furthermore, by using the same pre-equalization module in conjunction with configurable control logic, both pre-emphasis and de-emphasis modes can be implemented, allowing for flexible selection of the optimal equalization strategy based on channel characteristics. In addition, the pre-equalization module uses current injection / extraction to implement pre-emphasis and de-emphasis modes; the equalization strength can be achieved by precisely adjusting the current injection / extraction, thus enabling high-precision adjustment without affecting bandwidth.

[0086] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0087] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A signal pre-equalization circuit, characterized in that, The signal pre-equalization circuit includes: The driver module receives input data signals at its input terminal and its output terminal is coupled to the output node. The equalization control module receives the input data signal at its input terminal and is configured to generate corresponding control pulses in response to the transition of the input data signal; The pre-equalization module is coupled between the power supply, the output node, and ground, and is controlled by the control pulse; The pre-equalization module can operate in a pre-emphasis mode or a deemphasis mode; in the pre-emphasis mode, the pre-equalization module responds to the control pulse and injects or extracts transient current into the output node during the transition of the input data signal. In the de-emphasis mode, the pre-equalization module responds to the control pulse, is turned off during the input data signal transition, and provides a steady-state bias current to the output node when the input data signal is in a steady state, so as to reduce the amplitude of the output signal. The pre-equalization module includes a first controllable current path and a second controllable current path. The first controllable current path is coupled between the power supply and the output node, and the second controllable current path is coupled between the output node and ground. In the pre-emphasis mode, the first controllable current path is activated in response to the rising edge of the input data signal to inject transient current into the output node; the second controllable current path is activated in response to the falling edge of the input data signal to extract transient current from the output node. In the de-emphasis mode, when the input data signal is at a steady-state high level, the second controllable current path is activated to draw steady-state current from the output node; when the input data signal is at a steady-state low level, the first controllable current path is activated to inject steady-state current into the output node.

2. The signal pre-equalization circuit as described in claim 1, characterized in that, The first controllable current path includes a P-type switch, a first current source, and a first switching assembly. The drain of the P-type switch is coupled to the output node, the source of the P-type switch is coupled to the power supply through the first current source, and the gate of the P-type switch is coupled to the equalization control module through the first switching assembly. The second controllable current path includes an N-type switch, a second current source, and a second switching assembly. The drain of the N-type switch is coupled to the output node, the source of the N-type switch is coupled to ground through the second current source, and the gate of the N-type switch is coupled to the equalization control module through the second switching assembly.

3. The signal pre-equalization circuit as described in claim 2, characterized in that, The first switching assembly includes a first pre-emphasis enable switch and a first deemphasis enable switch; the second switching assembly includes a second pre-emphasis enable switch and a second deemphasis enable switch; and the equalization control module includes a first equalization control unit and a second equalization control unit. One end of the first pre-emphasis enable switch and the first de-emphasis enable switch is connected to the gate of the P-type switch, and one end of the second pre-emphasis enable switch and the second de-emphasis enable switch is connected to the gate of the N-type switch; the other end of the first pre-emphasis enable switch and the second de-emphasis enable switch is connected to the output terminal of the first equalization control unit; the other end of the first de-emphasis enable switch and the second pre-emphasis enable switch is connected to the output terminal of the second equalization control unit. In the pre-emphasis mode, the first pre-emphasis enable switch and the second pre-emphasis enable switch are synchronously turned on, and the first de-emphasis enable switch and the second de-emphasis enable switch are turned off. In the de-emphasis mode, when the input data signal is at a steady-state high level, the second de-emphasis enable switch is turned on, and the first pre-emphasis enable switch, the second pre-emphasis enable switch, and the first de-emphasis enable switch are all turned off; when the input data signal is at a steady-state low level, the first de-emphasis enable switch is turned on, and the first pre-emphasis enable switch, the second pre-emphasis enable switch, and the second de-emphasis enable switch are all turned off.

4. The signal pre-equalization circuit as described in claim 1, characterized in that, The equalization control module includes a first equalization control unit and a second equalization control unit. The input terminals of the first equalization control unit and the second equalization control unit both receive input data signals, and the output terminals of the first equalization control unit and the second equalization control unit are both coupled to the pre-equalization module. The first equalization control unit and the second equalization control unit are configured to generate corresponding first control pulses and second control pulses in response to the transition of the input data signal.

5. The signal pre-equalization circuit as described in claim 4, characterized in that, The first equalization control unit includes a first delay chain, a first inverter, and a first logic device. The first input terminal of the first logic device receives an input data signal. The first delay chain, the first inverter, and the second input terminal of the first logic device are connected in series. The first delay chain receives the input data signal. The output terminal of the first logic device is used to output the first control pulse. The second equalization control unit includes a second delay chain, a second inverter, and a second logic device. The first input terminal of the second logic device is connected to the second delay chain, and the second input terminal of the second logic device is connected to the second inverter. The input terminals of the second delay chain and the second inverter receive the input data signal, and the output terminal of the second logic device is used to output the second control pulse. The width of the first control pulse is determined by the delay time of the first delay chain, and the width of the second control pulse is determined by the delay time of the second delay chain.

6. The signal pre-equalization circuit as described in claim 5, characterized in that, The first logic device is a NAND gate, and the second logic device is an AND gate; or, Both the first logic device and the second logic device are selectors.

7. The signal pre-equalization circuit as described in claim 1, characterized in that, The driver module includes a drive control unit and a plurality of drive units connected in parallel. The drive control unit is connected to a switch in each of the drive units, and the input terminal of the drive control unit receives the input data signal and is configured to generate a corresponding drive signal in response to the transition of the input data signal.

8. The signal pre-equalization circuit as described in claim 7, characterized in that, Each drive unit includes a first switch and a second switch. The drive control unit includes a third logic device, a fourth logic device, and a third inverter. The first input terminal of the third logic device receives an input data signal, the second input terminal of the third logic device receives an enable control signal, and the output terminal of the third logic device is connected to the control terminal of the first switch. The first input terminal of the fourth logic device receives an enable control signal, the second input terminal of the fourth logic device is connected to the third inverter, the input terminal of the third inverter receives the input data signal, and the output terminal of the fourth logic device is connected to the control terminal of the second switch.

9. An electronic chip, characterized in that, The electronic chip includes the signal pre-equalization circuit as described in any one of claims 1 to 8.

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