Bandwidth optimization for storage device

Abstract

Facility (100), comprehensive: a memory interface circuit (130) configured to be coupled to a storage device (150) via an interface (140) having a command bus (144) clocked by a command clock signal (142), the storage device (150) comprising a plurality of banks; and a control circuit (120) coupled and configured with the memory interface circuit (130) to initiate a multi-bank memory operation by scheduling a sequence of bank-specific commands to be sent to the memory device (150) via the command bus (144), wherein the bank-specific commands for a given memory bank (152) include the following: a first activation instruction, followed by a second activation instruction two cycles of the instruction clock signal (142) later; and a read / write command that follows the second activation command by at least one minimum timing parameter specified for the storage device (150), wherein the read / write command specifies a type of operation to be performed; and where it is planned that every second read / write instruction during the multi-bank memory operation will be delayed beyond the minimum timing parameter, and where it is planned that remaining read / write instructions will not be delayed beyond the minimum timing parameter.

Description

BACKGROUND Technical area

[0001] This disclosure relates generally to memory controls and in particular to the scheduling of memory instructions in a manner that increases the utilization of a storage device's data bus. Description of the state of the art

[0002] A common type of computer memory that has been used for decades is dynamic random access memory (DRAM), a form of random access memory (RAM) that requires periodic refreshes to maintain the data stored within it. Older DRAM implementations were asynchronous, meaning that a system clock was not used to coordinate memory accesses, while many newer implementations are synchronous (SDRAM), meaning that a clock is used to coordinate memory accesses.

[0003] Memory, including SDRAM, is typically organized into subsections called banks. Banks are configured to operate independently, allowing the device to work on a memory access command in each bank simultaneously. This enables memory devices to achieve greater concurrency and higher data rates. One type of SDRAM is Low Power Dual Data Rate (LPDDR-SDRAM), which consumes less power than other implementations and is therefore well-suited for applications such as mobile computing.

[0004] International semiconductor memory standards have fostered high-volume markets for various electronic products by ensuring compatibility between products offered by different vendors. JEDEC, short for Joint Electron Device Engineering Council, publishes standards for many different microelectronic technologies. In February 2019, JEDEC published JESD209-5, the standard for Low Power Dual Data Rate 5 (LPDDR5 or LP5). This standard supports data transfer rates of 6400 Mbps and up to 16 banks per memory device.

[0005] US 10 490 239 B2 discloses a storage device and a method for repeatedly writing a programmable data pattern to memory without transferring the pattern over the data bus each time.

[0006] US 2019 / 0 171 598 A1 discloses a phase-based control for DDR controllers which, through fine-grained signal processing within a clock cycle, contributes to improving efficiency and bus utilization at different clock ratios between core and interface clocks.

[0007] US 2021 / 0011868A1 discloses a semiconductor memory system with a flexible clock synchronization mechanism between control and data clocks (WCK-CK), in which special instructions such as CAS instructions with configurable opcodes (e.g., WCKENL_OTF, WCKon_OTF) optimize the timing of synchronization and memory access operations and reduce energy consumption by selectively activating and deactivating clock signals.

[0008] US 10 777 242 B2 discloses a semiconductor device and a corresponding system which synchronizes an internal data strobe signal with a write signal by means of an internal command pulse controlled by an offset code in order to ensure stable alignment despite varying strobe timing signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure, with reference to the following figures, presents techniques for planning operations for a storage device. Fig. Figure 1 is a block diagram illustrating one embodiment of a planning paradigm for a multi-bank storage operation. Fig. Figure 2 is a block diagram illustrating an embodiment of a memory controller that can be used to implement the disclosed techniques. Fig. Figures 3A-F illustrate conflict and bus efficiency for different possible plans for a set of memory operations. Fig. Figures 4A-J illustrate different sections of a timing diagram for a memory read operation using a "2-6" cadence. Fig. Figures 5A-J illustrate different sections of a timing diagram for a memory write operation using a "2-6" cadence. Fig. Figures 6A-J illustrate different sections of a timing diagram for a memory write operation using a "6-2" cadence. Fig. 7 a flowchart of an embodiment of a method for implementing the disclosed planning techniques. Fig. Figure 8 is a block diagram illustrating an exemplary computing device for implementing the disclosed techniques. Fig. Figure 9 is a diagram illustrating exemplary applications for systems and devices that employ the disclosed techniques. Fig. Figure 10 is a block diagram illustrating an exemplary computer-readable medium that stores circuit design information for implementing devices that employ the disclosed techniques. DETAILED DESCRIPTION

[0010] The invention is described in the attached set of claims.

[0011] The LP5 high-frequency interface presents several challenges when attempting to extract high bandwidth utilization from the data bus. The standard specifies that two activation instructions are required for a given memory bank, each issued on different clock signals. Additionally, the standard requires a synchronization instruction to start the data clock for the memory. In one mode, this instruction is issued one clock cycle before the read or write instruction. (Alternatively, an "always-on" mode can be used, but this mode can consume significant power, which is usually undesirable.) Data for a read or write operation to a given memory bank is transferred in two beats of two clock cycles each. However, these beats cannot occur consecutively because LP5 memory cannot generate (or store) the data that quickly at a high frequency.Accordingly, there are two dead clock cycles between the two data beats. The limitations imposed by the LP5 standard therefore make it difficult to achieve maximum utilization of the data bus (which would improve the performance of the storage system) while still scheduling in a way that makes the scheduler implementation relatively efficient.

[0012] The present disclosure presents a scheduling paradigm that attempts to maximize memory data bus utilization while respecting the various limitations of the LP5 standard. The present disclosure proposes that the clock cycles on the interface between the memory controller and the memory be divided into two sets of alternating clock cycles (e.g., even and odd clock cycles). One of these sets of clock cycles (e.g., even clock cycles) is used to transmit activate instructions for different banks addressed in a multi-bank memory operation (LP5 supports up to 16 banks for some operations). The other set (e.g., odd clock cycles) is used to transmit everything else. Accordingly, each memory bank to be addressed has two activate instructions scheduled on consecutive even clock cycles.Other instructions are scheduled for odd clock cycles between the activation instructions.

[0013] Next, the present disclosure recognizes that the standard specifies a minimum timing delay from the end of the second activation for a given bank until reading to (or writing from) that bank can occur. For the LP5 standard, this delay corresponds to the RAS-to-CAS delay parameter (tRCDr for reads, tRCDw for writes). Under one version of the proposed scheduling paradigm, a first read / write operation in a set of transactions is delayed by two clock cycles beyond its specified tRCD value. The second read / write instruction is then scheduled in the next subsequent odd-numbered clock cycle. This aligns the data beats of the two instructions so that they are properly nested. The third instruction is delayed by six clock cycles (three even and three odd) from its normal timing, so that the first beat of the third instruction occurs immediately after the second beat of the second instruction.The fourth instruction is two clock cycles after the third. This "2-6" pattern repeats throughout the entire memory transaction, allowing the data bus to achieve full utilization, as shown in the various timing diagrams below. A "6-2" timing pattern can also achieve similar results. Both of these paradigms can be efficiently implemented by the scheduler.

[0014] More generally, under this paradigm, it is planned that alternating read / write commands for a multi-bank memory operation will be delayed by a multi-cycle window beyond the minimum timing delay. In the Fig. In the embodiment shown in Figure 1, the length of this multi-cycle window is two clock cycles, but it may be longer for other embodiments if this is ensured by the characteristics of the specific addressed memory device.

[0015] Fig. Figure 1 illustrates an example of this planning paradigm. As shown, the facility 100 includes a memory controller 110, which is coupled via an interface 140 to the storage device 150, which includes the instruction clock signal 142, the instruction bus 144, and the data bus 146. Various possible additional components within the facility 100 are described in relation to Fig. 8 discussed. Fig. Figure 9 illustrates that the device 100 can be a variety of types of electronic products. The storage device 150 can be any of a variety of DRAM devices, including those conforming to JEDEC JESD209-5, Low Power Dual Data Rate 5 (LPDDR5).

[0016] The memory controller 110 includes a memory interface circuit 130, which is configured to be coupled to the memory device 150 via the interface 140. The memory device 150 includes a plurality of memory banks 152. The memory controller 110 further includes a control circuit 120, which is coupled to the memory interface circuit 130 and configured to initiate a multi-bank memory operation, such as a burst operation. The multi-bank memory operation is initiated by scheduling a sequence of bank-specific instructions to be sent to the memory device 150 via the command bus 144.

[0017] An example of the timing for scheduling bank-specific instructions on four banks (banks AD) is shown in Table 180. In general, the bank-specific instructions for a given memory bank include a) a first activation instruction, b) a second activation instruction two cycles of the instruction clock signal 142 later, and c) a read / write instruction that follows the second activation instruction by at least one minimum timing parameter specified for the storage device. As its name suggests, the read / write instruction specifies the type of operation to be performed (i.e., whether it is a read or a write operation). Fig. 1 represents a read operation. In this example, the minimum timing parameter is referred to as the RAS-to-CAS delay, or tRCDr, for read operations. In the example shown, tRCDr = 15 clock cycles. The value RL, which specifies the delay between the read instruction and the data appearing on the bus, is 17 clock cycles.

[0018] As can be seen in Table 180, every second read instruction during the multi-bank memory operation is scheduled to be delayed beyond the minimum timing parameter tRCDr. Here, the read instructions for banks A and C are delayed by 2 clock cycles. Remaining read instructions for banks B and D are not delayed beyond tRCDr. Note that there is a similar timing parameter for write operations (tRCDw).

[0019] The result of delaying alternating read / write commands during multi-bank memory operations, starting with the first read / write command, is that these commands are scheduled in a repeating 2-cycle / 6-cycle ("2 / 6") cadence. In one iteration of this cadence, read / write commands for a first given bank (e.g., Bank A) and a second, subsequent bank (e.g., Bank B) are scheduled at intervals of two cycles. A single iteration of the cadence also includes read / write commands for the second given bank (Bank B) and a third, subsequent bank (Bank C), scheduled at intervals of six cycles. In another embodiment, alternating read / write commands, starting with the second read / write command, result in a repeating 6-cycle / 2-cycle ("6 / 2") cadence.In this embodiment, accesses to banks A and B are scheduled at intervals of 6 cycles, while accesses to banks B and C are scheduled at intervals of 2 cycles.

[0020] Table 180 also shows that the control circuit 120 is configured to schedule an activation instruction every second clock cycle of the instruction bus 144 to perform the multi-bank memory operation. In the illustrated example, the activation instructions are scheduled in even-numbered clock cycles, while other instructions are scheduled in odd-numbered clock cycles. The combination of scheduling activation instructions every second clock cycle, along with scheduling read / write instructions in the intervening clock cycles, results in greater utilization of the bandwidth of the data bus 146.In fact, the control circuit 120 can schedule instructions for specific storage operations that address each of the plurality of banks in the storage device 150 in a single pass, beginning with an initial bank and ending with a final bank, such that during a given pass through the plurality of banks, the data bus is fully utilized for a period between the time data for the initial bank and data for the final bank is present on the data bus. Indeed, Table 180 illustrates that the data bus 146 is fully utilized as soon as data for the read operation begins to appear on the bus in cycle 36.

[0021] Now, referring to Fig. Figure 2 is a block diagram of an embodiment of a memory controller 110. Fig. Figure 1 illustrates the memory controller 110. It receives memory requests from various components in the system (e.g., processors such as central processing units (CPUs) within a processor cluster, graphics processing units (GPUs), peripherals, etc.) via a communication fabric. In one embodiment, the communication fabric can include multiple independent interconnects. For example, one interconnect can transport memory requests from the CPU processes; another interconnect can transport memory requests from the GPUs; and yet another interconnect can transport memory requests from the peripherals. In another embodiment, the communication fabric can include a single interconnect, and memory requests from the various source components can be aggregated via the interconnect to the memory controller 110.

[0022] The memory controller 110 can include one or more request queues 210 to temporarily store memory requests until they can be served. In one embodiment, the memory controller 110 can retain the requests in request queues 210 until they are completed (return of data to the source component for a read operation or completion for certain write requests). In another embodiment, some write requests (so-called posted writes) do not receive completion but can continue to be tracked in the request queues until the write data has been written to memory (or to the memory cache, as discussed below).

[0023] The arbitrator circuit 220 can select from among the storage requests in queues 210A-C for service. The arbitrator circuit 220 can consider a variety of factors when selecting storage requests. For example, in one embodiment, requests can be assigned to traffic classes in a Quality of Service (QoS) mechanism, and the traffic classes can be a factor in the selection. Higher priority traffic classes may be selected more frequently over time than lower priority traffic classes. The priority of the traffic classes can be balanced by fairness and forward progression factors, which ensure that no traffic class or priority level is blocked indefinitely. The age of the requests (e.g., how long the requests have been in the request queues) can also be a factor.

[0024] Requests that win arbitration can access the memory cache 230, which stores previously accessed data from memory. Memory requests that meet the criteria of the memory cache 230 can read or write the data in the cache and are therefore complete. The memory cache can reduce the latency of memory requests and can also conserve power that would have been consumed in transferring the memory requests to the storage devices. Other embodiments may, if desired, omit a memory cache.

[0025] Memory requests received by the memory cache 230 can be forwarded to the memory device(s) controlled by the memory controller 110. The memory controller 110 can control one or more memory devices 150 within the memory and can include a memory channel unit (MCU) 240 to interface with each memory device. The memory address space mapped to the memory controller 110 can be divided among the memory devices controlled by the memory controller, and thus a given memory request can be delivered by the memory cache 230 to a given MCU 250 based on the address of the memory request and which of the memory devices is mapped to that memory device.For example, specific bits of the memory address can be decoded to identify a "level," allowing each memory address with the same value for those specific bits to be transferred to the same MCU / memory device. In one embodiment, the memory cache 230 can also be divided into levels. Accordingly, multiple memory requests at different levels can access the memory cache in parallel.

[0026] MCUs 240 include request queues 242 to store requests awaiting transmission to storage devices 150, and a scheduler circuit 244 configured to schedule requests for transmission. (The scheduler circuit 244 can be connected to the control circuit 120 in Fig. 1.) In particular, a given memory request may involve multiple transfers on the interface to the storage device to perform the request, as is the case for a burst operation.

[0027] If the page containing the data to be accessed is not yet open, an activation command is transmitted. Once the page is open, a read or write command is transmitted, and then the data is transferred (for a write operation) or received (for a read operation). As described earlier, Scheduler Circuit 244 can schedule activations, read / write commands, and certain other commands (e.g., a synchronization command to turn on the read / write clocks in the storage device, which can optionally be turned off if the storage device is not addressed; refresh commands to ensure that data remains correctly stored in the storage device; etc.).

[0028] Scheduler circuit 244 is configured to schedule instructions in a manner consistent with the storage system specification, as different storage devices have different protocols and timing requirements. Within this framework, scheduler circuit 244 is configured to attempt to schedule instructions in a way that efficiently utilizes the storage device's bandwidth. For example, read operations may be grouped together, and write operations may be grouped separately, because one or more clock cycles of bus turnarounds are required on the data bus when switching between read and write operations.Within the groups, storage requests can be subgrouped based on accessing different banks (so that different pages can be open in different banks) or accessing the same page in the same bank, allowing page activation to be shared across requests. Furthermore, the scheduling of commands can be performed by scheduler circuit 244 to increase data bandwidth, as described in [reference to relevant section]. Fig. 1 briefly described and as described in more detail below.

[0029] The memory devices 150 within the memory can be any suitable type of memory, including any DRAM memory. In particular, the DRAM can be dual-data-rate (DDR) DRAM implemented according to an industry-standard specification such as DDR1, DDR2, DDR3, etc., and / or one of the low-power specifications of DDR DRAM, such as LP3, LP4, etc., in addition to the LP5 specification. In some embodiments, the memory device 150 can be a single inline memory module (SIMM) or a dual inline memory module (DIMM) containing multiple memory chips mounted on an underlying substrate. The memory device 150 can also include a plurality of banks in various embodiments.

[0030] The techniques of this disclosure, although developed in response to the context of the LP5 memory standard, are not intended to be limited exclusively to memories conforming to this standard. Rather, the techniques of this disclosure may be applicable to other memory systems where similar problems arise in increasing data bus utilization, including, but not limited to, future LP5 memory standards and other low-power, double-data-rate RAM standards.

[0031] It should be noted that MCUs 240 can include the physical layer (PHY) circuits for driving and receiving signals via the interface to the storage devices. Alternatively, the PHY circuits can be inserted between the MCUs and the storage devices.

[0032] Read data returned from memory can be provided by the MCUs 240 to request queues 210 coupled to the communication fabric for return to the source components. Similarly, if a given write command includes a response, the response can be provided by the MCUs 240 to the request queues 210, or to a corresponding set of output queues. For simplicity, the return data paths are shown in Fig. 2 not shown.

[0033] With reference to Fig. 3A-F should refer back to the various limitations imposed by the LP5 memory standard. First, memory banks require two activation cycles. Second, there are various timing parameters that must be considered, including the timing between the second activation for a bank and a read or write operation to that bank (e.g., tRCDr = 15 cycles for a read operation in one embodiment) and the timing between the read or write operation and the data (e.g., 17 cycles for a read operation in one embodiment). Third, due to the frequency of LP5 memory, data for an access on the data bus will occur as two beats of two cycles each, with a rest period in between.Finally, the LP5 standard specifies that in one mode, the synchronization instruction (which starts the data clock) should be scheduled to occur in the cycle before the first read or write operation in a multi-bank memory operation. (As mentioned earlier, there are other synchronization options in LP5, such as an always-on mode, but this mode consumes significantly more power.)

[0034] Power consumption is one of several design considerations when attempting to schedule memory operations. In addition to judiciously turning on the data bus clock, it is also important to ensure that the data bus is utilized to the maximum extent during a memory operation—that is, that the number of data "holes" (i.e., bus cycles without data) is kept to a minimum. Some degree of non-utilization is unavoidable, particularly when initiating a transaction or switching from a series of read operations (e.g., a "read round") to a series of write operations (e.g., a "write round"). Accordingly, the present inventors have sought to achieve the greatest possible memory data bus utilization during a single pass through the banks of a memory device. However, care must be taken to ensure that there is no competition on either the instruction bus or the data bus.In other words, no planning regime can be assumed that would require two commands (or two data bursts from different banks) to appear simultaneously on the command bus or the data bus.

[0035] Given these various challenges, it is evident that there are many different ways to plan LP5 memory transactions. As shown below, many of these ways would lead to scenarios that produce undesirable results, including data holes, instruction bus conflicts, and / or data bus conflicts. Several of these possibilities are discussed in relation to Fig. 3A-E described. A planning paradigm that maximizes bus utilization but does not suffer from command or data bus competition is then described in relation to Fig. 3F described.

[0036] Fig. Tables 3A-F are all those describing the timing of various aspects of read accesses to eight memory banks, designated AH. (The timing of write accesses would be similar to that shown for reads.) The activities occurring on the instruction and data buses are both shown. On the instruction bus, the timing of the two enable instructions for a given bank, the synchronize instruction preceding the first read, and the RD instruction are shown, while on the data bus, the timing of the two data beats is shown. Note that each data beat is two clock cycles long. Accordingly, a data beat that begins at cycle 33 ends at cycle 34.

[0037] The timing of the read instruction is controlled by the memory parameter tRCDr, which is 15 clock cycles in this example. As mentioned earlier, this parameter means that the earliest time a read (RD) instruction can occur for a given bank is 15 clock cycles after the second activation for that bank. Thus, if the second activation for a bank occurs on clock cycle 2, the earliest time the RD instruction can be issued for that bank is clock cycle 17. Similarly, the timing between an RD instruction and the corresponding data appearing on the data bus is given by the parameter RL, which is 17 clock cycles in this example.

[0038] Fig. Figure 3A illustrates Table 310, which shows the resulting timing if activation instructions are issued consecutively without a gap—that is, at cycles 0 and 1 for Bank A, cycles 2 and 3 for Bank B, and so on. Table 310 shows that this approach leads to competition on both the instruction and data buses. In particular, the synchronization instruction scheduled for cycle 15, being one cycle before the RD in cycle 16, would conflict with the second activation for Bank H. Furthermore, it is evident that the data bus would also experience significant competition when using this schedule. Fig. 3A (the dashed circles and adjacent lines indicate competition on both the command and data buses). This approach is therefore unusable.

[0039] Fig. Figure 3B illustrates Table 320, which presents an alternative approach where the first activation instructions for banks are spaced at intervals of four clock cycles. Accordingly, the first activation instruction for Bank A occurs at 0 cycles, the first activation instruction for Bank B at 4 cycles, and so on. This paradigm also suffers from conflicts. As can be seen, the RD instructions for Bank AD conflict with the first activation instructions for Bank EH. Furthermore, the second data strike for a given bank conflicts with the first data strike for the next bank.

[0040] Fig. 3C illustrates a Table 330, which presents yet another approach where the first bank activation instructions are not only spaced at intervals of six clock cycles, but the first and second activation instructions are also separated by an intervening clock cycle. For example, the activation instructions for Bank A are scheduled at cycles 0 and 2, while the activation instructions for Bank B are scheduled at cycles 6 and 8, and so on. While this schedule does not result in any competition on either the instruction or data bus, it does introduce inefficiency on the data bus. As can be seen, this paradigm results in data bus gaps at cycles 36-37, 42-43, 48-49, 54-55, 60-61, 66-67, 72-73, and 78-79.

[0041] One insight the inventors had when addressing this problem is the assumption that activation instructions should be scheduled every second clock cycle, with other instructions scheduled on the intervening clock cycles. For example, even clock cycles could be reserved for activation instructions, with other instructions reserved for odd clock cycles. (Of course, activation instructions could also be scheduled for odd clock cycles, with other instructions scheduled for even clock cycles.) This approach is shown in Table 340 in Fig. Shown in 3D. As can be seen, this approach still suffers from two shortcomings. First, there is a conflict between the timing of the synchronization instruction (cycle 16, one cycle before the RD at cycle 17) and the first activation instruction for bank E. Second, there is also data bus conflict.

[0042] A second insight of the inventors is to delay every second read / write command beyond the minimum required timing. Fig. 3E illustrates Table 350, which presents such an approach. Fig. In 3E, every second RD instruction (starting with the first instruction) is delayed by two cycles beyond the minimum system timing (e.g., beyond tRCDr). Thus, the delay between the second activation and the RD instruction is 17 cycles for accesses to banks A, C, E, and G. Conversely, the delay between the second activation instruction and the RD instruction is 15 cycles for banks B, D, F, and H. This approach results in the "2-6" timing cadence. Therefore, the timing between the RDs for banks A and B is two cycles, while the timing between the RDs for banks B and C is six cycles. This pattern continues, as the RD timing difference is two cycles between banks C and D and six cycles between banks D and E. In particular, data bus congestion has now been eliminated.Furthermore, the data bus is also fully used between cycles 36-66, as data on the data bus is fully nested during this period.

[0043] This approach leaves a scheduling problem. There are several ways the synchronization command can be handled under the LP5 standard. The "always-on" synchronization mode allows the synchronization command to be scheduled as desired, but this approach means the data bus is unnecessarily powered on even when not needed, thus wasting power. However, scheduling the synchronization command in the most efficient way possible—i.e., in cycle 18, one cycle before the first RD command—conflicts with the second activation for Bank E.

[0044] The inventors realized that the synchronization instruction timing problem could be solved by adding a new operating mode to the storage device 150. The control circuit 120 can then be configured to put the storage device 150 into a "synchronization delay mode." Generally, this synchronization delay mode delays the storage device from responding to a received synchronization instruction for one or more cycles. Consider a scenario in which a storage specification indicates that a synchronization instruction should precede a read / write operation by an odd number of cycles, but the synchronization would occur in a cycle reserved for activation instructions.The synchronization delay mode can be used to internally delay the synchronization instruction in memory for a number of odd clock cycles, with the result that the synchronization instruction appears on instruction bus 144 in an odd clock cycle and the memory device responds to it in an even clock cycle (as specified by the memory).

[0045] In one embodiment, the storage device 150 uses such a mode to internally delay a received synchronization instruction by one cycle. The effect of this is that instead of a synchronization instruction scheduled in cycle N, which causes the data bus clock to start in cycle N+1, a synchronization instruction scheduled in cycle N will cause the data bus clock to start in cycle N+2. This mode would allow a synchronization instruction to be scheduled on the instruction bus two cycles before a read or write operation, but due to the internal delay, the memory will effectively treat the synchronization as if it occurs one cycle before the read / write operation.

[0046] Other amounts of synchronization delay are possible in alternative embodiments. The proposed synchronization delay mode can also be used in settings other than the proposed 2 / 6 or 6 / 2 timing cadences. A storage device implementing delayed synchronization includes a decoder circuit configured to decode various storage device instructions, including instructions that set a synchronization delay mode with a specified number of delay cycles. The decoder circuit is also configured to decode the synchronization instruction itself. Alternatively, instead of a synchronization delay mode instruction, the synchronization instruction format could include a desired number of delay cycles as a parameter, with the default being no delay.

[0047] After decoding a command, the decoding circuit is configured to forward the command to appropriate logic within the storage device that executes the command. For the synchronization command, the storage device includes a synchronization execution circuit configured to start the data bus clock. In one embodiment, the decoding circuit can delay sending the synchronization command until the specified delay has elapsed. In another embodiment, the synchronization execution circuit can include a multi-bit counter. Upon receiving a synchronization command, the decoding circuit can forward the synchronization command to the synchronization execution circuit along with the desired amount of delay. The synchronization execution circuit would then program the counter with the specified delay and then start the data bus clock after the counter reaches zero.(If the synchronization delay mode is not active, the delay parameter is zero and the counter may not be used.) Various other implementations of the storage device to achieve a synchronization delay are also possible. It should also be noted that the storage device may be configured to internally delay other delay instructions besides the synchronization instruction, as required for various scenarios, particularly when there is a mismatch between the desired memory bus scheduling and the required storage device timing.

[0048] In any case, if the synchronization delay mode is enabled, this allows the in Fig. The timing specified in 3E is adjusted by scheduling the synchronization instruction in cycle 17 instead of cycle 18. With storage device 150 operating in synchronization delay mode, scheduling the synchronization instruction in cycle 17 produces the same effect as scheduling the instruction in cycle 18 without synchronization delay mode. The results—increased bus utilization and no conflict—are described in Fig. 3F is shown. In addition, the planning paradigm is relatively easy to implement within the scheduler circuit 244.

[0049] Furthermore, there is no loss of latency or efficiency with this approach regarding the switch from a write round to a read round or vice versa. Consider a scenario where a write round occurs, and the first cycle in which a read operation could be performed is cycle 100. In previous designs, the first activation would be at cycle 83, the second activation at cycle 85, which would allow a read operation at cycle 100, assuming a tRCDr value of 15 cycles. However, in one implementation of the present disclosure, a first read (or write) operation in a set of transactions is delayed by two clock cycles beyond its specified tRCDr value, meaning that the first read / write operation would instead occur at tRCDr+2 cycles.However, since the previous write activation at the end of the write round would have occurred a sufficient number of cycles earlier, the first and second activations for the initial read operation in the read round could occur at cycles 81 and 83, respectively. This timing would still allow the first read operation to occur in cycle 100 after a delay of tRCDr+2 cycles.

[0050] Fig. Figures 4A-J illustrate different sections of a single timing diagram for a reading operation, which is performed according to the information relating to Fig. The planning paradigm described in 3F is implemented. Each of Fig. Figure 4 illustrates 10-12 cycles of C CK, which corresponds to the instruction clock signal 142. Fig. 4A begins at cycle 0 and Fig. 4J ends at cycle 100. In this multi-bank storage operation, sixteen banks (AP) are addressed. Dashed arrows indicate where every second read instruction is delayed by two cycles beyond tRCDr (i.e., 17 cycles instead of 15 cycles after the second activation). Data begins to appear at cycle 36. Data bus 146 is used to its maximum extent between cycle 36 and cycle 100, when the second data strike for the last bank (bank P) is completed.

[0051] The in Fig. The implementation shown in 4A-J exhibits a repeating 2 / 6 cadence. The delay between the cycle number at which the RD instruction is scheduled for the first and second memory banks is two cycles, while the delay between the RD cycle number for the second and third banks is six cycles. This pattern can be repeated until all banks have been addressed.

[0052] Fig. Figures 5A-J illustrate different sections of a single timing diagram for a write operation, also implemented according to the 2 / 6 timing pattern. The minimum timing parameters for the write operation differ from those of the read operation in some cases. Here, tRCDw is 7 cycles, and WL, which is the time delay between when the write command is scheduled and when data can be written to the bus, is 9 cycles. Again, the data bus is used a maximum of 146 times between cycles 20-83 (i.e., there are no data gaps).

[0053] As mentioned, the following are in Fig. 4A-J and Fig. The operations of the 2 / 6 timing cadence are shown in Figures 5A-J. Accordingly, read / write instructions for a first given bank and a second, subsequent bank to be addressed are scheduled at intervals of two instruction clock cycles. Furthermore, read / write instructions for the second given bank and a third, subsequent bank to be addressed are scheduled at intervals of six instruction clock cycles. This pattern repeats throughout the entire memory operation.

[0054] Fig. Figures 6A-J, on the other hand, illustrate different sections of a single timing diagram for a write operation implemented according to a 6 / 2 timing pattern. The write operation shown in this diagram has the same timing parameters as in Fig. 5A-J: tRCDw is 7 cycles and WL is 9 cycles. As with Fig. 4A-J and Fig. In 5A-J, it is still the case that every second write command is delayed by two cycles beyond the minimum timing parameter. Unlike the 2 / 6 timing pattern, where odd-numbered accesses are delayed and even-numbered accesses are not, the opposite is true for the 6 / 2 timing pattern. Here, the initial access (to bank A) is not delayed, as the write data appears on the bus seven cycles after the second activation. The second access (to bank B) is delayed by two cycles and is thus scheduled for cycle 15. In contrast to the 2 / 6 timing pattern, this Fig. The 6A-J shown 6 / 2 timing pattern has two gaps in the data bus between the initial and final data strokes: there is a gap in clock cycles 20-21 and 82-83. Otherwise, the data bus bandwidth is fully utilized.

[0055] Accordingly, in the 6 / 2 timing pattern, read / write instructions for a first given bank and a second, subsequent bank to be addressed are scheduled at intervals of six instruction clock cycles. Furthermore, read / write instructions for a second given bank and a third, subsequent bank to be addressed are scheduled at intervals of two instruction clock cycles. This pattern repeats throughout the entire memory operation. Example procedure

[0056] Fig. Figure 7 is a flowchart illustrating an embodiment of a method for implementing the disclosed memory planning techniques. The diagram shown in Figure 7 is a flowchart illustrating an embodiment of a method for implementing the disclosed memory planning techniques. Fig. The method shown in section 7 can be used, among other things, in conjunction with any of the computer logic, systems, devices, elements, or components disclosed herein. In various embodiments, some of the methods shown can be carried out simultaneously, in a different order than shown, or even without them. Further elements of the method can also be implemented as desired.

[0057] Method 700 begins at 710, in which a memory controller initiates a cadence for a multi-bank memory operation, such as a burst operation. As described below, the cadence involves scheduling instructions on an interface to a memory device relative to a clock signal that clocks the interface. In one embodiment, Method 700 can be performed with respect to a synchronous DRAM device, such as a memory device conforming to the LP5 standard. The cadence includes 720 and 730, which are performed relative to a given memory bank and the next memory bank, respectively, in a sequence of memory banks addressed by the multi-bank memory operation. For example, 720 can be performed relative to Bank A in memory, while 730 is performed relative to Bank B.

[0058] In 720, the memory controller schedules a first activate instruction, a second activate instruction, and a type instruction that specifies the type of instruction to be executed (e.g., a read or write operation). The second activate instruction is scheduled to occur two clock cycles after the first activate instruction. The type instruction is scheduled to occur a first period after the second activate instruction, where the first period is equal to two clock cycles plus a minimum timing delay specified for the memory device. The minimum timing delay can, for example, be a RAS-to-CAS delay, which specifies the minimum time that must elapse from bank activation until a type instruction can appear on the instruction bus.

[0059] In some memory specifications, this minimum timing delay may be referred to as tRCDr for read instructions and tRCDw for write instructions. For example, if a read operation on bank A were scheduled in 720 with tRCDr = 7 clock cycles, the read operation would be scheduled at least 9 clock cycles after the second activation instruction for bank A (7 cycles of tRCDr plus 2 cycles of delay).

[0060] In 730, the memory controller schedules a third activate instruction, a fourth activate instruction, and another instance of the type instruction specified in 720. (The third and fourth activate instructions are different instances of the first and second activate instructions, respectively.) As in 720, the fourth activate instruction is scheduled to occur two clock cycles after the third activate instruction. The type instruction in 730 is scheduled to occur a second period after the fourth activate instruction, where the second period is equal to the minimum timing delay. For example, if a read operation on bank B were scheduled in 730 with tRCDr = 7 clock cycles, the read operation would be scheduled 7 clock cycles after the fourth activate instruction for bank B. Thus, unlike in 720, the type instruction in 730 is scheduled so that it is not delayed beyond the minimum system timing requirement.

[0061] Next, in step 740, the memory controller repeats the cadence described in steps 720 and 730 for additional pairs of memory banks in the memory device to continue the multi-bank memory operation. For example, a subsequent cadence might address banks C and D, delaying the type instruction for bank C by two cycles, but not delaying the type instruction for bank D.

[0062] In various embodiments, the memory controller schedules activation instructions on even cycles, while type instructions such as read and write operations are scheduled to occur in intermediate, odd cycles.

[0063] In embodiments where activation instructions are scheduled every second clock cycle (e.g., Bank A in cycles 0 and 2, Bank B in cycles 4 and 6, etc.), this can pose a problem with the implementation of the synchronization instruction. This is because the most efficient synchronization mode in the LP5 standard specifies that a synchronization instruction should be scheduled in the clock cycle immediately preceding a corresponding type instruction, such as a read or write operation. This presents a potential problem in a paradigm where a read / write instruction is preceded by a cycle reserved for activation instructions (e.g., a read / write instruction scheduled for cycle 11 cannot be preceded by a synchronization instruction in cycle 10, since cycle 10 and other even cycles are reserved for activation instructions).

[0064] Accordingly, the storage device can be equipped with a synchronization delay mode in which, upon reception, the storage device internally delays a received synchronization signal by one clock cycle. This allows the paradigm to reserve every second clock cycle for activation instructions to operate in the context of LP5 memory. In such embodiments, Method 700 can further include the memory controller setting a synchronization delay mode for the storage device and then scheduling a synchronization instruction two clock cycles before a corresponding type instruction for an initial bank addressed in the multi-bank memory operation.

[0065] One effect of Method 700 can be the increased utilization of the memory data bus during multi-bank storage operations. In some memories, such as LP5, the frequencies for moving data in or out of memory are sufficiently high that data associated with a bank access comprises two data beats, each lasting two clock cycles. Also due to the timing, the two beats are separated by two clock cycles. This allows for the interleaving of data from different banks. In fact, applying embodiments of Method 700 can lead to full utilization of the data bus once the initial latency of the storage device has elapsed and data for the multi-bank storage operation appears on the data bus. Example device

[0066] Now, referring to Fig. Figure 8 shows a block diagram illustrating an exemplary embodiment of a device 800. In some embodiments, elements of the device 800 may be contained within a system-on-a-chip. In some embodiments, the device 800 may be contained in a mobile computing device, which may be battery-powered. Therefore, the power consumption of the device 800 may be an important design consideration. In the illustrated embodiment, the device 800 includes a fabric 810, a computing complex 820, an input / output bridge (I / O bridge) 850, a cache / memory controller 845, a graphics unit 875, and a display unit 865. In some embodiments, the device 800 may include other components (not shown) in addition to or instead of the illustrated components, such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0067] The Fabric 810 can include various interconnects, buses, MUXs, controllers, etc., and can be configured to enable communication between different elements of the Device 800. In some embodiments, sections of the Fabric 810 can be configured to implement different communication protocols. In other embodiments, the Fabric 810 can implement a single communication protocol, and elements connected to the Fabric 810 can internally convert from this single communication protocol to other communication protocols.

[0068] In the illustrated embodiment, the compute complex 820 includes a bus interface unit (BIU) 825, a cache 830, and cores 835 and 840. In various embodiments, the compute complex 820 can include different numbers of processors, processor cores, and caches. For example, the compute complex 820 can include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, the cache 830 is a set associative L2 cache. In some embodiments, the cores 835 and 840 can include internal instruction and data caches. In some embodiments, a coherence unit (not shown) can be configured in the fabric 810, the cache 830, or elsewhere in the device 800 to maintain coherence between different caches of the device 800.The BIU 825 can be configured to manage communication between the 820 compute unit and other elements of the 800 device. Processor cores, such as the 835 and 840 cores, can be configured to execute instructions of a specific Instruction Set Architecture (ISA), which may include operating system instructions and user application instructions.

[0069] The Cache / Memory Controller 845 can be configured to manage the transfer of data between the Fabric 810 and one or more caches and stores. For example, the Cache / Memory Controller 845 can be coupled to an L3 cache, which in turn can be coupled to system memory. In other embodiments, the Cache / Memory Controller 845 can be directly coupled to memory. In some embodiments, the Cache / Memory Controller 845 can include one or more internal caches.

[0070] As used herein, the term "coupled to" can indicate one or more connections between elements, and a coupling can include intervening elements. For example, in Fig. 8. The graphics unit 875 is described as being “coupled to” a memory by the Fabric 810 and the cache / memory controller 845. In contrast, in the illustrated embodiment of Fig. 8 the graphics unit 875 is “directly coupled” to the Fabric 810, as there are no intervening elements.

[0071] The Graphics Unit 875 can include one or more processors, such as one or more graphics processing units (GPUs). The Graphics Unit 875 can receive graphics-oriented instructions, such as OPENGL®, Metal, or DIRECT3D® instructions. The Graphics Unit 875 can execute specialized GPU instructions or perform other operations based on the received graphics-oriented instructions. The Graphics Unit 875 can generally be configured to process large blocks of data in parallel and can create images in a frame buffer for output to a display, which may be included in the device or be a separate device. The Graphics Unit 875 can include transformation, lighting, triangle, and rendering engines in one or more graphics processing pipelines. The Graphics Unit 875 can output pixel information for displaying images.The 875 graphics unit can, in various embodiments, include programmable shader switching logic, which includes highly parallel execution cores configured to run graphics programs that may include pixel, vertex, and computational tasks (which may or may not be related to graphics).

[0072] The Display Unit 865 can be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, the Display Unit 865 can be configured as a display pipeline. The Display Unit 865 can also be configured to concatenate multiple frames into a single output frame. Furthermore, the Display Unit 865 can include one or more interfaces (such as MIPI® or Embedded DisplayPort (eDP)) for coupling to a user display (such as a touchscreen or external display).

[0073] The I / O Bridge 850 can include various elements configured to implement, for example, Universal Serial Bus (USB) communication, security, audio, and low-power always-on functionality. The I / O Bridge 850 can also include interfaces such as Pulse Width Modulation (PBM), General-Purpose Input / Output (GPIO), Serial Peripheral Interface (SPI), and Inter-Integrated Circuit (I2C). Various types of peripheral devices and equipment can be connected to the Device 800 via the I / O Bridge 850.

[0074] In some embodiments, the device 800 includes (not explicitly shown) network interface switching logic that may be connected to the fabric 810 or the I / O bridge 850. The network interface switching logic may be configured to communicate over various networks, which may be wired, wireless, or both. For example, the network interface switching logic may be configured to communicate over a wired local area network, a wireless local area network (e.g., via Wi-Fi), or a wide area network (e.g., the internet or a virtual private network). In some embodiments, the network interface switching logic is configured to communicate over one or more cellular networks that use one or more radio access technologies. In some embodiments, the network interface switching logic is configured to communicate using device-to-device communication (e.g.,Bluetooth or WiFi Direct, etc. In various embodiments, the network interface switching logic of the Device 800 can provide connectivity to various other device and network types. Application examples

[0075] Now, referring to Fig. 9. Various types of systems may include any of the circuits, devices, or systems described above. The system or device 900, which may include or otherwise utilize one or more of the techniques described herein, may be used in a wide range of applications. For example, the system or device 900 may be used as part of the hardware of systems such as a desktop computer 910, a laptop computer 920, a tablet computer 930, a cellular telephone or mobile phone 940, or a television 950 (or a set-top box coupled with a television).

[0076] Similarly, the disclosed elements can be used in a wearable device 960, such as a smartwatch or a health monitoring device. Smartwatches, in many embodiments, can perform a variety of different functions, for example, accessing emails, mobile services, calendars, health monitoring, etc. A wearable device can also be designed to perform exclusively health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions like contact tracing, providing communication with an emergency medical service, etc.Other types of devices are also conceivable, including devices worn around the neck, devices that can be implanted in the human body, glasses or helmets that offer computer-generated reality experiences, such as those based on augmented and / or virtual reality, etc.

[0077] The system or device 900 can also be used in various other contexts. For example, the system or device 900 can be used in conjunction with a server computer system, such as a dedicated server or on shared hardware that implements a cloud-based service 970. Furthermore, the system or device 900 can be implemented in a wide range of specialized, everyday devices, including common household devices 980 such as refrigerators, thermostats, security cameras, etc. The networking of such devices is often referred to as the "Internet of Things" (IoT). The elements can also be implemented in various means of transportation. The system or device 900 could, for example, be used in the control systems, guidance systems, entertainment systems, etc., of various types of vehicles 990.

[0078] The in Fig. The nine illustrated applications are merely examples and are not intended to limit the possible future applications of the disclosed systems or devices. Other application examples include, without limitation, portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc. Example of a computer-readable medium

[0079] In the present disclosure, various exemplary circuits have been described in detail above. It is intended that the present disclosure not only covers embodiments that include such switching logic, but also a computer-readable storage medium that includes design information specifying such switching logic. Accordingly, the present disclosure is intended to support claims that cover not only a device that includes the disclosed switching logics, but also a storage medium that specifies the switching logic in a format recognized by a production system configured to manufacture hardware (e.g., an integrated circuit) that includes the disclosed switching logic. Claims to such a storage medium are intended, for example, to cover an entity that generates a circuit design but does not itself produce the design.

[0080] Fig. Figure 10 is a block diagram illustrating an exemplary non-transitory computer-readable storage medium that stores circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor fabrication system 1020 is configured to process the design information 1015 stored on the non-transitory computer-readable medium 1010 and to fabricate an integrated circuit 1030 based on the design information 1015.

[0081] The non-transitory computer-readable storage medium 1010 can comprise any of several suitable types of storage devices or storage devices. The non-transitory computer-readable storage medium 1010 can be an installation medium, such as a CD-ROM, floppy disks, or a tape device; computer system memory or random-access memory, such as DRAM, DDR-RAM, SRAM, EDO-RAM, Rambus-RAM, etc.; non-volatile memory, such as flash memory; magnetic media, such as a hard disk or optical storage; registers or other similar types of storage elements, etc. The non-transitory computer-readable storage medium 1010 can also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1010 can include two or more storage media, which may be located in different places, for example,in different computer systems that are connected via a network.

[0082] The design information 1015 can be specified using any of several suitable computer languages, including hardware description languages ​​such as, but not limited to: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1015 can be used by the semiconductor manufacturing system 1020 to fabricate at least one section of the integrated circuit 1030. The format of the design information 1015 can be recognized by at least one semiconductor manufacturing system 1020. In some embodiments, the design information 1015 can also include one or more cell libraries that specify the synthesis, layout, or both of the integrated circuit 1030. In some embodiments, the design information is specified wholly or partially in the form of a netlist that specifies the cell library elements and their connectivity.The design information 1015 may, on its own, contain sufficient information for the fabrication of a corresponding integrated circuit, but it does not necessarily have to. For example, the design information 1015 may specify the circuit elements to be fabricated, but not their physical layout. In this case, the design information 1015 may need to be combined with layout information to actually fabricate the specified circuit logic.

[0083] The integrated circuit 1030, in various embodiments, can include one or more user-defined macrocells, such as memory, analog or mixed-signal circuits, and the like. In such cases, the design information 1015 can include information relating to the included macrocells. Such information can include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device- or transistor-level netlists. As used herein, mask design data can be formatted according to the Graphics Data System (GDSII) or any other suitable format.

[0084] The Semiconductor Manufacturing System 1020 can include any of several suitable elements configured to manufacture integrated circuits. These can include, for example, elements for depositing semiconductor materials (e.g., onto a wafer, which may include masking), removing materials, changing the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), and so on. The Semiconductor Manufacturing System 1020 can also be configured to perform various tests on manufactured circuits to ensure their correct operation.

[0085] In various embodiments, the integrated circuit 1030 is configured to operate according to a circuit design specified by the design information 1015, which may include performing any of the functionality described herein. For example, the integrated circuit 1030 may perform any of the various functions described in Fig. 1 or Fig. The 2 elements shown are included. Furthermore, the 1030 integrated circuit can be configured to perform various functions described herein in conjunction with other components. The functionality described herein can also be performed by multiple interconnected integrated circuits.

[0086] As used herein, an expression of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured for the element to be satisfied. Rather, this expression indicates that the design information describes a circuit that, after manufacturing, will be configured to perform the specified actions or to include the specified components.

[0087] The present disclosure includes references to “an” embodiment or groups of “embodiments” (e.g., “some embodiments” or “various embodiments”). Embodiments are different implementations or instances of the disclosed concepts. References to “embodiment,” “an embodiment,” “a particular embodiment,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are considered, including those specifically disclosed, as well as modifications or alternatives that fall within the nature or scope of protection of the disclosure.

[0088] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily exhibit any or all potential advantages. Whether an advantage is achieved for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are several reasons why an implementation that falls within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular implementation might include different switching logic outside the scope of the disclosure, which, in conjunction with one of the disclosed embodiments, eliminates or reduces one or more of the disclosed advantages. Furthermore, a suboptimal design implementation of a particular implementation (e.g.,Implementation techniques or tools) negate or diminish disclosed benefits. Even assuming a qualified implementation, the attainment of benefits may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring on a particular occasion, thereby potentially preventing the benefit of its solution from being achieved. Due to the existence of possible factors outside of this disclosure, it is expressly intended that all potential benefits described herein are not to be construed as limitations on claims that must be satisfied to prove infringement.Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvement available to designers who benefit from this disclosure. Describing such benefits in a permissive manner (e.g., stating that a particular benefit “may occur”) is not intended to cast doubt on the attainability of such benefits, but instead to acknowledge the technical reality that achieving such benefits often depends on additional factors.

[0089] Unless otherwise stated, embodiments are not limiting. This means that the disclosed embodiments are not intended to limit the scope of protection of claims formulated on the basis of this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not limiting, unless the disclosure contains statements to the contrary. The application is thus intended to allow claims to cover disclosed embodiments as well as the alternatives, modifications, and equivalents that are obvious to a person skilled in the art who benefits from this disclosure.

[0090] For example, features in this application may be combined in any suitable way. Accordingly, during the further pursuit of this application (or an application claiming priority thereof), new claims may be formulated to any such combination of features. In particular, with reference to the accompanying claims, features from dependent claims may be combined with those of other dependent claims where appropriate, including claims dependent on other independent claims. Similarly, features from respective independent claims may be combined where appropriate.

[0091] While the accompanying dependent claims may be formulated such that each depends on a single other claim, additional dependencies are also considered. All combinations of features in the dependent claim that are consistent with this disclosure are considered and may be claimed in this or any other application. In summary, combinations are not limited to those specifically enumerated in the accompanying claims.

[0092] Where appropriate, consideration will also be given to ensuring that claims formulated in one format or statutory type (e.g., establishment) support corresponding claims of another format or statutory type (e.g., procedure).

[0093] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and legal interpretation. It is hereby announced that the following paragraphs, as well as definitions provided throughout this disclosure, shall be used in determining how claims formulated based on this disclosure are to be interpreted.

[0094] References to a singular form of an element (i.e., a noun or noun phrase preceded by "a" or "the") should, unless the context clearly indicates otherwise, mean "one or more." Thus, a reference to "an element" in a claim, without accompanying context, does not exclude additional instances of the element. A "multitude" of elements refers to a set of two or more of the elements.

[0095] The word “can / can” is used here in a permissive sense (i.e. having the potential to be able to) and not in an obligatory sense (i.e. must / must).

[0096] The terms “comprehensive” and “inclusive” and forms thereof are open and mean “including without being limited to”.

[0097] When the term “or” is used in this revelation in reference to a list of options, it is generally understood to be used in an inclusive sense, unless the context indicates otherwise. Thus, a statement of “x or y” is equivalent to “x or y or both” and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, a phrase such as “either x or y, but not both” makes it clear that “or” is used in an exclusive sense.

[0098] A statement of "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" is intended to cover all possibilities, from a single element to the total number of elements in the sentence. For example, in the sentence [w, x, y, z], these phrases cover every single element of the sentence (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "at least one of ... x, y, and z" thus refers to at least one element of the sentence [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase must not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0099] Various “labels” may appear before nouns or noun phrases in this disclosure. Unless the context indicates otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, when applied to a feature, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0100] The phrase "based on" or "based upon" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on stated factors or on the stated factors as well as other, unspecified factors. Consider the phrase "determine A based upon B." This phrase indicates that B is a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based upon another factor, such as C. This phrase is also intended to cover an embodiment in which A is determined solely based upon B. As used herein, the phrase "based on" or "based upon" is synonymous with the phrase "based at least partially upon."

[0101] The phrases "in response to" and "in reaction to" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either together with the stated factors or independently of them. That is, an effect may occur solely in response to these factors, or it may occur in response to the stated factors as well as other, unspecified factors. Consider the phrase "to perform A in response to B." This phrase indicates that B is a factor that triggers the performance of A or that triggers a particular outcome for A. This phrase does not exclude the possibility that performing A may also occur in response to another factor, such as C. Nor does it exclude the possibility that performing A may occur in response to both B and C.This phrase is also intended to cover an embodiment in which A is carried out solely based on B. As used herein, the phrase "in response to" is synonymous with the phrase "in response to at least part of". Similarly, the phrase "in response to" is synonymous with the phrase "at least part of in response to".

[0102] Within this disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed to be "configured" to perform one or more tasks or operations. This phrase—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., something physical). In particular, this phrase is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure may be described as "configured to" perform a task even if the structure is not currently operating.Thus, an entity described or specified as "configured to" perform a task refers to something physical, such as a device, a circuit, a system with a processing unit and memory that stores program instructions executable to implement the task, etc. This phrase is not used here to refer to something intangible.

[0103] In some cases, various units / circuits / components herein may be described as performing a set of tasks or operations. It is understood that these entities are "configured to" perform these tasks / operations, even if this is not specifically stated.

[0104] The term "configured to" should not be interpreted as "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a specific function. However, this unprogrammed FPGA could be "configurable to" perform that function. After appropriate programming, the FPGA could then be described as "configured to" perform the specific function.

[0105] For the purposes of U.S. patent applications based on this disclosure, a claim stating that a structure is "configured to" perform one or more tasks shall expressly not rely on the application of 35 U.S.C. § 112(f) for that claim element. If, during the grant proceedings of a U.S. patent application based on this disclosure, the applicant wishes to rely on the application of section 112(f), they shall state claim elements using the construct "means to" [perform a function]. Various "circuits" may be described in this disclosure. These circuits, or "switching logic," constitute hardware that incorporates various types of circuit elements, such as combinational logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, and memory (e.g.,This includes random access memory (RAF), embedded dynamic RAF, programmable logic arrays, and so on. Switching logic can be user-defined or taken from standard libraries. In various implementations, switching logic can include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits can be generally referred to as "units" (e.g., a decoding unit, an arithmetic logic unit (ALU), a functional unit, a memory management unit (MMU), etc.). Such units also refer to circuits or switching logic.

[0106] The disclosed circuits / units / components and other elements illustrated in the drawings and described herein thus include hardware elements such as those described in the preceding paragraph. In many cases, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decoding unit" can be described as performing the function of "processing an opcode of an instruction and redirecting that instruction to one or more of a plurality of functional units," meaning that the decoding unit is "configured to" perform this function. This functional description is sufficient for a person skilled in the art in computing to further define a set of possible structures for the circuit.

[0107] In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements can be defined by the functions or operations for which they are configured. The arrangement of these circuits / units / components in relation to one another and the way in which they interact constitute a microarchitectural definition of the hardware, which is ultimately fabricated in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, the microarchitectural definition is recognized by the person skilled in the art as a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitectural definition.This means that the person skilled in the art, to whom the microarchitecture definition provided according to this disclosure is presented, can implement the structure without undue experimentation and by applying average skills by encoding the description of the circuits / units / components in a hardware description language (HDL), such as Verilog or VHDL. The HDL description is often expressed in a way that may appear functional. However, to the person skilled in the art, this HDL description is the way in which the structure of a circuit, unit, or component is transformed to the next level of implementation detail. Such an HDL description may take the form of behavioral code (which is not usually synthesizable), register-transfer language (RTL) code (which, unlike behavioral code, is usually synthesizable), or structural code (e.g.,a netlist specifying logic gates and their connectivity). The HDL description can then be synthesized against a library of cells designed for a given integrated circuit fabrication technology and modified for timing, power, and other reasons to produce a final design database. This database is then sent to a foundry to generate masks and ultimately fabricate the integrated circuit. Some hardware circuits, or sections thereof, can also be custom-designed in a schematic editor and incorporated into the integrated circuit design along with synthesized switching logic. The integrated circuits can include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and connect the transistors and circuit elements.Some embodiments can implement multiple integrated circuits coupled together to implement the hardware circuits, and / or discrete elements can be used in some embodiments. Alternatively, the HDL design can be synthesized into a programmable logic array, such as a field-programmable gate array (FPGA), and implemented within the FPGA. This decoupling between the design of a group of circuits and the subsequent low-level implementation of those circuits typically results in a scenario where the circuit or logic designer never specifies a particular set of structures for low-level implementation beyond a description of what the circuit is configured for, as this process is performed at a different stage of the circuit implementation process.

[0108] The fact that many different low-level combinations of circuit elements can be used to implement the same circuit specification leads to a large number of equivalent structures for that circuit. As indicated, these low-level circuits can vary according to changes in the manufacturing technology, the foundry chosen to produce the integrated circuit, the library of cells provided for a particular project, and so on. In many cases, the choices made by different design tools or methodologies for producing these different implementations can be arbitrary.

[0109] Furthermore, for a single implementation of a particular functional specification of a circuit, it is common to include a large number of devices (e.g., millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete low-level specification of the structure used to implement a single embodiment, let alone the vast array of equivalent possible implementations. For this reason, the present disclosure describes a structure of circuits using the functional shorthand notation commonly employed in industry.

Claims

[1] Institution (100), comprising: a memory interface circuit (130) configured to be coupled to a storage device (150) via an interface (140) having a command bus (144) clocked by a command clock signal (142), the storage device (150) comprising a plurality of banks; and a control circuit (120) coupled and configured with the memory interface circuit (130) to initiate a multi-bank memory operation by scheduling a sequence of bank-specific commands to be sent to the memory device (150) via the command bus (144), wherein the bank-specific commands for a given memory bank (152) include the following: a first activation instruction, followed by a second activation instruction two cycles of the instruction clock signal (142) later; and a read / write command that follows the second activation command by at least one minimum timing parameter specified for the storage device (150), wherein the read / write command specifies a type of operation to be performed; and where it is planned that every second read / write instruction during the multi-bank memory operation will be delayed beyond the minimum timing parameter, and where it is planned that remaining read / write instructions will not be delayed beyond the minimum timing parameter. [2] Device (100) according to claim 1, wherein the multi-bank storage operation is a burst operation and wherein the control circuit (120) is configured to: Scheduling an activation instruction on every second clock cycle of the instruction bus (144) to perform the multi-bank memory operation; and Scheduling other types of instructions on intermediate clock cycles. [3] Device (100) according to claim 2, wherein it is planned that every second read / write instruction during the multi-bank memory operation, starting with an initial read / write instruction, is delayed by two cycles beyond the minimum timing parameter. [4] Device (100) according to claim 2, wherein it is planned that every second read / write instruction during the multi-bank memory operation, starting with a read / write instruction following an initial read / write instruction, is delayed by two cycles beyond the minimum timing parameter. [5] Device (100) according to claim 1, wherein the sequence of bank-specific commands addresses each of the plurality of banks during one or more passes, starting with an initial bank and ending with a final bank; and where commands in the sequence of bank-specific commands are planned such that during a specific pass through the multitude of banks, there is full utilization of a data bus (146) of the interface (140) during a period of time between which data for the initial bank and the final bank are available on the data bus (146). [6] Device (100) according to claim 2, wherein the interface (140) includes a data bus (146) which is clocked by a data clock signal, wherein the control circuit (120) is configured to set the storage device (150) in a specific mode for multi-bank storage operation, wherein the specific mode causes the storage device (150) to delay one clock cycle before starting the data clock signal in response to a synchronization command, and wherein the control circuit (120) is further configured to: When the specified mode is active, schedule the synchronization instruction two clock cycles before scheduling a read / write instruction for an initial bank addressed in the multi-bank memory operation. [7] Device (100) according to claim 6, wherein, in response to the fact that the read / write commands are read commands, the minimum timing parameter specifies a minimum RAS-to-CAS delay for read operations (tRCDr) between a second activation for a given memory bank (152) and a read command for the given memory bank (152); and where every second read instruction during the multi-bank memory operation is delayed by two cycles of the instruction clock signal (142) beyond tRCDr, while remaining read instructions are scheduled at a time equal to tRCDr after a corresponding second activation instruction. [8] Device (100) according to claim 6, wherein, in response to the fact that the read / write commands are write commands, the minimum timing parameter specifies a minimum RAS-to-CAS delay for write operations (tRCDw) between a second activation for a given memory bank (152) and a write command for the given memory bank (152); and where every second write instruction during the multi-bank memory operation is delayed by two cycles of the instruction clock signal (142) beyond tRCDw, while remaining write instructions are scheduled at a time equal to tRCDw after a corresponding second activation instruction. [9] Device (100) according to claim 1, wherein the device (100) is a mobile computing device that includes the storage device (150). [10] Device (100) according to claim 9, wherein the storage device (150) is compliant with JEDEC JESD209-5, Low Power Dual Data Rate 5 (LPDDR5). [11] Procedure, encompassing: Initiate, through a memory controller for a multi-bank memory operation, a cadence that includes the following: Plan, for a given memory bank (152) of a plurality of memory banks (152) in a storage device (150), a first activation instruction, a second activation instruction, and a type instruction specifying an instruction type, wherein the second activation instruction is scheduled to occur two cycles after the first activation instruction, wherein the type instruction is scheduled to occur one first period after the second activation instruction, and wherein the first period is equal to two clock cycles plus a minimum timing delay specified for the storage device (150); and Planning, for a next memory bank (152) of the plurality of memory banks (152), a third activation instruction, a fourth activation instruction, and the type instruction, wherein the fourth activation instruction is planned to occur two cycles after the third activation instruction, wherein the type instruction is planned to occur a second period after the fourth activation instruction, and wherein the second period is equal to the minimum timing delay; and Repeat, by means of the memory control, the cadence for additional pairs of memory banks (152) in the memory device (150) to continue the multi-bank memory operation. [12] Method according to claim 11, wherein the multi-bank memory operation is a burst operation, and wherein, in order to perform the burst operation, the memory controller schedules that activation instructions occur every second cycle and schedules that type instructions occur in intermediate cycles between those scheduled for activation instructions. [13] Method according to claim 12, wherein the minimum timing delay time is a RAS-to-CAS delay specified for the storage device (150), and wherein the storage device (150) is a synchronous dynamic random access memory (SDRAM). [14] The method of claim 13, further comprising: Setting, by the memory controller, a synchronization delay mode for the storage device (150); and Planning, through memory control, of a synchronization instruction two clock cycles prior to planning a type instruction for an initial bank addressed in the multi-bank memory operation; and wherein the synchronization delay mode causes the storage device (150) to internally delay a received synchronization command for one cycle. [15] Method according to claim 13, wherein data for a given memory bank (152) in the multi-bank memory operation includes two data beats on a data bus (146) of the storage device (150), each beat being two clock cycles long, the two beats being separated by two clock cycles, and wherein the repetition of the cadence interleaves data from different memory banks (152) to increase the utilization of the data bus (146) during the multi-bank memory operation. [16] Institution (100), comprising: a computer system that includes: one or more processor circuits; a communications fabric; a memory controller configured to receive memory requests from the one or more processor circuits via the communication fabric; and a storage system coupled to the storage controller via an interface (140) that includes a command bus (144) and a data bus (146), wherein the storage system includes a plurality of storage devices (150) that include multiple memory banks (152) accessible using activation and read / write commands, wherein the plurality of storage devices (150) exhibit a minimal timing delay between an activation sequence and a corresponding read / write command when accessing a given memory bank (152); and wherein the memory controller is configured in response to receiving a request for a burst memory operation with a particular of the plurality of memory devices (150) to schedule a sequence of read / write instructions on the instruction bus for a set of memory banks (152) within the particular memory device (150) such that alternate read / write instructions in the sequence are scheduled to be delayed by a multicycle window beyond the minimum timing delay, with remaining read / write instructions in the sequence being scheduled so that they are not delayed beyond the minimum timing delay. [17] Device (100) according to claim 16, wherein the plurality of storage devices (150) is accessed by using two activation instructions for a given memory bank (152), wherein the memory controller is configured to schedule activation instructions to occur every second clock cycle and to schedule other instructions to occur on intermediate clock cycles. [18] Device (100) according to claim 17, wherein the minimum timing delay is a RAS-to-CAS delay specified for the plurality of storage devices (150), and wherein the multi-cycle window is two clock cycles of a clock signal of the instruction bus. [19] Device (100) according to claim 18, wherein the plurality of storage devices (150) have an operating mode in which a synchronization instruction received from the storage controller is delayed by one or more clock cycles before a clock signal of the data bus (146) is started, and wherein the storage controller is configured to put the specific storage device (150) into the operating mode to perform the burst storage operation. [20] Device (100) according to claim 18, wherein the sequence of read / write commands is planned such that data from the set of memory banks (152) on the data bus (146) are fully nested.

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