Error correction code circuit, memory device, and memory system including same

Abstract

Disclosed is a memory device including: an input / output circuit receiving first data and first parity data from a memory controller; an ECC encoder that generates parity check data based on the first data; a syndrome generator that generates a syndrome based on the parity check data and the first parity data; an error vector generator performing ECC decoding based on the syndrome and generating an error vector; an error correction circuit generating error-corrected data based on the error vector, the first data, and the first parity data; and the storage unit array is used for storing the data after error correction. The error vector generator includes: an arithmetic circuit performing a common operation associated with ECC decoding based on a syndrome and generating a common arithmetic signal; and a plurality of comparison circuits that generate an error vector based on the syndrome and the common arithmetic signal.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0109401, filed on August 14, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure described herein relate to semiconductor memories, and more specifically, to error correction coding in memory devices. Background Technology

[0004] Semiconductor memories can be divided into volatile memories and non-volatile memories. Volatile memories lose the data stored in them when power is turned off, while non-volatile memories retain the data stored in them when power is turned off. Examples of volatile memories include static random access memory (SRAM) and dynamic random access memory (DRAM). Examples of non-volatile memories include flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0005] DRAM is widely used as system memory in mobile devices and computer equipment. Today, DRAM devices include error-correcting code (ECC) circuitry to improve the reliability of the data stored within. ECC circuitry corrects errors in the data stored in DRAM devices. With continuous technological advancements, the storage capacity of DRAM devices continues to increase, and the realization of ECC circuitry occupying a smaller area has become a desirable goal. Summary of the Invention

[0006] Embodiments of this disclosure provide an error correction code circuit that occupies a smaller area by reducing logic circuitry, a memory device including the error correction code circuit, and a memory system including the memory device.

[0007] According to an embodiment, a storage device includes: an input / output circuit for receiving first data and first parity data from a memory controller; an error-correcting code (ECC) encoder for generating parity check data based on the first data; a parity generator for generating a parity based on the parity check data and the first parity data; an error vector generator for performing ECC decoding based on the parity and generating an error vector; an error-correcting circuit for generating error-corrected data based on the error vector, the first data, and the first parity data; and a memory cell array for storing the error-corrected data. The error vector generator includes: an arithmetic circuit for performing a common operation associated with ECC decoding based on the parity and generating a common arithmetic signal; and multiple comparison circuits for generating the error vector based on the parity and the common arithmetic signal.

[0008] According to an embodiment, an error-correcting code (ECC) circuit generates error-corrected data based on first data and first parity data received from a memory controller. The ECC circuit includes: an ECC encoder that generates parity check data based on the first data; and an ECC decoder that performs ECC decoding based on the first data, the first parity data, and the parity check data, and outputs the error-corrected data. The ECC decoder includes: a parity generator that generates a parity based on the parity check data and the first parity data; an error vector generator that decodes the parity to generate an error vector; and an error-correcting circuit that generates the error-corrected data based on the error vector, the first data, and the first parity data. The error vector generator includes: an arithmetic circuit that performs a common operation associated with ECC decoding based on the parity and generates a common arithmetic signal; and multiple comparison circuits that generate the error vector based on the parity and the common arithmetic signal.

[0009] According to an embodiment, a memory system includes: a memory controller that outputs first data and first parity data generated based on the first data; and a storage device including an error correction code (ECC) circuit that receives the first data and the first parity data, generates error-corrected data based on the first data and the first parity data, and stores the error-corrected data. The ECC circuit includes: an ECC encoder that generates parity check data based on the first data; a parity check generator circuit that generates a parity check based on the parity check data and the first parity data; an error vector generator circuit that generates an error vector by performing ECC decoding on the parity check; and an error correction circuit that generates error-corrected data based on the error vector, the first data, and the first parity data. The error vector generator includes: an arithmetic circuit that performs a common operation associated with ECC decoding based on the parity check and generates a common arithmetic signal; and a plurality of comparison circuits that generate the error vector based on the parity check and the common arithmetic signal. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become clear from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0012] Figure 2 It shows Figure 1 A block diagram of the storage device.

[0013] Figure 3 It is used to describe Figure 2 A block diagram of the operation of the ECC circuit of the memory.

[0014] Figure 4 It shows Figure 3 The flowchart of the operation of the ECC circuit.

[0015] Figure 5 It shows the result of Figure 3 A diagram showing an example of a portion of the H matrix used in the memory ECC circuit.

[0016] Figure 6 It is a diagram used to describe ECC encoding operations.

[0017] Figure 7 It is used to describe Figure 3 Block diagram of the ECC encoder.

[0018] Figure 8 It is used to describe based on the comparison examples. Figure 7 The logic gate diagram of an example of a zeroth-order coded circuit.

[0019] Figure 9 It is used to describe Figure 7 The diagram of the zeroth encoding circuit.

[0020] Figure 10 It is based on the example. Figure 3 Functional block diagram of the ECC decoder.

[0021] Figure 11 It is based on the example. Figure 10 Functional block diagram of the error vector generator.

[0022] Figure 12A It is used to describe Figure 11 A diagram illustrating an example of the zeroth ECC decoding circuit.

[0023] Figure 12B It is used to describe Figure 11 The diagram of the checksum comparison signal.

[0024] Figure 13 It shows Figure 5 The zeroth submatrix.

[0025] Figure 14 It is used to describe Figure 11 Block diagram of the zeroth ECC decoding circuit.

[0026] Figure 15A , Figure 15B and Figure 15C It is used to describe Figure 14 A diagram of the common arithmetic circuit.

[0027] Figure 16A It is used to describe Figure 14 The diagram shows the first checker circuit.

[0028] Figure 16B It is used to describe Figure 14 The diagram shows the second checker circuit.

[0029] Figure 17 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0030] The embodiments of this disclosure will now be described in detail and clearly so that those skilled in the art can readily implement this disclosure.

[0031] In this detailed description, the functional blocks in the accompanying drawings, which correspond to the terms "block," "unit," "logic," etc., can be implemented in the form of software, hardware circuitry, or a combination thereof executed by a processor.

[0032] Embodiments of the present invention (such as those described below) provide memories and systems with reduced circuit complexity employing "parity check decoding," as well as ECC circuitry. By providing ECC encoders and decoders implemented with consideration of the structure (e.g., symmetry and common characteristics) of the parity check matrix ("H matrix"), circuit complexity can be reduced, thereby eliminating unnecessary arithmetic circuitry. This reduction in circuit complexity advantageously reduces the area occupied by the ECC circuitry and also reduces power consumption. The reduction in circuitry can be partly achieved by providing "common arithmetic circuitry" (e.g., Figure 14 Implemented using 114b_1), this "common arithmetic circuit" performs common operations associated with ECC decoding based on the checksum and generates common arithmetic signals (e.g., Figure 14 (CAS). Multiple comparator circuits (e.g., CMP0-CMP11) can be configured to generate error vectors in the parser decoding based on the parser and common arithmetic signals.

[0033] Figure 1 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure. (Refer to...) Figure 1 The memory system 10 may include a memory controller 11 and a storage device 100. In embodiments, the memory system 10 may be part of an information processing device (such as a personal computer (PC), laptop computer, server, workstation, smartphone, tablet PC, digital camera, and black box) configured to process various types of information and store processed information.

[0034] The memory controller 11 can store data in the storage device 100, or read data stored in the storage device 100. For example, the memory controller 11 can send a clock signal CK and a command / address signal CA to the storage device 100, and can exchange a data signal DQ and a data strobe signal DQS with the storage device 100. In an embodiment, data “DATA” can be sent from the memory controller 11 to the storage device 100, or vice versa, via the data signal DQ and the data strobe signal DQS. In an embodiment, the memory controller 11 and the storage device 100 can communicate with each other based on a DDR interface or an LPDDR interface, but this disclosure is not limited thereto.

[0035] In an embodiment, the memory controller 11 may include a controller error correction code (ECC) circuit 11a. The controller ECC circuit 11a may be configured to generate parity data by performing ECC encoding on corresponding first data sent from an external host (not shown). The memory controller 11 may send a data "DATA" including the first data and the parity data, along with a write command, to the storage device 100. Furthermore, the controller ECC circuit 11a may be configured to detect and correct errors in second data received from the storage device 100 in response to a read command. For example, when the second data is sent from the storage device 100 to the memory controller 11, errors may occur in the second data due to various factors. The controller ECC circuit 11a may perform ECC decoding based on the second data and may correct the errors in the second data.

[0036] Storage device 100 can receive first data and parity data from memory controller 11. In an embodiment, storage device 100 may include memory ECC circuitry 110. Memory ECC circuitry 110 may be configured to detect and correct errors in the first data and parity data. For example, when the first data and parity data are sent from memory controller 11 to memory 100, errors may occur in the first data or parity data due to various factors. Memory ECC circuitry 110 may perform ECC decoding based on the first data and parity data and may correct errors in the first data or parity data. Storage device 100 may store the corrected data. Simultaneously, when memory controller 11 generates a read command for third data stored in storage device 100, memory ECC circuitry 110 may be configured to generate third parity data by performing ECC encoding on the third data. Storage device 100 may send data “DATA”, including the third data and third parity data, to memory controller 11 in response to the read command.

[0037] In other words, the controller ECC circuit 11a can correct errors that occur during the process of sending data "DATA" from the storage device 100 to the memory controller 11. The memory ECC circuit 110 can correct errors that occur during the process of sending data "DATA" from the memory controller 11 to the storage device 100.

[0038] Simultaneously, the controller ECC circuit 11a and the memory ECC circuit 110 can perform ECC encoding and ECC decoding based on a parity check matrix (hereinafter referred to as the "H matrix"). In an embodiment, the controller ECC circuit 11a and the memory ECC circuit 110 can be configured to perform operations for ECC encoding and ECC decoding based on the H matrix structure. This allows the controller ECC circuit 11a and the memory ECC circuit 110 to be configured without requiring multiple identical arithmetic circuits to perform the same operations. Therefore, the area occupied by the controller ECC circuit 11a and the memory ECC circuit 110 in the memory system 10 can be minimized. As a result, a smaller size and complexity of the ECC circuit, the memory device including the ECC circuit, and the memory system including the memory device can be provided.

[0039] Figure 2 It shows Figure 1 A block diagram of the storage device. (Refer to...) Figure 1 and Figure 2 The storage device 100 may include a memory ECC circuit 110, a memory cell array 120, a CA buffer 130, an address decoder 140, a command decoder 150, a sense amplifier and a write driver 160, and an input / output circuit 170.

[0040] The memory ECC circuit 110 can generate read parity data RPRT by performing ECC encoding on read data RDT stored in the memory cell array 120. Alternatively or additionally, the memory ECC circuit 110 can correct errors in write data WDT or write parity data WPRT received from the memory controller 11 via input / output circuit 170 by performing ECC decoding based on write data WDT and write parity data WPRT. The configuration and operation of the memory ECC circuit 110 will be described in detail with reference to the following figures.

[0041] The memory cell array 120 may include a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines and a plurality of bit lines. In an embodiment, the plurality of word lines may be driven by an X decoder (or row decoder) (X-DEC), and the plurality of bit lines may be driven by a Y decoder (or column decoder) (Y-DEC).

[0042] CA buffer 130 can be configured to receive command / address signals CA and temporarily store or buffer the received signals.

[0043] Address decoder 140 can decode the address signal ADDR stored in CA buffer 130. Address decoder 140 can control X decoder and Y decoder based on the decoding result.

[0044] Command decoder 150 can decode commands (CMD) stored in CA buffer 130. Command decoder 150 can control components of storage device 100 based on the decoding result. For example, when the command signal stored in CA buffer 130 corresponds to a write command (i.e., when the command received from memory controller 11 is a write command), command decoder 150 can control memory ECC circuit 110 so that data “DATA” received through input / output circuit 170 is written to storage cell array 120 (e.g., after performing ECC decoding), and command decoder 150 can control the operation of sense amplifier and write driver 160 (i.e., the write driver can be activated).

[0045] Alternatively, when the command signal stored in CA buffer 130 corresponds to a read command (i.e., when the command received from memory controller 11 is a read command), command decoder 150 can control sense amplifier and write driver 160 (i.e., can activate sense amplifier) ​​so that data stored in memory cell array 120 is read, and command decoder 150 can control memory ECC circuit 110 (and can perform ECC encoding).

[0046] Under the control of the command decoder 150, the sense amplifier and write driver 160 can read data stored in the memory cell array 120 through multiple bit lines, or write data into the memory cell array 120 through multiple bit lines.

[0047] Based on the data signal DQ and the data strobe signal DQS, the input / output circuit 170 can receive data "DATA" from the memory controller 11 or send data "DATA" to the memory controller 11. For example, the input / output circuit 170 can send the write data WDT and write parity data WPRT included in the received data "DATA" to the memory ECC circuit 110. For example, the input / output circuit 170 can send data "DATA" including the read data RDT stored in the memory cell array 120 and the read parity data RPRT received from the memory ECC circuit 110 to the memory controller 11.

[0048] Figure 3 It is used to describe Figure 2 A block diagram illustrating the operation of the memory ECC circuit. (Refer to...) Figure 2 and Figure 3 The memory ECC circuit 110 may include an ECC encoder circuit (“ECC encoder”) ECC-ENC and an ECC decoder circuit (“ECC decoder”) ECC-DEC. The ECC encoder ECC-ENC can generate read parity data RPRT by performing ECC encoding on read data RDT stored in the memory cell array 120. For example, the ECC encoder ECC-ENC can generate 16-bit read parity data RPRT by performing ECC encoding on 272 bits of read data RDT stored in the memory cell array 120. The read data RDT and the read parity data RPRT can be sent to the memory controller 11 via input / output circuit 170.

[0049] Furthermore, the ECC encoder ECC-ENC can generate parity check data PCD by performing H-matrix-based ECC encoding on the write data WDT transmitted from the memory controller 11 via the input / output circuit 170. For example, the ECC encoder ECC-ENC can generate 16-bit parity check data PCD by performing ECC encoding on 272-bit write data WDT. The ECC encoder ECC-ENC can then send the parity check data PCD to the ECC decoder ECC-DEC.

[0050] In this embodiment, the ECC encoder ECC-ENC can be configured to perform ECC encoding based on the H matrix.

[0051] The ECC decoder ECC-DEC can output error-corrected data DT_cor by performing ECC decoding based on the write data WDT and write parity data WPRT transmitted from the memory controller 11 via the input / output circuit 170, and the parity check data PCD sent from the ECC encoder ECC-ENC. For example, the ECC decoder ECC-DEC can generate 288 bits of error-corrected data DT_cor by performing ECC decoding based on 272 bits of write data WDT, 16 bits of write parity data WPRT, and 16 bits of parity check data PCD. The error-corrected data DT_cor can be obtained by correcting errors in the write data WDT or the parity check data PCD.

[0052] In this embodiment, the ECC decoder ECC-DEC can be configured to perform ECC decoding based on the H matrix.

[0053] Figure 3The diagram illustrates the number of bits for reading data RDT, reading parity data RPRT, parity check data PCD, writing data WDT, writing parity data WPRT, and error-corrected data DT_cor, but this disclosure is not limited thereto. That is, the number of bits for reading data RDT, reading parity data RPRT, parity check data PCD, writing data WDT, writing parity data WPRT, and error-corrected data DT_cor can be varied or modified depending on the implementation.

[0054] In this embodiment, only 256 bits of the 272 bits written to the data WDT can be valid data bits. In this case, the ECC encoder ECC-ENC can be configured to generate parity check data PCD by performing ECC encoding on only the 256 bits of valid data. Furthermore, the ECC decoder ECC-DEC can be configured to output 272 bits of error-corrected data DT_cor by performing ECC decoding on only the 256 bits of valid data and the 16 bits of parity check data PCD.

[0055] Figure 3 It shows Figure 2 Example of memory ECC circuit 110. Figure 1 The controller ECC circuit 11a may have a similar or identical configuration to the memory ECC circuit 110. Therefore, the controller ECC circuit 11a may include an ECC encoder and an ECC decoder. The ECC encoder can generate write parity data by performing ECC encoding on write data sent from an external host. Furthermore, the ECC encoder can generate parity check data by performing ECC encoding on read data received from the storage device 100. The ECC decoder can generate error-corrected data by performing ECC decoding based on the read data, the parity check data, and the read parity data corresponding to the read data.

[0056] For ease of description and concise drawing, the following figures use memory ECC circuit 110 as an example for illustration, but the configuration and operation of controller ECC circuit 11a can be implemented in the same way as the configuration and operation of memory ECC circuit 110.

[0057] Figure 4 It shows Figure 3 The flowchart for the operation of the ECC circuit is shown below. Figure 1 , Figure 3 and Figure 4In operation S110, the memory ECC circuit 110 can receive write data WDT and write parity data WPRT from the memory controller 11. For example, the write parity data WPRT can be data generated by the ECC encoder of the controller ECC circuit 11a.

[0058] In operation S120, the memory ECC circuit 110 can generate parity check data PCD based on the write data WDT. In an embodiment, the ECC encoder ECC-ENC can generate the parity check data PCD by performing H-matrix-based ECC encoding on the write data WDT.

[0059] In operation S130, the memory ECC circuit 110 can generate a checksum SYD based on the parity check data PCD and the write parity data WPRT. Typically, the checksum is a specific pattern calculated based on the received data, and it indicates the presence and location of errors within the data. The checksum pattern allows the decoder to identify and correct errors. In this embodiment, the ECC decoder ECC-DEC can generate a 16-bit checksum SYD by performing a bitwise XOR operation on the parity check data PCD and the write parity data WPRT.

[0060] In operation S140, the memory ECC circuit 110 can generate an error vector ERV based on the parity SYD. To this end, the ECC decoder ECC-DEC can decode the parity SYD to generate the error vector ERV. In an embodiment, the ECC decoder ECC-DEC can detect the error locations of the written data WDT and the written parity data WPRT by comparing the H matrix with the parity SYD. Therefore, the error vector ERV can include information about the error locations of the written data WDT and the written parity data WPRT.

[0061] In operation S150, the memory ECC circuit 110 can generate the error-corrected data DT_cor based on the error vector ERV, the write data WDT, and the write parity data WPRT. The memory ECC circuit 110 can output the error-corrected data DT_cor by performing a bitwise XOR operation on the data WDT, WPRT, and the error vector ERV.

[0062] Figure 5 It shows the result of Figure 3 A diagram illustrating a portion of the H-matrix "H-mat" used in the memory ECC circuit. (See reference...) Figure 5The described H matrix H-mat is an example of a portion of an H matrix used for single-bit error correction (SEC). However, this disclosure is not limited thereto. For example, it will be understood that various modifications or changes can be made to the H matrix according to this disclosure, depending on the implementation of the memory ECC circuit 110.

[0063] The H-matrix H-mat can include a data check matrix (DCM) and a parity check matrix (PR). The DCM can be a 16×272 matrix. The PR can be a 16×16 identity matrix (IM). The rows of the H-matrix H-mat can correspond to bits S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15 of the 16-bit parity check SYD.

[0064] The data inspection matrix (DCM) may include multiple submatrices SM00 to SM11. Each of the zeroth to tenth submatrices SM00 may have a size of 16×24. The eleventh submatrice SM11 may have a size of 16×8. However, this disclosure is not limited thereto. Furthermore, each of the multiple submatrices SM00 to SM11 may include multiple "valid elements." Additionally, each of the multiple submatrices SM00 to SM11 may include multiple common areas. (See reference...) Figure 6 and Figure 13 Describe the valid elements and public areas in detail.

[0065] According to this disclosure, the ECC encoder ECC-ENC can be configured to perform ECC encoding by operations corresponding to valid elements rather than common areas. Furthermore, the ECC decoder ECC-DEC may include common (shared) arithmetic circuitry that performs operations corresponding to common areas. Based on the above description, unnecessary arithmetic circuitry can be omitted from both the ECC encoder ECC-ENC and the ECC decoder ECC-DEC. Therefore, the area of ​​the memory ECC circuitry 110 can be reduced.

[0066] Figure 6 This is a diagram used to describe ECC encoding operations. In detail, Figure 6 An example of a Data Inspection Matrix (DCM) is shown. (See reference...) Figure 3 , Figure 5 and Figure 6 For write operations, the ECC encoder ECC-ENC can generate parity check data (PCD) by performing ECC encoding based on the write data (WDT) and the data check matrix (DCM). Similarly, for read operations, the ECC encoder ECC-ENC can generate PCD by performing ECC encoding on the read data (RDT) and the data check matrix (DCM).

[0067] The columns of the Data Check Matrix (DCM) can correspond to the bits of the written data WDT (e.g., WDT0 to WDT271). The rows of the Data Check Matrix (DCM) can correspond to the bits of the parity check data PCD (e.g., PCD0 to PCD15). Furthermore, although... Figure 6 Although not shown in the diagram, each column of the Data Check Matrix (DCM) can correspond to a specific bit in the read data RDT. The rows of the Data Check Matrix (DCM) can each correspond to a bit in the read parity data RPRT.

[0068] In order to describe the embodiments of this disclosure concisely and clearly, some data values ​​or bit values ​​will be described as being at a specific level or a specific bit level (e.g., "1" or "0"). However, this disclosure is not limited thereto. In other examples, the data values ​​or bit values ​​used in this specification may be modified or changed in various ways.

[0069] ECC encoding can be performed based on the transpose of the data check matrix (DCM), referred to as the "parity generation matrix". For example, the parity generation matrix can be 272×16 in size. For example, the parity check data PCD can correspond to the result of multiplying a 272-bit write data WDT (e.g., a matrix of size 1×272) with the parity generation matrix.

[0070] The matrix multiplication operation based on the parity check generator matrix and the written data WDT can be achieved by performing a bitwise XOR operation on the column vectors of the data check matrix DCM, where each column vector corresponds to a "1" bit in the written data WDT. For example, as Figure 6 As shown, the bit values ​​of the eighth bit WDT8 and the twentieth bit WDT20 in the data WDT can be "1" (i.e., WDT(272b) = "0000 0000 1000 0000 00001000…0000", where WDT(272b) represents 272 bits of written data). In this case, the parity check data PCD can be the result of performing a bitwise XOR operation on the column vectors of the zeroth submatrix SM00 that correspond to the eighth bit WDT8 and the twentieth bit WDT20 respectively (e.g., "1000 0000 1100 0000" and "1000 0000 0011 0000") (e.g., PCD(16b) = "0000 0000 1111 0000").

[0071] Simultaneously, the Data Check Matrix (DCM) can include multiple "valid elements." For example, an element in the DCM that is "1" can be called such a valid element. As mentioned above, the matrix multiplication operation used for ECC encoding can be an XOR operation on the column vector of the DCM, which corresponds to the "1" bits (e.g., WDT8 and WDT20) written into the data WDT. Therefore, each bit value of the parity check data PCD bits PCD0 to PCD15 can be determined based on the bit value of the bit corresponding to each of the associated valid elements in bits PCD0 to PCD15 among the bits WDT0 to WDT271 written into the data WDT.

[0072] In Figure 6 In the different examples shown, all remaining elements of the data check matrix DCM except for the element of the zeroth submatrix SM00 are "0". In this case, the value of the zeroth bit PCD0 of the parity check data PCD can be determined based on the bit values ​​of bits WDT8 and WDT20 written to the data WDT. These bits WDT8 and WDT20 correspond to the valid elements associated with the zeroth bit PCD0 (i.e., the valid elements of the first row of the data check matrix DCM). For example, in Figure 6 In the example, when both the eighth bit WDT8 and the twentieth bit WDT20 are "1", the zeroth bit PCD0 of the parity check data PCD can be "0". For example, with Figure 6 Unlike the example, when both the eighth bit WDT8 and the twentieth bit WDT20 are "0", the zeroth bit PCD0 of the parity check data PCD can be "0". For example, with Figure 6 Unlike the example, when only one of the eighth bit WDT8 and the twentieth bit WDT20 is "0", the zeroth bit PCD0 of the parity check data PCD can be "1". Therefore, the zeroth bit PCD0 of the parity check data PCD can be the result of performing an XOR operation on the eighth bit WDT8 and the twentieth bit WDT20 of the written data WDT.

[0073] Similarly, the first bit PCD1 of the parity check data PCD can be the result of an XOR operation performed on the ninth bit WDT9 and the twenty-first bit WDT21 corresponding to the valid elements of the second row of the data check matrix DCM. Furthermore, the eighth bit PCD8 of the parity check data PCD can be the result of an XOR operation performed on the zeroth bit WDT0 through the eleventh bit WDT11 (e.g., "0000 0000 1000") corresponding to the valid elements of the ninth row of the data check matrix DCM (e.g., "1").

[0074] In other words, each bit of the parity check data PCD can be the result of performing an XOR operation on the bits corresponding to the valid elements of the rows of the data written to the WDT that are associated with each bit of the parity check data PCD in the data check matrix DCM. Therefore, matrix multiplication for ECC encoding can be implemented by performing an XOR operation on the bits of the data written to the WDT that correspond to the valid elements of the data check matrix DCM. According to this disclosure, the ECC encoder ECC-ENC can be configured to generate the parity check data PCD (i.e., perform ECC encoding) by performing an XOR operation on only the bits of the data written to the WDT, WDT0 to WDT271, that correspond to the valid elements of the data check matrix DCM. Therefore, unnecessary arithmetic circuitry can be omitted from the ECC encoder ECC-ENC. Thus, the area occupied by the ECC encoder ECC-ENC can be reduced.

[0075] Figure 7 It is used to describe Figure 3 A block diagram of the ECC encoder. (Refer to...) Figure 3 and Figure 7 The ECC encoder ECC-ENC may include a check data generator 111 and an XOR circuit 112. The check data generator 111 may be configured to output 16-bit check data CD0 to CD11 by performing ECC encoding on sub-matrices SM00 to SM11 of the data check matrix DCM based on the write data WDT.

[0076] The data generator 111 may include encoding circuits ENCC0 to ENCC11. Encoding circuits ENCC0 to ENCC11 may correspond to sub-matrices SM00 to SM11 of the data inspection matrix DCM, respectively. The zeroth encoding circuit ENCC0 may be configured to output 16 bits of zeroth inspection data CD0 by performing ECC encoding corresponding to the zeroth sub-matrix SM00 based on the zeroth sub-write data SWDT0. The first encoding circuit ENCC1 may be configured to output 16 bits of first inspection data CD1 by performing ECC encoding corresponding to the first sub-matrix SM01 based on the first sub-write data SWDT1. The eleventh encoding circuit ENCC11 may be configured to output 16 bits of eleventh inspection data CD11 by performing ECC encoding corresponding to the eleventh sub-matrix SM11 based on the eleventh sub-write data SWDT11.

[0077] For example, the zeroth sub-write data SWDT0 can be composed of bits of write data WDT (e.g., WDT0 to WDT23); the first sub-write data SWDT1 can be composed of bits of write data WDT (e.g., WDT24 to WDT47); and the eleventh sub-write data SWDT11 can be composed of bits of write data WDT (e.g., WDT264 to WDT271). Therefore, each of the sub-write data SWDT0 to SWDT11 can be composed of bits of write data WDT associated with the corresponding sub-matrix (e.g., one of SM00 to SM11).

[0078] Each of the check data CD0 to CD11 can be the result of performing ECC encoding on the corresponding submatrix SM00 to SM11 of the data check matrix DCM. XOR circuit 112 can be configured to output 16-bit parity check data PCD by performing a bitwise XOR operation on the check data CD0 to CD11. In an embodiment, XOR circuit 112 may include multiple XOR gates for performing bitwise XOR operations on the check data CD0 to CD11.

[0079] In this embodiment, during the read operation, the ECC encoder ECC-ENC can generate read parity data RPRT using a method similar to that used to generate parity check data PCD. To this end, the check data generator 111 can generate check data CD0 to CD11 by performing ECC encoding on a submatrix of the data check matrix DCM based on the read data RDT. The XOR circuit 112 can generate the read parity data RPRT by performing a bitwise XOR operation on the check data CD0 to CD11.

[0080] Figure 8 It is based on the comparison examples used for description Figure 7 The logic gate diagram of an example zeroth-order coded circuit. See also... Figure 7 and Figure 8 The zeroth encoding circuit ENCC0 may include encoding arithmetic circuits EAC0 to EAC15. The encoding arithmetic circuits EAC0 to EAC15 may be configured to output bits CD0[0] to CD0

[15] of the zeroth check data CD0 by performing an XOR operation based on the sub-data SD0 to SD15 included in the first sub-write data SWDT1.

[0081] The zeroth encoding arithmetic circuit EAC0 can be configured to output the zeroth bit CD0 of the zeroth check data CD0 by performing an XOR operation based on the zeroth sub-data SD0[0]; the first encoding arithmetic circuit EAC1 can be configured to output the first bit CD0 of the zeroth check data CD0 by performing an XOR operation based on the first sub-data SD1[1]; and the fifteenth encoding arithmetic circuit EAC15 can be configured to output the fifteenth bit CD0 of the zeroth check data CD0 by performing an XOR operation based on the fifteenth sub-data SD15

[15] .

[0082] As previously stated, the zeroth encoding circuit ENCC0 can perform ECC encoding corresponding to the zeroth submatrix SM00 of the data check matrix DCM. The zeroth encoding circuit EAC0 to the fifteenth encoding circuit EAC15 can generate bits CD0[0] to CD0

[15] of the zeroth check data CD0 by performing operations corresponding to the rows of the zeroth submatrix SM00. Specifically, the zeroth encoding arithmetic circuit EAC0 can be configured to perform operations corresponding to the first row of the zeroth submatrix SM00; the first encoding arithmetic circuit EAC1 can be configured to perform operations corresponding to the second row of the zeroth submatrix SM00; and the fifteenth encoding arithmetic circuit EAC15 can be configured to perform operations corresponding to the sixteenth row of the zeroth submatrix SM00.

[0083] Simultaneously, the zeroth sub-data SD0 can be constructed from bits WDT8 and WDT20 of the first sub-written data SWDT1, corresponding to the valid elements of the first row of the zeroth sub-matrix SM00. The first sub-data SD1 can be constructed from bits WDT9 and WDT21 of the first sub-written data SWDT1, corresponding to the valid elements of the second row of the zeroth sub-matrix SM00 (e.g., ...). Figure 6 (As shown). The fifteenth sub-data SD15 can be constructed from bits WDT7 and WDT19 in the first sub-data SWDT1 that correspond to the positions of the valid elements in the sixteenth row of the zeroth sub-matrix SM00 (as shown). Figure 6 (As shown).

[0084] For example, each of the encoding arithmetic circuits EAC0 to EAC15 can be configured to perform an XOR operation through a 4-stage XOR arithmetic circuit. That is, each of the encoding arithmetic circuits EAC0 to EAC15 can include 15 XOR gates. In this case, the zeroth encoding arithmetic circuit EAC0 can include multiple XOR gates X0 whose inputs receive "0". In this case, the bit value of the zeroth bit CD0[0] of the zeroth check data CD0 can be determined solely based on the bit values ​​of the eighth bit WDT8 and the twentieth bit WDT20 of the written data WDT. Therefore, when as Figure 8When implementing the coded arithmetic circuit (e.g., EAC0), the zeroth coded arithmetic circuit EAC0 may include multiple XOR gates (e.g., X0) that perform unnecessary operations. This could mean that the area of ​​the zeroth coded circuit ENCC0 becomes excessive.

[0085] Figure 9 According to the embodiments Figure 7 The logic circuit diagram of the zeroth encoding circuit. (Refer to...) Figure 6 , Figure 7 and Figure 9 The zeroth encoding circuit ENCC0 may include encoding arithmetic circuits EAC0 to EAC13, which are relative to Figure 8 The comparative examples generally have significantly fewer logic gates. The encoded arithmetic circuits EAC0 to EAC13 can be configured to output bits CD0[0] to CD0

[15] of the zeroth check data CD0 by performing an XOR operation based on the sub-data SD0 to SD13 included in the first sub-write data SWDT1. The sub-data SD0 to SD13 can be formed from some bits WDT0 to WDT24 of the first sub-write data SWDT1.

[0086] Each of the encoding arithmetic circuits EAC0 to EAC13 can be configured to perform an XOR operation corresponding to the corresponding row of the zeroth submatrix SM00. The zeroth encoding arithmetic circuits EAC0 to EAC7 can generate bits CD0[0] to CD0[7] of the zeroth check data CD0 by performing XOR operations corresponding to the first to eighth rows of the zeroth submatrix SM00. The eighth encoding arithmetic circuit EAC8 can generate the eighth bit CD0[8] and the ninth bit CD0[9] of the zeroth check data CD0 by performing XOR operations corresponding to the ninth and tenth rows of the zeroth submatrix SM00. The ninth encoding arithmetic circuit EAC9 can generate the tenth bit CD0

[10] and the eleventh bit CD0

[11] of the zeroth check data CD0 by performing XOR operations corresponding to the eleventh and twelfth rows of the zeroth submatrix SM00. The tenth coding arithmetic circuit EAC10 to the thirteenth coding arithmetic circuit EAC13 can generate the twelfth bit CD0

[12] to the fifteenth bit CD0

[15] of the zero check data CD0 by performing XOR operations corresponding to the thirteenth to sixteenth rows of the zero submatrix SM00.

[0087] In an embodiment, the encoding arithmetic circuits EAC0 to EAC13 can be configured to perform an XOR operation only on the bits corresponding to the valid elements in the bits written to the data WDT.

[0088] The zeroth sub-data SD0 can be a 2-bit data formed by bits WDT8 and WDT20 of the written data WDT, which correspond to the valid elements in the first row of the zeroth sub-matrix SM00. The zeroth encoding arithmetic circuit EAC0 can be implemented using an XOR gate configured to receive the 2-bit zeroth sub-data SD0 and output the zeroth bit CD0 of the zeroth check data CD0[0]. In other words, the zeroth encoding arithmetic circuit EAC0 can perform AND operations with a single XOR gate. Figure 8 The zeroth-coded arithmetic circuit EAC0 with 15 XOR gates performs the same operations. Therefore, the zeroth-coded arithmetic circuit EAC0 can omit arithmetic circuits used for unnecessary operations (e.g., Figure 8 (14 out of the 15 XOR gates X0).

[0089] Similarly, each of the first sub-data SD1 to the seventh sub-data SD7 can be formed by bits of the write data WDT, which correspond to valid elements in each of the second to eighth rows of the zeroth sub-matrix SM00, and each of the tenth sub-data SD10 to the thirteenth sub-data SD13 can be formed by bits of the write data WDT, which correspond to valid elements in each of the thirteenth to sixteenth rows of the zeroth sub-matrix SM00. Figure 6 As shown, each row of the data inspection matrix DCM, from the first to the eighth row and from the eleventh to the sixteenth row, can contain only two valid elements. Therefore, each of the first sub-data SD1 to the seventh sub-data SD7 and the tenth sub-data SD10 to the thirteenth sub-data SD13 can be 2 bits of data.

[0090] Therefore, each of the first to seventh coding arithmetic circuits EAC1 through EAC7 and the tenth to thirteenth coding arithmetic circuits EAC10 through EAC13 can be implemented using a single XOR gate, just like the zeroth coding arithmetic circuit EAC0. That is, each of the first to seventh coding arithmetic circuits EAC7 and the tenth to thirteenth coding arithmetic circuits EAC10 through EAC13 can omit arithmetic circuits used for unnecessary operations (e.g., Figure 8 Fourteen of the fifteen XOR gates (X0).

[0091] At the same time, such as Figure 6As shown, the ninth and tenth rows of the zeroth submatrix SM00 can have the same data pattern. The elements in the ninth and tenth rows that correspond to the zeroth bit WDT0 to the eleventh bit WDT11 of the written data WDT can be valid elements. Therefore, the eighth subdata SD8 can be composed of the zeroth bit WDT0 to the eleventh bit WDT11 of the written data WDT. In addition, the eighth encoding arithmetic circuit EAC8 can be a 3-stage XOR arithmetic circuit configured to perform an XOR operation on the eighth subdata SD8. The output signal of the eighth encoding arithmetic circuit EAC8 can be used as the eighth bit CD0[8] and the ninth bit CD0[9] of the zeroth check data CD0. Therefore, according to an embodiment of the present disclosure, the eighth encoding arithmetic circuit EAC8 can be configured to output the eighth bit CD0[8] and the ninth bit CD0[9] by performing an operation corresponding to the ninth and tenth rows of the zeroth submatrix SM00 with the same data pattern only once through an arithmetic circuit.

[0092] In addition, such as Figure 6 As shown, the eleventh and twelfth rows of the zeroth submatrix SM00 can have the same data pattern. The elements in the eleventh and twelfth rows that correspond to the twelfth bits WDT12 to the twenty-third bits WDT23 of the written data WDT can be valid elements. Therefore, the ninth encoding arithmetic circuit EAC8 can be a three-stage XOR arithmetic circuit configured to perform an XOR operation on the ninth subdata SD9. The ninth subdata SD9 can be formed by the twelfth bits WDT12 to the twenty-third bits WDT23 of the written data WDT. The output signal of the ninth encoding arithmetic circuit EAC9 can be used as the tenth bit CD0

[10] and the eleventh bit CD0

[11] of the zeroth check data CD0. Therefore, according to an embodiment of the present disclosure, the ninth encoding arithmetic circuit EAC9 can be configured to output the tenth bit CD0

[10] and the eleventh bit CD0

[11] of the zeroth check data CD0 by performing an operation corresponding to the eleventh and twelfth rows of the zeroth submatrix SM00 with the same data pattern only once through an arithmetic circuit.

[0093] Figure 9 Only the zeroth encoding circuit ENCC0 is shown. Figure 7 The other encoding circuits ENCC1 to ENCC11 can be implemented based on the structure of the corresponding submatrices SM01 to SM11 (i.e., the effective elements of each submatrix), just like the zeroth encoding circuit ENCC0.

[0094] As described above, the encoding circuit (e.g., ENCC0) according to embodiments of this disclosure can be configured to perform an XOR operation only on the bits corresponding to the valid elements of the associated submatrix (e.g., SM00) of the written data WDT. Therefore, with Figure 8 In different cases, the encoding circuit (e.g., ENCC0) can omit unnecessary arithmetic circuits (e.g., Figure 8 Many XOR gates (X0) in the matrix. Furthermore, the encoding circuit (e.g., ENCC0) can be configured to perform an XOR operation only once on rows of the correlated submatrix (e.g., SM00) having the same data pattern, via an arithmetic circuit (e.g., EAC8). Based on the above description, with Figure 8 Compared to the encoding circuit of this disclosure, Figure 9 The encoding circuit (e.g., ENCCO) can have a significantly smaller area.

[0095] Figure 10 It is based on the example. Figure 3 Functional block diagram of the ECC decoder. Figure 10 The ECC decoder can be configured to perform Figure 4 Operations S120 to S150. (Refer to...) Figure 3 and Figure 10 The ECC decoder may include a checksum generator circuit (“checksum generator”) 113, an error vector generator circuit (“error vector generator”) 114, and an error correction circuit 115.

[0096] The parity generator 113 can generate a parity SYD based on, for example, 16-bit write parity data WPRT and, for example, 16-bit parity check data PCD. The write parity data WPRT can be data received from the memory controller 11. The parity check data PCD can be data received from the ECC encoder ECC-ENC of the memory ECC circuit 110. In an embodiment, the parity generator 113 can generate a 16-bit parity SYD by performing a bitwise XOR operation on the 16-bit write parity data WPRT and the 16-bit parity check data PCD.

[0097] Error vector generator 114 can be configured to perform ECC decoding on the parity metric to generate an error vector. To do this, error vector generator 114 can generate the error vector ERV by comparing the H matrix H-mat with the parity metric SYD. The error vector ERV can have, for example, a size of 288 bits and can include information about the error locations of the written data WDT and the written parity data WPRT.

[0098] Error correction circuit 115 can correct errors in writing data WDT and parity data WPRT by using error vector ERV. Error correction circuit 115 can output the error-corrected data DT_cor by performing a bitwise XOR operation on error vector ERV and 288 bits of data including written data WDT and written parity data WPRT.

[0099] Figure 11 It is based on the example. Figure 10 The functional block diagram of the error vector generator. (Refer to...) Figure 10 and Figure 11 The error vector generator 114 may include a checker comparison signal (SCS) generation circuit 114a and an error vector generation circuit 114b.

[0100] The checksum comparison signal generation circuit 114a can generate a checksum comparison signal SCS based on the H matrix H-mat and the checksum SYD. The checksum comparison signal SCS can be a signal used to compare each column of the H matrix H-mat with the checksum SYD. The checksum comparison signal generation circuit 114a can generate the checksum comparison signal SCS by inverting the bits SYD0 to SYD15 of the checksum SYD that do not correspond to valid elements. (Refer to...) Figure 12B Describe the parity comparison signal SCS in detail.

[0101] The error vector generation circuit 114b can generate an error vector ERV by comparing each column of the H matrix H-mat with the parity check SYD based on the parity check comparison signal SCS. For example, all bits of the error vector ERV can be "0". In this case, the error vector ERV can indicate that no error occurred in the written data WDT and the written parity data WPRT. For example, only the second bit of the error vector ERV (e.g., the second bit of the zeroth vector VEC0 of the error vector ERV) can be "1". In this case, the error vector ERV can indicate that the second bit WDT2 of the written data WDT has an error.

[0102] Error vector generation circuit 114b may include ECC decoding circuits EDC0 to EDC11. Each of the ECC decoding circuits EDC0 to EDC11 may be configured to compare the correlation submatrix of H matrix H-mat (e.g., one of SM00 to SM11 and PR) with the check SYD.

[0103] For example, the zeroth ECC decoding circuit EDC0 can be configured to compare each column of the zeroth submatrix SM00 with the check SYD to output the zeroth vector VEC0. The zeroth submatrix SM00 can include 24 columns. Therefore, the zeroth vector VEC0 can include 24 bits. For example, the first ECC decoding circuit EDC1 can be configured to compare each column of the first submatrix SM01 with the check SYD to output the first vector VEC1. For example, the second ECC decoding circuit EDC2 can be configured to compare each column of the second submatrix SM02 with the check SYD to output the second vector VEC2. For example, the eleventh ECC decoding circuit EDC11 can be configured to compare each column of the eleventh submatrix SM11 with the check SYD to output the eleventh vector VEC11. The 288-bit error vector ERV can be implemented by combining the zeroth vectors VEC0 to the eleventh vector VEC11.

[0104] Figure 12A yes Figure 11 The logic circuit diagram of an example of the zeroth ECC decoding circuit, and Figure 12B It is used to describe Figure 11 A diagram illustrating an example of the checksum comparison signal. For the sake of simplicity and ease of description, in the following figures, each bit of the checksum SYD is labeled as S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15, and the inverted versions of the bits of the checksum SYD are labeled as S0B, S1B, S2B, S3B, S4B, S5B, S6B, S7B, S8B, S9B, S10B, S11B, S12B, S13B, S14B, and S15B.

[0105] Reference Figure 11 and Figure 12A The zeroth ECC decoding circuit EDC0 may include comparison circuits CMP0 to CMP23. Comparison circuits CMP0 to CMP23 may be configured to compare each column of the zeroth submatrix SM00 with the check SYD based on comparison signals CS0 to CS23 to output the corresponding bit of the zeroth vector VEC0 (e.g., VEC0[0] to VEC0

[23] ). For example, the zeroth comparison circuit CMP0 may be configured to compare the first column of the zeroth submatrix SM00 with the check SYD based on the zeroth comparison signal CS0 to output the zeroth bit VEC0[0] of the zeroth vector VEC0. The twelfth comparison circuit CMP12 is configured to compare the thirteenth column of the zeroth submatrix SM00 with the check value SYD based on the twelfth comparison signal CS12 to output the twelfth bit VEC0

[12] of the zeroth vector VEC0.

[0106] Comparison signals CS0 to CS23 correspond to columns of the zeroth submatrix SM00. Each of comparison signals CS0 to CS23 can be a signal used to compare the corresponding column with the checksum SYD. Comparison signals CS0 to CS23 can be generated by inverting the bits SYD0 to SYD15 of the checksum SYD that do not correspond to valid elements. Meanwhile, Figure 11 The checker comparison signal SCS can include comparison signals CS0 to CS23.

[0107] Reference Figure 12B In the zeroth submatrix SM00, elements belonging to the fifth, ninth, and tenth rows in the first column C1 can be valid elements. Therefore, the 16-bit zeroth comparison signal CS0 can be composed of S0B, S1B, S2B, S3B, S4, S5B, S6B, S7B, S8, S9, S10B, S11B, S12B, S13B, S14B, and S15B. Specifically, for example, when the checksum SYD is "0010 1000 1010 0000", the zeroth comparison signal CS0 can be "1101 1111 1001 1111". Simultaneously, elements belonging to the fifth, eleventh, and twelfth rows in the thirteenth column C13 of the zeroth submatrix SM00 can be valid elements. Therefore, the 16-bit twelfth comparison signal CS12 can be composed of S0B, S1B, S2B, S3B, S4, S5B, S6B, S7B, S8B, S9B, S10, S11, S12B, S13B, S14B, and S15B.

[0108] return Figure 12AWhen all bits of the received comparison signal (e.g., one of CS0 to CS23) are “1”, each of the zeroth comparison circuit CMP0 to the twenty-third comparison circuit CMP23 outputs “1”; otherwise (i.e., when at least one bit of the received comparison signal is “0”), it outputs “0”. For example, the zeroth comparator circuit CMP0 receives the zeroth comparator signal CS0; when all bits S0B, S1B, S2B, S3B, S4, S5B, S6B, S7B, S8, S9, S10B, S11B, S12B, S13B, S14B, and S15B of the zeroth comparator signal CS0 are "1", the zeroth comparator circuit CMP0 outputs "1", otherwise (that is, when at least one bit of the zeroth comparator signal CS0, S0B, S1B, S2B, S3B, S4, S5B, S6B, S7B, S8, S9, S10B, S11B, S12B, S13B, S14B, and S15B is "0"), it outputs "0". The twelfth comparator circuit CMP12 receives the twelfth comparator signal CS12. When all bits S0B, S1B, S2B, S3B, S4, S5B, S6B, S7B, S8B, S9B, S10, S11, S12B, S13B, S14B, and S15B of the twelfth comparator signal CS12 are "1", the twelfth comparator circuit CMP12 outputs "1"; otherwise (i.e., when at least one bit of the bits S0B, S1B, S2B, S3B, S4, S5B, S6B, S7B, S8B, S9B, S10, S11, S12B, S13B, S14B, and S15B of the twelfth comparator signal CS12 is "0"), the twelfth comparator circuit CMP12 outputs "0".

[0109] At the same time, such as Figure 12A As shown, each of the zeroth comparator circuit CMP0 to the twenty-third comparator circuit CMP23 can be implemented by a level 1 NAND arithmetic circuit (e.g., consisting of 8 NAND gates), a level 1 NOR arithmetic circuit (e.g., consisting of 4 NOR gates), a level 1 NAND arithmetic circuit (e.g., consisting of 2 NAND gates), and a level 1 NOR arithmetic circuit (e.g., consisting of 1 NOR gate).

[0110] The zeroth comparison circuit CMP0 may include: a first decoding arithmetic circuit DC1 that performs comparison operations corresponding to bits S0B, S1B, S2B, and S3B of the zeroth comparison signal CS0; a second decoding arithmetic circuit DC2 that performs comparison operations corresponding to bits S4, S5B, S6B, and S7B of the zeroth comparison signal CS0; a third decoding arithmetic circuit DC3 that performs comparison operations corresponding to bits S8, S9, S10B, and S11B of the zeroth comparison signal CS0; and a fourth decoding arithmetic circuit DC4 that performs comparison operations corresponding to bits S12B, S13B, S14B, and S15B of the zeroth comparison signal CS0.

[0111] like Figure 12B As shown, the first column C1 and the thirteenth column C13 of the zeroth submatrix SM00 can be the same except for the elements in rows 9 through 12. Correspondingly, the zeroth comparison signal CS0 and the twelfth comparison signal CS12 can be the same except for the bits corresponding to rows 9 through 12. That is, the twelfth comparison circuit CMP12 can include a first decoding arithmetic circuit DC1, a second decoding arithmetic circuit DC2, and a fourth decoding arithmetic circuit DC4 that perform comparison operations on the bits S0B, S1B, S2B, S3B, S4, S5B, S6B, S7B, S8B, S13B, S14B, and S15B of the twelfth comparison signal CS12. Furthermore, the twelfth comparison circuit CMP12 can include a fifth decoding arithmetic circuit DC5 that performs comparison operations on the bits S8B, S9B, S10, and S11 of the twelfth comparison signal CS12.

[0112] Therefore, the first comparator circuit CMP0 and the twelfth comparator circuit CMP12 may include multiple identical decoding arithmetic circuits DC1, DC2, and DC4 for performing the same operations. Similarly, the second comparator circuits CMP2 through eleventh comparator circuits CMP11 and thirteenth comparator circuits CMP13 through twenty-third comparator circuits CMP23 may include multiple identical decoding arithmetic circuits for performing the same operations based on the elements of each column of the zeroth submatrix SM00. Therefore, the area of ​​the zeroth ECC decoding circuit EDC0 may become excessively large.

[0113] Figure 13 It shows Figure 5 The zeroth submatrix. (Refer to...) Figure 13 The zeroth submatrix SM00 may include a first submatrix B1 and a second submatrix B2. The first submatrix B1 is the submatrix corresponding to the first to eleventh columns of the zeroth submatrix SM00, and the second submatrix B2 is the submatrix corresponding to the twelfth to twenty-third columns of the zeroth submatrix SM00.

[0114] Simultaneously, the zeroth submatrix SM00 may include common regions R1 to R5. The first common region R1 may correspond to the first comparison operation used for ECC decoding, the second common region R2 may correspond to the second comparison operation used for ECC decoding, the third common region R3 may correspond to the third comparison operation used for ECC decoding, the fourth common region R4 may correspond to the fourth comparison operation used for ECC decoding, and the fifth common region R5 may correspond to the fifth comparison operation used for ECC decoding. For example... Figure 13 As shown, except for the fourth common region R4 and the fifth common region R5, the first submatrix B1 can be the same as the second submatrix B2.

[0115] In an embodiment, the first comparison operation may be a decoding arithmetic circuit that receives bits S0B, S1B, S2B, and S3B of the checksum comparison signal SCS as input (e.g., Figure 12A The first decoding arithmetic circuit (DC1) performs the operation. The second comparison operation can be performed by a decoding arithmetic circuit (e.g., a level 1 NAND arithmetic circuit and a level 1 NOR arithmetic circuit, such as receiving bits S4B, S5B, S6B, and S7B of the parity comparison signal SCS as input) that takes these bits as input. Figure 12A The third comparison operation can be performed by the decoding arithmetic circuits (DC1 to DC5) that receive the bits S12B, S13B, S14B, and S15B of the parity comparison signal SCS as inputs (e.g., the decoding arithmetic circuits). Figure 12A The fourth decoding arithmetic circuit (DC4) performs the operation. The fourth comparison operation can be performed by a decoding arithmetic circuit that receives bits S8, S9, S10B, and S11B of the parity comparison signal SCS as input (e.g., Figure 12A The third decoding arithmetic circuit (DC3) performs the operation. The fifth comparison operation can be performed by the decoding arithmetic circuit (e.g., receiving bits S8B, S9B, S10, and S11 of the parity comparison signal SCS as input). Figure 12A The fifth decoding arithmetic circuit (DC5) performs the operation.

[0116] According to embodiments of this disclosure, each of the ECC decoding circuits EDC0 to EDC11 can be configured to perform operations on a common area of ​​a related submatrix using an arithmetic circuit. An arithmetic circuit may be referred to herein as a common arithmetic circuit or a shared arithmetic circuit. Therefore, multiple identical decoding arithmetic circuits can be omitted from the ECC decoding circuits EDC0 to EDC11. Consequently, the size and area occupied by the ECC decoding circuits EDC0 to EDC11 can be reduced. The ECC decoding circuits according to this disclosure will be described in detail below with reference to the accompanying drawings.

[0117] Figure 14 According to the embodiments Figure 11Block diagram of the zeroth ECC decoding circuit. (Refer to...) Figure 11 , Figure 13 and Figure 14 The zeroth ECC decoding circuit EDC0 may include a common arithmetic circuit 114b_1, a first checksum comparison circuit 114b_2, and a second checksum comparison circuit 114b_3. The common arithmetic circuit 114b_1 can generate a common arithmetic signal CAS based on the first comparison signal CS1. The common arithmetic circuit 114b_1 can be configured to perform AND operations with... Figure 13 The first to fifth comparison operations corresponding to the public areas R1 to R5.

[0118] In this embodiment, the first to fifth comparison operations can be referred to as "common operations".

[0119] The first checker circuit 114b_2 can be configured to output the zeroth bit VEC0[0] to the fifth bit VEC0[5] and the twelfth bit VEC0

[12] to the seventeenth bit VEC0

[17] of the zero vector VEC0 based on the common arithmetic signal CAS and the second comparison signal CS2. The first checker circuit 114b_2 may include the zero comparison circuit CMP0 to the fifth comparison circuit CMP5.

[0120] The zeroth comparator circuit CMP0 can be configured to compare the check SYD with the first and thirteenth columns of the zeroth submatrix SM00 to output the zeroth bit VEC0[0] and the twelfth bit VEC0

[12] of the zeroth vector VEC0. The first comparator circuit CMP1 can be configured to compare the check SYD with the second and fourteenth columns of the zeroth submatrix SM00 to output the first bit VEC0[1] and the thirteenth bit VEC0

[13] of the zeroth vector VEC0. The fifth comparator circuit CMP5 can be configured to compare the check SYD with the sixth and eighteenth columns of the zeroth submatrix SM00 to output the fifth bit VEC0[5] and the seventeenth bit VEC0

[17] of the zeroth vector VEC0.

[0121] The second check sub-comparison circuit 114b_3 can be configured to output the sixth bit VEC0[6] to the eleventh bit VEC0

[11] and the eighteenth bit VEC0

[18] to the twenty-third bit VEC0

[23] of the zero vector VEC0 based on the common arithmetic signal CAS and the third comparison signal CS3. The second check sub-comparison circuit 114b_3 may include the sixth comparison circuit CMP6 to the eleventh comparison circuit CMP11.

[0122] The sixth comparator circuit CMP6 can be configured to compare the check SYD with the seventh and nineteenth columns of the zero submatrix SM00 to output the sixth bit VEC0[6] and the eighteenth bit VEC0

[18] of the zero vector VEC0. The seventh comparator circuit CMP7 can be configured to compare the check SYD with the eighth and twentieth columns of the zero submatrix SM00 to output the seventh bit VEC0[7] and the nineteenth bit VEC0

[19] of the zero vector VEC0. The eleventh comparator circuit CMP11 can be configured to compare the check SYD with the twelfth and twenty-fourth columns of the zero submatrix SM00 to output the eleventh bit VEC0

[11] and the twenty-third bit VEC0

[23] of the zero vector VEC0.

[0123] In an embodiment, Figure 11 The checker comparison signal SCS may include the first comparison signal CS1 to the third comparison signal CS3.

[0124] The first checksum comparison circuit 114b_2 and the second checksum comparison circuit 114b_3 can be configured to generate the zeroth vector VEC0 by using the common arithmetic signal CAS corresponding to the first common region R1 to the fifth common region R5 of the zeroth sub-matrix SM00. That is, the first checksum comparison circuit 114b_2 and the second checksum comparison circuit 114b_3 can be configured to share the common arithmetic circuit 114b_1. Therefore, the decoding arithmetic circuits corresponding to the first common region R1 to the third common region R5 can be omitted from the first checksum comparison circuit 114b_2 and the second checksum comparison circuit 114b_3. Therefore, Figure 14 The area of ​​the zeroth ECC decoding circuit EDC0 is smaller than Figure 12A The area of ​​the zeroth ECC decoding circuit EDC0.

[0125] Figures 15A to 15C It is used to describe based on the example. Figure 14 A diagram of the common arithmetic circuit. (Refer to...) Figure 13 , Figure 14 and Figure 15A The common arithmetic circuit 114b_1 may include a first arithmetic circuit 114b_1a and a second arithmetic circuit 114b_1b. The first arithmetic circuit 114b_1a may be configured to output a first comparison operation signal AS1 to a third comparison arithmetic signal AS3 by performing comparison operations for ECC decoding based on a first common comparison signal CCS1. In an embodiment, the first arithmetic circuit 114b_1a may be configured to perform a first comparison operation to a third comparison operation corresponding to a first common region R1 to a third common region R3.

[0126] Reference Figure 15BThe first arithmetic circuit 114b_1a may include a first common decoding arithmetic circuit CDC1, a second common decoding arithmetic circuit CDC2, a third common decoding arithmetic circuit CDC3, and a first NAND gate N1 to a third NAND gate N3. Each of the first common decoding arithmetic circuit CDC1, the second common decoding arithmetic circuit CDC2, and the third common decoding arithmetic circuit CDC3 is implemented by a level 1 NAND arithmetic circuit and a level 1 NOR arithmetic circuit.

[0127] The first common decoding arithmetic circuit CDC1 can be configured to receive bits S0B, S1B, S2B, and S3B of the checksum comparison signal SCS corresponding to the first common region R1, and perform a first comparison operation. The first common decoding arithmetic circuit CDC1 can output a first output signal OS1 indicating the result of the first comparison operation.

[0128] The second common decoding arithmetic circuit CDC2 can be configured to receive bits S4B, S5B, S6B, and S7B of the parity comparison signal SCS corresponding to the second common region R2, and perform a second comparison operation. The second common decoding arithmetic circuit CDC2 can output a second output signal OS2 indicating the result of the second comparison operation.

[0129] The third common decoding arithmetic circuit CDC3 can be configured to receive bits S12B, S13B, S14B, and S15B of the parity comparison signal SCS corresponding to the third common region R3, and perform the third comparison operation. The third common decoding arithmetic circuit CDC3 can output a third output signal OS3 indicating the result of the third comparison operation.

[0130] The first NAND gate N1 can receive the first output signal OS1 and the second output signal OS2 as inputs, and can output the first comparison arithmetic signal AS1. The first comparison arithmetic signal AS1 can indicate the result of comparing the bits S0 to S7 of the parity subscript SYD with the first common area R1 and the second common area R2.

[0131] The second NAND gate N2 can receive the second output signal OS2 and the third output signal OS3 as inputs, and can output the second comparison arithmetic signal AS2. The second comparison arithmetic signal AS2 can indicate the result of comparing the bits S4 to S7 and S12 to S15 of the parity check SYD with the second common area R2 and the third common area R3.

[0132] The third NAND gate N3 can receive the first output signal OS1 and the third output signal OS3 as inputs, and can output the third comparison arithmetic signal AS3. The third comparison arithmetic signal AS3 can indicate the result of comparing the bits S0 to S3 and S12 to S15 of the parity check SYD with the first common area R1 and the third common area R3.

[0133] In an embodiment, the first common comparison signal CCS1 can be formed by bits S0B, S1B, S2B, S3B, S4B, S5B, S6B, S7B, S12B, S13B, S14B, and S15B of the checksum SYD used for the first to third comparison operations.

[0134] return Figure 15A The second arithmetic circuit 114b_1b can be configured to output a fourth comparison arithmetic signal AS4 and a fifth comparison arithmetic signal AS5 by performing comparison operations for ECC decoding based on the second common comparison signal CCS2. In an embodiment, the second arithmetic circuit 114b_1b can be configured to perform the fourth comparison operation and the fifth comparison operation corresponding to the fourth common region R4 and the fifth common region R5.

[0135] Reference Figure 15C The second arithmetic circuit 114b_1b may include a fourth common decoding arithmetic circuit CDC4 and a fifth common decoding arithmetic circuit CDC5.

[0136] The fourth common decoding arithmetic circuit CDC4 can be configured to receive bits S8, S9, S10B, and S11B of the checksum comparison signal SCS corresponding to the fourth common region R4, and perform the fourth comparison operation. The fourth common decoding arithmetic circuit CDC4 can output a fourth comparison arithmetic signal AS4 indicating the result of the fourth comparison operation.

[0137] In an embodiment, the fourth comparison arithmetic signal AS4 can indicate the result of comparing bits S8 to S11 of the check SYD with the fourth common area R4.

[0138] The fifth common decoding arithmetic circuit CDC5 can be configured to receive bits S8B, S9B, S10, and S11 of the checksum comparison signal SCS corresponding to the fifth common region R5, and perform the fifth comparison operation. The fifth common decoding arithmetic circuit CDC5 can output a fifth comparison arithmetic signal AS5 indicating the result of the fifth comparison operation.

[0139] In an embodiment, the fifth comparison arithmetic signal AS5 can indicate the result of comparing bits S8 to S11 of the check SYD with the fifth common area R5.

[0140] In an embodiment, the second common comparison signal CCS2 can be formed by bits S8, S9, S8B, S9B, S10, S11, S10B and S11B of the checksum SYD used for the fourth comparison operation and the fifth comparison operation.

[0141] In an embodiment, Figure 14 The first comparison signal CS1 may include a first common comparison signal CCS1 and a second common comparison signal CCS2.

[0142] In an embodiment, Figure 14 The common arithmetic signal CAS may include the first comparison arithmetic signal AS1 to the fifth comparison arithmetic signal AS5.

[0143] As described above, the common arithmetic circuit 114b_1 can be configured to perform an operation that compares the check SYD with the common regions (e.g., R1 to R5) of the correlated submatrices (e.g., SM00) of the H matrix H-mat.

[0144] Figure 16A It is used to describe Figure 14 The diagram of the first checker circuit, and Figure 16B It is used to describe Figure 14 The diagram shows the second checker circuit. (Refer to...) Figures 14 to 16A The first checker circuit 114b_2 may include zero-level comparator circuits CMP0 through fourth-level comparator circuits CMP4. For ease of description and brevity of the accompanying drawings, Figure 16A Only the zeroth comparator circuit CMP0 and the fourth comparator circuit CMP4 are shown, but the first comparator circuit CMP1, the second comparator circuit CMP2, the third comparator circuit CMP3, and the fifth comparator circuit CMP5 can be implemented in a similar manner to the zeroth comparator circuit CMP0 and the fourth comparator circuit CMP4.

[0145] The zeroth comparison circuit CMP0 can be configured to compare the parity SYD with the first and thirteenth columns of the zeroth submatrix SM00 to output the zeroth bit VEC0[0] and the twelfth bit VEC0

[12] of the zeroth vector VEC0. The zeroth comparison circuit CMP0 may include a first decoding circuit DC1 to a third decoding circuit DC3, each of which is implemented by a level 1 NAND arithmetic circuit and a level 1 NOR arithmetic circuit.

[0146] The elements in rows 5 through 8 of the first column of the zeroth submatrix SM00 (e.g., "1000") are the same as the elements in rows 5 through 8 of the thirteenth column (see reference). Figure 13The first decoding arithmetic circuit DC1 can be configured to perform a comparison operation between the elements (e.g., "1000") of rows 5 through 8 of the first column and rows 5 through 8 of the thirteenth column and bits S4 through S7 of the checksum SYD. The first decoding arithmetic circuit DC1 can receive bits S4, S5B, S6B, and S7B of the checksum comparison signal SCS as input. The output signal of the first decoding arithmetic circuit DC1 can indicate the result of comparing the elements (e.g., "1000") of rows 5 through 8 of the first column and rows 5 through 8 of the thirteenth column with bits S4 through S7 of the checksum SYD.

[0147] The second decoding arithmetic circuit DC2 can receive the output signal of the first decoding arithmetic circuit DC1, the third comparison arithmetic signal AS3, and the fourth comparison arithmetic signal AS4 as inputs, and can output the zeroth bit VEC0[0] of the zeroth vector VEC0. That is, the NAND gate of the second decoding arithmetic circuit DC2 can be connected to the output terminal of the first decoding arithmetic circuit DC1 and the output terminal of the fourth common decoding arithmetic circuit CDC4 (see reference). Figure 15C Furthermore, the NOR gate of the second decoding arithmetic circuit DC2 can be connected to the output terminal of the third NAND gate N3 (see reference). Figure 15B ).

[0148] The first to fourth rows of the first column of the zeroth submatrix SM00 can be included in the first common region R1, and the thirteenth to sixteenth rows are included in the third common region R3. The ninth to twelfth rows of the first column of the zeroth submatrix SM00 are included in the fourth common region R4 (see reference). Figure 13 As described above, the third comparison arithmetic signal AS3 corresponds to the first common region R1 and the third common region R3. Furthermore, the fourth comparison arithmetic signal AS4 corresponds to the fourth common region R4.

[0149] Correspondingly, the third comparison arithmetic signal AS3 can indicate the result of comparing bits S0 to S3 and S12 to S15 of the check SYD with rows 1 to 4 and rows 13 to 16 of the first column of the zeroth sub-matrix SM00. Furthermore, the fourth comparison arithmetic signal AS4 can indicate the result of comparing bits S8 to S11 of the check SYD with rows 9 to 12 of the first column of the zeroth sub-matrix SM00. Therefore, the zeroth bit VEC0[0] of the zeroth vector VEC0 can indicate the result of comparing the first column of the zeroth sub-matrix SM00 with the check SYD.

[0150] The third decoding arithmetic circuit DC3 can receive the output signal of the first decoding arithmetic circuit DC1, the third comparison arithmetic signal AS3 and the fifth comparison arithmetic signal AS5 as inputs, and can output the twelfth bit VEC0 of the zero vector VEC0

[12] . That is, the NAND gate of the third decoding arithmetic circuit DC3 can be connected to the output terminal of the first decoding arithmetic circuit DC1 and the output terminal of the fifth common decoding arithmetic circuit CDC5 (see reference). Figure 15C Furthermore, the NOR gate of the third decoding arithmetic circuit DC3 can be connected to the output terminal of the third NAND gate N3 (see reference). Figure 15B ).

[0151] The first to fourth rows of the thirteenth column of the zeroth submatrix SM00 can be included in the first common region R1, and the thirteenth to sixteenth rows are included in the third common region R3. The ninth to twelfth rows of the thirteenth column of the zeroth submatrix SM00 can be included in the fifth common region R5 (see reference). Figure 13 ).

[0152] Correspondingly, the third comparison arithmetic signal AS3 can indicate the result of comparing bits S0 to S3 and S12 to S15 of the check SYD with rows 1 to 4 and rows 13 to 16 of the 13th column of the zero sub-matrix SM00. In addition, the fifth comparison arithmetic signal AS5 can indicate the result of comparing bits S8 to S11 of the check SYD with rows 9 to 12 of the 13th column of the zero sub-matrix SM00. Therefore, the 12th bit VEC0

[12] of the zero vector VEC0 can indicate the result of comparing the 13th column of the zero sub-matrix SM00 with the check SYD.

[0153] The fourth comparison circuit CMP4 can be configured to compare the parity SYD with the fifth and seventeenth columns of the zero submatrix SM00 to output the fourth bit VEC0[4] and the sixteenth bit VEC0

[16] of the zero vector VEC0. The fourth comparison circuit CMP4 may include the fourth decoding circuit DC4 to the sixth decoding circuit DC6, each of which is implemented by a level 1 NAND arithmetic circuit and a level 1 NOR arithmetic circuit.

[0154] The elements in rows 13 to 16 of the fifth column of the zeroth submatrix SM00 (e.g., "1000") are the same as the elements in rows 13 to 16 of the seventeenth column of the zeroth submatrix SM00 (see reference). Figure 13The fourth decoding arithmetic circuit DC4 can be configured to perform a comparison operation between the elements (e.g., "1000") in rows 13 through 16 of the fifth column and rows 13 through 16 of the seventeenth column, and bits S12 through S15 of the checksum SYD. The fourth decoding arithmetic circuit DC4 can receive bits S12, S13B, S14B, and S15B of the checksum comparison signal SCS as input. The output signal of the fourth decoding arithmetic circuit DC4 can indicate the result of comparing the elements (e.g., "1000") in rows 13 through 16 of the fifth column and rows 13 through 16 of the seventeenth column with bits S12 through S15 of the checksum SYD.

[0155] The first to fourth rows of the fifth and seventeenth columns of the zeroth submatrix SM00 can be included in the first common area R1, and the fifth to eighth rows are included in the second common area R2. The ninth to twelfth rows of the fifth column of the zeroth submatrix SM00 are included in the fourth common area R4. The ninth to twelfth rows of the seventeenth column of the zeroth submatrix SM00 are included in the fifth common area R5 (see reference). Figure 13 ).

[0156] Correspondingly, the fifth decoding arithmetic circuit DC5 can receive the output signal of the fourth decoding arithmetic circuit DC4, the first comparison arithmetic signal AS1 and the fourth comparison arithmetic signal AS4 as inputs, and can output the fourth bit VEC0 of the zero vector VEC0[4]. That is, the NAND gate of the fifth decoding arithmetic circuit DC5 can be connected to the output terminal of the fourth decoding arithmetic circuit DC4 and the output terminal of the fourth common decoding arithmetic circuit CDC4 (see reference). Figure 15C Furthermore, the NOR gate of the fifth decoding arithmetic circuit DC5 can be connected to the output terminal of the first NAND gate N1 (see reference). Figure 15B ).

[0157] As described above, the first comparison arithmetic signal AS1 corresponds to the first common region R1 and the second common region R2, and the fourth comparison arithmetic signal AS4 corresponds to the fourth common region R4. Therefore, the fourth bit VEC0[4] of the zero vector VEC0 can indicate the comparison result of the fifth column of the zero submatrix SM00 with the check SYD.

[0158] Furthermore, the sixth decoding arithmetic circuit DC6 can receive the output signal of the fourth decoding arithmetic circuit DC4, the first comparison arithmetic signal AS1, and the fifth comparison arithmetic signal AS5 as inputs, and can output the sixteenth bit VEC0 of the zero vector VEC0

[16] . That is, the NAND gate of the sixth decoding arithmetic circuit DC6 can be connected to the output terminal of the fourth decoding arithmetic circuit DC4 and the output terminal of the fifth common decoding arithmetic circuit CDC5 (see reference). Figure 15CFurthermore, the NOR gate of the sixth decoding arithmetic circuit DC6 can be connected to the output terminal of the first NAND gate N1 (see reference). Figure 15B ).

[0159] As described above, the first comparison arithmetic signal AS1 corresponds to the first common region R1 and the second common region R2, and the fifth comparison arithmetic signal AS5 corresponds to the fifth common region R5. Therefore, the sixteenth bit VEC0

[16] of the zero vector VEC0 can indicate the comparison result of the seventeenth column of the zero submatrix SM00 with the check SYD.

[0160] In an embodiment, the bits (e.g., S4, S5B, S6B, S7B, S12, S13B, S14B, and S15B) input to the checksum comparison signal SCS into the comparison circuits CMP0 to CMP4 may include... Figure 14 In the second comparison signal CS2.

[0161] Reference Figures 14 to 16B The second comparator circuit 114b_3 may include the sixth comparator circuit CMP6 through the eleventh comparator circuit CMP11. For ease of description and concise drawing, Figure 16B Only the sixth comparator circuit CMP6 and the eleventh comparator circuit CMP11 are shown, but the seventh comparator circuit CMP7, the eighth comparator circuit CMP8, the ninth comparator circuit CMP9, and the tenth comparator circuit CMP10 can be implemented in a similar manner to the sixth comparator circuit CMP6 and the eleventh comparator circuit CMP11.

[0162] The sixth comparator circuit CMP6 can be configured to compare the parity SYD with the seventh and nineteenth columns of the zero submatrix SM00 to output the sixth bit VEC0[6] and the eighteenth bit VEC0

[18] of the zero vector VEC0. The sixth comparator circuit CMP6 may include the seventh decoding circuit DC7 to the ninth decoding circuit DC9, each of which is implemented by a level 1 NAND arithmetic circuit and a level 1 NOR arithmetic circuit.

[0163] The elements in rows 13 through 16 of column 7 of submatrix SM00 (e.g., "0010") are identical to the elements in rows 13 through 16 of column 19 of submatrix SM00. Rows 1 through 4 of column 7 and row 1 through 4 of column 19 of submatrix SM00 can be included in the first common area R1, and rows 5 through 8 can be included in the second common area R2. Furthermore, rows 9 through 12 of column 7 of submatrix SM00 can be included in the fourth common area R4, and rows 9 through 12 of column 19 can be included in the fifth common area R5 (see reference). Figure 15C ).

[0164] Therefore, the seventh decoding arithmetic circuit DC7 can be configured to receive bits S12B, S13B, S14, and S15B of the parity comparison signal SCS corresponding to rows 13 to 16.

[0165] The eighth decoding arithmetic circuit DC8 can receive the output signal of the seventh decoding arithmetic circuit DC7, the first comparison arithmetic signal AS1 corresponding to the first common region R1 and the second common region R2, and the fourth comparison arithmetic signal AS4 corresponding to the fourth common region R4. The eighth decoding arithmetic circuit DC8 can output the sixth bit VEC0, which indicates the comparison result of the seventh column of the zero sub-matrix SM00 with the check SYD [6]. The NAND gate of the eighth decoding arithmetic circuit DC8 can be connected to the output terminal of the seventh decoding arithmetic circuit DC7 and the output terminal of the fourth common decoding arithmetic circuit CDC4 (see reference). Figure 15C Furthermore, the NOR gate of the eighth decoding arithmetic circuit DC8 can be connected to the output terminal of the first NAND gate N1 (see reference). Figure 15B ).

[0166] The ninth decoding arithmetic circuit DC9 can receive the output signal of the seventh decoding arithmetic circuit DC7, the first comparison arithmetic signal AS1 corresponding to the first common region R1 and the second common region R2, and the fifth comparison arithmetic signal AS5 corresponding to the fifth common region R5. The ninth decoding arithmetic circuit DC9 can output the eighteenth bit VEC0, which indicates the comparison result of the nineteenth column of the zero sub-matrix SM00 with the check SYD

[18] . The NAND gate of the ninth decoding arithmetic circuit DC9 can be connected to the output terminal of the seventh decoding arithmetic circuit DC7 and the output terminal of the fifth common decoding arithmetic circuit CDC5 (see reference). Figure 15C Furthermore, the NOR gate of the ninth decoding arithmetic circuit DC9 can be connected to the output terminal of the first NAND gate N1 (see reference). Figure 15B ).

[0167] The eleventh comparator circuit CMP11 can be configured to compare the parity SYD with the twelfth and twenty-fourth columns of the zero submatrix SM00 to output the eleventh bit VEC0

[11] and the twenty-third bit VEC0

[23] of the zero vector VEC0. The eleventh comparator circuit CMP11 may include tenth decoding circuits DC10 to twelfth decoding circuits DC12, each of which is implemented by a level 1 NAND arithmetic circuit and a level 1 NOR arithmetic circuit.

[0168] Simultaneously, the elements of the first to fourth rows of the twelfth column of the zeroth sub-matrix SM00 (e.g., "0001") are identical to the elements of the first to fourth rows of the twenty-fourth column of the zeroth sub-matrix SM00. The fifth to eighth rows of the twelfth column and the fifth to eighth rows of the twenty-fourth column of the zeroth sub-matrix SM00 can be included in the second common area R2, and the thirteenth to sixteenth rows can be included in the third common area R3. Furthermore, the ninth to twelfth rows of the twelfth column of the zeroth sub-matrix SM00 can be included in the fourth common area R4, and the ninth to twelfth rows of the twenty-fourth column are included in the fifth common area R5 (see reference). Figure 13 ).

[0169] Therefore, the tenth decoding arithmetic circuit DC10 can be configured to receive bits S1B, S2B, S3B, and S4 of the parity comparison signal SCS corresponding to the first to fourth rows of each column in the twelfth and twenty-fourth columns of the zeroth sub-matrix SM00. The tenth decoding arithmetic circuit DC10 can perform a comparison operation on the zeroth bit S0 to the third bit S3 of the parity SYD with the first to fourth rows of each column in the twelfth and twenty-fourth columns of the zeroth sub-matrix SM00.

[0170] The eleventh decoding arithmetic circuit DC11 can receive the output signal of the tenth decoding arithmetic circuit DC10, the second comparison arithmetic signal AS2 corresponding to the second common region R2 and the third common region R3, and the fourth comparison arithmetic signal AS4 corresponding to the fourth common region R4. The eleventh decoding arithmetic circuit DC11 can be configured to output the eleventh bit VEC0, which indicates the comparison result of the twelfth column of the zero sub-matrix SM00 with the check SYD

[11] . The NAND gate of the eleventh decoding arithmetic circuit DC11 can be connected to the output terminal of the tenth decoding arithmetic circuit DC10 and the output terminal of the fourth common decoding arithmetic circuit CDC4 (see reference). Figure 15C Furthermore, the NOR gate of the eleventh decoding arithmetic circuit DC11 can be connected to the output terminal of the second NAND gate N2 (see reference). Figure 15B ).

[0171] The twelfth decoding arithmetic circuit DC12 can receive the output signal of the tenth decoding arithmetic circuit DC10, the second comparison arithmetic signal AS2 corresponding to the second common region R2 and the third common region R3, and the fifth comparison arithmetic signal AS5 corresponding to the fifth common region R5. The twelfth decoding arithmetic circuit DC12 can output the twenty-third bit VEC0, which indicates the comparison result of the nineteenth column of the zero sub-matrix SM00 with the check SYD

[23] . The NAND gate of the twelfth decoding arithmetic circuit DC12 can be connected to the output terminal of the tenth decoding arithmetic circuit DC10 and the output terminal of the fifth common decoding arithmetic circuit CDC5 (see reference). Figure 15C Furthermore, the NOR gate of the twelfth decoding arithmetic circuit DC12 can be connected to the output terminal of the second NAND gate N2 (see reference). Figure 15B ).

[0172] In an embodiment, the bits (e.g., S1B, S2B, S3B, S4, S12B, S13B, S14, and S15B) input to the checksum comparison signal SCS to the comparison circuits CMP6 to CMP11 may include... Figure 14 In the third comparison signal CS3.

[0173] As described above, the comparator circuits CMP0 to CMP11 can be configured to "share the common arithmetic circuit 114b_1" by performing operations based on the shared output signal CAS of the common arithmetic circuit 114b_1. Specifically, the comparator circuits CMP0 to CMP11 can be connected to at least some output terminals of the common arithmetic circuit 114b_1 (e.g., the output terminals of the first NAND gates N1 to the third NAND gates N3, the output terminals of the fourth common decoding arithmetic circuit CDC4, and the output terminals of the fifth common decoding arithmetic circuit CDC5). The comparator circuits CMP0 to CMP11 can compare the parity check SYD with each column of the submatrix SM00 of the H matrix H-mat by using the common arithmetic signal CAS output from the common arithmetic circuit 114b_1. Therefore, with Figure 12A Unlike other examples, the comparator circuits CMP0 through CMP6 can omit the repeated identical decoding circuitry (e.g., Figure 12A (DC1, DC2, and DC4). Therefore, the area of ​​the ECC decoding circuits EDC0 to EDC11 can be reduced.

[0174] For reference only Figures 14 to 16B Described Figure 11 The zeroth ECC decoding circuit EDC0, but Figure 11The first ECC decoding circuit EDC1 to the eleventh ECC decoding circuit EDC11 can also be implemented in a manner similar to the zeroth ECC decoding circuit EDC0. That is, each of the first ECC decoding circuits EDC1 to the eleventh ECC decoding circuit EDC11 may include a common arithmetic circuit that performs operations on the common region of the corresponding submatrices SM00 to SM11 of the H matrix H-mat and PR.

[0175] Figure 17 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure. (Refer to...) Figure 17 The memory system 1000 may include a memory controller 1100 and a memory device 1200.

[0176] The storage device 1200 can operate under the control of the memory controller 1100. The storage device 1200 may include an ECC circuit 1210. The ECC circuit 1210 can be configured to detect and correct errors in the data present in the storage device 1200. The ECC circuit 1210 can generate parity check data based on the read data present in the storage device 1200. The ECC circuit 1210 can generate a parity checksum based on the parity checksum and the read parity checksum corresponding to the read data, and generate an error vector by comparing the H matrix H-mat with the parity checksum. The ECC circuit 1210 can correct errors in the read data and the read parity checksum based on the read data, the read parity checksum, and the error vector.

[0177] In an embodiment, the ECC circuit 1210 can be implemented with reference to Figures 1 to 16B The described ECC circuit (e.g., Figure 3 The memory ECC circuit 1210 is identical to that of the memory ECC circuit 110. That is, the ECC circuit 1210 can be configured to generate parity check data by performing an XOR operation only on the valid elements of the H matrix H-mat. Furthermore, the ECC circuit 1210 may include a common arithmetic circuit that outputs a common arithmetic signal by performing operations corresponding to the common regions of the H matrix H-mat. The ECC circuit 1210 can be configured to generate an error vector based on the common arithmetic signal.

[0178] According to this disclosure, the ECC circuitry included in the memory device may include common (i.e., shared) arithmetic circuitry. This common arithmetic circuitry can perform operations on common regions among multiple regions of the H matrix and can output a common arithmetic signal. The ECC circuitry can perform ECC decoding based on the common arithmetic signal. Therefore, unnecessary arithmetic circuitry can be omitted from the ECC circuitry. Thus, the area occupied by the ECC circuitry in the memory device can be reduced. Therefore, an error correction code circuit with a smaller size compared to prior art ECC circuitry, a memory device including the error correction code circuitry, and a memory system including the memory device are provided.

[0179] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: The input / output circuitry is configured to receive first data and parity data from the memory controller. An error correction code (ECC) encoder is configured to generate parity check data based on the first data; A parity generator circuit is configured to generate a parity based on the parity check data and the parity data. An error vector generator is configured to perform ECC decoding based on the checksum and generate an error vector. The error correction circuit is configured to generate error-corrected data based on the error vector, the first data, and the parity data. as well as A storage cell array is configured to store the error-corrected data. The error vector generator includes: Arithmetic circuitry, configured to perform common operations associated with the ECC decoding based on the checksum and generate common arithmetic signals; and Multiple comparison circuits are configured to generate the error vector based on the checksum and the common arithmetic signal.

2. The storage device according to claim 1, wherein, The ECC encoder is also configured to generate the parity check data based on the parity check matrix, and The error vector generator is further configured to generate the error vector based on the parity check matrix.

3. The storage device according to claim 2, wherein, The ECC encoder includes: Multiple encoding circuits are configured to generate multiple check data based on the first data; and The XOR circuit is configured to generate the parity check data based on the plurality of check data.

4. The storage device according to claim 3, wherein, The first encoding circuit among the plurality of encoding circuits is configured to perform ECC encoding corresponding to the first sub-matrix among the plurality of sub-matrixes included in the parity check matrix based on the first sub-data included in the first data, so that the first check data among the plurality of check data is output.

5. The storage device according to claim 4, wherein, The first encoding circuit includes: The XOR gate is configured to receive the first and second bits of the first sub-data and output the first check bit of the first check data.

6. The storage device according to claim 2, wherein, The arithmetic circuit includes: A first arithmetic circuit is configured to output a first comparison arithmetic signal, a second comparison arithmetic signal, and a third comparison arithmetic signal corresponding to a first common region, a second common region, and a third common region among a plurality of common regions included in the parity check matrix; and The second arithmetic circuit is configured to output a fourth comparison arithmetic signal and a fifth comparison arithmetic signal corresponding to the fourth and fifth common regions among the plurality of common regions, and The common arithmetic signal includes the first comparison arithmetic signal, the second comparison arithmetic signal, the third comparison arithmetic signal, the fourth comparison arithmetic signal, and the fifth comparison arithmetic signal.

7. The storage device according to claim 6, wherein, The first arithmetic circuit includes: A first common decoding arithmetic circuit is configured to perform a first comparison operation corresponding to the first common region to output a first output signal; The second common decoding arithmetic circuit is configured to perform a second comparison operation corresponding to the second common region to output a second output signal; and The third common decoding arithmetic circuit is configured to perform a third comparison operation corresponding to the third common region to output a third output signal.

8. The storage device according to claim 7, wherein, The first arithmetic circuit further includes: The first NAND gate is configured to output a first comparison arithmetic signal corresponding to the first common region and the second common region based on the first output signal and the second output signal; A second NAND gate is configured to output a second comparison arithmetic signal corresponding to the second common region and the third common region based on the second output signal and the third output signal; and The third NAND gate is configured to output a third comparison arithmetic signal corresponding to the first common region and the third common region based on the first output signal and the third output signal.

9. The storage device according to claim 8, wherein, The second arithmetic circuit includes: The fourth common decoding arithmetic circuit is configured to perform a fourth comparison operation corresponding to the fourth common region to output the fourth comparison arithmetic signal; and The fifth common decoding arithmetic circuit is configured to perform a fifth comparison operation corresponding to the fifth common region to output the fifth comparison arithmetic signal.

10. The storage device according to claim 8, wherein, The plurality of comparison circuits includes a first comparison circuit and a second comparison circuit. The first comparison circuit is configured as follows: The first error bit is output based on the checksum, the third comparison arithmetic signal, and the fourth comparison arithmetic signal; and The second error bit is output based on the checksum, the third comparison arithmetic signal, and the fifth comparison arithmetic signal, and The error vector includes the first error bit and the second error bit.

11. The storage device according to claim 2, wherein, The error vector generator generates the error vector by comparing the checksum with each column of the parity check matrix.

12. The storage device according to claim 1, further comprising: The command and address buffer is configured to receive and buffer command / address signals (CA) from the memory controller; The address decoder is configured to receive address signals from the command and the address buffer and to decode the address signals; The command decoder is configured to receive command signals from the command and address buffers and to decode the command signals. The row decoder is configured to control multiple word lines connected to the memory cell array based on the address decoding result of the address decoder; The column decoder is configured to control multiple bit lines connected to the memory cell array based on the address decoding result of the address decoder; as well as The write drive is configured to store the error-corrected data in the storage cell array under the control of the command decoder.

13. An error correction code (ECC) circuit, the ECC circuit being configured to generate error-corrected data based on first data and parity data received from a memory controller, the ECC circuit comprising: The ECC encoder is configured to generate parity check data based on the first data; as well as The ECC decoder is configured to perform ECC decoding based on the first data, the parity data, and the parity check data, and output the error-corrected data. The ECC decoder includes: A parity generator circuit is configured to generate a parity based on the parity check data and the parity data. An error vector generator is configured to decode the checksum to generate an error vector; and An error correction circuit is configured to generate the error-corrected data based on the error vector, the first data, and the parity data. The error vector generator includes: Arithmetic circuitry, configured to perform common operations associated with the ECC decoding based on the checksum and generate common arithmetic signals; and Multiple comparison circuits are configured to generate the error vector based on the checksum and the common arithmetic signal.

14. The ECC circuit according to claim 13, wherein, The ECC encoder is also configured to generate the parity check data based on the parity check matrix, and The error vector generator is further configured to generate the error vector based on the parity check matrix.

15. The ECC circuit according to claim 13, wherein, The ECC encoder includes: Multiple encoding circuits are configured to generate multiple check data based on the first data; and The XOR circuit is configured to generate the parity check data based on the plurality of check data.

16. The ECC circuit according to claim 15, wherein, The first encoding circuit among the plurality of encoding circuits is configured to: perform an encoding operation corresponding to the first sub-matrix among the plurality of sub-matrixes included in the parity check matrix based on the first sub-data included in the first data, such that the first check data among the plurality of check data is output, and the first encoding circuit includes an XOR gate, the XOR gate being configured to receive the first bit and the second bit among the bits of the first sub-data, and output the first check bit among the bits of the first check data.

17. The ECC circuit according to claim 14, wherein, The arithmetic circuit includes: A first arithmetic circuit is configured to output a first comparison arithmetic signal, a second comparison arithmetic signal, and a third comparison arithmetic signal corresponding to a first common region, a second common region, and a third common region among a plurality of common regions included in the parity check matrix; and The second arithmetic circuit is configured to output a fourth comparison arithmetic signal and a fifth comparison arithmetic signal corresponding to the fourth and fifth common regions among the plurality of common regions, and The common arithmetic signal includes the first comparison arithmetic signal, the second comparison arithmetic signal, the third comparison arithmetic signal, the fourth comparison arithmetic signal, and the fifth comparison arithmetic signal.

18. The ECC circuit according to claim 17, wherein, The first arithmetic circuit includes: A first common decoding arithmetic circuit is configured to perform a first comparison operation corresponding to the first common region to output a first output signal; The second common decoding arithmetic circuit is configured to perform a second comparison operation corresponding to the second common region to output a second output signal; and The third common decoding arithmetic circuit is configured to perform a third comparison operation corresponding to the third common region to output a third output signal.

19. The ECC circuit according to claim 18, wherein, The first arithmetic circuit further includes: The first NAND gate is configured to output a first comparison arithmetic signal corresponding to the first common region and the second common region based on the first output signal and the second output signal; A second NAND gate is configured to output a second comparison arithmetic signal corresponding to the second common region and the third common region based on the second output signal and the third output signal; and The third NAND gate is configured to output a third comparison arithmetic signal corresponding to the first common region and the third common region based on the first output signal and the third output signal.

20. A memory system, comprising: The memory controller is configured to output first data and parity data generated based on the first data; as well as A storage device includes an error correction code (ECC) circuit, the ECC circuit being configured to: receive first data and parity data, generate error-corrected data based on the first data and the parity data, and store the error-corrected data. The ECC circuit includes: The ECC encoder is configured to generate parity check data based on the first data; A checksum generator is configured to generate a checksum based on the parity check data and the parity data. An error vector generator is configured to generate an error vector by performing ECC decoding on the checksum; and An error correction circuit is configured to generate the error-corrected data based on the error vector, the first data, and the parity data. The error vector generator includes: Arithmetic circuitry, configured to perform common operations associated with the ECC decoding based on the checksum and generate common arithmetic signals; and Multiple comparison circuits are configured to generate the error vector based on the checksum and the common arithmetic signal.

Images