Bare chip packaging method

Abstract

The invention relates to the technical field of microelectronic packaging, in particular to a bare chip packaging method which comprises the following steps: S1, preparing a solid-state battery isolating membrane base material; s2, coating the surface of the solid-state battery isolating membrane base material with a polymer coating to form a coated base material; s3, the coated base material is subjected to heat treatment, so that the polymer coating is cured, and a cured coating is formed; s4, depositing a protective layer on the surface of the cured coating to form a deposited protective layer structure; s5, patterning the deposited protective layer structure to form a patterned protective layer with a preset pattern; s6, combining the patterned protection layer with the electrode layer, and forming a combined assembly through a hot pressing process; and S7, finally carrying out vacuum packaging on the combined assembly. According to the invention, by constructing the ceramic-based composite packaging structure, collaborative improvement of packaging airtightness, interface stability and environmental adaptability is realized, and the packaging reliability and the service life of the bare chip are significantly enhanced.

Description

Technical Field

[0001] This invention relates to the field of microelectronic packaging technology, and more particularly to a bare chip packaging method. Background Technology

[0002] In recent years, as microelectronic devices and solid-state battery chips have developed towards higher energy density, miniaturization and high integration, traditional packaging technologies have been unable to meet their requirements for multiple performance aspects such as high electrochemical stability, thermal management and moisture and oxidation prevention. Existing bare chip packaging usually uses organic resin or epoxy-based packaging materials. Although these materials have good processability and flexibility, they have high dielectric constant and low thermal conductivity, and are prone to structural aging and performance degradation in high temperature or high humidity environments.

[0003] Furthermore, traditional polymer packaging structures suffer from problems such as ion migration, interface contamination, and mechanical stress concentration in devices with highly sensitive interfaces, such as lithium-based solid-state batteries and MEMS sensor chips, leading to a decrease in the reliability of the packaged devices. Therefore, there is an urgent need for a bare-chip packaging method to solve these problems. Summary of the Invention

[0004] To achieve the above objectives, the present invention provides a bare chip packaging method.

[0005] The bare die packaging method includes the following steps: S1: Substrate for preparing solid-state battery separator film; S2: A polymer coating is applied to the surface of a solid-state battery separator substrate to form a coated substrate; S3: Heat-treat the coated substrate to cure the polymer coating and form a cured coating; S4: Deposit a protective layer on the surface of the cured coating to form a deposited protective layer structure; S5: Pattern the structure of the deposited protective layer to form a patterned protective layer with a preset pattern; S6: The patterned protective layer is combined with the electrode layer, and the combined component is formed by hot pressing. S7: Finally, vacuum encapsulate the assembled components.

[0006] Optionally, the solid-state battery separator substrate is a Garnet-type LLZO, NASICON-type LATP, or LAGP ceramic film with a thickness of 10-50 μm and a porosity of 20%-40%.

[0007] Optionally, S2 specifically includes: S21: To prepare a polymer slurry, a solid polymer, lithium salt and organic solvent are mixed in a mass ratio of 15:2:65 and stirred at 50-70℃ for 2-4 hours until a slurry with a viscosity of 500-2000 cP is formed. S22: The polymer slurry is coated onto the surface of the solid battery separator substrate using a slot extrusion coating method, and the wet film thickness is controlled to be 20-60μm. S23: Place the substrate coated with wet film in an inert atmosphere at 40-60℃ for 1-3 minutes to perform leveling and pre-curing to form a partially cured coating. S24: Apply a staged heating program to the substrate treated by S23. First, heat the substrate to 80-100°C at a rate of 2-5°C / minute and hold for 10-20 minutes to completely remove the organic solvent.

[0008] Optionally, S3 specifically includes: S31: Transfer the coated substrate to a programmable temperature controlled heating furnace and introduce an inert protective gas into the furnace chamber to reduce the oxygen content to 100 ppm; S32: Perform a staged heat treatment procedure. First, heat from room temperature to 80-100℃ at a heating rate of 1-3℃ / min and hold at this temperature for 10-30 minutes. Then, continue heating to 110-130℃ at a heating rate of 0.5-2℃ / min and hold at this final temperature for 20-40 minutes. S33: After completing the heat preservation in S32, turn off the heating source and allow the heating furnace to cool naturally to 40°C in the inert protective gas atmosphere. Then take out the obtained product, which is the substrate with a cured coating.

[0009] Optionally, S4 specifically includes: S41: Fix the substrate with the cured coating onto the base inside the reaction chamber of the plasma-enhanced chemical vapor deposition equipment, and set and maintain the base temperature at 80°C to 120°C; S42: Evacuate the reaction chamber to achieve a background vacuum of 0.1 Pa, then introduce inert carrier gas into the reaction chamber and stabilize the working pressure at 50 Pa to 200 Pa. S43: Alternately introduce a metal precursor and a reaction precursor into the reaction chamber, wherein the metal precursor is trimethylaluminum or zirconium tetrachloride, and the reaction precursor is deionized water or oxygen plasma. S44: Control the pulse time of the precursor to be between 0.1 seconds and 0.5 seconds, and the purging time to be between 5 seconds and 15 seconds, and perform 100 to 500 deposition cycles to form a uniform and dense protective layer with a thickness of 50 nm to 500 nm on the surface of the cured coating, thereby obtaining the deposited protective layer structure.

[0010] Optionally, S5 specifically includes: S51: Spin-coat photoresist onto the surface of the protective layer, and after soft baking at 90-110℃, perform ultraviolet exposure using a photomask with a grid pattern, with an exposure energy of 100-200mJ / cm². S52: Place the exposed substrate in a 2.0-2.5% tetramethyl sodium hydroxide solution for 40-70 seconds to develop and form a patterned photoresist mask; S53: Reactive ion etching is performed in a mixed gas atmosphere of CF4 and O2, using a photoresist mask as a barrier layer. S54: Use an acetone solution at 40-50℃ to remove residual photoresist to obtain a patterned protective layer with a grid pattern of 5-20μm linewidth.

[0011] Optionally, the CF4 flow rate is 30-50 sccm, the O2 flow rate is 5-10 sccm, and the etching time is 2-5 minutes.

[0012] Optionally, S6 specifically includes: S61: Align the substrate with the patterned protective layer and the electrode layer in a vacuum environment so that the raised area of ​​the patterned protective layer contacts the surface of the electrode layer. S62: Place the aligned laminated structure in a hot press and apply an initial pre-compression pressure of 5-15MPa for 30-60 seconds; S63: Execute a staged hot pressing program. First, heat the temperature to 80-100℃ at a rate of 3-5℃ / minute and hold it at this temperature for 1-3 minutes. Then, continue to heat the temperature to 120-150℃ while increasing the pressure to 15-25MPa and hold the temperature and pressure for 2-5 minutes. S64: After hot pressing is completed, the temperature is slowly cooled to 60°C at a rate of 1-2°C / minute while maintaining pressure. After releasing the pressure, the assembly is removed to obtain the combined component.

[0013] Optionally, S7 specifically includes: S71: Transfer the combined components to a glove box filled with an inert atmosphere, where the water and oxygen content are both below 0.1 ppm; S72: Place the assembled component inside the aluminum-plastic film encapsulation housing, and lead out the positive and negative electrode tabs from the corresponding reserved openings in the encapsulation housing, respectively; S73: Use vacuum sealing equipment to heat seal the three open edges of the aluminum-plastic film packaging shell, wherein the heat sealing temperature is 150-180℃, the heat sealing pressure is 0.5-1.0MPa, and the heat sealing time is 3-5 seconds; S74: During the heat sealing process, the inside of the encapsulation housing is evacuated to a vacuum level of 0.01-0.1 Pa before final sealing is completed, forming a complete solid-state battery separator assembly.

[0014] The beneficial effects of this invention are: This invention introduces a solid-state battery separator as a substrate during the bare chip packaging process, and sequentially constructs a polymer coating, an atomic layer deposition protective layer, and a microstructured pattern layer on its surface, achieving structural compatibility and performance complementarity among the multilayer materials. The ceramic base film provides excellent thermal stability and ionic insulation performance, while the polymer layer enhances flexibility and interfacial adhesion, and the nanoscale protective layer further improves the overall airtightness and oxidation resistance, enabling the packaging structure to maintain stable mechanical and electrical properties under high temperature and high humidity environments.

[0015] This invention achieves high-precision conductivity in the electrode contact area and effective isolation in the non-contact area by forming a micron-scale patterned protective layer through photolithography and reactive ion etching technology. Combined with staged hot pressing and vacuum packaging processes, it significantly reduces interlayer thermal stress and gas residue, and can effectively extend the service life of micro solid-state battery chips and highly integrated devices. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a bare chip packaging method according to an embodiment of the present invention. Detailed Implementation

[0018] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should also be noted that, to make the embodiments more comprehensive, the following embodiments are the best and preferred embodiments, and those skilled in the art can use other alternative methods to implement some well-known technologies; moreover, the accompanying drawings are only for more specific description of the embodiments and are not intended to specifically limit the present invention.

[0019] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) should be within the knowledge of those skilled in the art.

[0020] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Additionally, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather, alternatively, depending at least partly on the context, to allow for the presence of other factors that are not necessarily explicitly described.

[0021] Example 1 like Figure 1 As shown, the bare chip packaging method includes the following steps: S1: Substrate for preparing solid-state battery separator film; S2: A polymer coating is applied to the surface of a solid-state battery separator substrate to form a coated substrate; S3: Heat-treat the coated substrate to cure the polymer coating and form a cured coating; S4: Deposit a protective layer on the surface of the cured coating to form a deposited protective layer structure; S5: Pattern the structure of the deposited protective layer to form a patterned protective layer with a preset pattern; S6: The patterned protective layer is combined with the electrode layer, and the combined component is formed by hot pressing. S7: Finally, vacuum encapsulate the assembled components.

[0022] The solid-state battery separator substrate is a garnet-type LLZO ceramic thin film with a thickness of 30 μm and a porosity of 30%.

[0023] S2 specifically includes: S21: Prepare polymer slurry by mixing solid polymer, lithium salt and organic solvent at a mass ratio of 15:2:65 and stirring at 60°C for 3 hours until a uniform slurry with a viscosity of 1000 cP is formed. S22: The polymer slurry is coated onto the surface of the solid battery separator substrate using a slot extrusion coating method, and the wet film thickness is controlled to be 40μm. S23: Place the substrate coated with wet film in an inert atmosphere at 50°C for 2 minutes to perform leveling and pre-curing, forming a partially cured coating. S24: Apply a staged heating program to the substrate treated in S23. First, heat the substrate to 90°C at a rate of 3°C / min and hold for 15 minutes to completely remove the organic solvent and complete the preparation of the coated substrate.

[0024] S3 specifically includes: S31: Transfer the coated substrate to a programmable temperature controlled heating furnace and introduce an inert protective gas into the furnace chamber to reduce the oxygen content to 100 ppm; S32: Perform a staged heat treatment procedure. First, heat from room temperature to 90°C at a heating rate of 2°C / min and hold at this temperature for 20 minutes. Then, continue heating to 120°C at a heating rate of 1°C / min and hold at this final temperature for 30 minutes. S33: After completing the heat preservation in S32, turn off the heating source and allow the heating furnace to cool naturally to 40°C in an inert protective gas atmosphere. Then take out the product, which is the substrate with a cured coating.

[0025] S4 specifically includes: S41: Fix the substrate with the cured coating onto the base inside the reaction chamber of the plasma-enhanced chemical vapor deposition equipment, and set and maintain the base temperature at 100°C; S42: Evacuate the reaction chamber to achieve a background vacuum of 0.1 Pa, then introduce inert carrier gas into the reaction chamber and stabilize the working pressure at 100 Pa. S43: Alternately introduce a metal precursor and a reaction precursor into the reaction chamber, wherein the metal precursor is trimethylaluminum and the reaction precursor is deionized water vapor or oxygen plasma. S44: Control the pulse time of the precursor to 0.3 seconds and the purging time to 10 seconds, and perform 300 deposition cycles to form a uniform and dense protective layer with a thickness of 200 nm on the surface of the cured coating, thereby obtaining the deposited protective layer structure.

[0026] S5 specifically includes: S51: Photoresist is spin-coated onto the surface of the protective layer, and after soft baking at 100℃, ultraviolet exposure is performed using a photomask with a grid pattern, with an exposure energy of 150mJ / cm². S52: The exposed substrate is placed in a 2.2% tetramethyl sodium hydroxide solution for 50 seconds to develop, forming a patterned photoresist mask; S53: Reactive ion etching is performed in a mixed gas atmosphere of CF4 and O2, using a photoresist mask as a barrier layer. S54: The residual photoresist was removed using an acetone solution at 45°C to obtain a patterned protective layer with a grid pattern of 10μm linewidth.

[0027] The CF4 flow rate was 40 sccm, the O2 flow rate was 8 sccm, and the etching time was 3 minutes.

[0028] S6 specifically includes: S61: Align the substrate with the patterned protective layer and the electrode layer in a vacuum environment so that the raised area of ​​the patterned protective layer contacts the surface of the electrode layer. S62: Place the aligned laminated structure in a hot press and apply an initial pre-compression pressure of 10 MPa for 45 seconds; S63: Execute a staged hot pressing program. First, heat the temperature to 90°C at a rate of 4°C / minute and hold it at this temperature for 2 minutes. Then, continue to heat the temperature to 130°C while increasing the pressure to 20MPa and hold the temperature and pressure for 3 minutes. S64: After hot pressing is completed, the temperature is slowly cooled to 60°C at a rate of 1.5°C / min while maintaining pressure. After releasing the pressure, the assembly is removed to obtain the bonded component.

[0029] S7 specifically includes: S71: Transfer the combined components to a glove box filled with an inert atmosphere, where the water and oxygen content are both below 0.1 ppm; S72: Place the assembled component inside the aluminum-plastic film encapsulation housing, and lead out the positive and negative electrode tabs from the corresponding reserved openings in the encapsulation housing, respectively; S73: Use vacuum sealing equipment to heat seal the three open edges of the aluminum-plastic film packaging shell, wherein the heat sealing temperature is 160℃, the heat sealing pressure is 0.8MPa, and the heat sealing time is 4 seconds; S74: During the heat sealing process, the inside of the encapsulation housing is evacuated to a vacuum level of 0.05Pa before final sealing is completed, forming a complete solid-state battery separator assembly.

[0030] Example 1 S1: A NASICON-type LATP ceramic film with a thickness of 10μm and a porosity of 20% is selected as the substrate for the solid-state battery separator. S2: Solid polymer, lithium salt and organic solvent are mixed at a mass ratio of 15:2:65 and magnetically stirred at 50°C for 2 hours to form a polymer slurry with a viscosity of approximately 500 cP. The slurry is then uniformly coated onto the surface of the solid battery separator substrate using a slot extrusion coating method, with the wet film thickness controlled at 20 μm. The coating is then allowed to stand in a nitrogen atmosphere at 40°C for 1 minute to allow it to level and pre-cur. Afterward, the temperature is increased to 80°C at a rate of 2°C / min and held for 10 minutes to completely remove the organic solvent. S3: Transfer the coated substrate to a temperature-controlled furnace and continuously introduce argon gas into the furnace chamber to reduce the oxygen content to 100 ppm. Use a staged heating program to raise the temperature from room temperature to 80°C at a rate of 1°C / min and hold for 10 minutes, then raise it to 110°C at a rate of 0.5°C / min and hold for 20 minutes to promote polymer segment crosslinking and structural curing. After heating, turn off the heating source and allow it to cool naturally to 40°C in an argon atmosphere. Remove the sample to obtain a substrate with a cured coating. S4: Fix the substrate with the cured coating onto the reaction chamber base of the plasma-enhanced chemical vapor deposition equipment and maintain the base temperature at 80°C; after evacuating the reaction chamber to 0.1 Pa, introduce argon gas to stabilize the working pressure at 50 Pa; then alternately introduce zirconium tetrachloride plasma (a metal precursor) and oxygen plasma (a reaction precursor), control the pulse time to 0.1 seconds and the purge time to 5 seconds, and perform 100 deposition cycles to finally form a dense Al2O3 protective layer with a thickness of 50 nm on the surface of the cured coating; S5: Spin-coat AZ-5214 positive photoresist onto the protective layer surface, and then soft bake at 90℃ for 60 seconds; use a mask with a 5μm grid pattern and expose it under ultraviolet light with an exposure energy of 100mJ / cm²; during the development stage, immerse the sample in a 2.0% tetramethyl sodium hydroxide solution for 40 seconds to form a patterned photoresist mask; using the photoresist mask as a barrier layer, perform reactive ion etching for 2 minutes in a mixed atmosphere of CF4 gas flow rate of 30sccm and O2 flow rate of 5sccm to remove the protective layer in the uncovered areas; then remove the photoresist in an acetone solution at 40℃ to obtain a patterned protective layer with a linewidth of 5μm; S6: The substrate with the patterned protective layer and the electrode layer are precisely aligned in a vacuum environment, so that the raised areas of the patterned protective layer are in close contact with the surface of the electrode layer; first, a pre-pressure of 5 MPa is applied and held for 30 seconds, then the temperature is increased to 80°C at a rate of 3°C / min and held for 1 minute, then the temperature is increased to 120°C and the pressure is increased to 15 MPa and held for 2 minutes to complete the thermo-press bonding; after bonding, the temperature is slowly cooled to 60°C at a rate of 1°C / min while maintaining the pressure, and the bonded component is removed after the pressure is released; S7: Transfer the component to an argon glove box where the water and oxygen content is below 0.1ppm, place it in an aluminum-plastic film encapsulation shell, and lead out the positive and negative electrode tabs from the corresponding reserved ports; finally, use a vacuum encapsulation device to heat seal for 3 seconds at 150℃ and 0.5MPa, and then evacuate to 0.01Pa to complete the final sealing and obtain a complete bare chip encapsulation structure.

[0031] Example 2 S1: LAGP ceramic film with a thickness of 50μm and a porosity of 40% is selected as the substrate for the solid-state battery separator. S2: Solid polymer, lithium salt, and organic solvent are mixed at a mass ratio of 15:2:65 and magnetically stirred at 70°C for 4 hours to form a polymer slurry with a viscosity of approximately 2000 cP. The slurry is then uniformly coated onto the surface of the solid battery separator substrate using a slot extrusion coating method, with the wet film thickness controlled at 60 μm. Subsequently, the coating is allowed to stand in a nitrogen atmosphere at 60°C for 3 minutes to allow it to level and pre-cur. Afterward, the temperature is increased to 100°C at a rate of 5°C / min and held for 20 minutes to completely remove the organic solvent. S3: Transfer the coated substrate to a temperature-controlled furnace and continuously introduce argon gas into the furnace chamber to reduce the oxygen content to 100 ppm. Use a staged heating program to raise the temperature from room temperature to 100°C at a rate of 3°C / min and hold for 30 minutes, then raise it to 130°C at a rate of 2°C / min and hold for 40 minutes to promote polymer segment crosslinking and structural curing. After heating, turn off the heating source and allow it to cool naturally to 40°C in an argon atmosphere. Remove the sample to obtain a substrate with a cured coating. S4: Fix the substrate with the cured coating onto the reaction chamber base of the plasma-enhanced chemical vapor deposition equipment and maintain the base temperature at 120°C; after evacuating the reaction chamber to 0.1 Pa, introduce argon gas to stabilize the working pressure at 200 Pa; then alternately introduce the metal precursor trimethylaluminum and the reaction precursor deionized water vapor, control the pulse time to 0.5 seconds and the purge time to 15 seconds, and perform 500 deposition cycles to finally form a dense Al2O3 protective layer with a thickness of 500 nm on the surface of the cured coating; S5: Spin-coat AZ-5214 positive photoresist onto the protective layer surface, and then soft bake at 110℃ for 60 seconds; use a mask with a 5μm grid pattern and expose it under ultraviolet light with an exposure energy of 200mJ / cm²; during the development stage, immerse the sample in a 2.5% tetramethyl sodium hydroxide solution for 70 seconds to form a patterned photoresist mask; using the photoresist mask as a barrier layer, perform reactive ion etching for 5 minutes in a mixed atmosphere of CF4 gas flow rate of 50sccm and O2 flow rate of 10sccm to remove the protective layer in the uncovered areas; then remove the photoresist in an acetone solution at 50℃ to obtain a patterned protective layer with a linewidth of 20μm; S6: The substrate with the patterned protective layer and the electrode layer are precisely aligned in a vacuum environment, so that the raised areas of the patterned protective layer are in close contact with the surface of the electrode layer; first, a pre-pressure of 15MPa is applied and held for 60 seconds, then the temperature is increased to 100℃ at a rate of 5℃ / min and held for 3 minutes, then the temperature is increased to 150℃ and the pressure is increased to 25MPa, and held for 5 minutes to complete the thermo-press bonding; after bonding, the temperature is slowly cooled to 60℃ at a rate of 2℃ / min while maintaining the pressure, and the bonded component is removed after the pressure is released; S7: Transfer the component to an argon glove box where the water and oxygen content are both below 0.1ppm, place it in an aluminum-plastic film encapsulation shell, and lead out the positive and negative electrode tabs from the corresponding reserved ports; finally, use a vacuum encapsulation device to heat seal at 180℃ and 1.0MPa for 5 seconds, and then evacuate to 0.1Pa to complete the final sealing and obtain a complete bare chip package structure.

[0032] Comparative Example 1 Step 1: The processed bare chip is bonded to the metal substrate using silver paste, with the silver paste thickness controlled at approximately 10 μm; after mounting, it is heat-cured at 120 ℃ for 30 minutes to ensure a strong bond between the chip and the substrate. Step 2: Use two-component epoxy resin as the encapsulation material and mix the main agent and curing agent at a mass ratio of 100:10. Use a dispensing machine to evenly cover the chip surface and its bonding area with the mixed epoxy resin, and control the thickness of the encapsulation layer to about 300 μm. Then cure at 100 ℃ for 1 hour to form a hardened protective layer. Step 3: Spray a polyimide film with a thickness of approximately 100 nm onto the surface of the encapsulated and cured sample to enhance the moisture resistance and corrosion resistance of the encapsulated surface. After spraying, cure at 200 °C for another 20 minutes to obtain the final encapsulated chip product.

[0033] Table 1 Comparison of Finished Product Performance Parameters As shown in Table 1, Example 1 exhibits the best overall performance. It utilizes a 30 μm thick Garnet-type LLZO ceramic thin film substrate with a porosity of 30%. Optimal matching was achieved in polymer coating thickness control, staged heating during heat treatment, and Al2O3 protective layer deposition parameters, resulting in an interfacial bonding strength of 42.6 MPa and an encapsulation leakage rate of only 1.2 × 10⁻⁶ MPa. -9 Pa·cm 3 / s, the insulation performance and thermal cycling stability are significantly better than other schemes; the performance of Examples 2 and 3 is second best, with Example 2 (LATP substrate) slightly lower in interface bonding and electrical performance, mainly due to the film thickness of only 10 μm and the thin protective layer (50 nm), which easily produces local micro-defects; although Example 3 (LAGP substrate) has good hermeticity, the coating viscosity is high and the film thickness is large (60 μm), resulting in slight interface stress concentration after thermal cycling; Comparative Example 1 has the worst performance; the traditional silver paste + epoxy encapsulation process has problems such as thick layer, high porosity, and stress concentration, resulting in an interface strength of only 18.3 MPa and poor hermeticity (leakage rate as high as 6.8 × 10). -8 Pa·cm 3 / s), and the high-temperature stability and electrode contact performance are far lower than those of the present invention; In summary, Example 1 demonstrates excellent performance in terms of mechanics, hermeticity, electrical properties, and thermal stability. In particular, the bonding strength is increased by approximately 132%, the leakage rate is reduced by approximately two orders of magnitude, and the packaging uniformity and appearance pass rate are significantly improved. This fully verifies the significant advantages of the method of the present invention in the field of high-sealing, high-temperature resistant, and long-life packaging of bare chips.

[0034] This invention encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this invention. To provide the public with a thorough understanding of this invention, specific details are described in detail in the following preferred embodiments; however, those skilled in the art will fully understand the invention even without these details. Furthermore, to avoid unnecessary misunderstanding of the essence of this invention, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0035] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A bare chip packaging method, characterized in that, Includes the following steps: S1: Substrate for preparing solid-state battery separator film; S2: A polymer coating is applied to the surface of a solid-state battery separator substrate to form a coated substrate; S3: Heat-treat the coated substrate to cure the polymer coating and form a cured coating; S4: Deposit a protective layer on the surface of the cured coating to form a deposited protective layer structure; S5: Pattern the structure of the deposited protective layer to form a patterned protective layer with a preset pattern; S6: The patterned protective layer is combined with the electrode layer, and the combined component is formed by hot pressing. S7: Finally, vacuum encapsulate the assembled components.

2. The bare chip packaging method according to claim 1, characterized in that, The solid-state battery separator substrate is a Garnet-type LLZO, NASICON-type LATP, or LAGP ceramic film with a thickness of 10-50 μm and a porosity of 20%-40%.

3. The bare chip packaging method according to claim 1, characterized in that, S2 specifically includes: S21: To prepare a polymer slurry, a solid polymer, lithium salt and organic solvent are mixed in a mass ratio of 15:2:65 and stirred at 50-70℃ for 2-4 hours until a slurry with a viscosity of 500-2000 cP is formed. S22: The polymer slurry is coated onto the surface of the solid battery separator substrate using a slot extrusion coating method, and the wet film thickness is controlled to be 20-60μm. S23: Place the substrate coated with wet film in an inert atmosphere at 40-60℃ for 1-3 minutes to perform leveling and pre-curing to form a partially cured coating. S24: Apply a staged heating program to the substrate treated by S23. First, heat the substrate to 80-100°C at a rate of 2-5°C / minute and hold for 10-20 minutes to completely remove the organic solvent.

4. The bare chip packaging method according to claim 1, characterized in that, S3 specifically includes: S31: Transfer the coated substrate to a programmable temperature controlled heating furnace and introduce an inert protective gas into the furnace chamber to reduce the oxygen content to 100 ppm; S32: Perform a staged heat treatment procedure. First, heat from room temperature to 80-100℃ at a heating rate of 1-3℃ / min and hold at this temperature for 10-30 minutes. Then, continue heating to 110-130℃ at a heating rate of 0.5-2℃ / min and hold at this final temperature for 20-40 minutes. S33: After completing the heat preservation in S32, turn off the heating source and allow the heating furnace to cool naturally to 40°C in the inert protective gas atmosphere. Then take out the obtained product, which is the substrate with the cured coating.

5. The bare chip packaging method according to claim 1, characterized in that, S4 specifically includes: S41: Fix the substrate with the cured coating onto the base inside the reaction chamber of the plasma-enhanced chemical vapor deposition equipment, and set and maintain the base temperature at 80°C to 120°C; S42: Evacuate the reaction chamber to achieve a background vacuum of 0.1 Pa, then introduce inert carrier gas into the reaction chamber and stabilize the working pressure at 50 Pa to 200 Pa. S43: Alternately introduce a metal precursor and a reaction precursor into the reaction chamber, wherein the metal precursor is trimethylaluminum or zirconium tetrachloride, and the reaction precursor is deionized water or oxygen plasma. S44: Control the pulse time of the precursor to be between 0.1 seconds and 0.5 seconds, and the purging time to be between 5 seconds and 15 seconds, and perform 100 to 500 deposition cycles to form a uniform and dense protective layer with a thickness of 50 nm to 500 nm on the surface of the cured coating, thereby obtaining the deposited protective layer structure.

6. The bare chip packaging method according to claim 1, characterized in that, S5 specifically includes: S51: Spin-coat photoresist onto the surface of the protective layer, and after soft baking at 90-110℃, perform ultraviolet exposure using a photomask with a grid pattern, with an exposure energy of 100-200mJ / cm². S52: Place the exposed substrate in a 2.0-2.5% tetramethyl sodium hydroxide solution for 40-70 seconds to develop and form a patterned photoresist mask; S53: Reactive ion etching is performed in a mixed gas atmosphere of CF4 and O2, using a photoresist mask as a barrier layer. S54: Use an acetone solution at 40-50℃ to remove residual photoresist to obtain a patterned protective layer with a grid pattern of 5-20μm linewidth.

7. The bare chip packaging method according to claim 6, characterized in that, The CF4 flow rate is 30-50 sccm, the O2 flow rate is 5-10 sccm, and the etching time is 2-5 minutes.

8. The bare chip packaging method according to claim 1, characterized in that, S6 specifically includes: S61: Align the substrate with the patterned protective layer and the electrode layer in a vacuum environment so that the raised area of ​​the patterned protective layer contacts the surface of the electrode layer. S62: Place the aligned laminated structure in a hot press and apply an initial pre-compression pressure of 5-15MPa for 30-60 seconds; S63: Execute a staged hot pressing program. First, heat the temperature to 80-100℃ at a rate of 3-5℃ / minute and hold it at this temperature for 1-3 minutes. Then, continue to heat the temperature to 120-150℃ while increasing the pressure to 15-25MPa and hold the temperature and pressure for 2-5 minutes. S64: After hot pressing is completed, the temperature is slowly cooled to 60°C at a rate of 1-2°C / minute while maintaining pressure. After releasing the pressure, the assembly is removed to obtain the combined component.

9. The bare chip packaging method according to claim 1, characterized in that, Specifically, S7 includes: S71: Transfer the combined components to a glove box filled with an inert atmosphere, where the water and oxygen content are both below 0.1 ppm; S72: Place the assembled component inside the aluminum-plastic film encapsulation housing, and lead out the positive and negative electrode tabs from the corresponding reserved openings in the encapsulation housing, respectively; S73: Use vacuum sealing equipment to heat seal the three open edges of the aluminum-plastic film packaging shell, wherein the heat sealing temperature is 150-180℃, the heat sealing pressure is 0.5-1.0MPa, and the heat sealing time is 3-5 seconds; S74: During the heat sealing process, the inside of the encapsulation housing is evacuated to a vacuum level of 0.01-0.1 Pa before final sealing is completed, forming a complete solid-state battery separator assembly.

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