A power amplifier and radio frequency chip

Abstract

The application belongs to the technical field of communication, and particularly relates to a power amplifier and a radio frequency chip. The power amplifier comprises input matching circuit, driving stage amplification circuit, inter-stage matching circuit, amplification stage amplification circuit and output matching circuit which are electrically connected in sequence; the input matching circuit is used for receiving radio frequency signals, and the output matching circuit is used for outputting signals; the inter-stage matching circuit comprises first capacitor, second capacitor, third capacitor, fourth capacitor, fifth capacitor, sixth capacitor, seventh capacitor, first inductor, second inductor, third inductor, fourth inductor, fifth inductor and first resistor. Compared with the prior art, the structure of the inter-stage matching circuit is improved, so that the power amplifier matching architecture of the application has a wide working bandwidth, higher efficiency and better flatness.

Description

TECHNICAL FIELD

[0001] The present application is suitable for the field of communication technology, and particularly relates to a power amplifier and a radio frequency chip. BACKGROUND

[0002] Radio frequency power amplifiers play a crucial role in modern wireless communication systems. The core function is to amplify the weak modulated radio frequency signals to provide sufficient energy for the signals to be effectively radiated through the antenna, thereby overcoming path loss, ensuring communication distance and coverage. At the same time, it must strike a difficult balance between efficiency and linearity, and its performance directly determines the coverage capability, energy cost and communication quality of the entire communication system. Whether it is a mobile terminal (such as a mobile phone), a base station device, a satellite communication system, or a broadcast television transmission system, it widely relies on power amplifiers to expand signal coverage and enhance link quality, thereby ensuring the stability and reliability of the communication process.

[0003] With the development of wireless communication technology, the requirements for power amplifiers are constantly increasing to support the growing demand for high data rate transmission. Modern communication standards such as 5G and future 6G have higher requirements for power amplifiers, not only supporting wider bandwidth and higher linearity, but also optimizing the balance between efficiency, heat and size to enable the system to efficiently transmit data in a wider frequency band. The performance of a power amplifier is usually measured by several key indicators, including efficiency, gain, linearity, stability, and bandwidth characteristics. Among them, efficiency directly affects the power consumption and thermal management of the system; linearity determines signal fidelity and out-of-band interference level; stability ensures the reliable operation of the amplifier under different load conditions; and bandwidth characteristics affect the range of supported frequency bands and data transmission potential. In order to enable the communication system to achieve wideband and high efficiency transmission, it is necessary to design a reasonable circuit architecture and matching method, in which the impedance matching network and the inter-stage matching network play a very important role.

[0004] The impedance matching network is mainly applied to the input or output port of the circuit system, and its core function is to achieve efficient energy transmission between the signal source and the load. By matching the load impedance and the signal source impedance, it can maximize power transmission and significantly reduce signal reflection caused by impedance mismatch, thereby ensuring signal integrity, improving system efficiency and ensuring device stability. The inter-stage matching network is used between the cascaded stages of a multi-stage circuit (such as a multi-stage amplifier), focusing on achieving maximum power gain and optimizing overall performance. It matches the output impedance of the previous stage circuit to the optimal input impedance of the next stage circuit, ensuring that each stage can be fully driven and work in the best state; the architecture of the inter-stage matching directly affects the realization of the bandwidth, linearity, efficiency, and gain indicators of the PA.

[0005] In order to design a power amplifier with wide bandwidth and high efficiency, the output power, gain, return loss and the like can be used as indexes for the power amplifier. Among them, the relative bandwidth is defined as:

[0006]

[0007] In the formula, Δω is the frequency band width satisfying the index requirement, and ω0 is the center frequency. Generally, the relative bandwidth is used to measure the bandwidth characteristics of the system. The relative bandwidth less than 20% is defined as narrowband, and the relative bandwidth greater than 20% is defined as wideband. In the matching architecture, the bandwidth of the matching network can be expanded by increasing the number of elements cascaded in the matching network, but the bandwidth is often limited by the input and output impedances, and it is impossible to increase indefinitely. According to the Bode-Fano criterion:

[0008]

[0009] In the formula, Γ (ω ) is the reflection coefficient of all lossless matching networks. If the reflection coefficient Γ (ω ) is constant in the frequency band, m Γ, the reflection coefficient |Γ (ω )|=1 outside the frequency band is in the full reflection state, and the wider the bandwidth of the matching network, the worse the modulus of the reflection coefficient. If you want to obtain a very wide bandwidth, you must sacrifice the perfection of the matching and accept a certain amount of reflection within the passband. Therefore, the Bode-Fano bandwidth theory points out that when the complex load is given, there is a basic limit to the achievable bandwidth, which will reduce the target load impedance and further deviate from the high efficiency condition, and after a certain bandwidth is reached, the efficiency will be poor.

[0010] The inter-stage matching network of the power amplifier commonly used in the prior art is shown in Figure 1 Figure 1 is a circuit diagram of a power amplifier provided by the related art, mainly composed of inductors (L1, L2, L3) and capacitors (C1, C2, C3), wherein the series inductor is connected to the output Pad of the driver stage die and the inductor L2, L2 is the drain stage feed inductor of the driver stage die, which provides the drain voltage for the driver stage die. L3 is the gate feed inductor of the final stage die, which provides the gate voltage for the final stage die. C1 is a DC blocking capacitor that separates the drain voltage of the driver amplifier tube and the gate voltage of the final stage amplifier tube. C2 and C3 are decoupling capacitors of the power supply end, which are used to eliminate power supply noise and voltage fluctuation. Another common inter-stage matching network of the power amplifier is shown in Figure 2 Figure 2 ​​​​is a circuit diagram of another power amplifier provided by the related art; mainly composed of inductors (L1, L2, L3) and capacitors (C1, C2, C3, C4), C1 is a DC blocking capacitor, C2 is connected in parallel to the ground, L1 is a series inductor, C2 and L1 participate in inter-stage matching, and impedance is optimized; L2 is a drain stage feed inductor of a driving stage die, and provides a drain voltage for the driving stage die. L3 is a gate feed inductor of a final stage die, and provides a gate voltage for the final stage die. C1 is a DC blocking capacitor, which separates the drain voltage of the driving amplifier tube and the gate voltage of the final amplifier tube. C2 and C3 are decoupling capacitors of the power supply end.

[0011] However, although the bandwidth of the inter-stage matching network architecture of the above two power amplifiers can be wide, the network matching loss is large, and the overall efficiency is low; for products covering a low frequency of 100Mhz and a bandwidth exceeding one octave, the above power amplifier architecture cannot be completely suitable.

[0012] Therefore, there is an urgent need for a new power amplifier and radio frequency chip to solve the above technical problems. SUMMARY

[0013] The present application provides a power amplifier and a radio frequency chip, aiming to provide a power amplifier with a wide matching architecture working bandwidth, high efficiency and good flatness.

[0014] In a first aspect, the present application provides a power amplifier, which comprises an input matching circuit, a driving stage amplification circuit, an inter-stage matching circuit, an amplification stage amplification circuit and an output matching circuit connected in sequence.

[0015] The inter-stage matching circuit comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor and a first resistor.

[0016] The first end of the first inductor is connected to the output end of the driving stage amplifier circuit as the input end of the inter-stage matching circuit, the second end of the first inductor is connected to the first end of the first capacitor, the first end of the second capacitor and the first end of the third capacitor respectively, the second end of the first capacitor is grounded, the second end of the second capacitor is connected to the first end of the second inductor, the first end of the fourth capacitor and the first end of the first resistor respectively, the second end of the second inductor is connected to the input end of the amplifying stage amplifier circuit as the output end of the inter-stage matching circuit, the second end of the fourth capacitor is grounded, the second end of the first resistor is connected to the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, the second end of the third capacitor is connected to the first end of the third inductor, the second end of the third inductor is connected to the second end of the second inductor and the first end of the fourth inductor respectively, the second end of the fourth inductor is used for connecting a first gate bias voltage, the first end of the seventh capacitor is connected to the second end of the fourth inductor, the second end of the seventh capacitor is grounded, the first end of the fifth inductor is connected to the first end of the first inductor, and the second end of the fifth inductor is used for connecting a first drain bias voltage, the first end of the sixth capacitor is connected to the second end of the fifth inductor, and the second end of the sixth capacitor is grounded.

[0017] Preferably, the input matching circuit comprises an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a sixth inductor, a seventh inductor, an eighth inductor and a second resistor.

[0018] The first end of the eighth capacitor is used for connecting an input signal as the input end of the input matching circuit, the second end of the eighth capacitor is connected to the first end of the sixth inductor, the first end of the tenth capacitor and the first end of the second resistor respectively, the second end of the tenth capacitor is grounded, the second end of the second resistor is connected to the first end of the eleventh capacitor, the second end of the eleventh capacitor is grounded, the second end of the sixth inductor is connected to the first end of the ninth capacitor, the second end of the ninth capacitor is connected to the input end of the driving stage amplifier circuit as the output end of the input matching circuit, the first end of the seventh inductor is connected to the first end of the eighth capacitor, the second end of the seventh inductor is connected to the second end of the sixth inductor and the first end of the ninth capacitor respectively, the first end of the eighth inductor is connected to the second end of the ninth capacitor, the second end of the eighth inductor is used for connecting a second gate bias voltage, the first end of the twelfth capacitor is connected to the second end of the eighth inductor, and the second end of the twelfth capacitor is grounded.

[0019] Preferably, the output matching circuit comprises a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a ninth inductor, a first micro inductor, a second micro inductor and a third micro inductor.

[0020] The first end of the first micro-inductor is an input end of the output matching circuit, the second end of the first micro-inductor is connected with the first end of the fourteenth capacitor and the first end of the second micro-inductor respectively, the second end of the fourteenth capacitor is grounded, the second end of the second micro-inductor is connected with the first end of the fifteenth capacitor and the first end of the third micro-inductor respectively, the second end of the fifteenth capacitor is grounded, the second end of the third micro-inductor is an output end of the output matching circuit, the first end of the ninth inductor is connected with the first end of the first micro-inductor, the second end of the ninth inductor is connected with a second drain bias voltage, the first end of the thirteenth capacitor is connected with the second end of the ninth inductor, and the second end of the thirteenth capacitor is grounded.

[0021] Preferably, the driving stage amplification circuit comprises a first transistor; an input end of the first transistor is an input end of the driving stage amplification circuit, an output end of the first transistor is an output end of the driving stage amplification circuit, and a ground end of the first transistor is grounded.

[0022] Preferably, the amplification stage amplification circuit comprises a second transistor; an input end of the second transistor is an input end of the amplification stage amplification circuit, an output end of the second transistor is an output end of the amplification stage amplification circuit, and a ground end of the second transistor is grounded.

[0023] Preferably, the first transistor and the second transistor are triodes or MOS transistors.

[0024] Preferably, the first transistor is a first MOS transistor, a gate of the first MOS transistor is an input end of the first transistor, a source of the first MOS transistor is a ground end of the first transistor, and a drain of the first MOS transistor is an output end of the first transistor; the second transistor is a second MOS transistor, a gate of the second MOS transistor is an input end of the second transistor, a source of the second MOS transistor is a ground end of the second transistor, and a drain of the second MOS transistor is an output end of the second transistor.

[0025] Preferably, the first transistor is a first triode, a base of the first triode is an input end of the first transistor, a collector of the first triode is an output end of the first transistor, and an emitter of the first triode is a ground end of the first transistor; the second transistor is a second triode, a base of the second triode is an input end of the second transistor, a collector of the second triode is an output end of the second transistor, and an emitter of the second triode is a ground end of the second transistor.

[0026] In a second aspect, the present application also provides a radio frequency chip, which comprises the power amplifier according to any one of the above embodiments.

[0027] Compared with the prior art, the present application improves the structure of the inter-stage matching circuit, and is applicable to a matching architecture of a wideband low-frequency power amplifier and an inter-stage matching circuit between multi-stage power amplifiers. The matching architecture can provide good return loss in a working frequency band, so that the flatness of the power amplifier is better and the efficiency is higher. The matching architecture is applicable to a low-frequency band, and the gain of a transistor is higher in the low-frequency band, so that the higher gain in the low-frequency band can be offset, the flatness is optimized, and the power amplifier remains stable in the working frequency. BRIEF DESCRIPTION OF DRAWINGS

[0028] The present application will be described in detail below with reference to the drawings. The above and other aspects of the present application will become more apparent and more readily appreciated by referring to the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a circuit diagram of a power amplifier provided by the related art;

[0030] Figure 2 is a circuit diagram of another power amplifier provided by the related art;

[0031] Figure 3 is a circuit diagram of an inter-stage matching circuit of a power amplifier provided by an embodiment of the present application;

[0032] Figure 4 is a circuit diagram of a power amplifier provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0034] Embodiment One

[0035] Please refer to Figures 3 to 4 The present application provides a power amplifier 100, which comprises an input matching circuit 1, a driving stage amplification circuit 2, an inter-stage matching circuit 3, an amplification stage amplification circuit 4 and an output matching circuit 5 connected in sequence. The input matching circuit 1 is used to receive a radio frequency signal, and the output matching circuit 5 is used to output a signal. The input matching circuit 1 and the output matching circuit 5 realize impedance matching for the power amplifier 100.

[0036] The inter-stage matching circuit 3 comprises a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5 and a first resistor R1.

[0037] The first end of the first inductor L1 is used as an input end of the inter-stage matching circuit 3 and is connected to an output end of the driving stage amplifier circuit, the second end of the first inductor L1 is connected to the first end of the first capacitor C1, the first end of the second capacitor C2 and the first end of the third capacitor C3 respectively, the second end of the first capacitor C1 is grounded, the second end of the second capacitor C2 is connected to the first end of the second inductor L2, the first end of the fourth capacitor C4 and the first end of the first resistor R1 respectively, the second end of the second inductor L2 is used as an output end of the inter-stage matching circuit 3 and is connected to an input end of the amplifying stage amplifier circuit 4, the second end of the fourth capacitor C4 is grounded, the second end of the first resistor R1 is connected to the first end of the fifth capacitor C5, the second end of the fifth capacitor C5 is grounded, the second end of the third capacitor C3 is connected to the first end of the third inductor L3, the second end of the third inductor L3 is connected to the second end of the second inductor L2 and the first end of the fourth inductor L4 respectively, the second end of the fourth inductor L4 is used for connecting a first gate bias voltage VG1, the first end of the seventh capacitor C7 is connected to the second end of the fourth inductor L4, the second end of the seventh capacitor C7 is grounded, the first end of the fifth inductor L5 is connected to the first end of the first inductor L1, and the second end of the fifth inductor L5 is used for connecting a first drain bias voltage VD1, the first end of the sixth capacitor C6 is connected to the second end of the fifth inductor L5, and the second end of the sixth capacitor C6 is grounded.

[0038] Specifically, the third capacitor C3 is a direct current blocking capacitor, the second capacitor C2 participates in the optimization of inter-stage matching impedance and has the function of blocking direct current signals. The fourth capacitor C4, the fifth capacitor C5 and the first resistor R1 form an equalizer architecture, the first resistor R1 is used as a series resistor and a fourth capacitor C4 connected in parallel to the ground, which can offset the higher gain at low frequencies, optimize the flatness in the entire frequency band, and the fifth capacitor C5 is a large capacitor, which can realize real impedance at low frequencies and also has the function of blocking direct current, avoiding the direct ground connection of the resistance in series with the radio frequency, so that the radio frequency loop and the direct current loop are short-circuited to the ground. The second inductor L2 and the second capacitor C2 form a frequency selection network, and the first capacitor C1, the second capacitor C2, the first inductor L1 and the second inductor L2 participate in the inter-stage matching to form a multi-order LC resonance, expand the radio frequency bandwidth and optimize the inter-stage impedance. The power amplifier 100 provided by the application can realize the coverage of 10Mhz to 7Ghz in the working frequency band.

[0039] In the embodiment of the present application, the input matching circuit 1 comprises an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a sixth inductor L6, a seventh inductor L7, an eighth inductor L8 and a second resistor R2;

[0040] The first end of the eighth capacitor C8 is used as the input end of the input matching circuit 1 and is connected to an input signal, the second end of the eighth capacitor C8 is connected to the first end of the sixth inductor L6, the first end of the tenth capacitor C10 and the first end of the second resistor R2 respectively, the second end of the tenth capacitor C10 is grounded, the second end of the second resistor R2 is connected to the first end of the eleventh capacitor C11, the second end of the eleventh capacitor C11 is grounded, the second end of the sixth inductor L6 is connected to the first end of the ninth capacitor C9, the second end of the ninth capacitor C9 is used as the output end of the input matching circuit 1 and is connected to the input end of the driving stage amplification circuit 2, the first end of the seventh inductor L7 is connected to the first end of the eighth capacitor C8, the second end of the seventh inductor L7 is connected to the second end of the sixth inductor L6 and the first end of the ninth capacitor C9 respectively, the first end of the eighth inductor L8 is connected to the second end of the ninth capacitor C9, the second end of the eighth inductor L8 is used to connect a second gate bias voltage VG2, the first end of the twelfth capacitor C12 is connected to the second end of the eighth inductor L8, and the twelfth capacitor C12 is grounded.

[0041] In the embodiment of the present application, the output matching circuit 5 comprises a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a ninth inductor L9, a first micro inductor ML1, a second micro inductor ML2 and a third micro inductor ML3.

[0042] The first end of the first micro inductor ML1 is used as the input end of the output matching circuit 5 and is connected to the output end of the amplification stage amplification circuit 4, the second end of the first micro inductor ML1 is connected to the first end of the fourteenth capacitor C14 and the first end of the second micro inductor ML2 respectively, the second end of the fourteenth capacitor C14 is grounded, the second end of the second micro inductor ML2 is connected to the first end of the fifteenth capacitor C15 and the first end of the third micro inductor ML3 respectively, the second end of the fifteenth capacitor C15 is grounded, the second end of the third micro inductor ML3 is used as the output end of the output matching circuit 5, the first end of the ninth inductor L9 is connected to the first end of the first micro inductor ML1, the second end of the ninth inductor L9 is connected to a second drain bias voltage VD2, the first end of the thirteenth capacitor C13 is connected to the second end of the ninth inductor L9, and the second end of the thirteenth capacitor C13 is grounded.

[0043] Specifically, the seventh inductor L7 constitutes a driving stage gate bias voltage circuit, the sixth capacitor C6 and the fifth inductor L5 constitute a driving stage drain bias voltage circuit, the seventh capacitor C7 and the fourth inductor L4 constitute a final stage gate bias voltage circuit, and the thirteenth capacitor C13 and the ninth inductor L9 constitute a final stage drain bias voltage circuit; the ninth capacitor C9 in the input matching circuit 1 is a direct current isolation capacitor, and the remaining devices participate in impedance matching of the input; the first micro-inductor ML1, the second micro-inductor ML2, the third micro-inductor ML3, the fourteenth capacitor C14, and the fifteenth capacitor C15 constitute an output matching circuit 5, and a multi-section impedance transformer architecture with Chebyshev distribution is adopted.

[0044] In the embodiment of the present application, the driving stage amplification circuit 2 comprises a first transistor HBT1; the input end of the first transistor HBT1 serves as the input end of the driving stage amplification circuit 2, the output end of the first transistor HBT1 serves as the output end of the driving stage amplification circuit 2, and the ground end of the first transistor HBT1 is grounded.

[0045] In the embodiment of the present application, the amplification stage amplification circuit 4 comprises a second transistor HBT2; the input end of the second transistor HBT2 serves as the input end of the amplification stage amplification circuit 4, the output end of the second transistor HBT2 serves as the output end of the amplification stage amplification circuit 4, and the ground end of the second transistor HBT2 is grounded.

[0046] In the embodiment of the present application, the first transistor HBT1 and the second transistor HBT2 are transistors or MOS tubes.

[0047] When the first transistor HBT1 is a first MOS tube, the gate of the first MOS tube serves as the input end of the first transistor HBT1, the source of the first MOS tube serves as the ground end of the first transistor HBT1, and the drain of the first MOS tube serves as the output end of the first transistor HBT1.

[0048] When the second transistor HBT2 is a second MOS tube, the gate of the second MOS tube serves as the input end of the second transistor HBT2, the source of the second MOS tube serves as the ground end of the second transistor HBT2, and the drain of the second MOS tube serves as the output end of the second transistor HBT2.

[0049] When the first transistor HBT1 is a first transistor, the base of the first transistor serves as the input end of the first transistor HBT1, the collector of the first transistor serves as the output end of the first transistor HBT1, and the emitter of the first transistor serves as the ground end of the first transistor HBT1.

[0050] When the second transistor HBT2 is a second triode, a base of the second triode serves as an input terminal of the second transistor HBT2, a collector of the second triode serves as an output terminal of the second transistor HBT2, and an emitter of the second triode serves as a ground terminal of the second transistor HBT2.

[0051] Compared with the prior art, the application can be applied to a matching architecture of a wideband low-frequency power amplifier and an inter-stage matching circuit between multi-stage power amplifiers by improving the structure of the inter-stage matching circuit, the matching architecture can provide good return loss in a working frequency band, so that the flatness of the power amplifier is better and the efficiency is higher, the matching architecture is suitable for a low-frequency band, the gain of a transistor is higher in the low-frequency band, so that the higher gain in the low-frequency band can be offset, the flatness is optimized, and the power amplifier remains stable in the working frequency.

[0052] Embodiment two

[0053] The embodiment of the application also provides a radio frequency chip, which comprises the power amplifier 100 in the above embodiment and can achieve the same technical effects, and the description in the above embodiment is referred to and will not be repeated here.

[0054] It should be noted that in this document, the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0055] The embodiments of the application are described above in combination with the drawings, the disclosed is only the preferred embodiments of the application, but the application is not limited to the above specific embodiments, the above specific embodiments are only illustrative, but not restrictive, and those skilled in the art can make many equivalent changes in form without departing from the purpose of the application and the scope of the claims, which are all within the protection of the application.

Claims

1. A power amplifier, characterized by, The power amplifier comprises an input matching circuit, a driving stage amplification circuit, an inter-stage matching circuit, an amplification stage amplification circuit and an output matching circuit connected in sequence; The inter-stage matching circuit comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor and a first resistor; The first end of the first inductor is used as an input end of the inter-stage matching circuit and is connected to an output end of the driving stage amplification circuit, the second end of the first inductor is connected to the first end of the first capacitor, the first end of the second capacitor and the first end of the third capacitor respectively, the second end of the first capacitor is grounded, the second end of the second capacitor is connected to the first end of the second inductor, the first end of the fourth capacitor and the first end of the first resistor respectively, the second end of the second inductor is used as an output end of the inter-stage matching circuit and is connected to an input end of the amplification stage amplification circuit, the second end of the fourth capacitor is grounded, the second end of the first resistor is connected to the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, the second end of the third capacitor is connected to the first end of the third inductor, the second end of the third inductor is connected to the second end of the second inductor and the first end of the fourth inductor respectively, the second end of the fourth inductor is used for connecting a first gate bias voltage, the first end of the seventh capacitor is connected to the second end of the fourth inductor, and the second end of the seventh capacitor is grounded.

2. The power amplifier of claim 1, wherein, The input matching circuit comprises an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a sixth inductor, a seventh inductor, an eighth inductor and a second resistor; The first end of the eighth capacitor is used as an input end of the input matching circuit and is used for connecting an input signal, the second end of the eighth capacitor is connected to the first end of the sixth inductor, the first end of the tenth capacitor and the first end of the second resistor respectively, the second end of the tenth capacitor is grounded, the second end of the second resistor is connected to the first end of the eleventh capacitor, and the second end of the eleventh capacitor is grounded; the second end of the sixth inductor is connected to the first end of the ninth capacitor, the second end of the ninth capacitor is used as an output end of the input matching circuit and is connected to an input end of the driving stage amplification circuit; the first end of the seventh inductor is connected to the first end of the eighth capacitor, the second end of the seventh inductor is connected to the second end of the sixth inductor and the first end of the ninth capacitor respectively, the first end of the eighth inductor is connected to the second end of the ninth capacitor, the second end of the eighth inductor is used for connecting a second gate bias voltage, the first end of the twelfth capacitor is connected to the second end of the eighth inductor, and the twelfth capacitor is grounded.

3. The power amplifier of claim 1, wherein, The output matching circuit comprises a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a ninth inductor, a first micro-inductor, a second micro-inductor and a third micro-inductor. The first end of the first micro-inductor is used as an input end of the output matching circuit and is connected to an output end of the amplification stage amplification circuit; the second end of the first micro-inductor is connected to the first end of the fourteenth capacitor and the first end of the second micro-inductor respectively; the second end of the fourteenth capacitor is grounded; the second end of the second micro-inductor is connected to the first end of the fifteenth capacitor and the first end of the third micro-inductor respectively; the second end of the fifteenth capacitor is grounded; the second end of the third micro-inductor is used as an output end of the output matching circuit; the first end of the ninth inductor is connected to the first end of the first micro-inductor; the second end of the ninth inductor is used for connecting a second drain bias voltage; the first end of the thirteenth capacitor is connected to the second end of the ninth inductor; and the second end of the thirteenth capacitor is grounded.

4. The power amplifier of claim 1, wherein, The driving stage amplification circuit comprises a first transistor; an input end of the first transistor is used as an input end of the driving stage amplification circuit; an output end of the first transistor is used as an output end of the driving stage amplification circuit; and a grounding end of the first transistor is grounded.

5. The power amplifier of claim 4, wherein, The amplification stage amplification circuit comprises a second transistor; an input end of the second transistor is used as an input end of the amplification stage amplification circuit; an output end of the second transistor is used as an output end of the amplification stage amplification circuit; and a grounding end of the second transistor is grounded.

6. The power amplifier of claim 5, wherein, The first transistor and the second transistor are triodes or MOS transistors.

7. The power amplifier of claim 6, wherein, The first transistor is a first MOS transistor; a gate of the first MOS transistor is used as an input end of the first transistor; a source of the first MOS transistor is used as a grounding end of the first transistor; and a drain of the first MOS transistor is used as an output end of the first transistor; the second transistor is a second MOS transistor; a gate of the second MOS transistor is used as an input end of the second transistor; a source of the second MOS transistor is used as a grounding end of the second transistor; and a drain of the second MOS transistor is used as an output end of the second transistor.

8. The power amplifier of claim 6, wherein, The first transistor is a first triode; a base of the first triode is used as an input end of the first transistor; a collector of the first triode is used as an output end of the first transistor; and an emitter of the first triode is used as a grounding end of the first transistor; the second transistor is a second triode; a base of the second triode is used as an input end of the second transistor; a collector of the second triode is used as an output end of the second transistor; and an emitter of the second triode is used as a grounding end of the second transistor.

9. A radio frequency chip, characterized by The radio frequency chip comprises the power amplifier according to any one of claims 1-8.

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