Signal amplitude adjustment device, electronic device, storage medium, and program product

Abstract

This disclosure provides a signal amplitude adjustment device, electronic device, storage medium, and program product, applied in the field of interconnect interface drivers. The device includes a driving unit; the driving unit includes a three-stage current-mode differential amplifier; each stage of the current-mode differential amplifier includes two field-effect transistors (FETs) and two load resistors; each load resistor includes a first FET, a second FET, a third FET, and a first resistor; the first FET is the control transistor of the load resistor, used to control the resistance of the second FET and the resistance of the third FET; the second FET is connected in series with the first resistor to isolate the control voltage from the first resistor; the third FET is connected in parallel with the first resistor; thus, the resistance value of the load resistor can be adjusted by controlling the voltage so that the signal amplitude is adjusted to the target amplitude after the signal passes through the driving unit including the three-stage current-mode differential amplifier.

Description

Technical Field

[0001] This disclosure relates to the field of interconnect interface driver technology, and in particular to a signal amplitude adjustment device, electronic device, storage medium and program product. Background Technology

[0002] In the digital age, computing power has become a key engine driving social progress. Its essence is data processing capability, relying on chips such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Application Specific Integrated Circuits (ASICs). It is widely used in servers, smart terminals, and computers, leveraging cloud computing and edge computing technologies to process massive amounts of digital applications and data. It is estimated that in recent years, the scale of intelligent computing power will reach 1037.3 exa floating-point operations per second (EFLOPS). High-computing-power fields such as artificial intelligence, 6th Generation Mobile Communication Technology (6G), big data computing, and automatic acceleration are developing rapidly, placing higher design requirements on the high speed and high reliability of interconnect interfaces. To meet these requirements, the four-level pulse amplitude modulation (PAM4) signal standard is gradually replacing the traditional non-return-to-zero (NRZ) signal, becoming the standard signal in interconnect interfaces.

[0003] Because PAM4 signals are difficult to meet the crossover requirements of various level transitions, the transmission quality of PAM4 signals, such as eye diagram opening and signal noise margin, is limited, and they can only be used in interconnect interfaces in low computing power scenarios. Summary of the Invention

[0004] This disclosure provides a signal amplitude adjustment device, electronic device, storage medium, and program product to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a signal amplitude adjustment device is provided, including a driving unit;

[0006] The driving unit includes a three-stage current-mode differential amplifier; each stage of the current-mode differential amplifier includes two field-effect transistors and two load resistors;

[0007] Each load resistor includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a first resistor;

[0008] The gate of the first field-effect transistor is used to receive the control voltage. The source of the first field-effect transistor is connected to the gate of the second field-effect transistor and the gate of the third field-effect transistor, respectively. The drain of the first field-effect transistor outputs the adjusted signal.

[0009] The source of the second field-effect transistor outputs the adjusted signal, and the drain of the second field-effect transistor is connected to the first terminal of the first resistor and the drain of the third field-effect transistor, respectively.

[0010] The source of the third field-effect transistor is connected to the drain of the field-effect transistor in the current-mode differential amplifier.

[0011] The second end of the first resistor is connected to the drain of the field-effect transistor in the current-mode differential amplifier;

[0012] The first field-effect transistor (FET) is a control transistor for the load resistor, used to control the resistance of the second and third FETs. The second FET is connected in series with the first resistor to isolate the control voltage from the first resistor. The third FET is connected in parallel with the first resistor. The resistance value of the load resistor is adjusted by inputting the control voltage so that the amplitude of the signal is adjusted to the target amplitude after the signal passes through the driving unit including the three-stage current-mode differential amplifier.

[0013] In the above scheme, the resistance value of each load resistor is determined based on the resistance values ​​of the second field-effect transistor, the third field-effect transistor, and the first resistor.

[0014] In the above scheme, the resistance value of each load resistor includes the sum of the resistance value of the first resistor and the resistance value of the third field-effect transistor connected in parallel, and the resistance value of the second field-effect transistor.

[0015] In the above scheme, the first field-effect transistor and the third field-effect transistor are N-channel field-effect transistors;

[0016] The second field-effect transistor is a P-channel field-effect transistor.

[0017] In any of the above schemes, in any of the current-mode differential amplifiers:

[0018] The gates of the fourth and fifth field-effect transistors are connected to the current signal so that the amplitude of the signal is adjusted to the target amplitude after passing through the three-stage current-mode differential amplifier.

[0019] The source stages of the fourth and fifth field-effect transistors are connected to the operating power supply;

[0020] The drain of the fourth field-effect transistor is connected to the first terminal of the first load resistor;

[0021] The drain of the fifth field-effect transistor is connected to the first terminal of the second load resistor;

[0022] The second end of the first load resistor is connected to the second end of the second load resistor, and the second end of the load resistors of other current-mode differential amplifiers is also connected to it.

[0023] In the above scheme, the second end of the first load resistor and the source of the third field-effect transistor correspond to the first end of the first load resistor.

[0024] In the first load resistor, the drain of the first field-effect transistor and the source of the second field-effect transistor correspond to the second terminal of the first load resistor.

[0025] In the above scheme, the drain of the fourth field-effect transistor is connected to the second terminal of the first resistor in the first load resistor, and the source of the third field-effect transistor.

[0026] The drain of the fifth field-effect transistor is connected to the second terminal of the first resistor in the second load resistor, and to the source of the third field-effect transistor.

[0027] In the above scheme, the fourth and fifth field-effect transistors are N-channel field-effect transistors.

[0028] In the above scheme, the driving unit further includes a sixth field-effect transistor, a seventh field-effect transistor, and an eighth field-effect transistor;

[0029] The gates of the sixth, seventh, and eighth field-effect transistors are respectively connected to the operating power supply.

[0030] The drain of the sixth field-effect transistor is connected to the source of the two field-effect transistors in the corresponding current-mode differential amplifier, and the source of the sixth field-effect transistor is grounded.

[0031] The drain of the seventh field-effect transistor is connected to the source of the two field-effect transistors in the corresponding current-mode differential amplifier, and the source of the seventh field-effect transistor is grounded.

[0032] The drain of the eighth field-effect transistor is connected to the source of the two field-effect transistors in the corresponding current-mode differential amplifier, and the source of the eighth field-effect transistor is grounded.

[0033] In the above scheme, the sixth, seventh and eighth field-effect transistors are all N-channel field-effect transistors.

[0034] In the above scheme, the device further includes a control unit and an isolation unit;

[0035] The control unit is used to determine the control voltage based on the amplitude of the current signal;

[0036] The isolation unit is used to shield the signal output by the drive unit from interference from external signals.

[0037] In the above scheme, the driving unit is used to receive the signal and adjust the amplitude of the signal based on the control voltage input by the control unit, so that the amplitude of the signal is adjusted to the target amplitude.

[0038] The control unit is connected to the output terminal of the drive unit, and is used to acquire the signal output by the drive unit, determine the control voltage based on two adjacent signals output by the drive unit, and transmit the control voltage to the drive unit.

[0039] The isolation unit receives the adjusted signal output by the drive unit.

[0040] In the above scheme, the control unit includes a delay unit, a subtractor, an absolute value unit, a comparator, a switch selector, and a multiplier.

[0041] In the above scheme, the delay unit is used to determine the amplitude of the previous signal adjacent to the current signal;

[0042] The subtractor is used to determine the actual amplitude difference between the current signal and the previous signal;

[0043] The absolute value unit is used to determine the absolute value of the actual amplitude difference;

[0044] The comparator and switch selector are used to determine the ideal amplitude difference based on the absolute value of the actual amplitude difference;

[0045] The subtractor is also used to determine the difference between the actual amplitude difference and the ideal amplitude difference;

[0046] The multiplier is used to determine the control level based on the difference between the actual amplitude difference and the ideal amplitude difference, and the product of the ideal amplitude difference;

[0047] The direction of change in the control level is determined by the sign of the actual amplitude difference.

[0048] In the above scheme, the comparator and switch selector are specifically used for:

[0049] The comparator determines the condition information that the actual amplitude difference satisfies the first, second, and third conditions; the condition information includes 3 binary digits, each of which corresponds to whether the corresponding condition is met, and is 1 if met and 0 if not.

[0050] The switch selector closes or opens the switch based on the condition information; the ideal amplitude difference is determined based on the result of the switch selector closing or opening the switch.

[0051] In the above scheme, the first condition includes that the actual amplitude difference is less than a first threshold.

[0052] The second condition includes that the actual amplitude difference is less than the second threshold.

[0053] The third condition includes that the actual amplitude difference is less than the third threshold; where the first threshold is less than the second threshold, and the second threshold is less than the third threshold.

[0054] In the above scheme, the comparator and switch selector are specifically used for:

[0055] The ideal amplitude difference is determined based on the absolute value of the actual amplitude difference; specifically, this includes:

[0056] The comparator determines the ideal amplitude difference to be less than or equal to a preset threshold.

[0057] The switch selector is used to determine whether the switch is open or closed based on the ideal amplitude difference.

[0058] In the above scheme, in response to a four-level pulse amplitude modulation signal, the ideal amplitude difference includes one of 2, 4, and 6.

[0059] According to a second aspect of this disclosure, a signal amplitude adjustment method is provided, implemented based on the aforementioned signal amplitude adjustment device, the method comprising:

[0060] The actual amplitude difference is determined based on the amplitude of the current signal and the amplitude of the previous signal;

[0061] The ideal amplitude difference is determined based on the actual amplitude difference;

[0062] The control voltage is determined based on the actual amplitude difference and the ideal amplitude difference;

[0063] The resistance value of the load resistor is adjusted based on the control voltage so that the amplitude of the signal is adjusted to the target amplitude after the signal passes through the drive unit including the load resistor.

[0064] According to a third aspect of this disclosure, an electronic device is provided, comprising:

[0065] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to control the apparatus of this disclosure to perform a signal amplitude adjustment function, or to perform the method of this disclosure.

[0066] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided that stores computer instructions for causing the computer to control the apparatus of this disclosure to perform a signal amplitude adjustment function or to execute the method described in this disclosure.

[0067] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, controls the apparatus of this disclosure to perform a signal amplitude adjustment function or to execute the method described in this disclosure.

[0068] The signal amplitude adjustment device disclosed herein achieves signal amplitude adjustment through a driving unit including a three-stage current-mode differential amplifier. Each stage of the current-mode differential amplifier includes two field-effect transistors (FETs) and two load resistors. Each load resistor includes a first FET, a second FET, a third FET, and a first resistor. The first FET acts as a control transistor for the load resistor, controlling the resistances of the second and third FETs. The second FET is connected in series with the first resistor to isolate the control voltage from the first resistor. The third FET is connected in parallel with the first resistor. Thus, the resistance value of the load resistor can be adjusted by controlling the voltage, so that the signal amplitude is adjusted to the target amplitude after passing through the driving unit including the three-stage current-mode differential amplifier.

[0069] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0070] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which:

[0071] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0072] Figure 1 The eye diagram of an ideal PAM4 signal is shown;

[0073] Figure 2 The eye diagram of the actual received signal is shown;

[0074] Figure 3 A schematic diagram of a first optional structure of the signal amplitude adjustment device provided in this embodiment of the present disclosure is shown;

[0075] Figure 4 A schematic diagram of a second optional structure of the signal amplitude adjustment device provided in an embodiment of this disclosure is shown;

[0076] Figure 5 A schematic diagram of a third optional structure of the signal amplitude adjustment device provided in this disclosure embodiment is shown;

[0077] Figure 6A circuit diagram of a driving unit in the related art is shown;

[0078] Figure 7 A schematic diagram of a fourth optional structure of the signal amplitude adjustment device provided in this disclosure embodiment is shown;

[0079] Figure 8 A schematic diagram of a fifth optional structure of the signal amplitude adjustment device provided in this disclosure embodiment is shown;

[0080] Figure 9 A schematic diagram of an optional flow of the signal amplitude adjustment method provided in an embodiment of this disclosure is shown;

[0081] Figure 10 A schematic diagram of the transition process provided in an embodiment of this disclosure is shown;

[0082] Figure 11 A schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0083] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0084] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0085] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0086] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0087] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0088] Table 1 shows the correspondence between PAM4 signals and NRZ signals.

[0089] Table 1

[0090]

[0091] In Table 1, "0" in the NRZ signal represents a low level, i.e., -1; "1" represents a high level, i.e., 1. Taking PAM4 "11" as an example, the amplitude of the upper branch NRZ signal is multiplied by 2, and the amplitude of the lower branch NRZ signal is multiplied by 1 to form the PAM4 "11" level, that is, 1×2+1×1=3; taking PAM4 "10" as an example, the amplitude of the upper branch NRZ signal is multiplied by 2, and the amplitude of the lower branch NRZ signal is multiplied by 1 to form the PAM4 "10" level, that is, 1×2+(-1)×1=1; taking PAM4 "01" as an example, the amplitude of the upper branch NRZ signal is multiplied by 2, and the amplitude of the lower branch NRZ signal is multiplied by 1 to form the PAM4 "01" level, that is, (-1)×2+1×1=-1; taking PAM4 "00" as an example, the amplitude of the upper branch NRZ signal is multiplied by 2, and the amplitude of the lower branch NRZ signal is multiplied by 1 to form the PAM4 "01" level, that is, (-1)×2+(-1)×1=-3.

[0092] Figure 1 The eye diagram of an ideal PAM4 signal is shown. Figure 2 The eye diagram of the actual received signal is shown.

[0093] like Figure 1 As shown in Figure 2, there are 12 level transitions in the PAM4 signal: 3 to 1, 3 to -1, 3 to -3, 1 to 3, 1 to -1, 1 to -3, -1 to 3, -1 to 1, -1 to 3, -3 to 3, -3 to 1, and -3 to -1. After level normalization, the transitions include: 1 to 1 / 3, 1 to -1 / 3, 1 to -1, 1 / 3 to 1, 1 / 3 to -1 / 3, 1 / 3 to -1, -1 / 3 to 1, -1 / 3 to 1, -1 / 3 to 1, -1 / 3 to 1, -1 / 3 to 1, -1 to 1, -1 to 1 / 3, and -1 to -1 / 3.

[0094] During data transmission, the absolute value of the difference between two consecutive signals may be 2, 4, or 6. In traditional high-speed link interfaces, PAM4 signals are driven and transmitted by only a driver, which is insufficient to meet the crossover requirements of various level transitions in PAM4 signals. The level transitions between two signals limit the eye diagram opening or noise margin, making PAM4 signals applicable only to interconnect interfaces in low-computing-power scenarios.

[0095] To address the shortcomings of related technologies, this disclosure provides a signal amplitude adjustment device that integrates a mathematical calculation unit and the on-resistance characteristics of a field-effect transistor (MOSFET). It utilizes the amplitude difference between adjacent signal transitions to achieve adjustable load resistance for the driving unit. Simultaneously, while using parallel and series connections of MOSFETs to achieve adjustable load resistance, it also isolates the control voltage from the passive resistor, improving impedance stability. This disclosure utilizes an adjustable load resistor to achieve variable PAM4 signal amplitude based on different level transitions, thereby improving PAM4 transmission quality and meeting the speed and reliability requirements of high-computing-power applications. It is suitable for chip-to-chip (C2C), chip-to-module (C2M), and die-to-die (D2D) interconnects.

[0096] Figure 3 A schematic diagram of a first alternative structure of the signal amplitude adjustment device provided in an embodiment of this disclosure is shown, and will be described in terms of each part.

[0097] Figure 3 The diagram shows an optional structure of the load resistor in the drive unit included in the signal amplitude adjustment device.

[0098] like Figure 3 As shown, the load resistor includes the first field-effect transistor (FET). ), second field-effect transistor ( ), third field-effect transistor ( ) and the first resistor (R1); wherein, the first field-effect transistor ( ), second field-effect transistor ( ), third field-effect transistor ( The resistance values ​​of the first resistor (R1) and the first resistor (R2) can be set according to actual needs or experimental results.

[0099] The gate of the first field-effect transistor is used to receive the control voltage ( The source of the first field-effect transistor is connected to the gate of the second field-effect transistor and the gate of the third field-effect transistor, respectively, and the drain of the first field-effect transistor outputs the adjusted signal.

[0100] The source of the second field-effect transistor outputs the adjusted signal, and the drain of the second field-effect transistor is connected to the first terminal of the first resistor and the drain of the third field-effect transistor, respectively.

[0101] The source of the third field-effect transistor is connected to the drain of the field-effect transistor in the current-mode differential amplifier.

[0102] The second end of the first resistor is connected to the drain of the field-effect transistor in the current-mode differential amplifier.

[0103] The first field-effect transistor (FET) is a control transistor for the load resistor, used to control the resistance of the second and third FETs. The second FET is connected in series with the first resistor to isolate the control voltage from the first resistor. The third FET is connected in parallel with the first resistor. The resistance value of the load resistor is adjusted by inputting the control voltage so that the amplitude of the signal is adjusted to the target amplitude after the signal passes through the driving unit including the three-stage current-mode differential amplifier.

[0104] The control voltage is determined based on the current signal, the amplitude of the previous signal, and the corresponding ideal amplitude difference. That is, different amplitudes of the current signal and / or the previous signal result in different control voltages.

[0105] In some embodiments, the resistance value of the load resistor is determined based on the resistance values ​​of the second field-effect transistor, the third field-effect transistor, and the first resistor; while the resistance values ​​of the second and third field-effect transistors are determined based on the control voltage.

[0106] In specific implementation, the resistance value of each load resistor includes the sum of the parallel connection of the first resistor and the resistance of the third field-effect transistor, and the resistance value of the second field-effect transistor, that is:

[0107]

[0108] in, The resistance value characterizing the load resistance. Characterizing the resistance of the second field-effect transistor, The resistance value characterizing the load resistance. Characterizing the resistance of the third field-effect transistor, " is the operator for parallel resistor connection.

[0109] In some embodiments, the first field-effect transistor and the third field-effect transistor are N-channel field-effect transistors; the second field-effect transistor is a P-channel field-effect transistor.

[0110] Figure 4 A schematic diagram of a second optional structure of the signal amplitude adjustment device provided in an embodiment of this disclosure is shown.

[0111] Figure 4 The diagram shows an optional structure of the current-mode differential amplifier included in the drive unit of the signal amplitude adjustment device.

[0112] like Figure 4 As shown, the current-mode differential amplifier includes two identical load resistors (R'), namely the first load resistor and the second load resistor, and its structure is as follows. Figure 3 As shown; the current-mode differential amplifier also includes a fourth field-effect transistor (FET). ) and the fifth field-effect transistor ( ).

[0113] In some embodiments, the gates of the fourth and fifth field-effect transistors are connected to the current signal ( ), so that after the signal passes through the three-stage current-mode differential amplifier, the signal ( The amplitude of the target amplitude is adjusted.

[0114] The source terminals of the fourth and fifth field-effect transistors are connected to the operating power supply. The drain of the fourth field-effect transistor is connected to the first terminal of the first load resistor; the drain of the fifth field-effect transistor is connected to the first terminal of the second load resistor; the second terminal of the first load resistor is connected to the second terminal of the second load resistor, and is also connected to the second terminal of the load resistor of other current-mode differential amplifiers.

[0115] In some embodiments, combined with Figure 3 The second terminal of the first resistor in the first load resistor and the source of the third field-effect transistor correspond to the first terminal of the first load resistor; the drain of the first field-effect transistor and the source of the second field-effect transistor correspond to the second terminal of the first load resistor.

[0116] Furthermore, the drain of the fourth field-effect transistor is connected to the second terminal of the first resistor in the first load resistor and the source of the third field-effect transistor; the drain of the fifth field-effect transistor is connected to the second terminal of the first resistor in the second load resistor and the source of the third field-effect transistor.

[0117] In some embodiments, the fourth and fifth field-effect transistors are N-channel field-effect transistors.

[0118] In some embodiments, in any current-mode differential amplifier, the first terminal of the first load resistor and the first terminal of the second load resistor output signals with adjusted amplitudes. ).

[0119] Figure 5 A schematic diagram of a third optional structure of the signal amplitude adjustment device provided in this disclosure embodiment is shown, and will be described in terms of each part.

[0120] Figure 5The diagram shows an optional structure of the drive unit in the signal amplitude adjustment device.

[0121] The driving unit includes a triode current-mode differential amplifier and a sixth field-effect transistor. 7th Field-Effect Transistor and the eighth field-effect transistor The structure of the current-mode differential amplifier is as follows: Figure 4 As shown.

[0122] like Figure 5 As shown, the gates of the sixth, seventh, and eighth field-effect transistors are connected to the operating power supply; the drain of the sixth field-effect transistor is connected to the source of the two field-effect transistors in the corresponding current-mode differential amplifier, and the source of the sixth field-effect transistor is grounded; the drain of the seventh field-effect transistor is connected to the source of the two field-effect transistors in the corresponding current-mode differential amplifier, and the source of the seventh field-effect transistor is grounded; the drain of the eighth field-effect transistor is connected to the source of the two field-effect transistors in the corresponding current-mode differential amplifier, and the source of the eighth field-effect transistor is grounded.

[0123] In some embodiments, the gate access signals of the fourth and fifth field-effect transistors included in each current-mode differential amplifier are ( In any current-mode differential amplifier, the first terminal of the first load resistor and the first terminal of the second load resistor output signals with adjusted amplitudes. ).

[0124] In some embodiments, the sixth, seventh, and eighth field-effect transistors are all N-channel field-effect transistors.

[0125] Figure 6 A circuit diagram of a driving unit in the related art is shown.

[0126] like Figure 6 As shown, the driving unit in the related technology includes a triode current-mode differential amplifier. Each current-mode differential amplifier includes two resistors and two field-effect transistors. The difference is that the resistors in the differential amplifier in the related technology are fixed-value resistors, which cannot be adjusted according to the amplitude of the signal or the amplitude difference between two adjacent signals.

[0127] Figure 7 A schematic diagram of a fourth optional structure of the signal amplitude adjustment device provided in the embodiments of this disclosure is shown, and will be described in terms of each part.

[0128] like Figure 7As shown, the signal amplitude adjustment device includes a driving unit, an isolation unit, and a control unit. The control unit determines the control voltage based on the current signal amplitude; the isolation unit shields the signal output by the driving unit from external interference.

[0129] In some embodiments, the driving unit is used to receive a signal and adjust the amplitude of the signal based on the control voltage input by the control unit, so that the amplitude of the signal is adjusted to a target amplitude; the control unit is connected to the output terminal of the driving unit and is used to acquire the signal output by the driving unit, determine the control voltage based on two adjacent signals output by the driving unit, and transmit the control voltage to the driving unit; the isolation unit receives the adjusted signal output by the driving unit.

[0130] In some embodiments, the control unit can receive signals of different voltages, select a suitable voltage signal based on adjacent input signals, and generate a control voltage.

[0131] Figure 8 A schematic diagram of a fifth optional structure of the signal amplitude adjustment device provided in the embodiments of this disclosure is shown, and will be described in terms of each part.

[0132] like Figure 8 The diagram shows the structure of the control unit, which includes a delay unit (T), a subtractor (-), and an absolute value unit (T). ), comparator, switch selector and multiplier (×).

[0133] In specific implementation, the delay unit is used to determine the amplitude of the previous signal adjacent to the current signal; the subtractor is used to determine the actual amplitude difference between the current signal and the previous signal; the absolute value unit is used to determine the absolute value of the actual amplitude difference; the comparator and switch selector are used to determine the ideal amplitude difference based on the absolute value of the actual amplitude difference; the subtractor is also used to determine the difference between the actual amplitude difference and the ideal amplitude difference; the multiplier is used to determine the value of the control level based on the product of the difference between the actual amplitude difference and the ideal amplitude difference, and the ideal amplitude difference; and the direction of change of the control level is determined based on the sign of the actual amplitude difference.

[0134] In some embodiments, the signal output by the drive unit is obtained through a delay. and the preceding signal adjacent to this signal. The signal and the preceding signal adjacent to this signal The input is fed into the subtractor to obtain the actual amplitude difference. ; to the actual amplitude difference The absolute value is input into the absolute value unit to obtain the absolute value of the actual amplitude difference. The ideal amplitude difference is determined based on the absolute value of the actual amplitude difference, a comparator, and a switch selector; the ideal amplitude difference is determined based on the absolute value of the actual amplitude difference. The difference between the two values ​​is determined by subtracting the difference from the ideal amplitude, and the value of the control level is determined by multiplying the difference between the two values ​​and the ideal amplitude difference.

[0135] In some embodiments, the direction of change of the control level is determined based on the sign of the actual amplitude difference; specifically, if the actual amplitude difference is positive, the direction of change of the control level is increasing, and if the actual amplitude difference is negative, the direction of change of the control level is negative.

[0136] In specific implementation, the comparator and switch selector are used to: determine the condition information that the actual amplitude difference satisfies the first, second, and third conditions based on the comparator; the condition information includes 3 binary digits, each binary digit corresponding to whether the corresponding condition is met, if met is 1, otherwise not met is 0; the switch selector closes or opens the switch based on the condition information; and the ideal amplitude difference is determined based on the result of the switch selector closing or opening the switch.

[0137] The first condition includes that the actual amplitude difference is less than a first threshold; the second condition includes that the actual amplitude difference is less than a second threshold; and the third condition includes that the actual amplitude difference is less than a third threshold. The first threshold is less than the second threshold, and the second threshold is less than the third threshold.

[0138] Furthermore, each binary digit in the condition information corresponds to whether a condition is met. For example, the first binary digit indicates whether the first condition is met; if it is 1, it means that the condition is met, and if it is 0, it means that the condition is not met. The second binary digit indicates whether the second condition is met; if it is 1, it means that the condition is met, and if it is 0, it means that the condition is not met. The third binary digit indicates whether the third condition is met; if it is 1, it means that the condition is met, and if it is 0, it means that the condition is not met.

[0139] Taking PAM4 as an example, the first threshold can be set to 2, the second threshold to 4, and the third threshold to 6, as shown in Table 2.

[0140] Table 2

[0141]

[0142] The first series of characteristics satisfies the first condition; the second series of characteristics satisfies the second condition; the third series of characteristics satisfies the third condition; the fourth series of characteristics is the range of the absolute value of the actual amplitude difference; and the fifth series of characteristics is the level of the ideal amplitude difference corresponding to the actual amplitude difference, where Vl represents 2, Vm represents 4, and Vb represents 6.

[0143] Taking an actual amplitude difference of -2.1 as an example, its absolute value is 2.1, which is less than 4 and less than 6, indicating that the second and third conditions are met, but the first condition is not met. Therefore, the corresponding value is 011, and the ideal amplitude difference level is Vm, which is 4. Furthermore, the corresponding control voltage includes (4-2.1)×2.1.

[0144] In other embodiments, the ideal amplitude difference that may be possible under ideal conditions can be determined in advance. For example, under PAM4 modulation, the ideal amplitude difference includes 2, 4, and 6. The ideal amplitude difference that is closest to the absolute value of the actual amplitude difference is further determined as the ideal amplitude difference corresponding to the actual amplitude difference.

[0145] Furthermore, the comparator determines an ideal amplitude difference that is less than or equal to a preset threshold; the switch selector is used to determine whether the corresponding voltage switch is open or closed based on the ideal amplitude difference.

[0146] Taking the actual amplitude difference as an example of -2.1, its absolute value is 2.1. The closest ideal amplitude difference is 2, so the corresponding control voltage is (2.1-2)×2.1.

[0147] Figure 9 A schematic diagram of an optional process for a signal amplitude adjustment method provided in an embodiment of this disclosure is shown, and the process will be described step by step.

[0148] Step S901: Determine the actual amplitude difference based on the amplitude of the current signal and the amplitude of the previous signal.

[0149] Step S902: Determine the ideal amplitude difference based on the actual amplitude difference.

[0150] Step S903: Determine the control voltage based on the actual amplitude difference and the ideal amplitude difference.

[0151] Step S904: Adjust the resistance value of the load resistor based on the control voltage.

[0152] In some embodiments, the control unit determines the actual amplitude difference based on the amplitude of the current signal and the amplitude of the previous signal, and determines the ideal amplitude difference based on the actual amplitude difference; determines the control voltage based on the actual amplitude difference and the ideal amplitude difference; and inputs the control voltage to the load resistor in the current-mode differential amplifier included in the drive unit to adjust the resistance value of the load resistor so that the amplitude of the signal is adjusted to the target amplitude after the signal passes through the drive unit including the load resistor.

[0153] Figure 10 A schematic diagram of the transition process provided in an embodiment of this disclosure is shown.

[0154] like Figure 10 As shown in (a), the transition process includes the jump from -3 to -1, 1, and 3, as follows: Figure 10As shown in (b), the transition process includes the jump from 3 to -1, 1, and -3, as follows: Figure 10 As shown in (c), the transition process includes the jump from -1 to -3, 1, and 3, as follows: Figure 10 As shown in (d), the transition process includes the jump from 3 to -1, 1, and -3.

[0155] refer to Figure 1 and Figure 2 In an eye diagram, to increase the eye opening, ideally, during signal transmission, when a change in signal value causes a level transition, the shorter the transition process, the better. Alternatively, the transition process can be viewed as a diagonal line, with a steeper slope being preferable. For example... Figure 10 The diagram illustrates the signal transition process. In some cases, the signal needs to transition from -3 to 3, while in others it needs to transition from 1 to -1. Large transition spans result in prolonged transition times, affecting the eye diagram opening. For example... Figure 1 The image shown is an ideal eye diagram, such as... Figure 2 As shown, due to the excessively long transition time, the change line has a certain slope, instead of being as shown... Figure 1 The value is close to infinity. Therefore, in order to shorten the transition time, the main purpose of this embodiment is to judge the signal level transition result in advance and adjust the level directly to the ideal result. For example, if the input signal is 1.2, its corresponding ideal level is 1. Then, the driving unit adjusts the 1.2 signal to 1 to achieve the ideal transition effect in advance.

[0156] Based on this, the embodiments of this disclosure cleverly integrate a simple mathematical calculation unit and the on-resistance characteristics of a MOSFET to realize an amplitude-adjustable PAM4 driver unit. It can distinguish and process different level transitions, improving the transitions between adjacent signals. Furthermore, by utilizing changes in resistance impedance, it achieves variable signal amplitude, enhancing the transmission performance of the PAM4 signal. In addition, the series-parallel connection of the MOSFET isolates the control voltage, avoiding the influence of the control voltage on the load resistance, greatly satisfying the interconnection requirements of high-performance computing scenarios.

[0157] In some embodiments, the signal is a PAM4 signal, for example.

[0158] In some embodiments, the signal amplitude adjustment device includes at least a variable impedance drive unit, an isolation unit, and a control unit.

[0159] The control unit receives the PAM4 signal output by the drive unit, monitors the amplitude difference between adjacent signals, and changes the amplitude of the signal in the driver by changing the amplitude difference, thereby speeding up or slowing down the signal edge transition.

[0160] The amplitude difference between adjacent signals is compared with the amplitude difference between adjacent signals in an ideal signal to adjust the control voltage of the control unit.

[0161] The drive unit is an improved version of the traditional structure, controlled by the control unit to change the load impedance.

[0162] The load impedance also incorporates MOS series and parallel connections, which not only enables adjustable load impedance but also isolates the influence of voltage on impedance transformation, enhancing impedance stability.

[0163] An isolation unit is an isolation network composed of resistors and capacitors to shield the output signal of the drive unit from the influence of external signals.

[0164] Specifically, such as Figure 6 As shown, the related technology consists of three identical current-mode differential amplifiers cascaded together, with the drive current increased by a tail current transistor, and the drive current controlled by Vctrl. In such... Figure 5 In the embodiment shown in this disclosure, the load resistor is composed of passive resistors, and the drive current and the load resistor form the level of the output signal.

[0165] like Figure 5 As shown, the difference from traditional drive units lies in the variability of the load resistance. This variability is achieved through the series or parallel connection of MOSFETs, such as... Figure 3 As shown. In Figure 3 middle, The tube is used as the control tube for the variable resistor. The transistor acts as a switch connected in series with the first resistor R1 (a passive resistor), and its resistance... by The control tube achieves isolation between Vctrl and the passive resistor R, avoiding... The effect on resistance impedance; The transistor acts as a switch connected in parallel with the first resistor R1, and its resistance... Controlled by transistor M1. Total load impedance. for

[0166]

[0167] Control voltage of load resistor The result is obtained by comparing the output signal of the drive unit with the ideal signal.

[0168] Before obtaining the control voltage, Figure 10 The diagram illustrates the level transition process in a PAM4 signal, including four cases, each with three transitions, for a total of twelve transitions. Figure 10 (a) and Figure 10 In (b), the absolute values ​​of the level differences between adjacent levels are 2, 4, and 6; Figure 10 (c) and Figure 10In (d), the absolute values ​​of the level differences between adjacent levels are 2 and 4. Overall, the absolute values ​​of the level differences are 2, 4, and 6. Figure 7 The Vl, Vm, and Vb values ​​of the control unit are 2, 4, and 6, respectively.

[0169] The control unit includes simple calculation modules such as timers, subtractors, absolute value generators, comparators, switch selectors, and multipliers.

[0170] In the control unit, the level difference between adjacent signals in the output signal of the drive unit is realized by using a delay unit and a subtractor, i.e., AD(n).

[0171] In the control unit, the level difference AD(n) between consecutive signals represents... The direction of change is determined by comparing the absolute value of ADP(n) with the level differences (Vl, Vm, and Vb) of the ideal signal. A suitable ideal level difference is selected, and the difference e between the actual level difference and the ideal level difference is calculated and multiplied by the actual level difference to output the result. This controls the load resistance, and thus the amplitude of the signal.

[0172] Taking the 1-to--1 transition as an example, when the actual level difference is -2.1 and the selected ideal level difference is 4, the difference e between the absolute value of the actual level difference and the ideal level difference is 1.9. The control voltage is obtained by multiplying these values. The larger the difference e, the larger the control voltage.

[0173] As shown in Table 2, when the actual level difference is less than 2, the comparator outputs a high level, i.e., 1; otherwise, it outputs a low level, i.e., 0. Since the actual level difference is less than 2, it is definitely less than 4 and 6. The ideal level difference is chosen as Vl.

[0174] By changing the impedance of the load resistor, the level amplitude of the PAM4 signal can be adjusted to approach the ideal PAM4 signal, thereby changing the quality of the PAM4 signal.

[0175] According to embodiments of this disclosure, this disclosure also provides an electronic device and a readable storage medium.

[0176] Figure 11 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0177] like Figure 11 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0178] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0179] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as signal amplitude adjustment methods, or implements signal amplitude adjustment functions based on signal amplitude adjustment devices. For example, in some embodiments, the signal amplitude adjustment method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the signal amplitude adjustment method described above can be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform a signal amplitude adjustment method by any other suitable means (e.g., by means of firmware).

[0180] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0181] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0182] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0183] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0184] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0185] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0186] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0187] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0188] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A signal amplitude adjustment device, characterized in that, The device includes: a drive unit, a control unit, and an isolation unit; The control unit includes a delay unit, a subtractor, an absolute value unit, a comparator, a switch selector, and a multiplier; it is used to determine the control voltage based on the amplitude of the current signal. The delay unit is used to determine the amplitude of the preceding signal adjacent to the current signal; the subtractor is used to determine the actual amplitude difference between the current signal and the preceding signal; the absolute value unit is used to determine the absolute value of the actual amplitude difference; the comparator and switch selector are used to determine the ideal amplitude difference based on the absolute value of the actual amplitude difference; the subtractor is also used to determine the difference between the actual amplitude difference and the ideal amplitude difference; the multiplier is used to determine the value of the control level based on the product of the difference between the actual amplitude difference and the ideal amplitude difference, and the ideal amplitude difference; the direction of change of the control level is determined based on the sign of the actual amplitude difference. The comparator and switch selector are specifically used for: determining, based on the comparator, condition information that the actual amplitude difference satisfies the first, second, and third conditions; the condition information includes 3 binary digits, each binary digit corresponding to whether the corresponding condition is met, 1 if met, and 0 if not met; the switch selector closes or opens the switch based on the condition information; and determining the ideal amplitude difference based on the result of the switch selector closing or opening the switch. The first condition includes that the actual amplitude difference is less than a first threshold; the second condition includes that the actual amplitude difference is less than a second threshold; the third condition includes that the actual amplitude difference is less than a third threshold; wherein the first threshold is less than the second threshold, and the second threshold is less than the third threshold. The isolation unit is used to shield the signal output by the drive unit from interference from external signals; The driving unit includes a three-stage current-mode differential amplifier; each stage of the current-mode differential amplifier includes two field-effect transistors and two load resistors; Each load resistor includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a first resistor; The gate of the first field-effect transistor is used to receive the control voltage. The source of the first field-effect transistor is connected to the gate of the second field-effect transistor and the gate of the third field-effect transistor respectively. The drain of the first field-effect transistor outputs the adjusted signal. The source of the second field-effect transistor outputs the adjusted signal, and the drain of the second field-effect transistor is connected to the first terminal of the first resistor and the drain of the third field-effect transistor, respectively. The source of the third field-effect transistor is connected to the drain of the field-effect transistor in the current-mode differential amplifier. The second end of the first resistor is connected to the drain of the field-effect transistor in the current-mode differential amplifier; The first field-effect transistor (FET) is a control transistor for the load resistor, used to control the resistance of the second and third FETs. The second FET is connected in series with the first resistor to isolate the control voltage from the first resistor. The third FET is connected in parallel with the first resistor. The resistance value of the load resistor is adjusted by inputting the control voltage so that the amplitude of the signal is adjusted to the target amplitude after the signal passes through the driving unit including the three-stage current-mode differential amplifier.

2. The apparatus according to claim 1, characterized in that, The resistance value of each load resistor is determined based on the resistance values ​​of the second field-effect transistor, the third field-effect transistor, and the first resistor.

3. The apparatus according to claim 2, characterized in that, The resistance value of each load resistor includes the sum of the resistance value of the first resistor and the resistance value of the third field-effect transistor connected in parallel, and the resistance value of the second field-effect transistor.

4. The apparatus according to claim 1, characterized in that, The first field-effect transistor and the third field-effect transistor are N-channel field-effect transistors; The second field-effect transistor is a P-channel field-effect transistor.

5. The apparatus according to claim 1, characterized in that, In any of the aforementioned current-mode differential amplifiers: The gates of the fourth and fifth field-effect transistors are connected to the current signal so that the amplitude of the signal is adjusted to the target amplitude after passing through the three-stage current-mode differential amplifier. The source stages of the fourth and fifth field-effect transistors are connected to the operating power supply; The drain of the fourth field-effect transistor is connected to the first terminal of the first load resistor; The drain of the fifth field-effect transistor is connected to the first terminal of the second load resistor; The second end of the first load resistor is connected to the second end of the second load resistor, and the second end of the load resistors of other current-mode differential amplifiers is also connected to it.

6. The apparatus according to claim 5, characterized in that, In the first load resistor, the second end of the first resistor and the source of the third field-effect transistor correspond to the first end of the first load resistor; In the first load resistor, the drain of the first field-effect transistor and the source of the second field-effect transistor correspond to the second terminal of the first load resistor.

7. The apparatus according to claim 5, characterized in that, The drain of the fourth field-effect transistor is connected to the second terminal of the first resistor in the first load resistor, and to the source of the third field-effect transistor. The drain of the fifth field-effect transistor is connected to the second terminal of the first resistor in the second load resistor, and to the source of the third field-effect transistor.

8. The apparatus according to claim 5, characterized in that, The fourth and fifth field-effect transistors are N-channel field-effect transistors.

9. The apparatus according to claim 1, characterized in that, The driving unit also includes a sixth field-effect transistor, a seventh field-effect transistor, and an eighth field-effect transistor; The gates of the sixth, seventh, and eighth field-effect transistors are respectively connected to the operating power supply. The drain of the sixth field-effect transistor is connected to the source of the two field-effect transistors in the corresponding current-mode differential amplifier, and the source of the sixth field-effect transistor is grounded. The drain of the seventh field-effect transistor is connected to the source of the two field-effect transistors in the corresponding current-mode differential amplifier, and the source of the seventh field-effect transistor is grounded. The drain of the eighth field-effect transistor is connected to the source of the two field-effect transistors in the corresponding current-mode differential amplifier, and the source of the eighth field-effect transistor is grounded.

10. The apparatus according to claim 9, characterized in that, The sixth, seventh, and eighth field-effect transistors are all N-channel field-effect transistors.

11. The apparatus according to claim 1, characterized in that, The driving unit is used to receive signals and adjust the amplitude of the signals based on the control voltage input by the control unit, so that the amplitude of the signals is adjusted to the target amplitude. The control unit is connected to the output terminal of the drive unit, and is used to acquire the signal output by the drive unit, determine the control voltage based on two adjacent signals output by the drive unit, and transmit the control voltage to the drive unit. The isolation unit receives the adjusted signal output by the drive unit.

12. The apparatus according to claim 1, characterized in that, The comparator and switch selector are specifically used for: The ideal amplitude difference is determined based on the absolute value of the actual amplitude difference; specifically, this includes: The comparator determines the ideal amplitude difference to be less than or equal to a preset threshold. The switch selector is used to determine whether the switch is open or closed based on the ideal amplitude difference.

13. The apparatus according to claim 1, characterized in that, In response to a four-level pulse amplitude modulation signal, the ideal amplitude difference includes one of 2, 4, or 6.

14. A method for adjusting signal amplitude, characterized in that, Based on the apparatus according to any one of claims 1 to 13, the method comprises: The actual amplitude difference is determined based on the amplitude of the current signal and the amplitude of the previous signal; The ideal amplitude difference is determined based on the actual amplitude difference; The control voltage is determined based on the actual amplitude difference and the ideal amplitude difference; The resistance value of the load resistor is adjusted based on the control voltage so that the amplitude of the signal is adjusted to the target amplitude after the signal passes through the drive unit including the load resistor.

15. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to control the device according to any one of claims 1-13 to perform a signal amplitude adjustment function; Alternatively, implement the method of claim 14.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to enable the computer to control the device according to any one of claims 1-13 to perform the signal amplitude adjustment function; Alternatively, implement the method of claim 14.

17. A computer program product, characterized in that, Includes a computer program, which, when executed by a processor, controls the device according to any one of claims 1-13 to perform a signal amplitude adjustment function; Alternatively, implement the method of claim 14.

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