Control circuit and chip of switching tube

Abstract

The embodiment of the invention provides a switch tube control circuit and a chip. The switch tube control circuit comprises a main controller, a plurality of acquisition circuits respectively connected with a plurality of parallel switch tubes, and a plurality of driving circuits respectively connected with the plurality of switch tubes, the acquisition circuit comprises a sampling resistor connected with the corresponding switch tube; the acquisition circuit is used for acquiring a voltage value of the sampling resistor and generating an indication signal; the main controller is used for determining the current turn-on delay time and the current turn-off delay time of the plurality of switching tubes according to the indication signal; and the main controller determines whether the plurality of switch tubes are in a current unbalance state according to the current turn-on delay time, the current turn-off delay time and the voltage value of the sampling resistor, and adjusts a control signal sent to a driving circuit corresponding to at least one switch tube under the condition of current unbalance, so that the driving circuit drives the plurality of switch tubes according to the control signal. And adjusting the working parameters of the corresponding switch tubes, thereby enabling the plurality of parallel switch tubes to be in a current balance state.

Description

Technical Field

[0001] This invention relates to the field of power switching transistor technology, and in particular to a control circuit and chip for a switching transistor. Background Technology

[0002] With the widespread application of silicon carbide (SiC) power devices in electric vehicles, renewable energy generation, and other fields due to their high voltage withstand capability, low loss, and high-temperature operation, multiple SiC MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are often connected in parallel in high-current applications to reduce conduction losses and increase system power ratings. However, in practical applications, parallel-operated SiC MOSFETs suffer from uneven static current distribution and other issues. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a control circuit and chip for a switching transistor that overcomes or at least partially solves the above problems.

[0004] To address the aforementioned problems, this invention discloses a control circuit for switching transistors, comprising: a main controller, multiple acquisition circuits connected to multiple switching transistors in parallel, and multiple drive circuits connected to the multiple switching transistors. The acquisition circuit includes a sampling resistor connected to a corresponding switching transistor; the acquisition circuit is used to acquire the voltage value of the sampling resistor and generate an indication signal; the indication signal is used to indicate whether the corresponding switching transistor is on or off; the indication signal is determined based on the voltage value of the sampling resistor. The main controller is configured to determine the current turn-on delay time and current turn-off delay time of the plurality of switching transistors according to the indication signal; determine whether the plurality of switching transistors are in a current imbalance state according to the current turn-on delay time, the current turn-off delay time and the voltage value of the sampling resistor; if the plurality of switching transistors are in a current imbalance state, adjust the control signal sent to the drive circuit corresponding to at least one switching transistor. The driving circuit is used to adjust the operating parameters of the corresponding switching transistor according to the control signal.

[0005] Optionally, the acquisition circuit further includes an operational amplifier and an analog-to-digital converter, which are respectively connected to the sampling resistor; The operational amplifier is used to generate an indication signal; the indication signal is determined based on a comparison between the voltage value of the sampling resistor and a preset voltage. The analog-to-digital converter is used to convert the voltage value of the sampling resistor into a digital voltage signal and transmit the digital voltage signal to the main controller; The main controller is used to determine the current turn-on delay time and current turn-off delay time of the plurality of switching transistors according to the indication signal; and to determine whether the plurality of switching transistors are in a current imbalance state according to the current turn-on delay time, the current turn-off delay time and the digital voltage signal.

[0006] Optionally, when the voltage value of the sampling resistor is greater than or equal to a preset voltage, the indication signal is at a first level; when the voltage value of the sampling resistor is less than the preset voltage, the indication signal is at a second level. The plurality of switching transistors are used to respond to the control signals sent by the main controller and adjust their operating state to be on or off; The main controller is used to determine the moment when the indicator signal changes to the first level as the instantaneous turn-on time point in the turn-on interval of each switching transistor; and to determine the current turn-on delay time of each switching transistor based on the instantaneous turn-on time point and the rising edge of the control signal. In the turn-off interval of each switch, the time point at which the indicator signal changes to the second level is taken as the turn-off instantaneous time point; the current turn-off delay time of each switch is determined based on the turn-off instantaneous time point and the falling edge of the control signal. The corresponding output current is determined based on the digital voltage signal corresponding to each switching transistor; Based on the current turn-on delay time, the current turn-off delay time, and the output current of each switch, determine whether each switch is in a current imbalance state.

[0007] Optionally, the current imbalance state includes a dynamic current imbalance state; The main controller is configured to determine that the plurality of switching transistors are in a dynamic current imbalance state if the difference between the current turn-on delay time of any switching transistor and the current turn-on delay time of the other switching transistors is greater than a first preset threshold, and / or the difference between the current turn-off delay time of any switching transistor and the current turn-off delay time of the other switching transistors is greater than a second preset threshold.

[0008] Optionally, when the multiple switching transistors are in a state of dynamic current imbalance, the main controller is used to send an adjusted first control signal to the drive circuit corresponding to the switching transistor with a larger turn-on delay time; the drive circuit is used to reduce the resistance of the control terminal of the corresponding switching transistor during the turn-on process according to the first control signal, so as to reduce the turn-on delay time of the corresponding switching transistor.

[0009] Optionally, the control circuit includes an on-control branch; the on-control branch includes an on-variable resistor, which is used to reduce the resistance value of the on-variable resistor according to the first control signal, so as to reduce the resistance of the control terminal of the corresponding switch during the on-process and reduce the on-delay time of the corresponding switch.

[0010] Optionally, when the multiple switching transistors are in a state of dynamic current imbalance, the main controller is used to send an adjusted second control signal to the drive circuit corresponding to the switching transistor with a larger turn-off delay time; the drive circuit is used to reduce the resistance of the control terminal of the corresponding switching transistor during the turn-off process according to the second control signal, so as to reduce the turn-off delay time of the corresponding switching transistor.

[0011] Optionally, the drive circuit includes a shutdown control branch; The shutdown control branch includes a shutdown variable resistor, which is used to reduce the resistance value of the shutdown variable resistor according to the second control signal, so as to reduce the resistance of the control terminal of the corresponding switch during the shutdown process and reduce the shutdown delay time of the corresponding switch.

[0012] Optionally, the current imbalance state includes a static current imbalance state; The main controller is configured to determine that the plurality of switching transistors are in a static current imbalance state if the difference between the output current of any switching transistor and the output current of the other switching transistors is greater than a third preset threshold.

[0013] Optionally, when the multiple switching transistors are in a static current imbalance state, the main controller is used to send an adjusted third control signal to the drive circuit corresponding to the switching transistor with the smaller output current; the drive circuit is used to increase the drive voltage of the control terminal of the corresponding switching transistor according to the third control signal, so as to increase the output current of the corresponding switching transistor.

[0014] Optionally, the driving circuit includes a forward converter; the forward converter is used to increase the driving voltage of the control terminal of the corresponding switching transistor according to the third control signal.

[0015] Optionally, the main controller is configured to send an adjusted fourth control signal to the drive circuit corresponding to the switch with a larger output current after sending an adjusted third control signal to the drive circuit corresponding to the switch with a smaller output current, provided that the plurality of switches are still in a static current imbalance state; the drive circuit is configured to reduce the drive voltage at the control terminal of the corresponding switch according to the fourth control signal, so as to reduce the output current of the corresponding switch.

[0016] Accordingly, embodiments of the present invention disclose a chip including a control circuit for a switching transistor as described in any of the preceding claims.

[0017] The embodiments of the present invention have the following advantages: The control circuit for the switching transistors in this embodiment of the invention includes a main controller, multiple acquisition circuits connected to multiple parallel switching transistors, and multiple drive circuits connected to multiple switching transistors. Each acquisition circuit includes a sampling resistor connected to a corresponding switching transistor. The acquisition circuit is used to acquire the voltage value of the sampling resistor and generate an indication signal. The indication signal is used to indicate whether the corresponding switching transistor is on or off. The indication signal is determined based on the voltage value of the sampling resistor. The main controller is used to determine the current turn-on delay time and current turn-off delay time of the multiple switching transistors based on the indication signal. Based on the current turn-on delay time, current turn-off delay time, and voltage value of the sampling resistor, it determines whether the multiple switching transistors are in a current imbalance state. If the multiple switching transistors are in a current imbalance state, it adjusts the control signal sent to the drive circuit corresponding to at least one switching transistor. The drive circuit is used to adjust the operating parameters of the corresponding switching transistor based on the control signal. In this embodiment of the invention, the main controller determines whether multiple switching transistors are in a current imbalance state based on the current turn-on delay time, the current turn-off delay time, and the voltage value of the sampling resistor. If the current is imbalanced, the controller adjusts the control signal sent to the drive circuit corresponding to at least one switching transistor, so that the drive circuit adjusts the operating parameters of the corresponding switching transistor according to the control signal, thereby making the multiple parallel switching transistors in a current balanced state. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the control circuit for a switching transistor according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the acquisition circuit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a driving circuit according to an embodiment of the present invention.

[0019] Reference numerals: Main controller 10, switching transistor 20, acquisition circuit 30, sampling resistor 31, operational amplifier 32, first resistor 321, second resistor 322, analog-to-digital converter 33, drive circuit 40, turn-on control branch 41, turn-on variable resistor 411, gate turn-on resistor 412, turn-on diode 413, turn-off control branch 42, turn-off variable resistor 421, gate turn-off resistor 422, turn-off diode 423, forward converter 43. Detailed Implementation

[0020] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] With the widespread application of silicon carbide (SiC) power devices in electric vehicles, renewable energy generation, and other fields due to their high voltage withstand capability, low loss, and high-temperature operation, multiple SiC MOSFETs are often connected in parallel in high-current applications to reduce conduction losses and increase system power ratings. However, in practical applications, parallel-operated SiC MOSFETs suffer from uneven static current distribution and other issues.

[0022] One of the core concepts of this invention is that the main controller determines whether multiple switching transistors are in a current imbalance state based on the current turn-on delay time, the current turn-off delay time, and the voltage value of the sampling resistor. In the case of current imbalance, the controller adjusts the control signal sent to the drive circuit corresponding to at least one switching transistor, so that the drive circuit adjusts the operating parameters of the corresponding switching transistor according to the control signal, thereby making the multiple parallel switching transistors in a current balanced state.

[0023] Reference Figure 1 The diagram shows a schematic of a control circuit for a switching transistor according to an embodiment of the present invention, which may specifically include the following structure: The main controller 10, multiple acquisition circuits 30 connected to multiple parallel switching transistors 20, and multiple drive circuits 40 connected to multiple switching transistors 20.

[0024] The main controller 10 can be a digital controller based on FPGA (Field-Programmable Gate Array) technology. The FPGA can be programmed and configured by the user as needed after manufacturing to implement specific digital logic functions. The switching transistor 20 can be a SiC MOSFET.

[0025] The acquisition circuit 30 includes a sampling resistor 31 connected to the corresponding switching transistor 20; the acquisition circuit 30 is used to acquire the voltage value of the sampling resistor 31 and generate an indication signal; the indication signal is used to indicate whether the corresponding switching transistor 20 is on or off; the indication signal is determined based on the voltage value of the sampling resistor 31.

[0026] The sampling resistor 31, acting as a current sensor, can be a high-bandwidth, high-precision surface-mount resistor connected in series with the drain channel of the corresponding switching transistor 20 to accurately measure the drain current of the corresponding switching transistor 20. The sampling resistor 31 converts the drain current of the corresponding switching transistor 20 into a voltage. The voltage value of the sampling resistor 31 corresponds to the drain current of the corresponding switching transistor 20. The acquisition circuit 30 generates an indication signal based on the voltage value of the sampling resistor 31. The indication signal is used to indicate whether the corresponding switching transistor 20 is on or off.

[0027] The main controller 10 is used to determine the current turn-on delay time and current turn-off delay time of the multiple switching transistors 20 according to the indication signal; to determine whether the multiple switching transistors 20 are in a current imbalance state according to the current turn-on delay time, current turn-off delay time and voltage value of sampling resistor 31; if the multiple switching transistors 20 are in a current imbalance state, the control signal sent to the drive circuit 40 corresponding to at least one switching transistor is adjusted.

[0028] The main controller 10 is connected to each of the acquisition circuits 30 and each of the drive circuits 40. The main controller 10 receives the indication signals and the voltage values ​​of the sampling resistors 31 transmitted by each acquisition circuit 30. Based on the indication signals, it determines the current turn-on delay time and current turn-off delay time of each switching transistor 20. Based on the current turn-on delay time, current turn-off delay time, and voltage values ​​of the sampling resistors 31 corresponding to each switching transistor 20, it determines whether multiple switching transistors 20 are in a current imbalance state. If multiple switching transistors 20 are in a current imbalance state, it adjusts the control signal sent to the drive circuit 40 corresponding to at least one switching transistor 20 and sends the adjusted control signal to the drive circuit 40 corresponding to at least one switching transistor 20. The control signal can be PWM (Pulse Width Modulation), which can adjust the turn-on and turn-off times of the PWM signal, or it can adjust the gate-source voltage, gate resistance, etc., of the switching transistor 20.

[0029] The drive circuit 40 is used to adjust the operating parameters of the corresponding switching transistor 20 according to the control signal.

[0030] The drive circuit 40 can be an active gate driver (AGD). Compared with traditional static gate drivers (which provide a fixed voltage during switching and maintain a constant high / low level during conduction), active gate drivers can dynamically adjust gate drive parameters through real-time monitoring or preset strategies to optimize switching performance, improve efficiency, reduce losses, and enhance system reliability. The drive circuit 40 is driven by instructions from the main controller 10. According to the control signals from the main controller 10, it adjusts the operating parameters of the corresponding switching transistors 20 to achieve balanced current control, thereby ensuring that the multiple switching transistors 20 are in a current-balanced state.

[0031] The control circuit for the switching transistors in this embodiment of the invention includes a main controller, multiple acquisition circuits connected to multiple parallel switching transistors, and multiple drive circuits connected to multiple switching transistors. Each acquisition circuit includes a sampling resistor connected to a corresponding switching transistor. The acquisition circuit is used to acquire the voltage value of the sampling resistor and generate an indication signal. The indication signal is used to indicate whether the corresponding switching transistor is on or off. The indication signal is determined based on the voltage value of the sampling resistor. The main controller is used to determine the current turn-on delay time and current turn-off delay time of the multiple switching transistors based on the indication signal. Based on the current turn-on delay time, current turn-off delay time, and voltage value of the sampling resistor, it determines whether the multiple switching transistors are in a current imbalance state. If the multiple switching transistors are in a current imbalance state, it adjusts the control signal sent to the drive circuit corresponding to at least one switching transistor. The drive circuit is used to adjust the operating parameters of the corresponding switching transistor based on the control signal. In this embodiment of the invention, the main controller determines whether multiple switching transistors are in a current imbalance state based on the current turn-on delay time, the current turn-off delay time, and the voltage value of the sampling resistor. If the current is imbalanced, the controller adjusts the control signal sent to the drive circuit corresponding to at least one switching transistor, so that the drive circuit adjusts the operating parameters of the corresponding switching transistor according to the control signal, thereby making the multiple parallel switching transistors in a current balanced state.

[0032] Reference Figure 2 The acquisition circuit 30 also includes an operational amplifier 32 and an analog-to-digital converter 33, which are respectively connected to the sampling resistor 31.

[0033] Operational amplifier 32 is used to generate an indication signal; the indication signal is determined based on the comparison between the voltage value of sampling resistor 31 and a preset voltage.

[0034] Operational amplifier 32 serves as a comparator circuit. Its inverting input is connected to a first resistor 321 and a second resistor 322, forming a voltage divider network. The inverting input receives a preset voltage (a set reference voltage). The non-inverting input is connected to a sampling resistor 31 to receive the voltage transmitted by the sampling resistor. Operational amplifier 32 compares the preset voltage with the voltage value of the sampling resistor 31 and outputs different indication signals based on the comparison result. The output of operational amplifier 32 is connected to the main controller 10 to transmit indication signals to the main controller 10.

[0035] The analog-to-digital converter 33 is used to convert the voltage value of the sampling resistor 31 into a digital voltage signal and transmit the digital voltage signal to the main controller 10.

[0036] One end of the analog-to-digital converter 33 is located between the sampling resistor 31 and the operational amplifier 32, and the other end is connected to the main controller 10. The analog-to-digital converter 33 is used to convert the voltage of the sampling resistor 31 into a digital voltage signal and transmit the digital voltage signal to the main controller 10 so that the main controller 10 can determine the corresponding current signal value based on the digital voltage signal.

[0037] Figure 2 The diagram only shows the connection between the sampling resistor 31 and the operational amplifier 32 and the analog-to-digital converter 33. However, the actual connection of the drain current is as follows: the sampling resistor 31 is connected in series between the source of the switching transistor 20 and ground. One end of the sampling resistor 31 is grounded, and the other end is connected to the source of the switching transistor 20. The drain current flows out from the drain of the switching transistor 20, returns to the source after passing through the external load, and then flows to ground through the sampling resistor 31. This generates a voltage signal that is proportional to the drain current across the sampling resistor 31. This voltage signal is then sent to the operational amplifier 32 and the analog-to-digital converter 33 for processing.

[0038] The main controller 10 is used to determine the current turn-on delay time and current turn-off delay time of the multiple switching transistors 20 according to the indication signal; and to determine whether the multiple switching transistors 20 are in a current imbalance state according to the current turn-on delay time, current turn-off delay time and digital voltage signal.

[0039] The current turn-on delay time, which is the delay time of the drain current of switch 20 in the turn-on range, refers to the time from the start of the rise of the gate drive signal of switch 20 to the start of a significant rise in the drain current. It reflects the response speed of switch 2 during the turn-on process and is mainly affected by factors such as gate resistance (RG), input voltage (VCC), and threshold voltage (Vth).

[0040] The current turn-off delay time, also known as the delay time of the drain current of switch 20 in the turn-off region, refers to the time from when the gate drive signal begins to decrease until the drain current begins to decrease significantly. It reflects the response speed of switch 20 during the turn-off process and is also affected by parameters such as the gate resistance.

[0041] The main controller 10 determines the corresponding current turn-on delay time and current turn-off delay time according to the indication signal of each switch, and determines whether each parallel switch 20 is in a current imbalance state according to the current turn-on delay time, current turn-off delay time and digital voltage signal.

[0042] The drain current of the switching transistor 20 is detected by sampling resistor 31, and the current signal is converted into a voltage signal. The voltage signal is input to operational amplifier 32 and analog-to-digital converter 33 respectively. Operational amplifier 32 compares the voltage of sampling resistor 31 with the set reference voltage and outputs an indication signal. The main controller 10 determines the current turn-on delay time and current turn-off delay time according to the time information of the change of the indication signal. Furthermore, analog-to-digital converter 33 converts the voltage of sampling resistor 31 into a digital voltage signal and transmits it to the main controller 10. Finally, the main controller 10 can accurately determine whether each parallel switching transistor 20 is in a current imbalance state based on the current turn-on delay time, current turn-off delay time and digital voltage signal of each switching transistor 20.

[0043] In this embodiment of the invention, when the voltage value of the sampling resistor 31 is greater than or equal to a preset voltage, the indication signal is at a first level; when the voltage value of the sampling resistor 31 is less than the preset voltage, the indication signal is at a second level.

[0044] When the switching transistor 20 is turned on, the drain current rises. When the corresponding voltage exceeds the reference voltage, that is, when the voltage value of the sampling resistor 31 is greater than or equal to the preset voltage, the indicator signal output by the operational amplifier 32 is high. When the transistor is turned off, the drain current decreases. When the corresponding voltage is lower than the reference voltage, that is, when the voltage value of the sampling resistor 31 is less than the preset voltage, the indicator signal output by the operational amplifier 32 is low. The output terminal Vout of the operational amplifier 32 is connected to the main controller 10. The changes in these high and low level signals represent the time information of the drain current in the turn-on and turn-off intervals. This information is transmitted to the main controller 10 in real time through the Vout terminal. After receiving these signals, the main controller 10 calculates the current turn-on delay time and current turn-off delay time of each switching transistor 20 based on the timing of the signal changes.

[0045] Multiple switching transistors 20 are used to respond to control signals sent by the main controller 10 and adjust their operating state to be on or off.

[0046] The main controller 10 can generate PWM signals to control the operation of the parallel switching transistors 20, and at the same time, based on the data obtained from the operational amplifier 32 and the analog-to-digital converter 33, determine whether each parallel switching transistor 20 is in a current imbalance state.

[0047] The main controller 10 is used to determine the moment when the indicator signal changes to the first level during the turn-on interval of each switch 20 as the turn-on instantaneous time point; and to determine the current turn-on delay time of each switch 20 based on the turn-on instantaneous time point and the rising edge of the control signal.

[0048] During the turn-on interval, when the voltage corresponding to the drain current exceeds the preset voltage, the operational amplifier 32 outputs a high-level signal, records the instant of turn-on, and uses the time difference between the rising edge of the control signal and the instant of turn-on as the current turn-on delay time.

[0049] In the turn-off interval of each switch 20, the time point when the indicator signal changes to the second level is taken as the turn-off instantaneous time point; based on the turn-off instantaneous time point and the falling edge of the control signal, the current turn-off delay time of each switch 20 is determined.

[0050] During the turn-off interval, when the voltage corresponding to the drain current is lower than the set reference voltage, the operational amplifier 32 outputs a low-level signal, records the time point of the turn-off instant, and uses the falling edge of the control signal and the time point of the turn-off instant as the current turn-off delay time.

[0051] The corresponding output current is determined based on the digital voltage signal corresponding to each switch 20.

[0052] Using Ohm's law, the corresponding output current, i.e. the drain current of each switching transistor 20, is determined based on the digital voltage signal corresponding to each switching transistor 20.

[0053] Based on the current turn-on delay time, current turn-off delay time and output current of each switch 20, determine whether each switch 20 is in a current imbalance state.

[0054] The current turn-on delay time and current turn-off delay time of each switch 20 provide key timing information for subsequent current balancing control. The output current of each switch 20 provides key current information for subsequent current balancing control. Based on the current turn-on delay time, current turn-off delay time and output current of each switch 20, the main controller 10 can accurately determine whether each switch 20 is in a current imbalance state and adjust the control parameters of each switch 20 accordingly to achieve current balancing control.

[0055] In this embodiment of the invention, the current imbalance state includes a dynamic current imbalance state; The main controller 10 is configured to determine that multiple switching transistors 20 are in a dynamic current imbalance state if the difference between the current turn-on delay time of any switching transistor 20 and the current turn-on delay time of the other switching transistors is greater than a first preset threshold, and / or the difference between the current turn-off delay time of any switching transistor 20 and the current turn-off delay time of the other switching transistors is greater than a second preset threshold.

[0056] If the main controller 10 detects that the current turn-on delay time of a certain switch 20 is too long, and / or detects that the turn-off delay time of a certain switch 20 is too long, then it determines that multiple switches 20 are in a dynamic current imbalance state. By calculating the difference in delay time among the parallel switches 20, it determines whether multiple switches 20 are in a dynamic current imbalance state, and thus performs dynamic current balancing control when multiple switches 20 are in a dynamic current imbalance state.

[0057] In this embodiment of the invention, when multiple switching transistors 20 are in a state of dynamic current imbalance, the main controller 10 is used to send an adjusted first control signal to the drive circuit 40 corresponding to the switching transistor 20 with a large turn-on delay time; the drive circuit 40 is used to reduce the resistance of the control terminal of the corresponding switching transistor 20 during the turn-on process according to the first control signal, so as to reduce the turn-on delay time of the corresponding switching transistor 20.

[0058] During the dynamic operating range of a SiC MOSFET, i.e., the turn-on and turn-off transients, the gate drive current is affected by the gate resistance. The gate resistance controls the magnitude of the gate current, which in turn affects the turn-on delay and drain current rise rate of the SiC MOSFET. For example, in the dynamic range of parallel SiC MOSFETs, the gate current of each SiC MOSFET will have different gate drive behaviors due to the difference in their respective gate resistances when charging and discharging the gate-source capacitance, resulting in dynamic current differences between parallel devices. Based on this, by adjusting the gate resistance of each SiC MOSFET, its gate current can be controlled, synchronizing the turn-on delay and turn-off delay as well as the drain current rise rate of the parallel devices, thus achieving dynamic current balance.

[0059] If a long turn-on delay is detected in a certain switch 20, the main controller 10 will appropriately increase the turn-on time delay of its PWM signal to advance its turn-on time and reduce the dynamic current difference. The PWM signal with the increased turn-on time delay is the adjusted first control signal. According to the adjusted first control signal, the drive circuit 40 reduces the gate resistance of the corresponding switch 20 during the turn-on process to reduce the turn-on delay time of the corresponding switch 20 and achieve dynamic current balance.

[0060] Reference Figure 3 The driving circuit 40 includes an on-control branch 41; the on-control branch 41 includes an on-variable resistor 411, which is used to reduce the resistance value of the on-variable resistor 411 according to the first control signal, so as to reduce the resistance of the control terminal of the corresponding switch 20 during the on-process and reduce the on-delay time of the corresponding switch 20.

[0061] The turn-on control branch 41 also includes a gate turn-on resistor 412, which is used to adjust the rise rate of the gate current and affect the turn-on characteristics of the switching transistor 20. The turn-on variable resistor 411 (Maux-on) is an auxiliary low-power MOSFET connected in series with the corresponding gate turn-on resistor 412. The turn-on variable resistor 411 is a low-voltage N-channel MOSFET operating in the ohmic region, and its drain-source resistance RDS(on) varies with the gate voltage. As a variable resistor, the turn-on variable resistor 411 can dynamically adjust the total resistance of the branch by controlling its gate-source voltage, thereby precisely controlling the magnitude and rate of change of the gate current. The turn-on variable resistor 411 is mainly used to control the gate current during the turn-on process.

[0062] The turn-on control branch 41 also includes a turn-on diode 413. The turn-on diode 413 is connected in series with the gate turn-on resistor 412 and the MOSFET as an ultra-fast recovery diode. It is used to independently adjust the charging and discharging path of the gate current to ensure fast response and stable control of the gate current. The turn-on diode 413 provides a fast current rise path during the turn-on process.

[0063] In dynamic current balancing, during the turn-on and turn-off processes of the switching transistor 20, the main controller 10 adjusts the duty cycle of the PWM signal based on the turn-on delay and turn-off delay information fed back by the operational amplifier 32. For example, during the turn-on process, if the turn-on delay of a certain switching transistor 20 is large, the main controller 10 will increase the duty cycle of its corresponding PWM signal, thereby reducing the on-resistance of the turn-on variable resistor 411 and accelerating the rise rate of the gate current, thus reducing the turn-on delay and achieving dynamic current balancing.

[0064] In this embodiment of the invention, when multiple switching transistors 20 are in a state of dynamic current imbalance, the main controller 10 is used to send an adjusted second control signal to the drive circuit 40 corresponding to the switching transistor 20 with a larger turn-off delay time; the drive circuit 40 is used to reduce the resistance of the control terminal of the corresponding switching transistor 20 during the turn-off process according to the second control signal, so as to reduce the turn-off delay time of the corresponding switching transistor 20.

[0065] If the main controller 10 detects that the turn-off delay of a certain switch 20 is too long, the main controller 10 will appropriately increase the turn-off time delay of its PWM signal, thus delaying the turn-off moment and reducing dynamic current differences. In addition, the main controller 10 can also precisely control the gate current by adjusting the gate resistance, thereby affecting the turn-on / turn-off delay and drain current rise / fall rate of the switch 20, achieving precise dynamic current balance. The PWM signal with increased turn-off time delay is the adjusted second control signal. According to the adjusted second control signal, the drive circuit 40 reduces the gate resistance of the corresponding switch 20 during the turn-off process, thereby reducing the turn-off delay time of the corresponding switch 20 and achieving dynamic current balance.

[0066] Reference Figure 3 The drive circuit 40 includes a turn-off control branch 42; the turn-off control branch 42 includes a turn-off variable resistor 421, which is used to reduce the resistance value of the turn-off variable resistor 421 according to the second control signal, so as to reduce the resistance of the control terminal of the corresponding switch 20 during the turn-off process and reduce the turn-off delay time of the corresponding switch 20.

[0067] The turn-off control branch 42 also includes a gate turn-off resistor 422, which is used to regulate the rate of decrease of the gate current, affecting the turn-off characteristics of the switching transistor 20. The turn-off variable resistor 421 (Maux-off) is an auxiliary low-power MOSFET connected in series with the corresponding gate turn-off resistor 422. The turn-off variable resistor 421 is a low-voltage N-channel MOSFET operating in the ohmic region, and its drain-source resistance RDS(on) varies with the gate voltage. As a variable resistor, the turn-off variable resistor 421 can dynamically adjust the total resistance of the branch by controlling its gate-source voltage, thereby precisely controlling the magnitude and rate of change of the gate current. The turn-off variable resistor 421 is mainly used to control the gate current during the turn-off process.

[0068] The shutdown control branch 42 also includes a shutdown diode 423, which is an ultra-fast recovery diode connected in series with the gate shutdown resistor 422 and the MOSFET to independently regulate the charging and discharging path of the gate current, ensuring fast response and stable control of the gate current. The shutdown diode 423 is used to provide a fast current drop path during the shutdown process.

[0069] In dynamic current balancing, during the turn-on and turn-off processes of the switching transistor 20, the main controller 10 adjusts the duty cycle of the PWM signal based on the turn-on delay and turn-off delay information fed back by the operational amplifier 32. During the turn-off process, if the turn-off delay of a certain switching transistor 20 is large, the main controller 10 increases the duty cycle of its corresponding PWM signal, thereby reducing the on-resistance of the turn-off variable resistor 421 and accelerating the rate of gate current decrease, thus reducing the turn-off delay and achieving dynamic current balancing.

[0070] In this embodiment of the invention, the current imbalance state includes the static current imbalance state; The main controller 10 is used to determine that multiple switching transistors 20 are in a static current imbalance state if the difference between the output current of any switching transistor 20 and the output current of the other switching transistors is greater than a third preset threshold.

[0071] When the quiescent current of a certain switch 20 is detected to be smaller than that of other devices, and / or when the quiescent current of a certain switch 20 is detected to be larger than that of other devices, it is determined that multiple switches 20 are in a dynamic current imbalance state. The main controller 10 determines the corresponding output current, that is, the drain current of the corresponding switch 20, based on the digital voltage signal of the sampling resistor 31 transmitted by the analog-to-digital converter 33. By comparing the drain currents of each switch 20, it determines whether multiple switches 20 are in a quiescent current imbalance state, and thus performs quiescent current balancing control when multiple switches 20 are in a quiescent current imbalance state.

[0072] The main controller 10 will accurately calculate the degree of static and dynamic current imbalance and time delay difference between each parallel branch based on the data collected and converted by the sampling resistor 31, operational amplifier 32 and analog-to-digital converter 33.

[0073] The sampling resistor 31 measures the drain current of each parallel switch 20. During the turn-on phase, the current needs to be measured at a specific sampling point (away from the transient steady region) to accurately assess the static current imbalance. During the turn-on and turn-off transient processes, the peak current of each switch 20 is measured separately to assess the dynamic current imbalance. In addition, during the turn-off phase, the maximum difference between the currents of the parallel switches 20 needs to be calculated to further refine the assessment of the dynamic current imbalance.

[0074] Whether it is a turn-on or turn-off transient, the main controller 10 will calculate the current difference between the parallel switching transistors 20. The difference is that during the turn-on phase, only ID and on-peak (peak current) are sampled and their difference is compared, while during the turn-off phase, in addition to sampling ID and off-peak, ΔID and off-max (the maximum difference between the currents of the two branches during the entire turn-off process) are also recorded in order to more strictly monitor the peak current that may occur at the moment of turn-off. The difference calculation is also performed during the turn-on phase.

[0075] In this embodiment of the invention, when multiple switching transistors 20 are in a static current imbalance state, the main controller 10 is used to send an adjusted third control signal to the drive circuit 40 corresponding to the switching transistor 20 with a smaller output current; the drive circuit 40 is used to increase the drive voltage of the control terminal of the corresponding switching transistor 20 according to the third control signal, so as to increase the output current of the corresponding switching transistor 20.

[0076] During the static operating range of a SiC MOSFET, i.e., the stable conduction phase, it can be considered an ohmic resistance. If the on-resistances of the parallel SiC MOSFETs differ, it will lead to uneven distribution of static current. According to Ohm's law, the drain current is closely related to the on-resistance and the drain-source voltage. By reasonably adjusting the gate-source voltage of each SiC MOSFET, its on-resistance can be changed, thereby achieving static current balance.

[0077] When the quiescent current of a certain switch 20 is detected to be smaller than that of other switches 20, the main controller 10 will correspondingly increase the gate-source voltage of that switch 20 to reduce its on-resistance and promote the current to rise until an equilibrium state is reached; conversely, if the quiescent current of a certain switch 20 is too large, its gate-source voltage will be reduced and its on-resistance will be increased to reduce the current.

[0078] When multiple switching transistors 20 are in a state of static current imbalance, the main controller 10 sends an adjusted third control signal to the drive circuit 40 corresponding to the switching transistor 20 with a smaller output current. The adjusted third control signal is used to increase the gate-source voltage of the switching transistor 20. The drive circuit 40 increases the gate-source voltage of the corresponding switching transistor 20 according to the third control signal, so as to increase the output current of the corresponding switching transistor 20, thereby achieving static current balance.

[0079] Reference Figure 3 The drive circuit 40 includes a forward converter 43; the forward converter 43 is used to increase the drive voltage of the control terminal of the corresponding switch 40 according to the third control signal.

[0080] The forward converter 43 (FC) dynamically adjusts the gate drive voltage, thereby affecting the on-resistance and achieving balanced regulation of the quiescent current. The forward converter 43 is an isolated DC-DC buck topology that converts high-voltage DC on the primary side into adjustable low-voltage DC (VCC) on the secondary side. It consists of power MOSFETs, an isolation transformer, rectifier diodes, and an LC filter. During operation, PWMVCC controls the duty cycle of the MOSFETs. The transformer couples energy to the secondary side and steps down the voltage, which is then rectified and filtered to obtain a smooth VCC. Due to the electrical isolation provided by the transformer, the secondary-side VCC is completely isolated from the primary-side Vin, ensuring both safety and precise voltage regulation: an increase in duty cycle corresponds to an increase in VCC, and a decrease in duty cycle corresponds to a decrease in VCC. Based on real-time commands (control signals) from the main controller 10, the forward converter 43 precisely adjusts VCC between 14–23 V to change the gate-source voltage of the switching transistor 20, thereby adjusting its on-resistance and achieving quiescent current balance among parallel devices.

[0081] During the static current balancing process, the main controller 10 adjusts the amplitude of VCC based on the static current imbalance information fed back by the sampling resistor 31 and the analog-to-digital converter 33. For the switching transistor 20 with a smaller current, its corresponding VCC is increased and its on-resistance is decreased, thus increasing the current; for the switching transistor 20 with a larger current, its corresponding VCC is decreased and its on-resistance is increased, thus decreasing the current, until the static current is balanced.

[0082] The drive circuit 40 can also precisely adjust the gate current by changing the total resistance of the gate resistor branch, thereby achieving balanced control of the dynamic current. The gate resistor branch consists of two symmetrical series paths (turn-on control branch 41 and turn-off control branch 42). The main controller 10 first calculates the required turn-on or turn-off slope and sends out a PWM signal with a variable duty cycle via PWMon (corresponding to turn-on) or PWMoff (corresponding to turn-off) to drive the respective forward converters 43. The forward converters 43 convert the duty cycle into a DC voltage of 0–5 V, which is directly applied to the gate of the turn-on variable resistor 411 (Maux-on) or turn-off variable resistor 421 (Maux-off). When the voltage increases, the RDS(on) (Drain-to-Source On-State Resistance, the conduction resistance between the drain and source in the fully on state) of the MOSFET decreases, the total series resistance decreases accordingly, the gate current rises faster, and the turn-on or turn-off delay is shortened. Conversely, when the voltage decreases, the total resistance increases, the current is suppressed, and the delay is lengthened. Through closed-loop iteration, the main controller 10 can continuously and independently change the equivalent resistance of the two branches between RG (gate drive resistance) and RG + MOSFET minimum RDS(on), thereby accurately matching the di / dt and td(on) / td(off) of the parallel devices and achieving dynamic current balance.

[0083] The drive circuit 40 adjusts the VCC and PWM signals and uses devices such as gate turn-on resistor 412, gate turn-off resistor 422, turn-on variable resistor 411, turn-off variable resistor 421, turn-on diode 413 and turn-off diode 423 to achieve precise control of the static and dynamic current of the switching transistor 20, thereby effectively solving the current imbalance problem of the parallel switching transistor 20.

[0084] The core function of the drive circuit 40 is to adjust the gate drive voltage and gate resistance to achieve precise control of the current of the switching transistor 20.

[0085] In this embodiment of the invention, the main controller 10 is used to send an adjusted fourth control signal to the drive circuit 40 corresponding to the switch 20 with a larger output current when multiple switches 20 are still in a static current imbalance state after sending an adjusted third control signal to the drive circuit 40 corresponding to the switch 20 with a smaller output current; the drive circuit 40 is used to reduce the drive voltage of the control terminal of the corresponding switch 20 according to the fourth control signal, so as to reduce the output current of the corresponding switch 20.

[0086] If the static current imbalance exceeds the third preset threshold, the main controller 10 prioritizes correcting the static current imbalance by increasing the gate drive voltage of the switch 20 with the smaller current. If the imbalance is not eliminated even after the gate drive voltage reaches its upper limit, the controller then reduces the gate drive voltage of the switch 20 with the larger current. Prioritizing the increase of the gate drive voltage of the switch with the smaller current, and then reducing the drive voltage of the switch with the larger current after reaching the upper limit, can reduce the on-resistance of the switch and thus reduce conduction losses. If the drive voltage of the large current switch is directly reduced, although the current it shares will decrease, its on-resistance will increase due to the reduction in drive voltage. Moreover, by actively "pulling up" the performance of the small current switch by increasing its drive voltage, the controller can intervene in the imbalance earlier and more proactively, prevent the large current switch from overheating, improve the thermal stability of the system, and enhance its robustness.

[0087] The main controller 10 starts by detecting current imbalance and adjusts the corresponding parameters according to the imbalance type (static or dynamic), polarity, and degree, in a preset priority order, until all currents reach a balanced state. When the static current imbalance exceeds the threshold, the VCC of the device with smaller current is increased first, until the maximum limit is reached, and then the VCC of the device with larger current is decreased. For dynamic current imbalance, the turn-on and turn-off time delays of the PWM signal are adjusted according to the delay and current difference, combined with gate current regulation.

[0088] The main controller 10 is responsible for generating PWM signals to control the operation of the switching transistors 20, and precisely regulating the current distribution of each switching transistor 20 based on real-time acquired current and time delay data. Its control logic is as follows: If the static current imbalance exceeds a preset threshold, the controller prioritizes correcting the static current imbalance by increasing the gate drive voltage of the device with the smaller current; if the imbalance is not eliminated even after the gate drive voltage reaches its upper limit, it then reduces the gate drive voltage of the device with the larger current. For dynamic current imbalance, the main controller 10 flexibly adjusts the time delay of the PWM signal based on the sign and magnitude of the turn-on and turn-off delays, and combines this with the regulation of the gate current to comprehensively suppress dynamic current imbalance. Throughout the control process, the controller stores effective control parameter adjustment schemes in real time for quick recall upon the next system startup, achieving instant current balancing and effectively avoiding overcurrent surges.

[0089] The control circuit for the switching transistors in this embodiment of the invention enables self-sustaining current balancing. The main controller 10 implements an intelligent algorithm via an FPGA to monitor the current of the parallel switching transistors 20 in real time, automatically detecting and adjusting static and dynamic current imbalances without manual intervention, reducing reliance on high-precision ADCs and lowering costs. Furthermore, the drive circuit 40 can automatically modify parameters such as the control voltage of each switching transistor 20, the time delay of the PWM signal, and the gate resistor according to the control signal from the main controller 10, to precisely adjust the current distribution of each device and achieve accurate balance between dynamic and static currents. In addition, the current measurement system based on a low-speed ADC (analog-to-digital converter 33) and a high-speed comparator (operational amplifier 32) utilizes the high-speed comparator to capture the timing information of the current, combined with the sampling data from the low-speed ADC, to achieve accurate measurement and rapid response of the current of the parallel SiC MOSFETs, improving system reliability and cost-effectiveness. Moreover, the control parameter adjustments made during the initial current balancing can be stored and directly called during subsequent system startup, enabling the system to achieve current balancing in the first startup cycle, avoiding overcurrent events and improving system safety and stability.

[0090] This invention achieves automatic balancing of static and dynamic currents in parallel switching transistors, avoiding safety issues such as overheating and overcurrent caused by current imbalance, thus improving device reliability and system safety. Utilizing a self-sustaining algorithm and the powerful computing capabilities of an FPGA, real-time monitoring and automatic adjustment of the current not only improves control accuracy and response speed but also reduces reliance on high-precision, high-cost ADCs, lowering implementation costs. Current balancing can be achieved in the first cycle of system startup, effectively preventing overcurrent events caused by current imbalance and enhancing system stability and reliability. It possesses good scalability and can be easily applied to current balancing control of more parallel devices, meeting the needs of medium- and high-power applications. This is of great significance for promoting the widespread application of SiC MOSFETs in electric vehicles, renewable energy systems, and other fields.

[0091] This invention uses an FPGA as its core, combining a self-sustaining algorithm and a hybrid measurement system to achieve current balancing by dynamically adjusting gate parameters (such as gate resistance, control voltage, and PWM signal delay) through real-time monitoring of the current of parallel SiC MOSFETs. Static and dynamic currents are measured in stages using high-bandwidth surface-mount resistors and high-speed comparators. The FPGA calculates the degree of current imbalance based on ADC sampling data and time information captured by the comparator. An improved active gate driver (AGD) adjusts the gate resistance and control voltage to synchronize dynamic characteristics. A parameter storage mechanism records the control parameters during the initial balancing, which can be directly called upon during subsequent startups to avoid overcurrent events. This implementation method combines digital calculation and dynamic hardware adjustment, balancing accuracy and response speed while supporting adaptability to asymmetric layouts. Static current balancing is based on Ohm's law, changing the on-resistance (RDS-on) by adjusting the gate-source voltage (VGS) to evenly distribute the static current of the parallel devices. Dynamic current balancing, on the other hand, changes the gate current by adjusting the gate resistance (RG) and synchronizing the turn-on / turn-off delay to suppress dynamic current imbalance.

[0092] This invention also provides a chip including a control circuit for a switching transistor as described in any of the preceding embodiments.

[0093] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0094] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0095] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1A device that provides the functions specified in one or more boxes.

[0096] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0097] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0098] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0099] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0100] The control circuit and chip for a switching transistor provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A control circuit for a switching transistor, characterized in that, The circuit includes: a main controller, multiple acquisition circuits connected to multiple parallel switching transistors, and multiple drive circuits connected to the multiple switching transistors. The acquisition circuit includes a sampling resistor connected to a corresponding switching transistor; the acquisition circuit is used to acquire the voltage value of the sampling resistor and generate an indication signal; the indication signal is used to indicate whether the corresponding switching transistor is on or off; the indication signal is determined based on the voltage value of the sampling resistor. The main controller is configured to determine the current turn-on delay time and current turn-off delay time of the plurality of switching transistors according to the indication signal; determine whether the plurality of switching transistors are in a current imbalance state according to the current turn-on delay time, the current turn-off delay time and the voltage value of the sampling resistor; if the plurality of switching transistors are in a current imbalance state, adjust the control signal sent to the drive circuit corresponding to at least one switching transistor. The driving circuit is used to adjust the operating parameters of the corresponding switching transistor according to the control signal.

2. The control circuit for the switching transistor according to claim 1, characterized in that, The acquisition circuit also includes an operational amplifier and an analog-to-digital converter, which are respectively connected to the sampling resistor; The operational amplifier is used to generate an indication signal; the indication signal is determined based on a comparison between the voltage value of the sampling resistor and a preset voltage. The analog-to-digital converter is used to convert the voltage value of the sampling resistor into a digital voltage signal and transmit the digital voltage signal to the main controller; The main controller is used to determine the current turn-on delay time and current turn-off delay time of the plurality of switching transistors according to the indication signal; Based on the current turn-on delay time, the current turn-off delay time, and the digital voltage signal, determine whether the plurality of switching transistors are in a current imbalance state.

3. The control circuit for the switching transistor according to claim 2, characterized in that, When the voltage value of the sampling resistor is greater than or equal to a preset voltage, the indication signal is at a first level; when the voltage value of the sampling resistor is less than the preset voltage, the indication signal is at a second level. The plurality of switching transistors are used to respond to the control signals sent by the main controller and adjust their operating state to be on or off; The main controller is used to determine the moment when the indicator signal changes to the first level as the instantaneous turn-on time point in the turn-on interval of each switching transistor; and to determine the current turn-on delay time of each switching transistor based on the instantaneous turn-on time point and the rising edge of the control signal. In the turn-off interval of each switch, the time point at which the indicator signal changes to the second level is taken as the turn-off instantaneous time point; the current turn-off delay time of each switch is determined based on the turn-off instantaneous time point and the falling edge of the control signal. The corresponding output current is determined based on the digital voltage signal corresponding to each switching transistor; Based on the current turn-on delay time, the current turn-off delay time, and the output current of each switch, determine whether each switch is in a current imbalance state.

4. The control circuit for the switching transistor according to claim 3, characterized in that, The current imbalance state includes the dynamic current imbalance state; The main controller is configured to determine that the plurality of switching transistors are in a dynamic current imbalance state if the difference between the current turn-on delay time of any switching transistor and the current turn-on delay time of the other switching transistors is greater than a first preset threshold, and / or the difference between the current turn-off delay time of any switching transistor and the current turn-off delay time of the other switching transistors is greater than a second preset threshold.

5. The control circuit for the switching transistor according to claim 4, characterized in that, When the multiple switching transistors are in a state of dynamic current imbalance, the main controller is used to send an adjusted first control signal to the drive circuit corresponding to the switching transistor with a large turn-on delay time; the drive circuit is used to reduce the resistance of the control terminal of the corresponding switching transistor during the turn-on process according to the first control signal, so as to reduce the turn-on delay time of the corresponding switching transistor.

6. The control circuit for the switching transistor according to claim 5, characterized in that, The driving circuit includes an on-control branch; the on-control branch includes an on-control variable resistor, which is used to reduce the resistance value of the on-control variable resistor according to the first control signal, so as to reduce the resistance of the control terminal of the corresponding switch during the on-process and reduce the on-delay time of the corresponding switch.

7. The control circuit for the switching transistor according to claim 4, characterized in that, When the multiple switching transistors are in a state of dynamic current imbalance, the main controller is used to send an adjusted second control signal to the drive circuit corresponding to the switching transistor with a larger turn-off delay time; the drive circuit is used to reduce the resistance of the control terminal of the corresponding switching transistor during the turn-off process according to the second control signal, so as to reduce the turn-off delay time of the corresponding switching transistor.

8. The control circuit for the switching transistor according to claim 7, characterized in that, The drive circuit includes a shutdown control branch; The shutdown control branch includes a shutdown variable resistor, which is used to reduce the resistance value of the shutdown variable resistor according to the second control signal, so as to reduce the resistance of the control terminal of the corresponding switch during the shutdown process and reduce the shutdown delay time of the corresponding switch.

9. The control circuit for the switching transistor according to claim 3, characterized in that, The current imbalance state includes the static current imbalance state; The main controller is configured to determine that the plurality of switching transistors are in a static current imbalance state if the difference between the output current of any switching transistor and the output current of the other switching transistors is greater than a third preset threshold.

10. The control circuit for the switching transistor according to claim 9, characterized in that, When the multiple switching transistors are in a static current imbalance state, the main controller is used to send an adjusted third control signal to the drive circuit corresponding to the switching transistor with the smaller output current; the drive circuit is used to increase the drive voltage of the control terminal of the corresponding switching transistor according to the third control signal, so as to increase the output current of the corresponding switching transistor.

11. The control circuit for the switching transistor according to claim 10, characterized in that, The driving circuit includes a forward converter; the forward converter is used to increase the driving voltage of the control terminal of the corresponding switching transistor according to the third control signal.

12. The control circuit for the switching transistor according to claim 11, characterized in that, The main controller is configured to send an adjusted fourth control signal to the drive circuit corresponding to the switch with a larger output current after sending an adjusted third control signal to the drive circuit corresponding to the switch with a smaller output current, while the plurality of switches are still in a static current imbalance state; the drive circuit is configured to reduce the drive voltage at the control terminal of the corresponding switch according to the fourth control signal, so as to reduce the output current of the corresponding switch.

13. A chip, characterized in that, The control circuit includes the switching transistor as described in any one of claims 1-12.

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