Overvoltage amplitude limiting signal input circuit
By using a combination of transmission gates and comparator modules in MCU or DSP chips, and utilizing MOSFETs to limit the amplitude of input signals, the chip malfunction problem caused by input signals exceeding the range is solved, achieving a simple and accurate signal limiting effect.
Patent Information
- Application Number
- CN202511792931.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-01
- Publication Date
- 2026-03-03
AI Technical Summary
In MCU or DSP chips, the input signal voltage range is diverse, but the input signal range required by the internal circuit is fixed, which leads to abnormal operation of the internal circuit of the chip.
By combining a transmission gate and a comparator module, and using a MOSFET to limit the amplitude of the input signal, the output signal is ensured not to exceed the reference voltage by comparing the input signal with a reference voltage and controlling the conduction state of the transmission gate.
It achieves simple and accurate limitation of input signal amplitude. The circuit structure is simple, small in area, and low in cost, making it suitable for integration into chips.
Smart Images
Figure CN121602986A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to an overvoltage limiting signal input circuit. Background Technology
[0002] In MCU or DSP chip applications, the range of input signal voltages processed is diverse, but the range of input signals required by the internal circuit is often fixed. That is, the highest voltage of the input signal is often larger than the range of input signals required by the internal circuit, or even much larger than the power supply voltage of the entire chip. In this case, it often causes abnormal operation of the internal circuit of the chip.
[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide an overvoltage limiting signal input circuit that can simply and accurately limit the amplitude of the input signal.
[0005] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:
[0006] An overvoltage limiting signal input circuit includes a transmission gate and a comparison module. The comparison module compares the magnitude of an input signal and a reference voltage and generates a comparison signal. The transmission gate includes a first MOSFET and a second MOSFET. A first terminal of the first MOSFET is connected to a second terminal of the second MOSFET to receive the input signal. The second terminal of the first MOSFET is connected to a first terminal of the second MOSFET to generate an output signal. The control terminal of the first MOSFET is connected to the comparison module to receive the comparison signal. The control terminal of the second MOSFET is connected to a reference voltage and remains on based on the control of the reference voltage.
[0007] In one or more embodiments of the present invention, the first MOS transistor is a P-channel MOS transistor.
[0008] In one or more embodiments of the present invention, the second MOS transistor is an N-channel MOS transistor, and the substrate of the second MOS transistor is grounded.
[0009] In one or more embodiments of the present invention, the comparison module includes a third MOS transistor, a first current source, and a control voltage unit. The control voltage unit is used to generate a control voltage based on a reference voltage. The control terminal of the third MOS transistor is connected to the control voltage unit to receive the control voltage. The first terminal of the third MOS transistor is connected to an input signal, and the second terminal of the third MOS transistor is connected to ground voltage through the first current source and used to generate a comparison signal.
[0010] In one or more embodiments of the present invention, the third MOS transistor is a high-voltage P-channel MOS transistor.
[0011] In one or more embodiments of the present invention, the first current source includes a fourth MOS transistor, the control terminal of the fourth MOS transistor is connected to a reference voltage, the second terminal of the fourth MOS transistor is connected to the second terminal of a third MOS transistor, and the first terminal of the fourth MOS transistor is connected to ground voltage.
[0012] In one or more embodiments of the present invention, the control voltage unit includes a fifth MOS transistor and a load unit. The first terminal of the fifth MOS transistor is connected to a reference voltage. The second terminal of the fifth MOS transistor, the control terminal of the fifth MOS transistor, and the first terminal of the load unit are connected to the control terminal of a third MOS transistor to generate a control voltage. The second terminal of the load unit is connected to ground voltage.
[0013] In one or more embodiments of the present invention, the fifth MOS transistor is a low-voltage P-channel MOS transistor.
[0014] In one or more embodiments of the present invention, the threshold voltage of the fifth MOS transistor is 100-200mV lower than the threshold voltage of the third MOS transistor.
[0015] In one or more embodiments of the present invention, the load unit includes a second current source, a first terminal of which is connected to a second terminal of a fifth MOS transistor, and the second terminal of which is connected to ground voltage; and / or the load unit includes a resistor, a first terminal of which is connected to a second terminal of a fifth MOS transistor, and the second terminal of which is connected to ground voltage.
[0016] Compared with the prior art, the overvoltage limiting signal input circuit of the present invention achieves the function of limiting the amplitude of the input signal to no more than the reference voltage through a simple circuit structure. The circuit is simple, small in area, low in cost, and easy to integrate into a chip. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a circuit diagram of the signal input circuit in one embodiment of the present invention. Detailed Implementation
[0019] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.
[0020] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.
[0021] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.
[0022] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.
[0023] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0024] Various components and devices may be mentioned or shown in the singular form herein, but only for the convenience of discussion, and any element mentioned in the singular form may include multiple such elements as taught herein.
[0025] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.
[0026] like Figure 1 As shown, the overvoltage limiting signal input circuit in one embodiment of the present invention includes a transmission gate 10 and a comparison module 20.
[0027] The comparison module 20 compares the input signal VIN with the reference voltage VREF and generates a comparison signal VG2. The transmission gate 10 includes a first MOSFET MTGP and a second MOSFET MTGN. The first terminal of the first MOSFET MTGP is connected to the second terminal of the second MOSFET MTGN to receive the input signal VIN. The second terminal of the first MOSFET MTGP is connected to the first terminal of the second MOSFET MTGN to generate an output signal VOUT. The control terminal of the first MOSFET MTGP is connected to the comparison module 20 to receive the comparison signal VG2. The control terminal of the second MOSFET MTGN is connected to the reference voltage VREF and remains on based on the control of the reference voltage VREF.
[0028] In one embodiment, the first MOSFET MTGP is a P-channel MOSFET. The first terminal of the first MOSFET MTGP is the source, the second terminal of the first MOSFET MTGP is the drain, the control terminal of the first MOSFET MTGP is the gate, and the substrate of the first MOSFET MTGP is connected to the source.
[0029] In one embodiment, the second MOSFET MTGN is an N-channel MOSFET, and the substrate of the second MOSFET MTGN is grounded. The first terminal of the second MOSFET MTGN is the source, the second terminal of the second MOSFET MTGN is the drain, and the control terminal of the second MOSFET MTGN is the gate.
[0030] In the transmission gate 10 of the present invention, the gate control of the PMOS is achieved through the output of the comparator module 20, while the NMOS is always on and its gate is controlled by the reference voltage VREF. This enables the output signal VOUT to be limited to less than the reference voltage VREF when the PMOS is completely turned off by the comparator signal VG2.
[0031] like Figure 1As shown, the comparison module 20 includes a third MOSFET MPH, a first current source 21, and a control voltage VG1 unit 22. The control voltage VG1 unit 22 is used to generate a control voltage VG1 based on a reference voltage VREF. The control terminal of the third MOSFET MPH is connected to the control voltage VG1 unit 22 to receive the control voltage VG1. The first terminal of the third MOSFET MPH is connected to the input signal VIN, and the second terminal of the third MOSFET MPH is connected to ground voltage through the first current source 21 and is used to generate a comparison signal VG2.
[0032] In one embodiment, the third MOSFET MPH is a high-voltage P-channel MOSFET. The first terminal of the third MOSFET MPH is the source, the second terminal of the third MOSFET MPH is the drain, and the control terminal of the third MOSFET MPH is the gate.
[0033] In one embodiment, the first current source 21 includes a fourth MOSFET MNH, the control terminal of the fourth MOSFET MNH is connected to the reference voltage VREF, the second terminal of the fourth MOSFET MNH is connected to the second terminal of the third MOSFET MPH, and the first terminal of the fourth MOSFET MNH is connected to the ground voltage.
[0034] Furthermore, the fourth MOSFET MNH is an N-channel MOSFET. The first terminal of the fourth MOSFET MNH is the source, the second terminal of the fourth MOSFET MNH is the drain, and the control terminal of the fourth MOSFET MNH is the gate.
[0035] In other embodiments, the first current source 21 may also adopt other forms of current source circuit structure.
[0036] like Figure 1 As shown, the control voltage VG1 unit 22 includes a fifth MOSFET MPL and a load unit 221. The first terminal of the fifth MOSFET MPL is connected to the reference voltage VREF. The second terminal of the fifth MOSFET MPL, the control terminal of the fifth MOSFET MPL, and the first terminal of the load unit 221 are connected to the control terminal of the third MOSFET MPH to generate the control voltage VG1. The second terminal of the load unit 221 is connected to the ground voltage.
[0037] In one embodiment, the fifth MOSFET MPL is a low-voltage P-channel MOSFET. The first terminal of the fifth MOSFET MPL is the source, the second terminal of the fifth MOSFET MPL is the drain, and the control terminal of the fifth MOSFET MPL is the gate.
[0038] Further, the threshold voltage of the fifth MOS transistor MPL is 100 to 200 mV lower than the threshold voltage of the third MOS transistor MPH. Exemplarily, the third MOS transistor MPH is a high-voltage PMOS transistor of 25OD33 (on the basis of a 2.5V device, the overdrive is adjusted to 3.3V through the process), and the fifth MOS transistor MPL is a 2.5V PMOS device.
[0039] In one embodiment, the load unit 221 includes a second current source IB. The first end of the second current source IB is connected to the second end of the fifth MOS transistor MPL, and the second end of the second current source IB is connected to the ground voltage. The second current source IB can adopt a single MOS transistor current source or other current source circuit structures.
[0040] In other embodiments, the load unit 221 may also include a resistor. The first end of the resistor is connected to the second end of the fifth MOS transistor MPL, and the second end of the resistor is connected to the ground voltage.
[0041] During the actual working process, the control voltage VG1 is: VG1 = VREF - Vth_MPL, where Vth_MPL is the threshold voltage of the fifth MOS transistor MPL.
[0042] The turn-on voltage of the third MOS transistor MPH is: VIN - VG1 = VIN - (VREF - Vth_MPL) = (VIN - VREF) + Vth_MPL.
[0043] When the input signal VIN is lower than the reference voltage VREF plus the threshold voltage difference between the fifth MOS transistor MPL and the third MOS transistor MPH, that is, VIN < VREF + (Vth_MPH - Vth_MPL), the turn-on voltage of the third MOS transistor MPH is less than its threshold voltage, and the third MOS transistor MPH is turned off. The comparison signal VG2 is pulled down to a low level, and the first MOS transistor MTGP is turned on. At this time, both the first MOS transistor MTGP and the second MOS transistor MTGN are turned on, and the output signal VOUT is equal to the input signal VIN.
[0044] When the input signal VIN is higher than the reference voltage VREF plus the threshold voltage difference between the fifth MOS transistor MPL and the third MOS transistor MPH, that is, VIN > VREF + (Vth_MPH - Vth_MPL), the turn-on voltage of the third MOS transistor MPH is greater than its threshold voltage, and the third MOS transistor MPH is turned on. The comparison signal VG2 is pulled up to the voltage value of the input signal VIN, and the first MOS transistor MTGP is turned off. At this time, only the second MOS transistor MTGN in the transmission gate 10 is turned on, and the output signal VOUT is approximately: VREF - Vth_MTGN, where Vth_MTGN is the threshold voltage of the second MOS transistor MTGN.
[0045] In the above process, since the second MOSFET MTGN is always conducting and connecting the input signal VIN and the output signal VOUT, the function of this circuit is a normally open switch. When the input voltage is 100~200mV higher than the reference voltage VREF, it can limit the voltage of the output signal VOUT to be slightly lower than the reference voltage VREF, thereby realizing the overvoltage limiting function.
[0046] Because the fifth MOSFET, MPL, uses a low-threshold transistor with a relatively low threshold voltage to cooperate with the high-voltage third MOSFET, MPH, to generate the comparison signal VG2, there is no matching requirement for the second current source, IB, and it is even unnecessary to replace the current source with a lower-cost resistor. The entire circuit has the advantages of simple structure, low cost, small area, and low process complexity, making it easy to integrate into a chip.
[0047] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0048] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A signal input circuit for overvoltage limiting, characterized in that, The system includes a transmission gate and a comparison module. The comparison module is used to compare the magnitude of an input signal and a reference voltage and generate a comparison signal. The transmission gate includes a first MOSFET and a second MOSFET. The first terminal of the first MOSFET is connected to the second terminal of the second MOSFET to receive the input signal. The second terminal of the first MOSFET is connected to the first terminal of the second MOSFET to generate an output signal. The control terminal of the first MOSFET is connected to the comparison module to receive the comparison signal. The control terminal of the second MOSFET is connected to the reference voltage and remains on based on the control of the reference voltage.
2. The overvoltage limiting signal input circuit according to claim 1, characterized in that, The first MOSFET is a P-channel MOSFET.
3. The overvoltage limiting signal input circuit according to claim 1, characterized in that, The second MOS transistor is an N-channel MOS transistor, and the substrate of the second MOS transistor is grounded.
4. The overvoltage limiting signal input circuit according to claim 1, characterized in that, The comparison module includes a third MOS transistor, a first current source, and a control voltage unit. The control voltage unit is used to generate a control voltage based on a reference voltage. The control terminal of the third MOS transistor is connected to the control voltage unit to receive the control voltage. The first terminal of the third MOS transistor is connected to the input signal, and the second terminal of the third MOS transistor is connected to the ground voltage through the first current source and used to generate a comparison signal.
5. The overvoltage limiting signal input circuit according to claim 4, characterized in that, The third MOSFET is a high-voltage P-channel MOSFET.
6. The overvoltage limiting signal input circuit according to claim 4, characterized in that, The first current source includes a fourth MOS transistor, the control terminal of which is connected to a reference voltage, the second terminal of which is connected to the second terminal of a third MOS transistor, and the first terminal of which is connected to ground.
7. The overvoltage limiting signal input circuit according to claim 4, characterized in that, The control voltage unit includes a fifth MOSFET and a load unit. The first terminal of the fifth MOSFET is connected to a reference voltage. The second terminal of the fifth MOSFET, the control terminal of the fifth MOSFET, and the first terminal of the load unit are connected to the control terminal of a third MOSFET to generate a control voltage. The second terminal of the load unit is connected to ground.
8. The overvoltage limiting signal input circuit according to claim 7, characterized in that, The fifth MOSFET is a low-voltage P-channel MOSFET.
9. The overvoltage limiting signal input circuit according to claim 8, characterized in that, The threshold voltage of the fifth MOS transistor is 100-200mV lower than that of the third MOS transistor.
10. The overvoltage limiting signal input circuit according to claim 7, characterized in that, The load unit includes a second current source, the first terminal of which is connected to the second terminal of the fifth MOSFET, and the second terminal of which is connected to ground; and / or The load unit includes a resistor, the first end of which is connected to the second end of the fifth MOS transistor, and the second end of which is connected to ground voltage.