Digital phase locked loop for tuning frequency and correcting phase error using variable capacitance based on pulse signal

Abstract

A digital phase-locked loop that tunes frequency and corrects phase errors using a variable capacitance based on a pulse signal is provided. The digital phase-locked loop comprises: a phase detector for comparing a phase of a reference signal with a phase of a feedback signal; a digital loop filter for outputting an adjustment signal for adjusting the duty ratio of the first time period based on the lifting signal of the phase detector; the variable capacitance controller is used for outputting a capacitance control signal with a duty ratio based on the feedback signal, the adjusting signal and the lifting signal; a digitally controlled oscillator for changing a first capacitance of the capacitor bank circuit based on the capacitance control signal and adjusting a phase based on an average of the first capacitance during a first time period; and the frequency divider is used for carrying out frequency division on the output signal.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0114488, filed on August 26, 2024, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0144351, filed on October 21, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to an electronic device, and more specifically, to a digital phase-locked loop (PLL) that uses a pulse-signal-based variable capacitor to tune the frequency and correct phase errors, an electronic device, and a method of operating the digital PLL. Background Technology

[0004] The demand for phase-locked loops (PLLs) is growing in electronic systems such as wireless and wired systems to meet high data rate communications, high-speed data signal processing, and high-performance jitter specifications.

[0005] For charge pump phase-locked loops (CPPLLs), which typically include a charge pump, there are structural difficulties in improving low jitter. Furthermore, for sampled phase-locked loops (SPLLs) (e.g., sub-sampled PLLs), the locking range (or range locking) required to achieve phase locking is relatively narrow, making it difficult to obtain stable phase locking. To ensure the locking range, a separate loop, such as a frequency-locked loop, needs to be added to the sampled PLL, which makes it difficult to reduce manufacturing costs or increase integration density.

[0006] For digital PLLs including LC cavity oscillators (LCOSCs), the target frequency is adjusted by the inductance and total capacitance of the LC cavity. In this case, frequency variation is adjusted based on the capacitance of the tuning capacitor, and a varactor diode receiving a DC voltage input and having a corresponding capacitance can be used as a variable capacitor. However, varactor diodes are susceptible to power supply noise, and their capacitance varies significantly with temperature; moreover, their low quality factor can bottleneck the quality factor of the LC cavity. Therefore, while replacing the varactor diode, a method needs to be found to correct the frequency and phase through fine-tuning the capacitance. Summary of the Invention

[0007] The embodiments provide a digital phase-locked loop that uses a pulse signal-based variable capacitor instead of a varactor diode to tune the frequency and correct the phase, an electronic device, and a method for operating the digital phase-locked loop.

[0008] According to one aspect of this disclosure, a digital phase-locked loop includes: a phase detector configured to compare the phase of a reference signal with the phase of a feedback signal and output a rising / falling signal representing the result of the comparison; a digital loop filter configured to output an adjustment signal including a digital code based on the rising / falling signal, the adjustment signal being used to adjust the duty cycle of a first time period corresponding to a time period of the feedback signal; a variable capacitor controller configured to output a capacitor control signal having a duty cycle based on the feedback signal, the adjustment signal, and the rising / falling signal; a digitally controlled oscillator including: an inductor; a capacitor bank circuit configured to change a first capacitor based on the capacitor control signal; a negative voltage-to-current converter configured to output an output signal having a phase adjusted based on the inductance of the inductor and the average value of the first capacitor during the first time period; and a frequency divider configured to generate a feedback signal by dividing the output signal.

[0009] According to one aspect of this disclosure, a method for operating a digital phase-locked loop is provided, the method comprising: generating a rising / falling signal representing the result of a comparison between the phase of the reference signal and the phase of the feedback signal based on the reference signal and a feedback signal; generating an adjustment signal including a digital code based on the rising / falling signal, the adjustment signal being used to adjust the duty cycle of a first time period corresponding to a time period of the feedback signal; generating a capacitor control signal having a duty cycle based on the feedback signal, the adjustment signal, and the rising / falling signal; setting a first capacitor during a second time period corresponding to the duty cycle of the capacitor control signal; adjusting the phase based on an inductance and the average value of the first capacitor during the first time period to generate an output signal having a phase; and generating a feedback signal by frequency division of the output signal.

[0010] According to one aspect of this disclosure, an electronic device for generating an output clock signal based on a reference clock signal includes: a phase detector configured to compare the phase of the reference clock signal with the phase of a feedback clock signal and output a rising / falling signal representing the result of the comparison; a digital loop filter configured to output an adjustment signal including a digital code based on the rising / falling signal, the adjustment signal being used to adjust the duty cycle of a first time period corresponding to a time period of the feedback clock signal; a variable capacitor controller configured to output a capacitor control signal having a duty cycle based on the feedback clock signal, the adjustment signal, and the rising / falling signal; a digitally controlled oscillator configured to change the capacitance of a capacitor bank circuit based on the capacitor control signal and adjust the phase of the output clock signal based on the average value of the capacitance during the first time period; and a frequency divider configured to generate the feedback clock signal by dividing the output clock signal.

[0011] According to one or more embodiments, a capacitor bank replaces a varactor diode for tuning frequency and phase. Accordingly, it is possible to improve the power supply rejection ratio (PSRR) characteristics caused by the varactor diode, improve the jitter performance of the numerically controlled oscillator caused by temperature changes, improve the frequency drift caused by temperature changes, and improve the quality of service (QoS) of the numerically controlled oscillator or the quality factor Q of the LC resonator. Attached Figure Description

[0012] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 It is a block diagram of a digital phase-locked loop according to one or more embodiments;

[0014] Figure 2 It is a block diagram of a digital phase-locked loop according to one or more embodiments;

[0015] Figure 3 This is a circuit diagram of a numerically controlled oscillator according to one or more embodiments;

[0016] Figure 4 It is a timing diagram of signals in a digital phase-locked loop according to one or more embodiments;

[0017] Figure 5 and Figure 6 This is a block diagram of adaptive bandwidth calibration (ABC) according to one or more embodiments;

[0018] Figure 7 It is a block diagram of pulse width modulation (PWM) according to one or more embodiments;

[0019] Figure 8 This is a circuit diagram of a pulse generator according to one or more embodiments;

[0020] Figure 9 It is a circuit diagram of a delay unit according to one or more embodiments;

[0021] Figure 10 yes Figure 8 and Figure 9 The timing diagram of the signal shown;

[0022] Figure 11 This is a diagram showing a variable capacitor;

[0023] Figure 12 This is a flowchart illustrating a method of operating a digital phase-locked loop according to one or more embodiments;

[0024] Figure 13 It shows Figure 12A flowchart of an example of operation S200 in the process;

[0025] Figure 14 It shows Figure 12 A flowchart of another example of operation S200;

[0026] Figure 15 It shows Figure 12 A flowchart of an example of operation S300 in the process;

[0027] Figure 16 It shows Figure 15 A flowchart of an example of operation S320 in the process;

[0028] Figure 17 It is a block diagram of an electronic device according to one or more embodiments. Detailed Implementation

[0029] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0030] As used herein, terms such as "first," "second," etc., can modify various components regardless of their order and / or importance, and are used only to distinguish one component from others, without limiting the components. For example, "first user equipment" and "second user equipment" can refer to different user equipment, regardless of order or importance. For example, a first component can be called a second component, and similarly, a second component can be called a first component.

[0031] Figure 1 This is a block diagram of a digital phase-locked loop 100 according to an embodiment.

[0032] Reference Figure 1 The digital phase-locked loop 100 can generate an output signal FOUT based on a reference signal FREF and a feedback signal FFEED. The reference signal FREF can be generated by a crystal oscillator, etc. The reference signal FREF can have a reference frequency. The feedback signal FFEED can include a signal divided from the output signal FOUT by a frequency divider 160. The feedback signal FFEED can have a feedback frequency, and this feedback frequency can be less than the output frequency of the output signal FOUT. The output signal FOUT can have an output frequency, and the ideal or target-matched output frequency of the output signal FOUT can be obtained by multiplying the reference frequency by a desired multiple. In an embodiment, the reference signal FREF, the feedback signal FFEED, and the output signal FOUT can be used as clock signals for sampling received data or synchronizing the timing of internal operations. The reference signal FREF, the feedback signal FFEED, and the output signal FOUT can be referred to herein as the reference clock signal, the feedback clock signal, and the output clock signal, respectively.

[0033] The digital phase-locked loop 100 may include an automatic frequency calibration 110, a phase detector 120, a digital loop filter 130, a digitally controlled oscillator 140, a variable capacitor controller 150, and a frequency divider 160.

[0034] Automatic frequency calibration 110 can generate a digital code for tuning the output frequency of the output signal FOUT during the coarse tuning (or coarse adjustment) operation of the digital phase-locked loop 100, causing the output frequency of the output signal FOUT to vary within a preset frequency range. Based on the reference signal FREF and the feedback signal FFEED, automatic frequency calibration 110 can provide the digital code for tuning the output frequency of the output signal FOUT to the numerically controlled oscillator 140.

[0035] Phase detector 120 can compare the phase of the reference signal FREEF with the phase of the feedback signal FFEED and output the comparison result. For example, the comparison result can indicate that the phase of the feedback signal FFEED is faster than the phase of the reference signal FREEF, or it can indicate that the phase of the feedback signal FFEED is slower than the phase of the reference signal FREEF. Phase detector 120 can determine whether the phase of the reference signal FREEF leads or lags the phase of the feedback signal FFEED, and provides the determination result to digital loop filter 130.

[0036] The digital loop filter 130 can change the loop gain of the digital phase-locked loop 100 during a shifting operation, and sets the final changed loop gain during the shifting operation as the target loop gain. The loop gain can correspond to the amount of compensation for the phase difference between the phase of the reference signal FEF and the phase of the feedback signal FFEED. For example, as the loop gain increases, the amount of phase difference compensation can increase. Conversely, as the loop gain decreases, the amount of phase difference compensation can decrease.

[0037] Digital loop filter 130 can provide multiple segments of digital code to numerically controlled oscillator 140 to compensate for the phase difference between the phase of the reference signal FEF and the phase of the feedback signal FFEED based on a set target loop gain. In embodiments, digital loop filter 130 may include a proportional path, an integral path, etc. The proportional path has a value of proportional gain Kp, and the integral path can be implemented as an integral gain Ki and an integrator. Digital loop filter 130 can receive the feedback signal FFEED from frequency divider 160 and can update the value of the output code used to control the frequency of numerically controlled oscillator 140 at each time interval of the feedback signal FFEED based on the output value of phase detector 120. Furthermore, digital loop filter 130 can receive k times the feedback signal kFFEED to perform operations to improve the frequency resolution of numerically controlled oscillator 140. k can be an integer greater than or equal to 2 and can be set to achieve a relatively small resolution.

[0038] The digital loop filter 130 can generate multiple digital codes to adjust the duty cycle (or duty rate) of the pulse signal generated by the variable capacitor controller 150.

[0039] The numerically controlled oscillator 140 can adjust the output frequency of the output signal FOUT and generate the output signal FOUT based on received digital codes and / or pulse signals. In one or more embodiments, the numerically controlled oscillator 140 can be implemented as an LC oscillator including an inductor and a capacitor. The output frequency of the LC-based numerically controlled oscillator 140 can be set based on the inductance of the inductor and the capacitance of the capacitor. For example, the output frequency can be inversely proportional to the square root of the product of the inductance and capacitance. In one or more embodiments, the LC-based numerically controlled oscillator 140 can include an inductor, multiple capacitor banks, and a negative voltage-to-current converter employing a cross-coupling structure to provide negative resistance. This voltage-to-current converter can be referred to as a transconductance (or gm) unit. The multiple capacitor banks can provide capacitance based on digital codes or pulse signals. The combined capacitance of the numerically controlled oscillator 140 can vary depending on the capacitance provided by the multiple capacitor banks, and accordingly, the output frequency can change. In one or more embodiments, the multiple capacitor banks can include capacitor banks that replace varactor diodes.

[0040] The variable capacitor controller 150 can provide pulse signals to the numerically controlled oscillator 140 during fine-tuning (or micro-adjustment) operations of the digital phase-locked loop 100 to tune the output frequency of the output signal FOUT to a target frequency. For example, the variable capacitor controller 150 can provide pulse signals to some of the capacitor banks that replace varactor diodes among multiple capacitor banks, and some capacitor banks can provide capacitance for a time period corresponding to the duty cycle of the pulse signal. Accordingly, the average capacitance over one period of the pulse signal can be reflected in the combined capacitance of the numerically controlled oscillator 140.

[0041] Frequency divider 160 can output a feedback signal FFEED by dividing the output signal FOUT. In one or more embodiments, frequency divider 160 can output a feedback signal kFFEED multiplied by k.

[0042] A digital phase-locked loop (PLL) 100 can achieve a smaller area by implementing the loop filter (a passive component with a large area) as a digital component. Furthermore, because the digital PLL 100 is robust to pole / zero variations, leakage, and noise in the loop filter, it is insensitive to process variations. Additionally, due to its ease of testing and calibration, the digital PLL 100 can have a short turnaround time (TAT).

[0043] According to one or more of the above embodiments, it is possible to improve the power supply rejection ratio (PSRR) characteristics, improve ultra-low jitter, improve frequency drift caused by temperature changes, and improve the quality of service (QoS) of the numerically controlled oscillator or the quality factor Q of the LC resonator.

[0044] Figure 2 This is a block diagram of a digital phase-locked loop 200 according to one or more embodiments.

[0045] Reference Figure 2 The digital phase-locked loop 200 may include an automatic frequency calibration (AFC) 210, a Bang-Bang phase detector (BBPD) 220, a digital loop filter (DLF) 230, a digitally controlled oscillator (DCO) 240, a pulse width modulation (PWM) 250, and a multimode divider (MMD) 260.

[0046] AFC 210 can correspond to Figure 1An example of automatic frequency calibration 110 in the example. Based on the reference signal FREF and the feedback signal FFEED, AFC 210 can output a frequency correction signal AFCCD, which includes a digital code for coarsely adjusting the output frequency of the output signal FOUT. For example, the output signal FOUT that matches the target signal can be M times the reference signal FREF (where M is an integer greater than or equal to 2). AFC 210 can compare the frequency of the feedback signal FFEED with the frequency of the reference signal FREF at each reference cycle (e.g., 8 cycles) of the reference signal FREF and adjust the output frequency of DCO 240 based on the comparison result. For example, when the phase of the feedback signal FFEED lags behind the phase of the reference signal FREF (i.e., when the feedback signal FFEED is slower than the reference signal FREF), AFC 210 can output the frequency correction signal AFCCD to increase the output frequency of DCO 240. For example, when the phase of the feedback signal FFEED leads the phase of the reference signal FEF (i.e., when the feedback signal FFEED is faster than the reference signal FEF), AFC 210 can output a frequency correction signal AFCCD to reduce the output frequency of DCO 240. AFC 210 can change the code value of the frequency correction signal AFCCD according to a binary search method, where the code changes sequentially from the most significant bit (MSB) to the least significant bit (LSB). In one or more embodiments, AFC 210 can sample the reference signal FEF using the feedback signal FFEED and use the sampled value (e.g., 0 or 1) to determine the correlation between the edges of the feedback signal FFEED and the reference signal FEF. According to the above embodiments, the error in the comparison between edges can be reduced by accumulating the reference period. AFC 210 can determine to reduce the combined capacitance inside DCO 240, thereby increasing the output frequency of the output signal FOUT and reducing the value of the digital code of the frequency correction signal AFCCD. AFC 210 can determine to increase the combined capacitor inside DCO 240, thereby reducing the output frequency of the output signal FOUT and increasing the value of the digital code of the frequency correction signal AFCCD. In an embodiment, AFC 210 can sequentially perform six sample value comparisons to output a frequency correction signal AFCCD including a 6-bit code. After the six comparison operations are completed, AFC 210 can change the logic level of the first enable signal AFC_END from a first logic level to a second logic level. For example, the first logic level of the first enable signal AFC_END can represent a logic low level, and the second logic level of the first enable signal AFC_END can represent a logic high level. However, the embodiment is not limited to the above example.

[0047] BBPD 220 can correspond to Figure 1An example of a phase detector 120 is shown. Based on a reference signal FEF and a feedback signal FFEED, the BBPD 220 can output an up-down signal UPDN. The up-down signal UPDN can include a signal representing the result of a comparison between the phase of the reference signal FEF and the phase of the feedback signal FFEED. For example, when the phase of the feedback signal FFEED leads the phase of the reference signal FEF, the up-down signal UPDN can have a first logic level representing a "falling" phase. When the phase of the feedback signal FFEED lags the phase of the reference signal FEF, the up-down signal UPDN can have a second logic level representing a "rising" phase. For example, the first logic level of the up-down signal UPDN can represent a logic low level, and the second logic level of the up-down signal UPDN can represent a logic high level.

[0048] DLF 230 can correspond to Figure 1 The digital loop filter 130 is included. The DLF 230 may include a gate shifter (GS) 231, an integral gain operator 232, an integrator 233, an adder (or accumulator) 234, a proportional gain operator 235, a binary-to-thermometer (B2T) decoder 236, a bypass circuit 237, a delta-sigma modulator (DSM) 238, and an adaptive bandwidth calibration (ABC) 239. In one or more embodiments, the GS 231, integral gain operator 232, integrator 233, adder 234, proportional gain operator 235, B2T decoder 236, bypass circuit 237, and ABC 239 may all operate synchronously with the feedback signal FFEED. The DSM 238 may operate synchronously with k times the feedback signal kFFEED.

[0049] GS 231 can be enabled in response to the second logic level of the first enable signal AFC_END of AFC 210. GS 231 can receive a target gain signal TIKI, which includes a digital code representing a target loop gain. The target gain signal TIKI can be generated by a core or the like located outside the digital phase-locked loop 200. During a shift operation, GS 231 can sequentially change the loop gain from an initial loop gain (e.g., maximum loop gain) to a target loop gain based on the rise / fall signal UPDN. For example, the digital code representing the value of the loop gain can change whenever the logic level of the rise / fall signal UPDN changes from a first logic level to a second logic level or from a second logic level to a first logic level. After the shift operation is complete, GS 231 can change the logic level of the second enable signal AGS_END from a first logic level (e.g., logic low) to a second logic level (e.g., logic high).

[0050] GS 231 can output a first control signal DCOX, including a digital code, based on the target loop gain and the logic level of the rise / fall signal UPDN. For example, the first control signal DCOX may include a 19-bit digital code, but embodiments are not limited to the examples described above. For instance, the logic level of the rise / fall signal UPDN may have a first logic level when the phase of the feedback signal FFEED is faster than the phase of the reference signal FEF. Since the output frequency must be reduced, the combined capacitance inside DCO 240 can be increased. GS 231 can increase the value of the digital code, thereby increasing the capacitance inside DCO 240. When the phase of the feedback signal FFEED is slower than the phase of the reference signal FEF, the logic level of the rise / fall signal UPDN may have a second logic level. Since the output frequency must be increased, the combined capacitance inside DCO 240 can be decreased. GS 231 can increase the value of the digital code, thereby decreasing the capacitance inside DCO 240.

[0051] Integrator gain arithmetic unit 232 can add the value of integral gain Ki(β) to the value of the digital code of the first control signal DCOX, or subtract the value of integral gain Ki(β) from the value of the digital code of the first control signal DCOX. Integrator 233 can integrate the signal value calculated by integral gain arithmetic unit 232. Proportional gain arithmetic unit 235 can add the value of proportional gain Kp(α) to the value of the digital code of the first control signal DCOX, or subtract the value of proportional gain Kp(α) from the value of the digital code of the first control signal DCOX. The value of proportional gain Kp(α) can be zero when the logic level of the second enable signal AGS_END changes from the first logic level to the second logic level. Adder 234 can add the value of the integration path (e.g., integral gain arithmetic unit 232 and integrator 233) to the value of the proportional path (e.g., proportional gain arithmetic unit 235) and output a second control signal including a digital code representing the sum. For example, the second control signal may include a 19-bit digital code, but the embodiments are not limited to the above examples. The second control signal may include a first high-order signal INT1, a second high-order signal INT2, and a low-order signal FRAC. For example, when the second control signal is 19 bits (e.g., [18:0]), the low-order signal FRAC can be 10 bits (e.g., FRAC[9:0]), the second high-order signal INT2 can be 3 bits (e.g., INT[2:0]), and the first high-order signal INT1 can be 6 bits (e.g., INT[8:3]).

[0052] B2T decoder 236 can decode the digital code of the first high-order signal INT1 into thermometer code and output a thermometer signal THER including the thermometer code. Bypass circuit 237 can bypass the second high-order signal INT2 and output a bypass signal BIN including the bypass digital code. When the value of the digital code of the low-order signal FRAC overflows, DSM 238 can output a jitter signal DTH in response to the rising edge of the k-fold feedback signal kFFEED. The jitter signal DTH can be a 1-bit signal used to trigger the jitter operation of DCO 240. For example, when the value of the digital code of the 10-bit low-order signal FRAC is "1111111111", and the value is increased by 1b (i.e., when the low-order signal FRAC carries to the 11th bit), a pulse signal with a duty cycle can be output as the jitter signal DTH. However, the embodiments are not limited to the above examples. DSM 238 can improve resolution by jittering the 1 LSB capacitor bank, thereby minimizing quantization error. When DSM 238 operates in response to the rising edge of the k-fold feedback signal kFFEED, it can reduce the quantization noise level and mitigate the impact of quantization errors. ABC 239 can be enabled in response to the second logic level of the second enable signal AGS_END. ABC 239 can adjust the gain of PWM 250 to obtain the optimal bandwidth (e.g., the range of output frequency variation) with minimal jitter. ABC 239 can output an adjustment signal IKP based on the rise / fall signal UPDN. The adjustment signal IKP includes a signal for adjusting the gain of PWM 250 and may include a digital code for adjusting the duty cycle of a first time period corresponding to one cycle of the feedback signal FFEED.

[0053] DCO 240 can correspond to Figure 1 The numerically controlled oscillator 140 is included. The DCO 240 may include an inductor, multiple capacitor bank circuitry, and a negative voltage-to-current converter (e.g., a negative GM unit). The multiple capacitor bank circuitry may include a capacitor bank circuitry that receives a first signal PWM_UP and a second signal PWM_DN from PWM 250, and this capacitor bank circuitry can change a first capacitance based on the first signal PWM_UP and the second signal PWM_DN. The negative voltage-to-current converter can compensate for resistive elements in the LC resonant circuit to achieve oscillation conditions. Compared to a ring oscillator, the DCO 240 exhibits superior noise performance, used to improve ultra-low jitter.

[0054] PWM 250 can correspond to Figure 1An example of a variable capacitor controller 150. Based on the feedback signal FFEED, the adjustment signal IKP, and the rise / fall signal UPDN, the PWM 250 can output a first signal PWM_DN or a second signal PWM_UP with a duty cycle corresponding to the adjustment signal. The duty cycle of the first signal PWM_DN and the second signal PWM_UP with a specific logic level can be determined based on the logic level of the rise / fall signal UPDN. For example, when the rise / fall signal UPDN is at a first logic level, the first signal PWM_DN can have a duty cycle with a specific logic level. When the rise / fall signal UPDN is at a second logic level, the second signal PWM_UP can have a duty cycle with a specific logic level. The first signal PWM_UP and the second signal PWM_DN can be included in the capacitor control signal.

[0055] In one or more embodiments, the PWM 250 can detect the logic level of the rise / fall signal UPDN in response to the falling edge of the feedback signal FFEED. In response to the rising edge of the feedback signal FFEED, the PWM 250 can output a pulse signal as a capacitor control signal, which is used to shift the phase of the output signal FOUT according to the logic level of the rise / fall signal UPDN.

[0056] MMD 260 can correspond to Figure 1 An example of a frequency divider 160.

[0057] Figure 3 This is a circuit diagram of DCO 240 according to one or more embodiments.

[0058] Reference Figure 3 The DCO 240 may include an inductor L, multiple capacitor bank circuits 241 to 249, and a negative voltage-to-current converter VIC.

[0059] Inductor L can be connected to the first node N11 and the second node N12. Inductor L can be inductive.

[0060] The capacitor bank circuit 241 can set the capacitance based on the frequency correction signal AFCCD[p:0] during the coarse adjustment operation and provide the capacitance after the coarse adjustment operation is completed. The frequency correction signal AFCCD[p:0] may include p+1 bits of digital code. The capacitor bank circuit 241 may include multiple capacitor banks connected to the first node N11 and the second node N12. The number of capacitor banks included in the capacitor bank circuit 241 may correspond to the number of digital codes in the frequency correction signal AFCCD[p:0]. Each capacitor bank in the capacitor bank circuit 241 may include two capacitors and a transistor located between the two capacitors. The digital code of the corresponding frequency correction signal AFCCD[p:0] can be received at the gate electrode of the corresponding transistor. For example, the gate electrode of transistor TR11 can receive the frequency correction signal AFCCD[0], the gate electrode of transistor TR12 can receive the frequency correction signal AFCCD[1], and the gate electrode of transistor TR1p can receive the frequency correction signal AFCCD[p]. The capacitance of the capacitors in the multiple capacitor banks may be C1, 2C1, ... and 2C1. p C1.

[0061] Capacitor bank circuits 242 to 245 can set the capacitance based on the thermometer signal THER[q:0] and the bypass signal BIN[r:0] during the shift operation, and provide the capacitance after the shift operation is completed.

[0062] Capacitor bank circuits 242 and 243 can receive a thermometer signal THER[q:0] including a q+1 bit digital code. Capacitor bank circuit 242 can include multiple capacitor banks connected to the first node N11. The number of capacitor banks included in capacitor bank circuit 242 can correspond to the number of digital codes in the thermometer signal THER[q:0]. Each capacitor bank in capacitor bank circuit 242 can include a capacitor and a transistor connected in series with each other. For example, the gate electrode of transistor TR21 can receive the thermometer signal THER[0], the gate electrode of transistor TR22 can receive the thermometer signal THER[1], and the gate electrode of transistor TR2q can receive the thermometer signal THER[q]. The capacitors in the multiple capacitor banks can all have the same capacitance C2. Capacitance C2 can be less than capacitance C1. Capacitor bank circuit 243 is connected to the second node N12 and can include circuitry symmetrical to capacitor bank circuit 242.

[0063] The capacitor bank circuit 244 may include multiple capacitor banks, each capacitor bank including a capacitor and a transistor connected in series with each other at the first node N11. The capacitances of the capacitors in the multiple capacitor banks may be C2, 2C2, ... and 2C2. rC2. The capacitor bank circuit 245 is connected to the second node N12 and may include circuitry symmetrical to the capacitor bank circuit 244.

[0064] Capacitor bank circuits 246 and 247 can provide capacitance based on the jitter signal DTH during fine-tuning operation. Capacitor bank circuit 246 may include a capacitor bank comprising a capacitor and a transistor connected in series at the first node N11. The gate electrodes of transistors TR41 and TR42, respectively included in capacitor bank circuits 246 and 247, can receive the jitter signal DTH. When the logic level of the jitter signal DTH is a second logic level, transistors TR41 and TR42 are turned on. Furthermore, the capacitors in capacitor bank circuits 246 and 247 can be connected to the first node N11 and the second node N12 to provide capacitance.

[0065] The capacitor bank circuit 248 can provide capacitance based on the first signal PWM_DN after phase-locked operation. The capacitor bank circuit 248 can be connected between one end of the inductor L and ground, and can include a capacitor bank that provides the first capacitance in response to the activation level of the first signal PWM_DN. The capacitor bank may include a capacitor and a transistor connected in series at the first node N11. The transistor TR51 is turned on in response to a second logic level of the first signal PWM_DN. Since the capacitor in the capacitor bank circuit 248 is connected to the first node N11 via the turned-on transistor TR51, the first capacitance can be provided. The first capacitance may be C2.

[0066] The capacitor bank circuit 249 can provide capacitance based on the second signal PWM_UP after phase-locked operation. The capacitor bank circuit 249 can be connected between the other end of the inductor L and ground, and can include a capacitor bank that provides a first capacitance in response to the activation level of the second signal PWM_UP. The capacitor bank may include a capacitor and a transistor connected in series at the second node N12. The transistor TR52 is turned on in response to a second logic level of the second signal PWM_UP. Since the capacitor in the capacitor bank circuit 249 is connected to the second node N12 via the turned-on transistor TR52, capacitance C2 of the capacitor can be provided.

[0067] Figure 3 The transistors TR11 to TR1p, TR21 to TR2q, TR31 to TR3r, TR41, TR42, TR51, and TR52 shown can be implemented as N-type metal-oxide-semiconductor (NMOS) transistors and can have different sizes. However, the inventive concept is not limited to these. Figure 3 The example shown.

[0068] The negative voltage-to-current converter VIC may include transistors TR61 and TR62. Transistor TR61 is connected between the first node N11 and ground, and its gate electrode is connected to the second node N12. An inverted output signal FOUTB can be output from the first node N11. Transistor TR62 is connected between the second node N12 and ground, and its gate electrode is connected to the first node N11. An output signal FOUT can be output from the second node N12.

[0069] Figure 4 It is a signal timing diagram in a digital phase-locked loop 200 according to one or more embodiments.

[0070] Reference Figure 4 The digital phase-locked loop 200 can effectively eliminate the phase error accumulated in the DCO 240 by using a capacitor bank that receives pulse signals with variable pulse widths, thereby achieving low jitter. The digital phase-locked loop 200 can perform coarse adjustment operation CT_STEP, shift operation GS_STEP (or phase-locking operation), and jitter elimination operation JC_STEP from the start time STARTUP.

[0071] During the coarse adjustment operation CT_STEP, the output frequency FREQ.OFF OUT of the output signal FOUT can be adjusted so that the output frequency FREQ.OFF OUT is within a specific frequency range. For example, when the output frequency FREQ.OFF OUT of the output signal FOUT is less than the target frequency, the output frequency FREQ.OFF OUT of the output signal FOUT can be increased according to the output value of AFC 210. When the output frequency FREQ.OFF OUT of the output signal FOUT is within the specific frequency range, the coarse adjustment operation CT_STEP terminates, and the logic level of the first enable signal AFC_END can change from logic low to logic high.

[0072] To reliably lock the output frequency of the output signal FOUT to the target frequency, cycle slip needs to be prevented. The locking range (representing the range within which the frequency is locked without cycle slip) can be proportional to the loop gain of the digital phase-locked loop 200. Therefore, a shift operation GS_STEP is performed to set the initial loop gain to a large value to reliably correct even relatively large phase differences, and then the loop gain is sequentially reduced from the initial loop gain to the target loop gain. In an embodiment, during the shift operation GS_STEP, whenever the logic level of the first sample signal UPDN_R changes, the value of the loop gain IKI[3:0] can be sequentially reduced from an initial value (e.g., 13) to a target value (e.g., 3). The first sample signal UPDN_R can correspond to the rise / fall signal UPDN. The target value can be set by the target gain signal TIKI, as referenced above. Figure 2As described above. For example, based on the logic level of the first sampling signal UPDN_R, the values ​​of the high-order signals INTY[8:0] and FRAC[9:0] can be changed, and a jitter signal DTH is generated. Accordingly, the output frequency and phase of the output signal FOUT can be tuned. When the logic level of the first sampling signal UPDN_R changes from the first logic level to the second logic level (or from the second logic level to the first logic level), the internal enable signal GSEN can appear as a flag signal, and the loop gain value IKI[3:0] can decrease by 1 in response to the internal enable signal GSEN. The high-order signals INTY[8:0] and FRAC[9:0] can be included in a second control signal with a 19-bit digital code, for example, as referred to above. Figure 2 As described above. For example, some signals INTY[8:3] in the high-order signals INTY[8:0] can correspond to the first high-order signal INT1, some signals INTY[2:0] in the high-order signals INTY[8:0] can correspond to the second high-order signal INT2, and the low-order signal FRAC[9:0] can correspond to the low-order signal FRAC. When the bit signals of FRAC[9:0] are accumulated in the DSM 238, the carry bit generated generates a 1-bit jitter signal (1-bit DTH signal). The phase difference between the reference signal FREF and the feedback signal FFEED (see Figure 4 The phase difference between FFEED and FREF will gradually approach zero. When the loop gain IKI[3:0] is set to the target value, the value of the high-order signal INTY[8:0] is locked, the shift operation GS_STEP is terminated, and the logic level of the second enable signal AGS_END can change from logic low to logic high.

[0073] During the jitter clearing operation JC_STEP, a first signal PWM_DN and a second inverted signal PWM_UPB can be generated based on the logic level of the first sampled signal UPDN_R. Correspondingly, the output frequency and phase of the output signal FOUT can be tuned. The second inverted signal PWM_UPB can represent the signal formed by inverting the second signal PWM_UP. When the logic level of the first sampled signal UPDN_R is logic low, the first signal PWM_DN can have a logic high duty cycle, and the second inverted signal PWM_UPB can remain logic high. When the logic level of the first sampled signal UPDN_R is logic high, the first signal PWM_DN can remain logic low, and the second inverted signal PWM_UPB can have a logic high duty cycle. The duty cycle of either the first signal PWM_DN or the second inverted signal PWM_UPB can vary depending on the value of the adjustment signal IKP. After the shift operation GS_STEP, the values ​​of the high-order signals INTY[8:0] can remain unchanged, and the values ​​of the low-order signals FRAC[9:0] can change very little. This could mean that the output frequency of the DCO 240 varies less.

[0074] The jitter clearing operation JC_STEP refers to the operation that effectively eliminates the accumulated error in DCO 240 during each time period of the reference signal FREF after the shift operation GS_STEP. An example of tuning the output frequency and phase of the output signal FOUT during the jitter clearing operation JC_STEP is described below.

[0075] Figure 5 and Figure 6 These are block diagrams of ABC 239a and ABC 239b according to embodiments.

[0076] Reference Figure 5 ABC 239a may include a delay unit DLY, an exclusive logical sumoperator XORG1, and an accumulator ACC.

[0077] The delay unit DLY can delay the rise / fall signal UPDN and output a delayed rise / fall signal UPDN_D. For example, the delayed rise / fall signal UPDN_D can represent a signal that is delayed by one cycle compared to the rise / fall signal UPDN.

[0078] The XOR operator XORG1 performs an XOR operation between the logic level of the rising / falling signal UPDN and the logic level of the delayed rising / falling signal UPDN_D, and outputs a result signal UPDN_X1 representing the result of the XOR operation. For example, when the logic level of the rising / falling signal UPDN is equal to the logic level of the delayed rising / falling signal UPDN_D, the logic level of the result signal UPDN_X1 can be logic low. Conversely, when the logic level of the rising / falling signal UPDN is different from the logic level of the delayed rising / falling signal UPDN_D, the logic level of the result signal UPDN_X1 can be logic high.

[0079] The accumulator ACC accumulates the result signal UPDN_X1, changes the value of the digital code based on the accumulated result, and outputs an adjustment signal IKP. The accumulated result may, for example, correspond to the gain value (represented by an 8-bit digital code) of the variable capacitor controller 150 (e.g., PWM 250). The on-time of the capacitor bank switch (e.g., transistor TR) can be adjusted according to the adjustment signal IKP, which will be referred to below. Figure 9 Describe it.

[0080] Reference Figure 6 ABC 239b may include a logical product operator ANDG, a first sampler FF11, a second sampler FF12, an XOR operator XORG2, and an accumulator ACC.

[0081] The logic product operator ANDG can perform a logic product operation between the logic level of the first enable signal AFC_END and the logic level of the rise / fall signal UPDN, and can provide the result of the logic product operation to the first sampler FF11. According to one or more embodiments, in the shift operation GS_STEP and the jitter clear operation JC_STEP, the logic level of the first enable signal AFC_END can be a second logic level (e.g., a logic high level). In the shift operation GS_STEP and the jitter clear operation JC_STEP, the logic product operator ANDG can provide the logic level of the rise / fall signal UPDN to the first sampler FF11.

[0082] The first sampler FF11 can sample the logical product operation result of the logical multiplier ANDG in response to the edge of the feedback signal FFEED, and output the first sampled signal UPDN_R. According to one or more embodiments, in the shift operation GS_STEP and the jitter clear operation JC_STEP, the first sampler FF11 can sample the rise / fall signal UPDN in response to the rising edge of the feedback signal FFEED.

[0083] In response to the edge (e.g., rising edge) of the feedback signal FFEED, the second sampler FF12 can sample the first sample signal UPDN_R and output the second sample signal UPDN_RR.

[0084] As a non-limiting example, the first sampler FF11 and the second sampler FF12 can be implemented as triggers.

[0085] The XOR operator XORG2 can perform an XOR operation on the logic levels of the first sampled signal UPDN_R and the second sampled signal UPDN_RR, and output the result signal UPDN_X2 representing the result of the XOR operation.

[0086] The accumulator ACC can change the value of the digital code of the adjustment signal IKP based on the operation result signal UPDN_X2, and output the adjustment signal IKP. In one or more embodiments, when the logic levels of the rise and fall signals UPDN remain at the same logic level, the logic level of the operation result signal UPDN_X2 can be a first logic level. In this case, the accumulator ACC can determine that the gain of PWM 250 is low, and can increase the gain of PWM 250 by increasing the value of the adjustment signal IKP. When the logic level of the rise and fall signals UPDN continuously changes, the logic level of the operation result signal UPDN_X2 can be a second logic level. In this case, the accumulator ACC can determine that the gain of PWM 250 is high, and can decrease the gain of PWM 250 by decreasing the value of the adjustment signal IKP.

[0087] Figure 7 This is a block diagram of a PWM 250 according to one or more embodiments; Figure 8 This is a circuit diagram of a pulse generator according to one or more embodiments; and Figure 9 This is a circuit diagram of a delay unit according to one or more embodiments.

[0088] Reference Figures 7 to 9 The PWM 250, as an example of a variable capacitor controller, may include a pulse generator 251 and a delay unit 252.

[0089] The pulse generator 251 can receive a second enable signal AGS_END, a rise / fall signal UPDN, and a feedback signal FFEED. The pulse generator 251 can sample the second enable signal AGS_END and the rise / fall signal UPDN in response to the edge of the feedback signal FFEED. Based on the sampled enable signal PULSE and the sampled rise / fall signal UPDN_S, the pulse generator 251 can output a first signal PWM_UP and a second signal PWM_DN as capacitor control signals. The pulse generator 251 can be reset in response to the delay signal PULSE_D.

[0090] Reference Figure 8 In an embodiment, the pulse generator 251 may include a first inverter INV1 and a second inverter INV2, a first flip-flop FF21, a second flip-flop FF22 and a third flip-flop FF23, a logic AND unit ORG, a negative logic AND unit NORG, and a negative logic product unit NANDG.

[0091] The first inverter INV1 can invert the feedback signal FFEED and provide the inverted feedback signal to the first flip-flop FF21.

[0092] The first flip-flop FF21 can sample the second enable signal AGS_END in response to the edge of the inverted feedback signal. The first flip-flop FF21 can output a feedback reset signal FEED_R. The first flip-flop FF21 can be reset in response to the reset signal PULSE_R.

[0093] The second flip-flop FF22 can sample the second enable signal AGS_END in response to the edge of the feedback signal FFEED. The second flip-flop FF22 can output the sampling enable signal PULSE. The second flip-flop FF22 can be reset in response to the reset signal PULSE_R.

[0094] The third flip-flop FF23 can sample the rise / fall signal UPDN in response to the edge of the feedback signal FFEED and output the sampled rise / fall signal UPDN_S. The third flip-flop FF23 can be reset in response to the second enable signal AGS_END. According to one or more embodiments, in the jitter clearing operation JC_STEP, the second enable signal AGS_END can be maintained at a second logic level (e.g., logic high). Therefore, the third flip-flop FF23 can remain reset in the fine-tuning operation FT_STEP, and the logic level of the sampled rise / fall signal UPDN_S can be maintained at a first logic level.

[0095] The ORG logic unit can perform a logical AND operation between the logic level of the feedback reset signal FEED_R and the logic level of the delay signal PULSE_D, and output the reset signal PULSE_R.

[0096] The second inverter INV2 can invert the sampling enable signal PULSE and provide the inverted enable signal to the negative logic AND unit NORG and the negative logic product unit NANDG.

[0097] The negative logic AND unit NORG performs a negative logic AND operation between the logic level of the sampled rise / fall signal UPDN_S and the logic level of the inverted enable signal. NORG outputs a first signal PWM_DN, which causes a phase lag in the output signal FOUT.

[0098] The negative logic product operator NANDG performs a negative logic product operation between the logic level of the sampled rise / fall signal UPDN_S and the logic level of the sampled enable signal PULSE. The negative logic product operator NANDG outputs a second signal PWM_UP, which causes a phase lead in the output signal FOUT.

[0099] Delay unit 252 can receive a sampled enable signal PULSE and an adjustment signal IKP[n-1:0]. In one or more embodiments, the adjustment signal IKP[n-1:0] may include an n-bit digital code. Delay unit 252 can determine the delay time of the sampled enable signal PULSE based on the adjustment signal IKP[n-1:0]. Delay unit 252 can output a delayed signal PULSE_D by delaying the sampled enable signal PULSE using the delay time.

[0100] In one or more embodiments, delay unit 252 may include an inverter INV and an RC delay circuit RCDC. The inverter INV may invert the sampled enable signal. The RC delay circuit RCDC may represent a delay circuit including a variable resistor and a variable capacitor. The RC delay circuit RCDC may determine the amount of delay of the signal inverted by the inverter INV based on the digital code of the adjustment signal IKP[n-1:0], and provide the delayed signal PULSE_D to the pulse generator 251.

[0101] Reference Figure 7 and Figure 9 In one or more embodiments, the inverter INV of delay unit 252 may include a first transistor TR71 and a second transistor TR72. The RC delay circuit RCDC of delay unit 252 may include a variable resistor VR and a capacitor bank array CBA.

[0102] The first transistor TR71 of the inverter INV can send the power supply voltage VDD to the first node N21 in response to the first logic level of the sampled enable signal PULSE.

[0103] The second transistor TR72 of the inverter INV can send the ground voltage to the second node N22 in response to the second logic level of the sampled enable signal PULSE. In one or more embodiments, the first transistor TR71 can be implemented as a P-type MOS (PMOS) transistor, and the second transistor TR72 can be implemented as an NMOS transistor.

[0104] The variable resistor VR of the RC delay circuit RCDC can be connected between the first node N21 and the second node N22. The resistance (or resistance value) of the variable resistor VR can be set by the core or other components located outside the digital phase-locked loop 200.

[0105] The capacitor bank array CBA of the RC delay circuit RCDC is connected between the second node N22 and ground, and can provide a second capacitance corresponding to the delay amount based on the digital code. The capacitor bank array CBA can include multiple capacitor banks. Each capacitor bank in the capacitor bank array CBA can include a transistor and a capacitor. The adjustment signal IKP[n-1:0] can include an n-bit digital code. The number of capacitor banks receiving the high bits of the n-bit digital code can be twice the number of capacitor banks receiving the low bits of the n-bit digital code. For example, 128 capacitor banks can receive the adjustment signal IKP[n-1], 64 capacitor banks can receive the adjustment signal IKP[n-2], 2 capacitor banks can receive the adjustment signal IKP[1], and 1 capacitor bank can receive the adjustment signal IKP[0]. However, the embodiments are not limited to the above examples. As the value of the digital code of the adjustment signal IKP[n-1:0] increases or decreases, the number of capacitor banks conducting in the capacitor bank array CBA can increase or decrease, and the delay amount or delay time caused by the RC delay circuit RCDC can vary. For example, as the value of the digital code of the adjustment signal IKP[n-1:0] increases, the number of capacitor banks in the capacitor bank array CBA that are turned on can increase, and the delay amount or delay time can increase. Conversely, as the value of the digital code of the adjustment signal IKP[n-1:0] decreases, the number of capacitor banks in the capacitor bank array CBA can decrease, and the delay amount or delay time can decrease.

[0106] Figure 10 yes Figure 8 and Figure 9 Timing diagrams for the FFEED, PULSE, PULSE_D, UPDN, PWM_UP, and PWM_DN signals. Figure 10 In this context, we assume that the first logic level is logic low and the second logic level is logic high.

[0107] Reference Figures 8 to 10Assume that during the time period from the first time point t1 to the fourth time point t4, the logic level of the rise / fall signal UPDN is the second logic level; during the time period from the fourth time point t4 to the eighth time point t8, the logic level of the rise / fall signal UPDN is the first logic level; and starting from the eighth time point t8, the logic level of the rise / fall signal UPDN changes from the first logic level to the second logic level.

[0108] In one or more embodiments, the logic level of the rise / fall signal UPDN can be detected in response to the falling edge of the feedback signal FFEED. After the falling edge of the feedback signal FFEED occurs, either the first signal PWM_DN or the second signal PWM_UP can be output as a pulse in response to the rising edge of the feedback signal FFEED. Accordingly, no glitches occur.

[0109] Although not shown in the figure, it is assumed that before the first time point t1, at the falling edge of the feedback signal FFEED, the logic level of the rise / fall signal UPDN is detected to be the first logic level.

[0110] At the first time point t1, in response to the rising edge of the feedback signal FFEED, the logic level of the sampled enable signal PULSE can be the second logic level. Correspondingly, the logic level of the second signal PWM_UP can also be the second logic level.

[0111] As the rising edge of the sampling enable signal PULSE appears, the rising edge of the delayed signal PULSE_D, which is delayed by a delay time RC DELAY, can appear at the second time point t2. In this case, the logic level of the reset signal PULSE_R changes to the second logic level, and the first flip-flop FF21 and the second flip-flop FF22 can be reset. In this case, the logic level of the sampling enable signal PULSE can change from the second logic level to the first logic level.

[0112] At the third time point t3, the logic level of the reset signal PULSE_R can change from the second logic level to the first logic level.

[0113] At the fourth time point t4, the falling edge of the feedback signal FFEED can occur, and the logic level of the rise / fall signal UPDN can be detected. In this case, the logic level of the rise / fall signal UPDN can be the first logic level. The frequency correction timing used to cause phase lag in the output signal FOUT or to reduce the output frequency of the output signal FOUT can be at the moment when the rising edge of the feedback signal FFEED occurs after the fourth time point t4.

[0114] At the fifth time point t5, the logic level of the sampled enable signal PULSE changes from the first logic level to the second logic level in response to the rising edge of the feedback signal FFEED, and correspondingly, the logic level of the first signal PWM_DN can change from the first logic level to the second logic level.

[0115] After the fifth time point t5 (t6, t7, and t8), the timing of the signals represented by the reference numerals FFEED, PULSE, PULSE_D, UPDN, PWM_UP, and PWM_DN is similar to the timing of the signals represented by the reference numerals FFEED, PULSE, PULSE_D, UPDN, PWM_UP, and PWM_DN from the second time point t2 to the fourth time point t4, therefore their description is omitted. Furthermore, at the eighth time point t8, the logic level of the rise / fall signal UPDN can be detected as the second logic level in response to the falling edge of the feedback signal FFEED. In this case, the timing of the signals represented by the reference numerals FFEED, PULSE, PULSE_D, UPDN, PWM_UP, and PWM_DN can be similar to the timing of the signals represented by the reference numerals FFEED, PULSE, PULSE_D, UPDN, PWM_UP, and PWM_DN from the first time point t1 to the fourth time point t4.

[0116] Figure 11 This is a schematic diagram showing a variable capacitor.

[0117] Reference Figure 11 The first DCO, DCO1, may include a MOSFET-based varactor diode VTR. The capacitance of the varactor diode VTR can vary in response to a DC voltage DC. As the DC voltage increases, the capacitance of the varactor diode VTR also increases, and can converge to a maximum capacitance. For example, in... Figure 11 In the voltage-capacitance diagram shown, the capacitance of the varactor diode VTR can be 0.25C when the input DC voltage DC is a specific value. When the input DC voltage DC changes, the capacitance also changes, which can cause the output frequency of the first DCO, DCO1, to change. Therefore, the varactor diode VTR is susceptible to power supply noise or interference. The threshold voltage of the MOSFET in the varactor diode VTR can change with temperature, and therefore the capacitance can also change. Thus, the varactor diode VTR will experience frequency drift due to temperature. Furthermore, the quality factor of the capacitance of the varactor diode VTR is lower than that of a metal capacitor. In addition, the varactor diode VTR produces a voltage-capacitance curve with non-linear characteristics. Therefore, the first DCO, DCO1, has relatively high jitter sensitivity, is susceptible to temperature changes, and has a low quality factor.

[0118] On the other hand, according to one or more embodiments, digital phase-locked loops 100 and 200 include a second DCO, DCO2. The second DCO, DCO2, may include a first capacitor bank CPBK1 and a second capacitor bank CPBK2, replacing the varactor diode VTR of the first DCO, DCO1. The first capacitor bank CPBK1 may receive a first signal PWM_DN, and the second capacitor bank CPBK2 may receive a second signal PWM_UP. When the first signal PWM_DN or the second signal PWM_UP occurs in pulse form, the switch of the capacitor bank receiving the pulse signal is turned on, and the capacitor bank can provide capacitance for a time period corresponding to the pulse width. In this case, the capacitor bank receiving the pulse signal can provide an average capacitance for one time period of the pulse signal. To set the capacitance to be equal to the 0.25C capacitance of the varactor diode VTR, a first signal PWM_DN with a duty cycle of 0.25% can be generated. In this case, the first capacitor bank CPBK1 provides capacitance C during 1 / 4 of the time period of the first signal PWM_DN through the on state of the switch, and does not provide capacitance during 3 / 4 of the time period of the first signal PWM_DN through the off state of the switch. Therefore, during a certain time period of the first signal PWM_DN, the average capacitance of the first capacitor bank CPBK1 in the LC resonant cavity can be 0.25C.

[0119] According to the above embodiments, unlike the comparative example where the output frequency is corrected by inputting a DC voltage DC to the varactor diode VTR, the average capacitance in the LC resonant cavity is adjusted by adjusting the on-off time of the capacitor bank. Accordingly, these embodiments can overcome the limitations of the varactor diode VTR (e.g., poor power supply rejection ratio (PSRR), output frequency drift due to temperature changes, limited low-jitter performance, etc.).

[0120] The above embodiments can significantly reduce the frequency error in the initial period of the feedback signal FFEED, thereby reducing the root mean square (RMS) jitter.

[0121] Figure 12 This is a flowchart illustrating a method of operating a digital phase-locked loop according to one or more embodiments.

[0122] Reference Figure 12 In operation S100, the digital phase-locked loop can generate a rise / fall signal based on a reference signal and a feedback signal. The rise / fall signal can include a signal representing the result of a comparison between the phase of the reference signal and the phase of the feedback signal. Operation S100 can be... Figure 1 Phase detector 120 and / or Figure 2 BBPD 220 is executed.

[0123] In operation S200, the digital phase-locked loop can generate an adjustment signal including a digital code based on the rise / fall signal. This adjustment signal may include a signal for adjusting the duty cycle of a first time period corresponding to the time period of the feedback signal. Operation S200 can be... Figure 1 The digital loop filter 130 and / or Figure 2 ABC 239 is executed.

[0124] In operation S300, the digital phase-locked loop can generate a capacitor control signal with a duty cycle based on the feedback signal, adjustment signal, and rise / fall signal. Operation S300 can be... Figure 1 The variable capacitor controller 150 and / or Figure 2 PWM 250 is executed.

[0125] In operation of S400, the digital phase-locked loop can set a first capacitor for a second time period corresponding to the duty cycle of the capacitor control signal.

[0126] In operation S500, the digital phase-locked loop can set the output frequency based on the average value of the inductor and the first capacitor during the first time period, and then generate an output signal with that output frequency. Operations S400 and S500 can be... Figure 1 The numerically controlled oscillator 140 and / or Figure 2 DCO 240 is executed.

[0127] In operating the S600, the digital phase-locked loop can generate a feedback signal by dividing the output signal. Figure 1 Frequency divider 160 and / or Figure 2 MMD 260 is executed.

[0128] Figure 13 It shows Figure 12 A flowchart of an example of operation S200 in the process.

[0129] Reference Figure 13 Operation S200 may include operations S211, S213, S215, and S217. Operations S211, S213, S215, and S217 can be performed by... Figure 5 ABC 239a is executed.

[0130] In operation S211, the digital phase-locked loop can delay the rise and fall signals. Operation S211 can be performed by... Figure 5 The delayer DLY in the process is executed.

[0131] In operation S213, the digital phase-locked loop can perform an XOR operation between the logic level of the rising / falling signal and the logic level of the delayed rising / falling signal. Operation S213 can be performed by... Figure 5 The XOR operator XORG1 in the code is executed.

[0132] In operation S215, the digital phase-locked loop (PLL) can accumulate the result of the XOR operation. In operation S217, the PLL can change the value of the digital code based on the accumulated result. Operations S215 and S217 can be... Figure 5 The accumulator ACC in the process is executed.

[0133] Figure 14 It shows Figure 12 The flowchart shows another example of operation S200.

[0134] Reference Figure 14 Operation S200 may include operations S222, S224, S226, and S228. Operations S222, S224, S226, and S228 can be... Figure 6 Execute ABC 239b in the code.

[0135] In operation S222, the digital phase-locked loop can sample the rising and falling signals in response to the edge of the feedback clock signal, thereby generating the first sampled signal. Operation S222 can be... Figure 6 The first sampler FF11 in the process is executed.

[0136] In operation S224, the digital phase-locked loop can sample the first sampled signal in response to the edge of the feedback clock signal, thereby generating the second sampled signal. Operation S224 can be... Figure 6 The second sampler FF12 in the process is executed.

[0137] In operation S226, the digital phase-locked loop can perform an XOR operation between the logic level of the first sampled signal and the logic level of the second sampled signal. Operation S226 can be performed by... Figure 6 The XOR operator XORG2 in the code is executed.

[0138] In operation S228, the digital phase-locked loop can change the value of the digital code based on the result of the XOR operation. Operation S228 can be... Figure 6 The accumulator ACC in the process is executed.

[0139] Figure 15 It shows Figure 12 A flowchart of an example of operation S300 in the process.

[0140] Reference Figure 15Operation S300 may include operations S310 and S320. Operations S310 and S320 can be referred to above. Figures 7 to 10 The PWM 250 described is executed.

[0141] In operation of S310, the digital phase-locked loop can detect the logic level of the rise and fall signals in response to the falling edge of the feedback signal.

[0142] In operation of S320, the digital phase-locked loop can generate a pulse signal as a capacitor control signal in response to the rising edge of the feedback signal. The pulse signal may include a signal used to shift the phase of the output signal according to the logic level of the rising or falling signal.

[0143] Figure 16 It shows Figure 15 A flowchart of an example of operation S320 in the process.

[0144] Reference Figure 16 Operation S320 may include operations S321, S322, and S323. Operations S321, S322, and S323 can be referred to above. Figures 7 to 10 The PWM 250 described is executed.

[0145] In operation S321, the digital phase-locked loop determines whether the logic level of the rise / fall signal is a first logic level. In some embodiments, the digital phase-locked loop can also determine whether the logic level of the rise / fall signal is a second logic level.

[0146] When the logic level of the rise / fall signal is the first logic level (S321, Yes), the digital phase-locked loop can generate a first pulse signal in response to the first logic level of the rise / fall signal in operation S322. This first pulse signal causes a phase lag in the output signal.

[0147] When the logic level of the rise / fall signal is the second logic level (S321, No), the digital phase-locked loop can generate a second pulse signal in response to the second logic level of the rise / fall signal in operation S323. This second pulse signal causes the output signal to lead in phase.

[0148] Figure 17 This is a block diagram of an electronic device 300 according to one or more embodiments.

[0149] Reference Figure 17Electronic device 300 may include antenna 310, duplexer 320, receiver 330, transmitter 340, processor 350, and PLL 360. Duplexer 320 can transmit or receive radio frequency (RF) signals via antenna 310. Receiver 330 can receive RF signals, convert the received RF signals into data signals, and provide the data signals to processor 350. Transmitter 340 can receive data signals from processor 350, convert the received data signals into RF signals, and output the RF signals. Receiver 330 or transmitter 340 can operate in response to an output clock signal from PLL 360. Processor 350 can control the operation of receiver 330 or transmitter 340. Processor 350 can process data signals in response to an output clock signal from PLL 360. PLL 360 may correspond to... Figure 1 Digital phase-locked loop 100 and / or Figure 2 The digital phase-locked loop 200 is mentioned above. Figures 1 to 16 The described embodiments can be applied to PLL 360.

[0150] According to the above embodiments, digital phase-locked loops 100 and 200, PLL 360, and electronic device 300 achieve small area and high performance by utilizing capacitor banks with relatively small capacitance.

[0151] While certain embodiments have been specifically shown and described, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A digital phase-locked loop, comprising: A phase detector is configured to compare the phase of a reference signal with the phase of a feedback signal and output a rise / fall signal representing the result of the comparison. A digital loop filter is configured to output an adjustment signal including a digital code based on the rise / fall signal, the digital code being used to adjust the duty cycle of a first time period corresponding to the time period of the feedback signal; A variable capacitor controller is configured to output a capacitor control signal having the duty cycle based on the feedback signal, the adjustment signal, and the rise / fall signal; Numerical control oscillator, including: Inductor; A capacitor bank circuit is configured to change a first capacitor based on the capacitor control signal; and A negative voltage-to-current converter is configured to output an output signal having a phase adjusted based on the inductance of the inductor and the average of the first capacitance during the first time period; and The frequency divider is configured to generate the feedback signal by dividing the output signal.

2. The digital phase-locked loop according to claim 1, wherein, The digital loop filter includes: A delay unit is configured to delay the rise / fall signal and output a delayed rise / fall signal; An XOR operator is configured to perform an XOR operation based on the rising / falling signal and the delayed rising / falling signal, and output a result signal representing the result of the XOR operation; and An accumulator is configured to accumulate the operation result signal, change the value of the digital code according to the accumulation result, and output the adjustment signal.

3. The digital phase-locked loop according to claim 1, wherein, The digital loop filter includes: A first sampler is configured to sample the rise / fall signal in response to the edge of the feedback signal and output a first sampled signal; A second sampler is configured to sample the first sampled signal in response to an edge of the feedback signal and output a second sampled signal. An XOR operator is configured to perform an XOR operation based on the first sampled signal and the second sampled signal, and output a result signal representing the result of the XOR operation; and An accumulator is configured to change the value of the digital code based on the operation result signal and output the adjustment signal.

4. The digital phase-locked loop according to claim 1, wherein, The variable capacitor controller includes: A pulse generator is configured to receive an enable signal from the digital loop filter, sample the enable signal and the rise / fall signal in response to an edge of the feedback signal, and output the capacitor control signal based on the sampled enable signal and the sampled rise / fall signal; and The delay unit is configured to determine the delay time of the sampled enable signal based on the adjustment signal, and to delay the sampled enable signal using the delay time to output a delayed signal.

5. The digital phase-locked loop according to claim 4, wherein, The pulse generator includes: A first inverter is configured to invert the feedback signal and output an inverted feedback signal; The first flip-flop is configured to output a feedback reset signal in response to the edge of the inverted feedback signal, and to reset in response to the reset signal; The second trigger is configured to output the sampled enable signal in response to the edge of the feedback signal, and to be reset in response to the reset signal; The third trigger is configured to output the sampled rise / fall signal in response to the edge of the feedback signal, and to be reset in response to the enable signal; A logic and arithmetic unit is configured to perform a logic and arithmetic operation based on the feedback reset signal and the delay signal, and to output the reset signal; The second inverter is configured to invert the sampled enable signal and output an inverted enable signal. A negative logic AND operator is configured to perform a negative logic AND operation based on the sampled rising / falling signal and the inverted enable signal, and output a first signal as the capacitor control signal, the first signal causing a phase hysteresis in the output signal; and A negative logic product operator is configured to perform a negative logic product operation based on the sampled rise / fall signal and the sampled enable signal, and output a second signal as the capacitor control signal, the second signal causing a phase lead of the output signal.

6. The digital phase-locked loop according to claim 5, wherein, The capacitor bank circuit includes: A first capacitor bank, connected between a first terminal of the inductor and ground, is configured to provide the first capacitance in response to the first signal; and A second capacitor bank is connected between the second terminal of the inductor and ground, and is configured to provide the first capacitance in response to the second signal.

7. The digital phase-locked loop according to claim 4, wherein, The delay unit includes: An inverter is configured to invert the sampled enable signal; and A delay circuit is configured to determine the amount of delay of the signal inverted by the inverter based on the digital code of the adjustment signal, and to output the delayed signal.

8. The digital phase-locked loop according to claim 7, wherein, The inverter includes: A first transistor, configured to send a power supply voltage to a first node in response to a first logic level of the sampled enable signal; and The second transistor is configured to send a ground voltage to the second node in response to a second logic level of the sampled enable signal; and The delay circuit includes: Resistors, connected to the first node and the second node; and A capacitor bank array is connected between the second node and ground and is configured to provide a second capacitance corresponding to the delay amount based on the digital code.

9. The digital phase-locked loop according to claim 8, wherein, The digital code consists of n bits, where n is an integer greater than or equal to 2; The capacitor array includes multiple capacitor banks that receive the n-bit digital code, and The first number of capacitor banks receiving the high bits of the n-bit digital code is twice the second number of capacitor banks receiving the low bits of the n-bit digital code.

10. The digital phase-locked loop according to claim 1, wherein, The variable capacitor controller is configured to: The logic level of the rise / fall signal is detected in response to the falling edge of the feedback signal; as well as The output pulse signal is used as the capacitor control signal in response to the rising edge of the feedback signal. The pulse signal is used to shift the phase of the output signal according to the logic level of the rising and falling signals.

11. A method for operating a digital phase-locked loop, the method comprising: Generate a rising or falling signal that represents the result of comparing the phase of the reference signal with the phase of the feedback signal; An adjustment signal including a digital code is generated based on the rise and fall signal. The digital code is used to adjust the duty cycle of a first time period corresponding to the time period of the feedback signal. A capacitor control signal with the duty cycle is generated based on the feedback signal, the adjustment signal, and the rise / fall signal; The first capacitor is set during a second time period corresponding to the duty cycle of the capacitor control signal; The average phase adjustment is based on the inductance and the first capacitor during the first time period to generate an output signal having the phase. as well as The feedback signal is generated by dividing the output signal by frequency.

12. The method according to claim 11, wherein, Generating the adjustment signal includes: The rise and fall signals are delayed; Perform an XOR operation between the aforementioned rise / fall signal and the delayed rise / fall signal; The result of the XOR operation is summed; and The value of the digital code is changed based on the result of the cumulative calculation.

13. The method according to claim 11, wherein, Generating the adjustment signal includes: The rise / fall signal is sampled in response to the edge of the feedback signal to generate a first sampled signal; The first sampled signal is sampled in response to the edge of the feedback signal to generate a second sampled signal; Perform an XOR operation between the first sampled signal and the second sampled signal; and The value of the digital code is changed based on the result of the XOR operation.

14. The method according to claim 11, wherein, Generating the capacitor control signal includes: The logic level of the rise / fall signal is detected in response to the falling edge of the feedback signal; and A pulse signal is generated in response to the rising edge of the feedback signal as the capacitor control signal. The pulse signal is used to shift the phase of the output signal according to the logic level of the rising and falling signals.

15. The method according to claim 14, wherein, Generating the pulse signal as the capacitor control signal includes: A first pulse signal is generated in response to a first logic level of the rise / fall signal, the first pulse signal causing a phase lag in the output signal; and A second pulse signal is generated in response to the second logic level of the rise / fall signal, and the second pulse signal causes the output signal to lead in phase.

16. An electronic device for generating an output clock signal based on a reference clock signal, the electronic device comprising: A phase detector is configured to compare the phase of a reference clock signal with the phase of a feedback clock signal and output a rise / fall signal representing the result of the comparison. A digital loop filter is configured to output an adjustment signal including a digital code based on the rise and fall signal, the digital code being used to adjust the duty cycle of a first time period corresponding to the time period of the feedback clock signal; A variable capacitor controller is configured to output a capacitor control signal having the duty cycle based on the feedback clock signal, the adjustment signal, and the rise / fall signal; A numerically controlled oscillator is configured to change the capacitance of a capacitor bank circuit based on the capacitor control signal, and to adjust the phase of the output clock signal based on the average capacitance during the first time period. as well as A frequency divider is configured to generate the feedback clock signal by dividing the output clock signal.

17. The electronic device according to claim 16, wherein, The digital loop filter includes: A delay unit is configured to delay the rise / fall signal and output a delayed rise / fall signal; An XOR operator is configured to perform an XOR operation based on the rising / falling signal and the delayed rising / falling signal, and output a result signal representing the result of the XOR operation; and An accumulator is configured to accumulate the operation result signal, change the value of the digital code according to the accumulation result, and output the adjustment signal.

18. The electronic device according to claim 16, wherein, The digital loop filter includes: A first sampler is configured to sample the rise / fall signal in response to the edge of the feedback clock signal and output a first sampled signal; The second sampler is configured to sample the first sample signal in response to the edge of the feedback clock signal and output a second sample signal; An XOR operator is configured to perform an XOR operation based on the first sampled signal and the second sampled signal, and output a result signal representing the result of the XOR operation; and An accumulator is configured to change the value of the digital code based on the operation result signal and output the adjustment signal.

19. The electronic device according to claim 16, wherein, The variable capacitor controller includes: A pulse generator is configured to receive an enable signal from the digital loop filter, sample the enable signal and the rise / fall signal in response to the edge of the feedback clock signal, and output the capacitor control signal based on the sampled enable signal and the sampled rise / fall signal; and The delay unit is configured to determine the delay time of the sampled enable signal based on the adjustment signal, and to delay the sampled enable signal using the delay time to output a delayed signal.

20. The electronic device according to claim 16, wherein, The variable capacitor controller is also configured to: The logic level of the rise / fall signal is detected in response to the falling edge of the feedback clock signal; as well as In response to the rising edge of the feedback clock signal, an output pulse signal is used as the capacitor control signal. The pulse signal is used to shift the phase of the output clock signal according to the logic level of the rising and falling signals.

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