ADC circuit with DAC including capacitance

Abstract

An ADC circuit includes an ADC that converts an input analog signal into a digital signal. The ADC circuit includes a filter circuit that receives the analog input signal and provides a filtered signal to a synthesizer circuit. The ADC circuit includes a DAC that converts the digital signal back into an analog signal provided to a synthesizer circuit. The DAC includes one or more capacitive paths having capacitors between an input of the DAC and an output of the DAC.

Description

Technical Field

[0001] This invention relates to an analog-to-digital circuit including a digital-to-analog converter with a capacitor. Background Technology

[0002] Some analog-to-digital converter (ADC) circuits, such as continuously timed pipelined ADC circuits, include digital-to-analog converters (DACs) for converting converted digital values ​​back to analog values. Summary of the Invention

[0003] In one embodiment, an analog-to-digital converter (ADC) circuit includes: a circuit input configured to receive an analog signal; a filter circuit including an input coupled to the circuit input to receive the analog signal and an output for providing a filtered signal; a first ADC including an input coupled to the circuit input to receive the analog signal and an output for providing a first digital signal as a digital representation of the analog signal; a digital-to-analog converter (DAC) including an input coupled to receive the first digital signal and an output for providing an analog signal representing the first digital signal, wherein the first digital signal is received by the DAC from the first ADC on at least one signal line; a synthesizer circuit including a first input coupled to the filter circuit to receive the filtered signal and a second input coupled to the output of the DAC to receive the analog signal from the DAC; wherein for each of the at least one signal line on which the first digital signal is received, the DAC includes a resistor circuit in a resistor path connected between the respective input terminal of the DAC and the output of the DAC, and includes a capacitor in a plurality of capacitors in a capacitor path between the respective input terminal of the DAC and the output.

[0004] In another embodiment, the filter circuit includes at least one capacitor located between the input and output of the filter circuit, wherein the total effective capacitance of the capacitor between the input and output of the DAC is matched with the total effective capacitance of at least one capacitor between the input and output of the filter circuit.

[0005] In another embodiment, the analog signal is a differential signal, and the input of the filter circuit includes a first differential input terminal and a second differential input terminal for receiving the analog signal; the output of the filter circuit includes a first differential output terminal and a second differential output terminal; the filter circuit includes a first capacitor located in a first path between the first differential input terminal and the second differential output terminal, and includes a second capacitor located in a path between the second differential input terminal and the first differential output terminal.

[0006] In another embodiment, the first digital signal is a differential signal and includes a first differential digital signal component and a second differential digital signal component; the input of the DAC includes one or more first input terminals for receiving the first differential digital signal component, and includes one or more second input terminals for receiving the second differential digital signal component; the output of the DAC includes a first differential output and a second differential output; the plurality of capacitors includes a first subset of one or more capacitors, each of the one or more capacitors in the first subset being located in a capacitor path between a corresponding first input terminal and the first differential output; the plurality of capacitors includes a second subset of one or more capacitors, each of the one or more capacitors in the second subset being located in a capacitor path between a corresponding second input terminal and the second differential output.

[0007] In another embodiment, the synthesizer circuit includes a first differential node and a second differential node; each capacitor in a first subset of a plurality of capacitors includes an end coupled to the first differential node; wherein each capacitor in a second subset of a plurality of capacitors includes an end coupled to the second differential node.

[0008] In another embodiment, the ADC circuit further includes an amplifier, which includes an input coupled to the synthesizer circuit and an output.

[0009] In another embodiment, the amplifier is configured in a passive summing configuration together with the DAC, filter circuitry, and synthesizer circuitry.

[0010] In another embodiment, the ADC circuit further includes a second ADC, which includes an input to the output of the amplifier to provide a second digital signal as a digital representation of the amplifier's output.

[0011] In another embodiment, the ADC circuit further includes: a second filter circuit having a first input for receiving a first digital signal and a second input for receiving a second digital signal, and an output for generating a third digital signal as a digital representation of an analog signal based on the first and second digital signals.

[0012] In another embodiment, the ADC circuit further includes a second DAC, the second DAC including an input for receiving a digital jitter injection signal and an output for providing an analog representation of the digital jitter injection signal to a synthesizer circuit, the second DAC including at least one capacitor path including a capacitor and at least one resistor path including a resistor circuit between the input and the output of the second DAC.

[0013] In another embodiment, the digital jitter injection signal is a differential signal, wherein the input of the second DAC includes a first differential input and a second differential input, and the output of the second DAC includes a first differential output and a second differential output; at least one capacitor path of the second DAC includes a first capacitor path with a capacitor between the first differential input and the first differential output, and includes a second capacitor path with a capacitor between the second differential input and the second differential output.

[0014] In another embodiment, the first digital signal is a differential signal and includes a first differential digital signal component and a second differential digital signal component; the input of the DAC includes a first differential input at one or more first input terminals for receiving the first differential digital signal component, and a second differential input at one or more second input terminals for receiving the second differential digital signal component; the output of the DAC includes a first differential output and a second differential output; a plurality of capacitors includes a first subset of one or more capacitors, each capacitor in the first subset being located in a capacitor path between a corresponding first input terminal and a first differential output; a plurality of capacitors includes a second subset of one or more capacitors, each capacitor in the second subset being located in a capacitor path between a corresponding second input terminal and a second differential output; wherein the capacitor in the first capacitor path of the second DAC matches the capacitance of each capacitor in the first subset of the one or more capacitors of the DAC; wherein the capacitor in the second capacitor path of the second DAC matches the capacitance of each capacitor in the second subset of the one or more capacitors of the DAC.

[0015] In another embodiment, the synthesizer circuit includes a first differential node and a second differential node; the capacitor in the first capacitor path includes an end coupled to the first differential node, and the capacitor in the second capacitor path includes an end coupled to the second differential node.

[0016] In another embodiment, the digital jitter injection signal is characterized as a pseudo-random digital signal.

[0017] In another embodiment, the ADC circuit further includes: an amplifier including an input coupled to a synthesizer circuit and an output; a second ADC including an input coupled to the output of the amplifier to provide a second digital signal as a digital representation of the amplifier's output; a second filter circuit having a first input for receiving a first digital signal and a second input for receiving a second digital signal, and an output for providing a third digital signal as a digital representation of an analog signal based on a set of filter coefficients of the first and second digital signals; and a processing system that receives a digital jitter injection signal and the second digital signal, and adjusts at least one filter coefficient of a set of filter coefficients based on a comparison between the digital jitter injection signal and the second digital signal.

[0018] In another embodiment, an analog-to-digital converter (ADC) circuit includes: a first circuit input and a second circuit input, the first circuit input and the second circuit input being for receiving an analog signal, wherein the analog signal is a differential signal, and the first circuit input and the second circuit input are differential inputs; a filter circuit, the filter circuit including a first filter input coupled to the first circuit input and a second filter input coupled to the second circuit input, wherein the first filter input and the second filter input are differential inputs; a first ADC, the first ADC including an input for receiving an analog signal and including an output for providing a first digital signal as a digital representation of the analog signal, the first digital signal being a differential signal having a first differential signal component having one or more first component bits and a second differential signal component having one or more second component bits; and a digital-to-analog converter (DAC), the DAC including a first set of one or more inputs and one or more... A second set of input terminals, wherein each input terminal in the first set is configured to receive a corresponding component bit from one or more first component bits, and each input terminal in the second set is configured to receive a corresponding component bit from one or more second component bits; a synthesizer circuit, the synthesizer circuit including a first synthesizer node and a second synthesizer node, wherein the first synthesizer node and the second synthesizer node are differential synthesizer nodes; wherein for each input terminal in the first set of one or more input terminals of the DAC, the DAC includes a resistor circuit in a resistor path between each input terminal and the first synthesizer node, and includes a capacitor in a capacitor path between each input terminal and the first synthesizer node; wherein for each input terminal in the second set of one or more input terminals of the DAC, the DAC includes a resistor circuit in a resistor path between each input terminal and the second synthesizer node, and includes a capacitor in a capacitor path between each input terminal and the second synthesizer node.

[0019] In another embodiment, the ADC circuit further includes an amplifier having a first input coupled to a first synthesizer node and a second input coupled to a second synthesizer node, the first and second inputs being differential inputs.

[0020] In another embodiment, there is no feedback path from the amplifier's output to the amplifier's input.

[0021] In another embodiment, the ADC circuit further includes: a second DAC, the second DAC including a first input terminal and a second input terminal, the first input terminal and the second input terminal being differential input terminals; the first input terminal receiving a first differential component of the jitter signal, and the second input terminal receiving a second digital component of the jitter signal; the second DAC including a first capacitor path including a first capacitor between the first input terminal of the second DAC and a first synthesizer node; the second DAC including a second capacitor path including a second capacitor between the second input terminal of the second DAC and a second synthesizer node.

[0022] In another embodiment, the ADC circuit is characterized as a continuously timed pipelined ADC. Attached Figure Description

[0023] The invention will be better understood by referring to the accompanying drawings, and many of its objectives, features and advantages will become apparent to those skilled in the art.

[0024] Figure 1 This is a circuit diagram of an existing ADC circuit.

[0025] Figure 2 This is a more detailed circuit diagram of existing ADC circuits.

[0026] Figure 3 This is a circuit diagram of a portion of an existing ADC circuit.

[0027] Figure 4 This is a circuit diagram of an ADC circuit according to at least one embodiment of the present invention.

[0028] Figure 5 This is a more detailed circuit diagram of an ADC circuit according to at least one embodiment of the present invention.

[0029] Figure 6 This is a circuit diagram of an ADC circuit according to at least one embodiment of the present invention.

[0030] Figure 7 This is a more detailed circuit diagram of an ADC circuit according to at least one embodiment of the present invention.

[0031] Unless otherwise specified, the same reference numerals are used in different figures to indicate the same items. Figures are not necessarily drawn to scale. Detailed Implementation

[0032] The following provides a detailed description of the modes used to carry out the invention. This description is intended to illustrate the invention and should not be considered limiting.

[0033] As described herein, an ADC circuit includes an ADC that converts an input analog signal into a digital signal. The ADC circuit includes a filter circuit that receives the analog input signal and provides a filtered signal to a synthesizer circuit. The ADC circuit includes a DAC that converts the digital signal back into an analog signal provided to the synthesizer circuit. The DAC includes one or more capacitive paths with capacitors located between the input and output of the DAC.

[0034] In some embodiments, implementing a capacitor in the DAC of the ADC circuit can provide the ADC circuit with a flat delay profile, higher gain, and greater usable bandwidth. Furthermore, this feature allows the ADC circuit to be implemented with an amplifier configuration that consumes less power. Therefore, embodiments of such circuitry can be advantageous in high-frequency applications.

[0035] Figure 1 This is a circuit diagram of a prior art continuous timing pipelined ADC circuit 101. Circuit 101 includes an analog input for receiving an analog signal provided to a coarse quantization ADC 105. ADC 105 generates a digital signal (D1) as a digital representation of the analog signal. In the example shown, D1 is a multi-bit digital signal. ADC circuit 101 includes a residual DAC 107 that converts the digital signal D1 back to an analog signal and provides the digital signal to synthesizer circuit 113. Circuit 101 also includes a filter 103 that provides a delay to the analog signal at its output to provide a filtered analog signal to synthesizer circuit 113. The delay of filter 103 is designed to match the synthesis delay of ADC 105 and DAC 107 when providing the reconstructed analog signal to synthesizer circuit 113.

[0036] Synthesizer circuit 113 subtracts the output of DAC 107 from the output of filter 103 and provides the resulting signal to amplifier 109. The resulting signal represents the quantization error between the analog input and D1. Amplifier 109 is configured as a transimpedance amplifier in conjunction with impedance circuit 114, which is configured in a feedback configuration with amplifier 109. The output of amplifier 109 represents the quantization error between the analog input and D1. The output of amplifier 109 is provided to ADC 111 to generate digital signal D2, which is a digital representation of the quantization error of ADC circuit 101. D2 can be synthesized with D1 to provide a more accurate digital representation of the analog signal received at the analog input.

[0037] Figure 2 This is a more detailed circuit diagram of part of the ADC circuit 101. Figure 2 In this circuit, the analog input is a differential input, comprising two input terminals (IN+, IN-). Filter 103 includes a resistor path comprising resistors R1-R3 located between the non-inverting input terminal IN+ and the non-inverting output terminal (OUT+) of filter 103. Filter 103 also includes another resistor path comprising resistors R4-R6 located between the inverting input terminal IN- and the inverting output terminal (OUT-) of filter 103. OUT+ is connected to the non-inverting node 205 of synthesizer circuit 113, and OUT- is connected to the inverting node 207 of synthesizer circuit 113. Filter 103 includes a capacitor C2 connected between nodes 231 and 237, and a capacitor C1 connected between nodes 235 and 233.

[0038] Digital signal D1 is a multi-bit differential signal with inverted differential components [D1-DN]-, where each inverted differential component passes through a resistor circuit in resistor circuit 213 of DAC 107 coupled to non-inverting node 205. Signal D1 also includes non-inverted differential components [D1-DN]+, where each non-inverted differential component passes through a resistor circuit in resistor circuit 215 of DAC 107 coupled to non-inverting node 205.

[0039] Node 205 is connected to the non-inverting input of amplifier 109, and node 207 is connected to the inverting input of amplifier 109. Impedance 221 of impedance circuit 114 is connected between the non-inverting input and the inverting output of amplifier 109. Impedance 223 of impedance circuit 114 is connected between the inverting input and the non-inverting output of amplifier 109.

[0040] The RC delay network of filter 103 is based on an RC lattice structure designed for current-mode summation. This requires amplifier 109 to be in a transimpedance amplifier configuration to provide high gain and a wide unity-gain bandwidth, as well as high slew rate capability. The voltages of the analog input and the output of DAC 107 are converted into currents. The current of the delayed input analog signal is subtracted from the current of DAC 107, and the resulting residual current produces a voltage drop proportional to the impedances ZL (221 and 223) of impedance circuit 114.

[0041] It is desirable that filter 103 provides a constant delay across the entire bandwidth of the analog signal to minimize signal leakage into amplifier 109. However, when using Figure 1 and 2 In the transimpedance amplifier configuration, to achieve a nearly flat delay distribution, the maximum permissible frequency of the analog signal must be less than one-third of the analog signal's sampling rate. Furthermore, the loop gain of this configuration is not constant across the entire signal bandwidth, especially considering the selection of ZL (e.g., a capacitor in parallel with a resistor) for first-order low-pass filtering of the image in the reconstructed signal from DAC 107. Therefore, even for a modest gain (e.g., G = 2), the unity-gain bandwidth frequency of amplifier 109 needs to be considerably large relative to the signal bandwidth (e.g., 25 times larger). The unity-gain bandwidth requirement becomes even more stringent as the gain increases. This problem is further exacerbated by the reduction in loop gain due to parasitic input capacitive loads at the input of amplifier 109.

[0042] Furthermore, the transimpedance amplifier draws current from the analog input as well as switching current from the DAC. Therefore, amplifier 109 requires good slew rate capability, which increases power dissipation. Implementing a transimpedance amplifier can be challenging, especially for high-frequency applications, due to the high unity-gain bandwidth and high slew rate requirements.

[0043] Instead of using a transimpedance configuration, a circuit with a passive summing configuration can be used to generate the residual voltage. For some passive summing configurations, the required unity-gain bandwidth relative to the signal bandwidth is much smaller than that for a transimpedance amplifier configuration (e.g., 4 times smaller at a gain of 2). Therefore, this configuration can be beneficial for high-frequency applications. However, the passive summing configuration inherently attenuates the residual signal by at least two times, which needs to be compensated for. For some passive summing configurations used for residual voltage generation, there is an inherent attenuation at the synthesis circuit (e.g., at least 0.5 times). This attenuation factor increases with increasing frequency due to the capacitive component of the RC lattice of the delay filter. Therefore, the maximum usable bandwidth of this configuration is less than the desired bandwidth, especially at larger signal bandwidths (e.g., 3 GHz and above).

[0044] Another problem with some passive summing configurations is that the attenuation of both the filter and DAC paths is frequency-dependent, which reduces the effective bandwidth for voltage residual regeneration. This affects the unity-gain bandwidth and the DAC's sampling impulse response, which determines the gain of each stage of the ADC circuitry.

[0045] Figure 3 This is a circuit diagram of a prior art ADC circuit 301, which includes a filter 303, a DAC 304, a synthesizer circuit 312, and an amplifier 308 implemented in a passive summing configuration. Figure 3 In this circuit, the analog input is a differential input, comprising two input terminals (IN+, IN-). Filter 303 includes a resistor path comprising resistors R1-R3 located between the non-inverting input terminal IN+ and the non-inverting output terminal (OUT+) of filter 303. Filter 303 also includes another resistor path comprising resistors R4-R6 located between the inverting input terminal IN- and the inverting output terminal (OUT-) of filter 303. OUT+ is connected to the non-inverting node 305 of synthesizer circuit 323, and OUT- is connected to the inverting node 307 of synthesizer circuit 312. Filter 303 includes a capacitor C2 connected between nodes 331 and 337, and a capacitor C1 connected between nodes 335 and 333.

[0046] Digital signal D1 is a multi-bit differential signal with inverted differential components [D1-DN]-, where each inverted differential component passes through a resistor circuit in resistor circuit 313 of DAC 304 coupled to non-inverting node 305. Signal D1 also includes non-inverted differential components [D1-DN]+, where each non-inverted differential component passes through a resistor circuit in resistor circuit 315 of DAC 304 coupled to inverting node 307 of synthesizer circuit 312. Node 305 is connected to the non-inverting input of amplifier 308, and node 307 is connected to the inverting input of amplifier 308.

[0047] The transfer function at synthesizer circuit 312 is given as:

[0048] Equation 1

[0049] Where R is the total series resistance of resistors R1-R3 and the total resistance of resistors R4-R6. R is also the total resistance of the parallel resistor circuit 313 and the parallel resistor circuit 315. C is the capacitance of capacitors C1 and C2. VD1 is the effective differential voltage of DAC 304, expressed as (D1+D2+…DN) / N. The resistance of resistors R2 and R5 is 1 / 2R, and the resistance of resistors R1, R3, R4, and R6 is 1 / 4R. The letter 's' indicates the Laplace transform.

[0050] As shown in Equation 1 above, the filter path and DAC path Both paths exhibit frequency-dependent attenuation. This frequency-dependent attenuation reduces the effective bandwidth of circuit 301. Therefore, this configuration is less than ideal, especially for high-frequency applications.

[0051] Figure 4 This is the circuit diagram of the ADC circuit 401. Figure 1 In this embodiment, the ADC circuit 401 is a continuous-time pipelined ADC. Circuit 401 includes an analog input for receiving an analog signal. Circuit 401 includes a coarse-quantization ADC 405 that converts the analog signal into a digital representation D1 of the analog signal. Circuit 401 includes a DAC 407 that converts D1 back to an analog signal. Circuit 401 includes a filter 403 that provides a filtered signal with a delay at its output. The delay of filter 403 is designed to match the synthesis delay of ADC 405 and DAC 407. The output of filter 403 is connected to synthesizer circuit 413. At synthesizer circuit 413, the analog output of DAC 407 is subtracted from the output signal of filter 403. The output of synthesizer circuit 413 is provided to amplifier 409. Figure 4 In this embodiment, filter 403, DAC 407, synthesizer circuit 413, and amplifier 409 are arranged in a passive summing configuration. The output of amplifier 409 represents the quantization error of signal D1 relative to the analog signal received at the analog input. The output of amplifier 409 is provided to ADC 411, which provides a digital signal D2, which is a digital representation of the quantization error in signal D1. D2 and D1 are combined to provide a more accurate digital representation of the analog signal received at the analog input.

[0052] Figure 5 This is a more detailed circuit diagram of the filter 403, DAC 407, synthesis circuit 413, and amplifier 409 according to some embodiments of the present invention. Figure 5 In this embodiment, the analog signal received at the analog input is a differential signal. The analog input includes differential input terminals 521 and 522.

[0053] Filter 403 implements an RC ladder network, which includes a resistive path with resistor 507 between input 521 and node 525 of synthesizer circuit 413, and a resistive path with resistor 510 between input 522 and node 526 of synthesizer circuit 413. The output of filter 403 is located at its connection to nodes 525 and 526. Filter 403 also includes a capacitor path including capacitor 509 between input 521 and node 526. Filter 403 further includes another capacitor path including capacitor 508 between input 522 and node 525. In the illustrated embodiment, resistors 507 and 510 have resistance values ​​R, and capacitors 508 and 509 have capacitance values ​​C.

[0054] exist Figure 5 In this embodiment, the digital signal D1 is a multi-bit differential digital signal, including non-inverted signal bit components D11+ to D1N+ and inverted signal bit components D11- to D1N-. N is an integer representing the number of signal bit components of signal D1, including both inverted (D11- to D1N-) and non-inverted (D11+ to D1N+) components. Each signal line transmitting the signal bit components (D11- to D1N- and D11+ to D1N+) of signal D1 is connected to the input of DAC 407, wherein... Figure 5 The signal bit component D1N- connected to input 523 is shown.

[0055] DAC 407 includes a set of resistors 501-503 and a set of capacitors 504-506. Each resistor in 501-503 is located in the resistive path between the input terminal (e.g., terminal 523) of DAC 407 that receives the inverted signal bit components (D11- to D1N-) and node 525 of the non-inverting synthesizer circuit. Each capacitor in 504-506 is located in the capacitive path between the input terminal (e.g., terminal 523) of DAC 407 and node 525 of the non-inverting synthesizer circuit. DAC 407 also includes a set of resistors 511-513 and another set of capacitors 514-516. Each resistor in 511-513 is located in the resistive path between the input terminal of DAC 407 that receives the non-inverted signal bit components (D11+ to D1N+) and node 526 of the inverting synthesizer circuit. Each of capacitors 514-516 is located in the capacitive path between the input terminal of DAC 407 receiving the non-inverting signal bit components (D11+ to D1N+) and node 526 of the inverting synthesizer circuit. Figure 5 In one embodiment, the output of DAC 407 includes its connection to a node of synthesizer circuit 413.

[0056] like Figure 5 As shown, the non-inverting input of amplifier 409 is connected to non-inverting synthesizer node 525, and the inverting input of amplifier 409 is connected to inverting synthesizer node 526. There is no feedback impedance path between the input and output of amplifier 409, thereby providing higher gain bandwidth for circuit 401 while consuming less current.

[0057] In the illustrated embodiment, resistors 501-503 and 511-513 each have a resistance value equal to N*R, where R is the resistance value of resistor 507 and the resistance value of resistor 510. Since resistors 501-503 connected to the non-inverting synthesizer node 525 are in a "parallel" configuration and resistors 511-513 connected to the inverting synthesizer node 526 are in a "parallel" configuration, the total effective resistance from the input of DAC 407 to the output of DAC 407 (the connection points with nodes 525 and 526) matches the effective resistance of filter 403 from its input (terminals 521 and 522) to its output (the connection points with nodes 525 and 526).

[0058] Capacitors 504-506 and 514-516 each have a capacitance value equal to C / N, where C is the capacitance value of capacitor 508 and capacitor 509. Since capacitors 504-506 connected to the non-inverting synthesizer node 525 are in a "parallel" configuration and capacitors 514-516 connected to the inverting synthesizer node 526 are in a "parallel" configuration, the total effective capacitance from the input of DAC 407 to the output of DAC 407 (the connection points with nodes 525 and 526) matches the effective capacitance of filter 403 from its input (terminals 521 and 522) to its output (the connection points with nodes 525 and 526).

[0059] Because the DAC 407 includes capacitors in the capacitive path from its input to its output, the transfer function from the analog input to the synthesizer circuit is similar to... Figure 3 The transfer function of the circuit is different, the difference being that the frequency-dependent attenuation of the transfer function is eliminated. For Figure 5 The transfer function of the circuit from the analog input to the synthesizer circuit is given as follows:

[0060] Equation 2

[0061] As shown above, since the effective capacitance of DAC 407 is matched with the effective capacitance of filter 403, the attenuation factor of DAC 407 is... The frequency components in the numerator and denominator are the same (1+sRC), therefore they cancel each other out, leaving a residual attenuation factor (-0.5) that is independent of frequency. Therefore, when combined with a DAC without considering the impedance load... Figure 3Compared to the circuit described above, the frequency-dependent attenuation of circuit 401 is reduced, thereby improving the frequency response of circuit 401. Therefore, Figure 5 The residual generation configuration of the circuit has a higher efficiency than Figure 3 It has a wider unity-gain bandwidth.

[0062] The elimination of the frequency-dependent attenuation factor in DAC 407 provides a flatter frequency distribution for the circuit, which increases the effective bandwidth of ADC circuit 401 and the sampling impulse response of DAC 407. Compared to other passive summing configurations, this increases the effective number of bits (ENOB) of the ADC circuit.

[0063] In some simulations, similar to Figure 3 Compared to the 5.3 GHz unity-gain bandwidth of the circuit, it has the same... Figure 5 The circuit configuration, similar to that of the embodiment, has a unity-gain bandwidth of 12.8 GHz. This simulation also shows that, compared to similar... Figure 3 Compared to the sampling pulse response value of the DAC 304 circuit, it is comparable to Figure 5 The circuitry similar to that of the DAC 407 provides a sampling pulse response that is at least 1.5 times higher, indicating a greater gain.

[0064] in addition, Figure 5 The passive summation configuration of the circuit provides efficient residual generation, which consumes less current than... Figure 2 There are far fewer transimpedance amplifier solutions because passive summing configurations do not pass through a feedback impedance path (e.g., Figure 2 The impedances 221 and 223 absorb current.

[0065] Figure 6 This is a circuit diagram of an ADC circuit 601 according to another embodiment. Items with the same reference numerals as circuit 401 are similar. The difference between circuit 601 and circuit 401 is that it includes using a dithering signal (PRBS) to set the filter coefficients 605 of a digital reconstruction filter 603, which generates a final digital output (DOUT) from digital signals D1 and D2.

[0066] In one embodiment, the PRBS signal is a digital pseudo-random bit sequence generated by PRBS generator 621. The PRBS signal is injected into DAC 615, and synthesizer circuit 613 subtracts the output of DAC 615 from the output of filter 403. The output of synthesizer circuit 613 is provided to amplifier 409. In one embodiment, the configuration of DAC 615 is a replica of the unit element of DAC 407. ADC 411 provides a digital representation (D2) of the residual voltage generated at the output of amplifier 409. Reconstruction filter 603 uses the residual signal D2 to adjust the digital signal D1 to produce the final digital output DOUT, minimizing the quantization error of the output of ADC 405.

[0067] Circuit 601 includes a back-end digital processing system 607. System 607 includes an input for receiving a signal D2 from the output of ADC 411 and a PRBS sequence from generator 621. By comparing the two received signals, system 607 determines the transfer function characteristics of DAC 615, synthesizer circuit 613, amplifier 409, and ADC 411. Based on the determined transfer function characteristics, system 607 adjusts the filter coefficients 605 of digital reconstruction filter 603, which define how filter 603 adjusts signal D1 to generate DOUT based on residual signal D2.

[0068] In some embodiments, system 607 may be implemented using hardware, processor circuitry that executes code or firmware, or a combination thereof.

[0069] Figure 7 This is a more detailed circuit diagram of the ADC circuit 601. It has the same characteristics as... Figure 5 The items with the same reference numerals are similar. Figure 7 In this embodiment, the PRBS signal is a differential signal, including a non-inverting signal bit component (PRBS+) provided to input 712 and an inverting signal bit component (PRBS-) provided to input 704. DAC 615 includes a resistor 703 in the resistive path from input 704 to the non-inverting node 525. DAC 615 includes a capacitor 706 in the capacitive path from input 704 to the non-inverting node 525. DAC 615 includes a resistor 711 in the resistive path from input 712 to the inverting node 526. DAC 615 includes a capacitor 714 in the capacitive path from input 712 to the non-inverting node 526.

[0070] In one embodiment, the resistance of resistors 703 and 711 is N*R, where R is the resistance value of resistors 507 and 510, and N is the number of digital signal component bits for the non-inverting signal components (D11+ to D1N+) and the inverting signal components (D11- to D1N-) of D1. The capacitance of capacitors 706 and 714 is C / N, where C is the capacitance value of capacitors 508 and 509. However, in other embodiments, the capacitors and resistors may have other values. In one embodiment, Figure 7 The transfer function of the circuit configuration is given by the following equation:

[0071] Equation 3

[0072] As shown in Equation 3 above, the attenuation factor is attributed to the PRBS signal. It is not frequency-dependent. Therefore, compared to the passive summing configuration that does not include the capacitor path in the jitter DAC 615, it has a larger unity-gain bandwidth, a flatter delay distribution, and higher gain.

[0073] Figure 4 and 6 Such ADC circuits can be used in many applications requiring analog-to-digital conversion. These circuits may be particularly advantageous in high-frequency applications with wide bandwidth (e.g., 2 GHz or greater) and relatively fast sampling times (e.g., 4 GHz or greater). In some embodiments, the circuit can provide 10 effective bits, with a bandwidth exceeding 3 GHz and a sampling rate of 10 GHz. However, other embodiments can provide circuits with different operating parameters. Such ADC circuits can be used in communication systems and automated sensor systems. However, embodiments of these circuits can also be used in other applications.

[0074] Modifications can be made to the embodiments shown and described herein. For example, although Figure 5 and 7 An ADC circuit configured to operate using differential signals is shown, but other embodiments can also be configured to operate using single-ended signals. Furthermore, although... Figure 4 and 6 The ADC circuit is shown as a single-stage ADC circuit, but the ADC circuit of the DAC including a capacitor in the capacitor path as described herein can be implemented as a multi-stage ADC circuit. Additionally, filter 403 can have other configurations, wherein multiple resistors can be included in the resistor path, and the resistors and capacitors can have different values. Furthermore, DACs (e.g., 407, 615) can have other configurations and / or include resistors and capacitors with different values. Furthermore, synthesis circuits 413 and 613 can also have other configurations.

[0075] The features described herein with respect to one embodiment may be implemented in other embodiments described herein. Two devices may be "coupled" to each other via current paths having other devices or by means of being connected to each other. For example, refer to Figure 2 Resistor R1 is coupled to resistor R3 via a current path that includes resistor R2. Resistor R1 is also coupled to capacitor C2 by means of a connection to capacitor C2. Despite manufacturing-related differences, two characteristics are considered "matched" if they are designed to be virtually identical. Similarly, as used herein, a capacitor in a capacitive path between two nodes or a resistor in a resistive path between two nodes can include other means in paths between two nodes besides the capacitive or resistive path.

[0076] While specific embodiments of the invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, other changes and modifications may be made without departing from the invention and its broader aspects, and therefore the appended claims are intended to cover all such changes and modifications within the true spirit and scope of the invention.

Claims

1. An analog-to-digital converter (ADC) circuit, characterized in that, include: A circuit input configured to receive analog signals; A filter circuit, the filter circuit including an input coupled to the circuit input to receive the analog signal and an output for providing a filtered signal; A first ADC, the first ADC including an input coupled to the circuit input to receive the analog signal and including an output for providing a first digital signal as a digital representation of the analog signal; A digital-to-analog converter (DAC) includes an input coupled to receive the first digital signal and an output for providing an analog signal representing the first digital signal, wherein the first digital signal is received by the DAC from the first ADC on at least one signal line. A synthesizer circuit, the synthesizer circuit including a first input coupled to the filter circuit to receive the filtered signal and a second input coupled to the output of the DAC to receive the analog signal from the DAC; For each of the at least one signal line on which the first digital signal is received, the DAC includes a resistor circuit in a resistor path connected between the corresponding input terminal of the DAC and the output of the DAC, and includes a capacitor in a capacitor path between the corresponding input terminal of the DAC and the output.

2. The ADC circuit according to claim 1, characterized in that, The filter circuit includes at least one capacitor located between the input and the output of the filter circuit, wherein the total effective capacitance of the capacitor between the input and the output of the DAC is matched with the total effective capacitance of the at least one capacitor between the input and the output of the filter circuit.

3. The ADC circuit according to claim 1, characterized in that: The analog signal is a differential signal, and the input of the filter circuit includes a first differential input terminal and a second differential input terminal for receiving the analog signal. The output of the filter circuit includes a first differential output terminal and a second differential output terminal; The filter circuit includes a first capacitor located in a first path between the first differential input terminal and the second differential output terminal, and a second capacitor located in a path between the second differential input terminal and the first differential output terminal.

4. The ADC circuit according to claim 1, further characterized in that: The first digital signal is a differential signal, and includes a first differential digital signal component and a second differential digital signal component; The input of the DAC includes one or more first differential inputs with first input terminals for receiving the first differential digital signal component, and includes one or more second differential inputs with second input terminals for receiving the second differential digital signal component. The output of the DAC includes a first differential output and a second differential output; The plurality of capacitors includes a first subset of one or more capacitors, each of the one or more capacitors in the first subset being located in a capacitor path between a corresponding first input terminal of the one or more first input terminals and the first differential output; The plurality of capacitors includes a second subset of one or more capacitors, each of the one or more capacitors in the second subset being located in a capacitor path between a corresponding second input terminal and the second differential output.

5. The ADC circuit according to claim 4, characterized in that: The synthesizer circuit includes a first differential node and a second differential node; Each capacitor in the first subset of the plurality of capacitors includes an end coupled to the first differential node; Each capacitor in the second subset of the plurality of capacitors includes an end coupled to the second differential node.

6. The ADC circuit according to claim 1, characterized in that, In addition, including: An amplifier, the amplifier including an input coupled to the synthesizer circuit, the amplifier including an output.

7. The ADC circuit according to claim 6, characterized in that, In addition, including: The second ADC includes an input to the output of the amplifier to provide a second digital signal as a digital representation of the output of the amplifier.

8. The ADC circuit according to claim 1, characterized in that, In addition, including: The second DAC includes an input for receiving a digital jitter injection signal and an output for providing an analog representation of the digital jitter injection signal to the synthesizer circuit. The second DAC includes at least one capacitor path including a capacitor and at least one resistor path including a resistor circuit between the input and the output of the second DAC.

9. The ADC circuit according to claim 8, characterized in that: The digital dithering injection signal is a differential signal, wherein the input of the second DAC includes a first differential input and a second differential input, and the output of the second DAC includes a first differential output and a second differential output; The at least one capacitor path of the second DAC includes a first capacitor path with a capacitor between the first differential input and the first differential output, and a second capacitor path with a capacitor between the second differential input and the second differential output.

10. An analog-to-digital converter (ADC) circuit, characterized in that, include: A first circuit input terminal and a second circuit input terminal are used to receive analog signals, wherein the analog signals are differential signals, and the first circuit input terminal and the second circuit input terminal are differential input terminals. A filter circuit, the filter circuit including a first filter input terminal coupled to the input terminal of the first circuit and a second filter input terminal coupled to the input terminal of the second circuit, wherein the first filter input terminal and the second filter input terminal are differential terminals; A first ADC, the first ADC including an input for receiving the analog signal and an output for providing a first digital signal as a digital representation of the analog signal, the first digital signal being a differential signal having a first differential signal component having one or more first component bits and a second differential signal component having one or more second component bits; A digital-to-analog converter (DAC) includes a first set of one or more input terminals and a second set of one or more input terminals, wherein each input terminal in the first set is configured to receive a corresponding component bit from the one or more first component bits, and each input terminal in the second set is configured to receive a corresponding component bit from the one or more second component bits; A synthesizer circuit, the synthesizer circuit including a first synthesizer node and a second synthesizer node, wherein the first synthesizer node and the second synthesizer node are differential synthesizer nodes; For each of the first set of one or more inputs of the DAC, the DAC includes a resistor circuit in a resistor path between each input and the first synthesizer node, and includes a capacitor in a capacitor path between each input and the first synthesizer node; For each of the second set of one or more inputs of the DAC, the DAC includes a resistor circuit in a resistor path between each input and the second synthesizer node, and includes a capacitor in a capacitor path between each input and the second synthesizer node.

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