Field programmable gate array (FPGA)-based Loran C receiver signal searching method and system

Abstract

The invention discloses a Loran C receiver signal searching method and system based on an FPGA, and the method specifically comprises the steps: carrying out the filtering processing of an input AD sampling signal, filtering out-of-band noise, and obtaining a filtered signal; performing down-sampling processing on the filtered signal to obtain a down-sampled signal; performing accumulation processing on the down-sampling signal to obtain an accumulated signal; performing sliding reading and sign bit extraction on the accumulated signal to obtain a sign bit signal; performing sliding correlation detection on the sign bit signal and the fixed primary and secondary station phase coding sequence to obtain a correlation detection result; and carrying out peak value judgment and main and auxiliary station time difference judgment on related detection results, and identifying main and auxiliary station signals of the station chain. According to the invention, rapid and accurate capture of the Roland C signal is realized, the requirements of the system for computing power and storage resources are reduced, and the requirements of a dynamic scene and real-time performance are met.

Description

Technical Field

[0001] This invention relates to the field of longwave signal reception, and in particular to a signal search method and system for a Roland C receiver based on FPGA. Background Technology

[0002] Loland C, a long-range radio navigation system based on low-frequency (100kHz band) continuous wave pulse groups, plays a vital role in numerous fields such as navigation, aviation, and emergency rescue. It provides users with high-precision position, navigation, and timing (PNT) services by accurately measuring the arrival times of pulse signals from multiple stations (master and slave stations) and calculating the time difference (TD) between the master and slave stations. In the actual operation of the Loland receiver, signal search is the crucial first step in realizing its navigation function. The receiver needs to quickly and accurately acquire the pulse signals of the target Loland C station chain in a complex and ever-changing electromagnetic environment. Only in this way can subsequent time difference measurements and positioning calculations be successfully carried out, thereby providing users with reliable navigation information.

[0003] Traditional Loran-C systems primarily employ two common coarse-search strategies for signal acquisition: step-by-step search and parallel search. The step-by-step coarse-search method operates as follows: integration detection is performed within a single phase encoding period. Once the detection result exceeds a pre-set decision threshold, the search continues into the next adjacent time window, repeating the integration correlation operation and detection process. While this search method is logically simple, it has significant drawbacks. Because detection can only be performed within one phase encoding period at a time, and the search needs to be performed window by window, the search process is cumbersome and time-consuming, making it unsuitable for applications with high real-time requirements.

[0004] Parallel coarse search is another traditional search strategy. It involves capturing a signal segment of equal length to the TRG period at once, utilizing the time lag between the secondary stations and the primary station to perform relevant peak detection within a single integration loop, while simultaneously determining the search points for both stations. While parallel coarse search improves search efficiency to some extent by acquiring more information within a single loop, it also suffers from several drawbacks. This method requires processing a relatively long signal segment at once, placing extremely high demands on the system's computing power. It requires significant computational capabilities to support complex integration operations and peak detection. Furthermore, the processing requires storing large amounts of data, resulting in substantial storage resource consumption. Moreover, even with parallel processing, the acquisition time remains long when facing complex electromagnetic environments and dynamically changing signal scenarios, making it difficult to meet the urgent need for rapid signal acquisition in dynamic situations.

[0005] In summary, both coarse-grained search methods in the traditional Roland C system, whether step-by-step search or parallel search, inevitably suffer from common bottlenecks such as high computational power requirements, high storage resource consumption, and long capture times. These problems severely limit the application effectiveness of the Roland C system in dynamic scenarios and fields with high real-time requirements, and prevent it from providing users with efficient and reliable navigation services. Summary of the Invention

[0006] The purpose of this invention is to provide a signal search method and system for a Roland C receiver based on FPGA, so as to solve at least one of the above-mentioned problems in the prior art.

[0007] In a first aspect, the present invention provides a signal search method for a Roland C receiver based on an FPGA, the method specifically comprising: The input AD sampling signal is filtered by a bandpass filter module to remove out-of-band noise and obtain the filtered signal. The filtered signal is downsampled using a 100μs interval sampling module to obtain a downsampled signal. The downsampled signal is accumulated using the TRG periodic accumulation module to obtain the accumulated signal. The accumulated signal is read by sliding and the sign bit is extracted by the sign phase correlation control module to obtain the sign bit signal; The symbol bit signal and the fixed master and slave station phase coding sequence are subjected to sliding correlation detection by a parallel phase coding search module to obtain the correlation detection results; The signal search and decision module performs peak value judgment and main / secondary station time difference judgment on the relevant detection results to identify the main and secondary station signals of the platform chain.

[0008] Secondly, the present invention provides a signal search system for a Roland C receiver based on an FPGA, the system specifically comprising: The first signal search unit is used to filter the input AD sampling signal through the bandpass filter module to remove out-of-band noise and obtain the filtered signal. The second signal search unit is used to downsample the filtered signal through a 100μs interval sampling module to obtain a downsampled signal. The third signal search unit is used to accumulate the downsampled signal through the TRG periodic accumulation module to obtain the accumulated signal. The fourth signal search unit is used to perform sliding read and sign bit extraction on the accumulated signal through the sign phase correlation control module to obtain the sign bit signal; The fifth signal search unit is used to perform sliding correlation detection on the symbol bit signal and the fixed master and slave station phase coding sequence through the parallel phase coding search module to obtain the correlation detection result; The sixth signal search unit is used to identify the main and secondary station signals of the stage chain by performing peak value judgment and main / secondary station time difference judgment on the relevant detection results through the signal search judgment module.

[0009] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, and a computer program stored in the memory, wherein when the computer program is executed on the processor, it implements the FPGA-based Roland C receiver signal search method as described in any of the above methods.

[0010] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the FPGA-based Roland C receiver signal search method as described in any of the above methods.

[0011] Compared with the prior art, the present invention has at least one of the following technical effects: 1. This invention enables rapid and accurate acquisition of Loran C signals, reduces the system's demand for computing power and storage resources, meets the requirements of dynamic scenarios and real-time performance, and provides more efficient and reliable navigation support for fields such as navigation, aviation and emergency rescue; 2. Before the signal search begins, the present invention employs a downsampling operation, which greatly reduces the amount of computation and RAM resource consumption in the FPGA during the signal search process. At the same time, by using multi-point sampling to determine the current 100μs sampling point through symbol decision, the interference of noise on the sampling point signal under low signal-to-noise ratio can be reduced. 3. In the parallel phase coding search, the present invention stores a fixed phase coding sequence in the phase coding search window and uses a 1-bit sign bit and a 1-bit phase coding sequence XOR operation to replace the traditional correlation operation method to perform sliding correlation search on the input signal, which further simplifies the correlation detection process. 4. In the signal search process, this invention employs orthogonal dual-channel parallel search, which increases the success rate of signal search; 5. This invention determines the design parameters of the bandpass filter based on the characteristics of the Loran C signal and generates filter coefficients, which are then imported into the FIR IP core of the FPGA to form a module. This module can accurately filter out out-of-band noise, provide high-quality signals for subsequent signal processing, and improve the accuracy and reliability of signal search. 6. This invention obtains a downsampled signal by selecting sampling values ​​of the filtered signal according to specific rules through the main and orthogonal downsampling channels, which effectively reduces the amount of data and the amount of subsequent processing calculations, while retaining key signal information, which is beneficial for subsequent module processing. 7. This invention stores the downsampled signal in RAM and reads and accumulates it according to the TRG period length, which can suppress in-band noise, enhance signal quality, make subsequent symbol bit extraction and correlation detection more accurate, and improve the stability of signal search. 8. This invention stores the accumulated signal in RAM and uses a state machine to control the sliding read and extract the sign bit to obtain a 1-bit sign bit signal, which simplifies the signal form, reduces data complexity, and facilitates subsequent processing by the parallel phase encoding search module. 9. This invention inputs the sign bit signal into the phase encoding search windows of the main and secondary stations respectively and performs a sliding XOR operation with a fixed sequence to obtain relevant detection results. It can quickly and accurately detect signals that match the phase encoding of the main and secondary stations, providing a reliable basis for subsequent decisions. 10. This invention extracts signal points in the main station phase encoding search window according to different indexes of odd and even periods, and accumulates them after performing a sliding XOR operation with the main station sequence. This can accurately obtain the main station phase encoding search results and effectively identify the main station signal characteristics. 11. The present invention extracts signal points in the secondary station phase encoding search window according to different indexes of odd and even periods, and accumulates them after performing a sliding XOR operation with the secondary station sequence. This can accurately obtain the secondary station phase encoding search results and effectively identify the characteristics of the secondary station signal. 12. This invention performs peak value and time difference judgment on the phase encoding search results of the main and auxiliary stations, which can accurately identify the main and auxiliary station signals of the outgoing chain, realize the core function of signal search of the Roland C receiver, and provide users with accurate navigation information. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a flowchart illustrating a Roland C receiver signal search method based on FPGA provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a module for a Roland C receiver signal search method based on FPGA provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of an orthogonal signal after noise-free downsampling provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the search results for orthogonal two-channel master station signals under noise-free conditions provided by an embodiment of the present invention; Figure 5 This is a schematic diagram of the search results for orthogonal dual-channel secondary station signals under noise-free conditions provided by an embodiment of the present invention; Figure 6 This is a schematic diagram of search results for orthogonal two-channel master station signals at a signal-to-noise ratio of -20dB, provided by an embodiment of the present invention. Figure 7 This is a schematic diagram of search results for orthogonal two-channel secondary station signals at a signal-to-noise ratio of -20dB, provided by an embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of a Roland C receiver signal search system based on FPGA provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0014] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0015] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0016] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0017] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0018] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0019] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0020] In this application embodiment, the entity executing the process includes a terminal device. This terminal device includes, but is not limited to, devices capable of executing the methods disclosed in this application, such as servers, computers, smartphones, and tablets. Figure 1 A flowchart illustrating a signal search method for a Roland C receiver based on FPGA, according to an embodiment of the present invention, is shown below in detail: S101 filters the input AD sampling signal through a bandpass filter module to remove out-of-band noise and obtain the filtered signal. S102, the filtered signal is downsampled using a 100μs interval sampling module to obtain a downsampled signal; S103 uses the TRG periodic accumulation module to accumulate the downsampled signal to obtain the accumulated signal; S104, the accumulated signal is read by sliding and the sign bit is extracted by the sign phase correlation control module to obtain the sign bit signal; S105, the parallel phase coding search module performs sliding correlation detection on the symbol bit signal and the fixed main and secondary station phase coding sequence to obtain the correlation detection result; S106 uses the signal search and decision module to perform peak value decision and main / secondary station time difference decision on the relevant detection results to identify the main and secondary station signals of the platform chain.

[0021] In this embodiment, the input AD sampling signal in the Loland C receiver contains various frequency components, including a large amount of out-of-band noise, which can interfere with subsequent signal processing. Therefore, as... Figure 2 As shown, the input AD sampling signal is first filtered using a bandpass filter module. The bandpass filter module is designed to allow signals within a specific frequency band (around 100kHz, where the Roland C system operates) to pass through, while effectively filtering out noise signals outside this band. After processing by the bandpass filter module, a relatively clean filtered signal is obtained, which removes most of the out-of-band noise interference, laying a good foundation for subsequent signal processing.

[0022] Even after bandpass filtering, the signal still has a large amount of data. To reduce the computational complexity of subsequent processing, such as... Figure 2 As shown, the filtered signal is downsampled using a 100μs interval sampling module. This module samples the filtered signal at 100-microsecond intervals, selecting one signal sample every 100 microseconds. This downsampling method significantly reduces the amount of data in the signal while preserving key information, resulting in a downsampled signal and thus improving the efficiency of subsequent signal processing.

[0023] After obtaining the downsampled signal, such as Figure 2 As shown, the downsampled signal is accumulated using a TRG periodic accumulation module. The TRG period is an important time period concept in the Loran C system. The TRG periodic accumulation module accumulates multiple consecutive downsampled signal samples according to the TRG period. The purpose of accumulation is to enhance the signal energy, improve the signal-to-noise ratio (SNR), and make subsequent signal detection easier and more accurate. After processing by the TRG periodic accumulation module, the accumulated signal is obtained, which has higher energy and better SNR characteristics.

[0024] like Figure 2 As shown, the accumulated signal enters the symbol phase correlation control module, which performs sliding read and symbol bit extraction operations on the accumulated signal. Sliding read refers to sequentially reading the data in the accumulated signal according to a certain step size, while symbol bit extraction is the extraction of symbol bit information from the read data. In this way, the symbol phase correlation control module obtains the symbol bit signal, which contains the symbol feature information of the signal, providing the necessary data for subsequent correlation detection with the fixed master and slave station phase coding sequences.

[0025] like Figure 2 As shown, the symbol signal enters the parallel phase coding search module, which performs sliding correlation detection between the symbol signal and a fixed master / slave station phase coding sequence. The fixed master / slave station phase coding sequence represents the pre-known phase coding characteristics of the master and slave station signals in the Loran C system. The parallel phase coding search module calculates the correlation between the symbol signal and the master / slave station phase coding sequence at different time offsets using sliding correlation detection. This parallel processing method allows for detection at multiple possible time offsets in a single operation, quickly finding the signal position that best matches the master / slave station phase coding sequence and obtaining the correlation detection result.

[0026] like Figure 2As shown, the relevant detection results enter the signal search and decision module, which performs peak value judgment and master / slave station time difference judgment on the relevant detection results. Peak value judgment is performed by setting a judgment threshold; when a peak value in the relevant detection results exceeds the threshold, a possible signal is considered detected. Master / slave station time difference judgment is performed by determining whether the time difference information between the detected master and slave station signals conforms to the normal time difference range between the master and slave stations, combined with the positioning principle of the Loland C system. Through these two decision steps, the signal search and decision module can accurately identify the master and slave station signals on the line chain, thereby completing the signal search process of the Loland C receiver and providing an accurate signal basis for subsequent time difference measurement and positioning calculation.

[0027] Through the implementation of the above steps, the FPGA-based Loran C receiver signal search method can quickly and accurately capture the pulse signal of the target Loran C stage chain in complex electromagnetic environments. It effectively solves the problems of high computing power requirements, high storage resource consumption, and long acquisition time in the signal search process of traditional Loran C systems, and provides an efficient and reliable signal search solution for Loran C systems in dynamic scenarios and fields with high real-time requirements.

[0028] In some embodiments, in step S101 above, before filtering the input AD sampling signal through the bandpass filter module to remove out-of-band noise and obtain the filtered signal, the method further includes: The design parameters of the bandpass filter are determined based on the carrier frequency of the Loran C signal and the sampling rate of the analog-to-digital converter. Based on the design parameters, the corresponding filter coefficients are generated using filter design tools. The filter coefficients are imported into the FIR IP core in the FPGA to form a bandpass filter module.

[0029] In this embodiment, the bandpass filter module is used to filter the Loran C signal acquired by the analog-to-digital converter to remove out-of-band noise; the bandpass filter is designed using the Matlab filter design tool to generate filter coefficients, which are then imported into the FIR IP core in the FPGA for implementation.

[0030] The mathematical formula for the Roland pulse is: In the formula, x(t) represents the Rowland signal current, C is the normalization coefficient; t is time, in μs; ECD is the envelope difference, in μs; PC is the phase code, positive phase code PC=0; negative phase code PC= .

[0031] In one possible implementation, the design parameters of the bandpass filter are first determined based on the carrier frequency of the Loran-C signal and the sampling rate of the analog-to-digital converter (ADC). The Loran-C system operates in the low-frequency 100kHz band, and its carrier frequency has a specific range, which is the core frequency component of the signal. The sampling rate of the ADC determines the frequency at which the analog signal is digitized, which affects the spectral characteristics of the digitized signal. For example, if the sampling rate is too high, it may introduce unnecessary high-frequency noise; if the sampling rate is too low, it may lead to aliasing of the signal spectrum. Therefore, both factors must be considered when determining the design parameters of the bandpass filter. Specifically, the passband cutoff frequency needs to be determined to accurately cover the carrier frequency range of the Loran-C signal, ensuring that the effective components of the signal pass through; at the same time, the stopband cutoff frequency needs to be determined to effectively suppress out-of-band noise. In addition, parameters such as passband ripple and stopband attenuation need to be set. Passband ripple determines the amplitude fluctuation range of the signal within the passband, while stopband attenuation reflects the filter's ability to suppress noise within the stopband. Reasonable parameter settings can ensure that the filter has a good processing effect on both signal and noise.

[0032] Next, based on the determined design parameters, the corresponding filter coefficients are generated using filter design tools. Currently, several professional filter design tools are available, such as the Filter Design Toolbox in MATLAB. The previously determined design parameters are input into the tool, such as the passband cutoff frequency, stopband cutoff frequency, passband ripple, and stopband attenuation. Simultaneously, an appropriate filter type is selected based on actual needs. Since FIR (Finite Impulse Response) filters have linear phase characteristics, ensuring that the signal phase remains undistorted during filtering, they are more suitable for processing Loran C signals, and are therefore typically chosen. Furthermore, the filter order needs to be determined. Higher filter orders result in better frequency selectivity and stronger ability to distinguish between signals and noise, but also increase computational complexity and resource consumption. Therefore, a reasonable trade-off needs to be struck between performance and resource consumption. After setting these parameters, the filter design tool is run. It will automatically calculate the required filter coefficients based on the input parameters. These coefficients are key parameters describing the filter's frequency response characteristics and determine how the filter processes signals of different frequencies.

[0033] Finally, the generated filter coefficients are imported into the FIR IP core in the FPGA to form a bandpass filter module. FPGAs (Field-Programmable Gate Arrays) offer high flexibility and programmability, enabling the implementation of various digital circuit functions through hardware description languages. Many FPGA development platforms provide dedicated FIR IP cores. These IP cores already implement the basic structure and functions of FIR filters; users only need to import the designed filter coefficients to quickly build an FIR filter that meets specific requirements. In practice, the filter coefficients are imported into the FIR IP core according to the prescribed format and order through the interface or tools provided by the FPGA development environment. After importation, the FIR IP core undergoes necessary configuration and initialization, such as setting its operating mode, input / output data bit width, and other parameters to ensure proper functioning. These steps successfully build the bandpass filter module in the FPGA. When the input AD sampling signal enters the FPGA, it first passes through this bandpass filter module for filtering, removing out-of-band noise and obtaining a filtered signal. This provides high-quality input for subsequent signal processing stages, ensuring the accuracy and reliability of the entire Loran C receiver signal search method.

[0034] In some embodiments, in step S102 above, the step of downsampling the filtered signal using a 100μs interval sampling module to obtain a downsampled signal specifically includes: The filtered signal is input to the main downsampling channel, and multiple sampling point data are continuously acquired according to the carrier period. The sign bit of multiple sampling point data is determined. When the number of positive numbers is greater than or equal to a preset threshold, the data with the largest value is selected as the main channel sampling value for the current 100μs interval. When the number of negative numbers is greater than or equal to a preset threshold, the data with the smallest value is selected as the current main channel sampling value for the 100μs interval. The filtered signal is delayed by a quarter of a carrier cycle and then input into the quadrature downsampling channel to continuously acquire multiple sampling point data according to the carrier cycle; The sign bit of multiple sampling point data is determined. When the number of positive numbers is greater than or equal to a preset threshold, the data with the largest value is selected as the positive traffic channel sampling value for the current 100μs interval. When the number of negative numbers is greater than or equal to a preset threshold, the data with the smallest value is selected as the positive traffic channel sampling value for the current 100μs interval; The main channel sample value and the positive traffic channel sample value are used together as a downsampling signal and output to the TRG period accumulation module.

[0035] In this embodiment, the filtered signal is first input to the main downsampling channel. The main downsampling channel continuously acquires multiple sampling points of data per carrier cycle, for example, acquiring 8 sampling points of data within one carrier cycle. These sampling points of data reflect the instantaneous characteristics of the signal within that time period. Subsequently, the sign bits of these multiple sampling points of data are determined. The purpose of sign bit determination is to preliminarily judge the trend of the signal within that time period by counting the number of positive and negative numbers. When the number of positive numbers is greater than or equal to a preset threshold, it indicates that the signal is predominantly positive within that time period. In this case, the data with the largest value is selected as the main channel sampling value for the current 100μs interval. The largest positive number can represent the positive peak characteristics of the signal within that time period, thus preserving the key information of the signal. Conversely, when the number of negative numbers is greater than or equal to a preset threshold, it indicates that the signal is predominantly negative within that time period. In this case, the data with the smallest value is selected as the main channel sampling value for the current 100μs interval. The smallest negative number can represent the negative peak characteristics of the signal within that time period, also preserving the key information of the signal.

[0036] Next, to obtain more feature information of the signal, the filtered signal is delayed by a quarter carrier cycle. The purpose of delaying by a quarter carrier cycle is to create a certain phase shift in the signal, thereby allowing the signal characteristics to be observed from different angles. The delayed signal is then input to the quadrature downsampling channel. The quadrature downsampling channel also continuously acquires multiple sampling points of data according to the carrier cycle, for example, acquiring 8 sampling points of data within one carrier cycle. Then, the sign bits of these multiple sampling points of data are determined. The determination rule is the same as that of the main downsampling channel: when the number of positive numbers is greater than or equal to a preset threshold, the data with the largest value is selected as the positive channel sampling value for the current 100μs interval; when the number of negative numbers is greater than or equal to a preset threshold, the data with the smallest value is selected as the positive channel sampling value for the current 100μs interval.

[0037] Finally, the main channel sampled values ​​and the positive traffic channel sampled values ​​are combined as the downsampled signal. The main channel sampled values ​​and the positive traffic channel sampled values ​​reflect the signal characteristics from different phase perspectives; combining them allows for a more comprehensive preservation of the signal's key information. The combined downsampled signal is output to the TRG periodic accumulation module for further processing and analysis by subsequent modules. This downsampling method using a 100μs interval sampling module effectively preserves the signal's key features while reducing the amount of data processing, providing reliable data support for subsequent signal search and processing.

[0038] In one possible implementation, the filtered signal is connected to a 100μs interval sampling module for downsampling. A point is sampled every 10μs within the 100μs interval, for a total of 5 sampling points. First, a sign decision is performed; if there are three or more integers, the largest value is used as the downsampled signal; otherwise, the smallest value is used. Similarly, the orthogonal second channel, after adding an initial offset of 2.5μs, undergoes downsampling in the same manner. The downsampled signal is as follows: Figure 3 As shown.

[0039] The 100μs interval sampling module downsamples the input signal. The effective pulse duration of the Rowland C pulse is greater than 200μs, and the sampling interval is reduced to 100μs to satisfy the Nyquist sampling theorem.

[0040] The downsampling process involves first acquiring five data points consecutively from the filtered signal according to the carrier cycle (the sign bits of the data points spaced at integer multiples of the cycle are the same), and then determining their sign bits. If the number of positive numbers is greater than or equal to three, the largest data point among the five data points is taken as the sampling value for the current 100μs interval. If the number of negative numbers is greater than or equal to three, the smallest data point among the five data points is taken as the sampling value for the current 100μs interval.

[0041] When the 100μs interval sampling module performs downsampling, in order to avoid the sampling point falling at the amplitude of 0, causing all subsequent sampling points to fall at the amplitude of 0, a downsampling channel orthogonal to the first channel is added. The filtered signal is delayed by a quarter of a carrier period and then five data points are continuously acquired according to the carrier period. The sampling value of the current 100μs interval is selected in the same way. Therefore, the 100μs interval sampling module outputs two orthogonal downsampling signals.

[0042] In some embodiments, step S103 above, which involves accumulating the downsampled signal using the TRG periodic accumulation module to obtain the accumulated signal, specifically includes: The downsampled signal is stored in RAM, and the corresponding downsampled signal data is read from RAM according to the TRG period length; The read downsampled signal data is accumulated to obtain the accumulated signal. The accumulation process is used to suppress in-band noise. The accumulated signal is output to the symbol phase correlation control module.

[0043] In this embodiment, the downsampled data is input into the TRG accumulation module, and the data is accumulated using RAM (Random Access Memory) for TRG cycles.

[0044] Specifically, firstly, the downsampled signal obtained after processing by the 100μs interval sampling module is stored in RAM. RAM, as a high-speed data storage device, can quickly read and write data, facilitating subsequent data retrieval according to the TRG cycle length. During storage, the downsampled signal is stored in the corresponding memory cells of RAM according to a specific order and rules, ensuring data integrity and accessibility.

[0045] Next, the corresponding downsampled signal data is read from RAM according to the TRG period length. The TRG period is a specific time period in the Loran C system, reflecting an important characteristic of the signal. Based on the preset TRG period length, the downsampled signal data for the corresponding time period is accurately read from RAM. This step requires precise control of the start position and the amount of data read to ensure that the read data completely covers one TRG period. For example, if the TRG period length is 10ms, then the downsampled signal data corresponding to this 10ms time period is read from RAM.

[0046] Then, the read downsampled signal data is accumulated. Accumulation is an effective method for suppressing in-band noise. During signal transmission and processing, various types of noise are inevitably introduced, which can interfere with the accuracy and reliability of the signal. By accumulating the downsampled signal data within one TRG cycle, the useful components of the signal can be superimposed and enhanced, while the noise, due to its randomness, will partially cancel each other out during the accumulation process, thus achieving the goal of suppressing in-band noise. For example, assuming there are N downsampled signal data points within one TRG cycle, adding these N data points sequentially yields the signal after noise suppression.

[0047] Finally, the accumulated signal is output to the symbol phase correlation control module. After suppressing in-band noise, the accumulated signal is clearer and more accurate, providing a high-quality input signal for the subsequent symbol phase correlation control module. The output process needs to ensure signal integrity and timeliness to guarantee the smooth progress of the entire signal search process. The symbol phase correlation control module will use these accumulated signals for further sliding reads and symbol bit extraction to continue advancing the subsequent steps of the signal search.

[0048] This embodiment can effectively suppress in-band noise in the signal, improve signal quality and reliability, and provide strong support for the Loland C receiver to accurately search for signals in complex electromagnetic environments.

[0049] In some embodiments, step S104 above, which involves performing sliding readout and sign bit extraction on the accumulated signal through the sign phase correlation control module to obtain the sign bit signal, specifically includes: The accumulated signal is stored in RAM. A state machine controls the sliding read operation of RAM. Each read operation acquires a preset number of data points, and the read interval between adjacent data points is 1ms. The sign bit is extracted from the read data points to obtain a 1-bit sign bit signal.

[0050] In this embodiment, the accumulated signal obtained after processing by the TRG periodic accumulation module is first stored in RAM. During the storage process, the accumulated signal is stored in the corresponding storage unit of RAM according to a specific order and rules to ensure data integrity and accessibility, laying the foundation for subsequent sliding read operations.

[0051] Next, a sliding read operation is performed on the RAM using a state machine. A state machine is a commonly used control structure in digital circuit design; it can perform state transitions and control outputs according to a predetermined logical flow based on different states and input conditions. In this embodiment, the state machine is configured to control the RAM reading process. During each read operation, the state machine controls the acquisition of a preset number of data points from the RAM. This preset number is pre-set based on the characteristics of the Rowland C signal and the requirements of subsequent processing; for example, it can be set to read 16 data points each time. Simultaneously, the reading interval between adjacent data points is set to 1ms. This interval setting is to match the time characteristics of the Rowland C signal, ensuring accurate capture of signal changes. During the sliding read process, the state machine reads data sequentially from different positions in the RAM according to a certain order and rules, achieving the sliding read effect. For example, the first time, 16 data points are read from the starting position of the RAM. The next time, the starting position is moved backward a certain distance (determined based on the 1ms interval and sampling rate), and another 16 data points are read, and so on, completing the sliding read of the entire accumulated signal.

[0052] Next, the sign bit of the read data points is extracted. The sign bit is an important characteristic of the data, reflecting its positive or negative nature. In this embodiment, for each data point read from RAM, its sign bit is determined through specific logical judgment. Specifically, if the value of the data point is greater than or equal to 0, its sign bit is determined to be 1; if the value of the data point is less than 0, its sign bit is determined to be 0. Through such logical judgment, each data point is converted into a 1-bit sign bit signal. For example, for a read data point with a value of 5, its sign bit signal is 1; for a read data point with a value of -3, its sign bit signal is 0.

[0053] Finally, the extracted 1-bit sign bit signal is output for use by the subsequent parallel phase encoding search module. These sign bit signals retain key feature information of the accumulated signal, while the data volume is significantly compressed, facilitating further processing and analysis by subsequent modules. The parallel phase encoding search module will use these sign bit signals to perform sliding correlation detection with a fixed master and slave station phase encoding sequence to continue advancing the subsequent steps of the signal search.

[0054] In one possible implementation, the symbol phase correlation control module uses a state machine to perform a sliding read of RAM, reading 8 data points at a time, with each data point spaced 1ms apart, corresponding to the characteristics of the Rowland pulse group. The sign bit is then extracted from the read data and input into the parallel phase encoding search module.

[0055] This embodiment can effectively extract key feature information from the accumulated signal, providing accurate and concise data support for subsequent signal search and processing, and helping to improve the efficiency and accuracy of the entire Loland C receiver signal search.

[0056] In some embodiments, step S105 above, which involves performing sliding correlation detection on the symbol bit signal and a fixed master / slave station phase coding sequence using a parallel phase coding search module to obtain the correlation detection result, specifically includes: The sign bit signal is input to the main station phase encoding search window and the secondary station phase encoding search window, respectively. The main station phase encoding search window stores the main station phase encoding sequence P. M =[0 0 1 1 0 1 0 1 0 1 1 0 0 0 00], the secondary station phase encoding search window fixedly stores the secondary station phase encoding sequence P. S =[0 1 1 0 0 0 0 0 0 0 0 00 1 1 0]; In the master station phase code search window, the sign bit signal and the master station phase code sequence are subjected to a sliding XOR operation to obtain the master station phase code search result; In the secondary station phase coding search window, the sign bit signal and the secondary station phase coding sequence are subjected to a sliding XOR operation to obtain the secondary station phase coding search result; The main station phase encoding search results and the secondary station phase encoding search results are combined as relevant detection results and output to the signal search and decision module.

[0057] In this embodiment, the phase encoding search window M in the parallel phase encoding search module stores the master station phase encoding sequence P. M =[0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0]; Phase encoding search window S is fixed to store the secondary station phase encoding sequence P. S=[0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0]; To reduce the computational load of correlation detection in the phase-coded search window, the search window uses a 1-bit fixed-code sequence and the input 1-bit sign bit to perform an XOR operation to achieve the correlation detection function. The operation expression is as follows: In the formula Search results for main station phase encoding; The result is the phase encoding search result for the secondary station; k is the sampling point obtained in the 100μs interval sampling module; i represents the index of the encoding sequence; x(k+i*10) represents the signal point extracted every 1ms in odd periods; x(k+i*10+GRI) represents the signal point extracted every 1ms after a GRI interval in even periods, which conforms to the characteristics of the Loran signal. Main station phase encoding sequence; The sub-station phase encoding sequence; GRI is the repetitive pulse period of the station chain group.

[0058] Furthermore, the step of performing a sliding XOR operation between the sign bit signal and the main station phase encoding sequence in the main station phase encoding search window to obtain the main station phase encoding search result specifically includes: In odd periods, the first signal point is extracted from the sign bit signal using an index of k+i*10; In even periods, the first signal point is extracted from the sign bit signal according to the index k+i*10+GRI; Where k is the sampling point obtained from the 100μs interval sampling module, i represents the index of the encoded sequence, and GRI is the repetition pulse period of the chain group; The extracted first signal point is compared with the main station phase encoding sequence P. M Perform a sliding XOR operation on [0 0 1 1 0 1 0 1 0 1 1 0 0 0 00] to obtain the first sliding XOR operation result; The results of the first sliding XOR operation are accumulated to obtain the main station phase encoding search result.

[0059] In this embodiment, the Loran pulse is phase-coded according to the two-phase two-cycle complementary rule, where two-phase means that the initial phase of the signal carrier can be either 0 or π; two-cycle complementary means that in one coding cycle, odd-numbered cycles (GRI-A) and even-numbered cycles (GRI-B) alternately compile the original code and the complement code.

[0060] First, the signal extraction rules must be clearly defined, extracting the first signal point from the symbol signal based on whether the period is odd or even. In the odd period, the first signal point is extracted from the symbol signal according to the index rule "k + i * 10". Here, k is the sampling point obtained from the 100μs interval sampling module, representing a specific position of the signal during the sampling process; i represents the index of the encoded sequence, used to locate the specific element position in the master station phase encoded sequence. Using this index calculation method of "k + i * 10", the signal point related to the corresponding position in the master station phase encoded sequence can be accurately found from the symbol signal. For example, when i = 0, a signal point is extracted from the symbol signal starting at position k as the first signal point; when i = 1, the signal point is extracted from a position offset 10 units from k, and so on.

[0061] In even-numbered periods, the first signal point is extracted from the sign bit signal according to the indexing rule "k + i * 10 + GRI". Here, GRI is the repetition pulse period of the chain group, an important parameter of the Loran C system reflecting the repetitive characteristics of the chain signal. This indexing method in even-numbered periods is used to match the timing characteristics of the Loran C signal in even-numbered periods, ensuring accurate extraction of the signal point corresponding to the main station's phase-coded sequence. For example, when i = 0, the position of the first signal point extracted in an even-numbered period will be shifted backward by GRI units compared to an odd-numbered period, thus ensuring correct signal point acquisition in different periods.

[0062] Next, the extracted first signal point is compared with the main station phase encoding sequence P. M =[0 0 1 1 0 1 0 1 0 11 0 0 0 0 0] is subjected to a sliding XOR operation. XOR is a logical operation; when two input signals are the same, the output is 1; when they are different, the output is 0. During the sliding XOR operation, the first signal point is sequentially XORed with each element in the master station phase-encoded sequence. For example, the first extracted first signal point is XORed with the first element 0 of the master station phase-encoded sequence to obtain one result; then the second first signal point is XORed with the second element 0 of the master station phase-encoded sequence to obtain another result, and so on, completing the XOR operation of the entire sequence to obtain the first sliding XOR result. This result is a sequence of 0s and 1s, reflecting the similarity between the sign bit signal and the master station phase-encoded sequence at corresponding positions.

[0063] Finally, the results of the first sliding XOR operation are summed. The summation operation adds all elements of the first sliding XOR result to obtain a total value. This total value is the master station phase encoding search result, which comprehensively reflects the similarity between the symbol signal and the master station phase encoding sequence over the entire sequence length. The larger the total value, the higher the similarity between the symbol signal and the master station phase encoding sequence, and the more likely it is to be the master station signal; conversely, the smaller the total value, the lower the similarity. This master station phase encoding search result, together with the subsequent slave station phase encoding search results, is used as the correlation detection result and output to the signal search and decision module for further peak value determination and master / slave station time difference determination, thereby accurately identifying the master and slave station signals of the off-chain.

[0064] This embodiment can effectively detect the similarity between the symbol bit signal and the main station phase coding sequence, providing a reliable basis for accurately identifying the main station signal and helping to improve the accuracy and reliability of the entire Loland C receiver signal search.

[0065] Furthermore, in the secondary station phase encoding search window, performing a sliding XOR operation between the sign bit signal and the secondary station phase encoding sequence to obtain the secondary station phase encoding search result specifically includes: In odd periods, the second signal point is extracted from the sign bit signal using an index of k+i*10; In even periods, the second signal point is extracted from the sign bit signal according to the index k+i*10+GRI; The extracted second signal point is compared with the secondary station phase encoding sequence P. S Perform a sliding XOR operation on [0 1 1 0 0 0 0 0 0 0 0 0 0 1 10] to obtain the second sliding XOR result; The results of the second sliding XOR operation are accumulated to obtain the sub-station phase encoding search result.

[0066] In this embodiment, firstly, the second signal point is accurately extracted from the sign bit signal based on different period conditions, namely odd and even periods. In the odd period, the indexing rule "k+i*10" is followed. Here, k is the sampling point obtained from the 100μs interval sampling module, representing a specific position of the signal in the sampling process and a key parameter for determining the starting position of the signal point; i represents the index of the encoded sequence, used to locate the specific element in the secondary station phase encoding sequence. Through this indexing calculation method of "k+i*10", the signal point related to the corresponding position in the secondary station phase encoding sequence can be accurately found from the sign bit signal. For example, when i is 0, k is used as the starting position to extract a signal point from the sign bit signal as the second signal point; when i is 1, the signal point is extracted from a position offset 10 units from k, and so on, gradually completing the extraction of the corresponding signal points for the entire sequence.

[0067] In even-cycle periods, the second signal point is extracted from the sign bit signal using the indexing rule "k + i * 10 + GRI". Here, GRI is the repetition pulse period of the chain group, a core parameter of the Loran C system reflecting the repetitive characteristics of the chain signal. This indexing method is used in even-cycle periods to match the timing characteristics of the Loran C signal in even-cycle periods, ensuring accurate extraction of the signal point corresponding to the sub-station phase encoding sequence. For example, when i is 0, the position of the second signal point extracted in an even-cycle period will be shifted backward by GRI units compared to an odd-cycle period. This ensures correct signal point acquisition in different periods, providing accurate data for subsequent calculations.

[0068] Next, the extracted second signal point is compared with the secondary station phase encoding sequence P. S =[0 1 1 0 0 0 0 0 0 0 0 0 1 1 0] performs a sliding XOR operation. XOR is a basic logical operation where the output is 1 when the two input signals are the same and 0 when they are different. In the sliding XOR operation, the second signal point is sequentially XORed with each element in the sub-station phase encoding sequence. For example, the first extracted second signal point is XORed with the first element 0 of the sub-station phase encoding sequence, resulting in one result; then the second second signal point is XORed with the second element 1 of the sub-station phase encoding sequence, resulting in another result. This process continues until the entire sequence is XORed, yielding the final sliding XOR result. This result is a sequence of 0s and 1s, which visually reflects the similarity between the sign bit signal and the sub-station phase encoding sequence at corresponding positions.

[0069] Finally, the result of the second sliding XOR operation is summed. Summation involves adding all elements of the second sliding XOR result to obtain a total value. This total value is the secondary station phase encoding search result, which comprehensively reflects the similarity between the sign bit signal and the secondary station phase encoding sequence over the entire sequence length. The larger the total value, the higher the similarity between the sign bit signal and the secondary station phase encoding sequence, and the more likely it is to be a secondary station signal; conversely, the smaller the total value, the lower the similarity. This secondary station phase encoding search result, together with the primary station phase encoding search result, is used as the correlation detection result and output to the signal search and decision module for further peak value determination and primary / secondary station time difference determination, thereby accurately identifying the primary and secondary station signals of the off-chain.

[0070] This embodiment can effectively detect the similarity between the symbol bit signal and the phase coding sequence of the secondary station, providing a reliable basis for accurately identifying the secondary station signal. This helps to improve the accuracy and reliability of the entire Loland C receiver signal search, thereby providing users with better navigation services.

[0071] In some embodiments, step S106 above, which involves using a signal search and decision module to perform peak value determination and master / slave station time difference determination on the relevant detection results to identify the master and slave station signals of the platform chain, specifically includes: Peak value determination is performed on the main station phase encoding search results and the secondary station phase encoding search results of the orthogonal two-way output of the parallel phase encoding search module. When the relevant peak value of either channel exceeds the preset threshold, it is determined to pass the peak value determination. The time difference between the main station and the secondary station is calculated by using the signal position points of the main station and the secondary station that pass the peak decision. The time difference between the primary and secondary stations is compared with the standard time difference of the target station chain. When the difference is within the allowable range, the primary and secondary station signals of the target station chain are successfully identified.

[0072] In this embodiment, the signal search and decision module needs to perform a double decision to identify the master and slave station signals of the platform chain. First, it performs a peak decision on the detection results of the master and slave stations output by the two orthogonal paths. After the peak decision, it performs a master and slave station time difference decision based on the search platform chain. Finally, it determines that the master and slave station signals of the platform chain have been found.

[0073] Specifically, firstly, peak determination is performed on the main station phase encoding search results and the secondary station phase encoding search results output orthogonally by the parallel phase encoding search module. When processing signals, the parallel phase encoding search module outputs two orthogonal detection results, corresponding to the signal characteristics of the main station and the secondary station, respectively. For the main station phase encoding search result, the maximum value is found in its data sequence and compared with a preset threshold. This preset threshold is determined based on factors such as the signal characteristics of the Loran C system, noise level, and the reliability requirements for signal detection in the actual application scenario. If the maximum value of the main station phase encoding search result exceeds the preset threshold, it indicates that a sufficiently strong signal peak has been detected in the main station signal detection, and the main station signal is determined to have passed the peak determination. Similarly, the same method is used for the secondary station phase encoding search results, finding the maximum value in its data sequence and comparing it with the preset threshold. When the maximum value of the secondary station phase encoding search result exceeds the preset threshold, the secondary station signal is determined to have passed the peak determination. If the relevant peak value of any channel in the master station or slave station signal exceeds the preset threshold, it is determined to pass the peak value judgment. This means that in the current detection, at least one valid master station or slave station signal has been detected, which provides a basis for subsequent master station and slave station time difference calculation.

[0074] Next, the position points of the primary and secondary station signals, which pass the peak decision, are calculated to obtain the time difference between the primary and secondary stations. Once both the primary and secondary station signals pass the peak decision, their specific positions in the signal sequence can be determined. Since the primary and secondary station signals in the Loland C system have a certain temporal order, and this order is relatively stable, the time difference can be obtained by calculating the time interval between their positions. Specifically, based on the signal sampling frequency and the index information of the position points, the exact times of the primary and secondary station signals on the time axis can be accurately calculated. Then, the time difference between the time of the secondary station signal and the time of the primary station signal is obtained. This time difference reflects the order and interval of the arrival of the primary and secondary station signals at the receiver, and is one of the important parameters for positioning and navigation in the Loland C system.

[0075] Finally, the calculated time difference between the primary and secondary stations is compared with the standard time difference of the target station chain. The standard time difference of the target station chain is determined in advance through measurement and calibration. It represents the theoretical time difference between the primary and secondary station signals in the chain and is an important basis for identifying the target station chain. The calculated time difference between the primary and secondary stations is subtracted from the standard time difference to obtain the difference. Then, it is determined whether this difference is within the allowable range. This allowable range is set based on factors such as the accuracy requirements of the Loland C system and the fault tolerance of the actual application scenario. If the difference is within the allowable range, it means that the calculated time difference between the primary and secondary stations matches the standard time difference of the target station chain, and the primary and secondary station signals of the target station chain can be successfully identified. At this point, the receiver can further carry out subsequent positioning calculations based on the identified primary and secondary station signals, providing users with accurate and reliable navigation information.

[0076] In one possible implementation, the signal search and decision module first performs peak value judgment on the input orthogonal master-slave station correlation detection results, determining whether the correlation peak values ​​of the master and slave stations are greater than 14. If they are, it is considered that the master and slave station signals have been found. Then, the difference between the 100μs position points corresponding to the master and slave station signals is calculated to obtain the master-slave station time difference. It is then determined whether this time difference is close to the time difference of the searched station chain. If they are close, it is considered that the master and slave station signals of that station chain have been found.

[0077] Search results on the main and secondary platforms in a noise-free environment are as follows: Figure 4 and Figure 5 As shown, both the primary and secondary stations had search points exceeding the threshold values ​​in both the I and Q paths. Taking the I path as an example, this indicates that the primary station signal was detected at the 957th 100μs interval, and the secondary station signal was detected at the 1109th and 1240th 100μs intervals. The time difference TD1 between the primary and secondary stations is 15200μs, and the time difference TD2 between the primary and secondary stations is 28300μs, which is close to the time difference between the primary and secondary stations in the South China Sea station chain.

[0078] Search results for main and secondary stations at a signal-to-noise ratio of -20dB are as follows: Figure 6 and Figure 7 As shown, the master station has search points exceeding the threshold in the Q channel, indicating that the master station signal was detected at the 1010th 100μs interval, but not in the I channel. The slave station also has search points exceeding the threshold in the Q channel, indicating that the slave station signal was detected at the 1162nd and 1294th 100μs intervals, but not in the I channel. The time difference TD1 between the master and slave stations is 15200μs, and the time difference TD1 between the master and slave stations is 28400μs, which is close to the time differences between the master and slave stations in the South China Sea signal chain.

[0079] This embodiment can accurately and reliably identify the main and auxiliary station signals of the outer chain, effectively solving the problems of signal search and identification in the traditional Roland C system, improving the performance and reliability of the Roland C receiver in complex electromagnetic environments, and providing users with better navigation services.

[0080] Reference Figure 8 An embodiment of the present invention provides a Roland C receiver signal search system 8 based on FPGA, wherein the Roland C receiver signal search system 8 based on FPGA specifically includes: The first signal search unit 801 is used to filter the input AD sampling signal through the bandpass filter module to remove out-of-band noise and obtain the filtered signal. The second signal search unit 802 is used to downsample the filtered signal through a 100μs interval sampling module to obtain a downsampled signal. The third signal search unit 803 is used to accumulate the downsampled signal through the TRG period accumulation module to obtain the accumulated signal; The fourth signal search unit 804 is used to perform sliding read and sign bit extraction on the accumulated signal through the sign phase correlation control module to obtain the sign bit signal; The fifth signal search unit 805 is used to perform sliding correlation detection on the symbol bit signal and the fixed main and secondary station phase coding sequence through the parallel phase coding search module to obtain the correlation detection result; The sixth signal search unit 806 is used to perform peak value judgment and main / secondary station time difference judgment on the relevant detection results through the signal search judgment module to identify the main and secondary station signals of the stage chain.

[0081] It is understandable that, such as Figure 1 The content of the FPGA-based Roland C receiver signal search method embodiment shown is applicable to the FPGA-based Roland C receiver signal search system embodiment. The specific functions implemented in the FPGA-based Roland C receiver signal search system embodiment are the same as those shown below. Figure 1 The illustrated FPGA-based Roland C receiver signal search method embodiment is the same, and achieves the same beneficial effects as shown below. Figure 1 The beneficial effects achieved by the FPGA-based Roland C receiver signal search method embodiment shown are also the same.

[0082] It should be noted that the information interaction and execution process between the above systems are based on the same concept as the method embodiments of the present invention. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.

[0083] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0084] Reference Figure 9 The present invention also provides a computer device 9, including: a memory 902 and a processor 901, and a computer program 903 stored in the memory 902. When the computer program 903 is executed on the processor 901, it implements the FPGA-based Roland C receiver signal search method as described in any of the above methods.

[0085] The computer device 9 may be a desktop computer, laptop, handheld computer, or cloud server, etc. The computer device 9 may include, but is not limited to, a processor 901 and a memory 902. Those skilled in the art will understand that... Figure 9 The computer device 9 is merely an example and does not constitute a limitation on the computer device 9. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0086] The processor 901 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0087] In some embodiments, the memory 902 may be an internal storage unit of the computer device 9, such as a hard disk or memory of the computer device 9. In other embodiments, the memory 902 may be an external storage device of the computer device 9, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the computer device 9. Furthermore, the memory 902 may include both internal and external storage units of the computer device 9. The memory 902 is used to store the operating system, applications, boot loader, data, and other programs, such as the program code of the computer program. The memory 902 can also be used to temporarily store data that has been output or will be output.

[0088] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the FPGA-based Roland C receiver signal search method as described in any of the above methods.

[0089] In this embodiment, if the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0090] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0091] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0092] In the embodiments disclosed in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0093] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

Claims

1. A signal search method for a Roland C receiver based on FPGA, characterized in that, The method specifically includes: The input AD sampling signal is filtered by a bandpass filter module to remove out-of-band noise and obtain the filtered signal. The filtered signal is downsampled using a 100μs interval sampling module to obtain a downsampled signal. The downsampled signal is accumulated using the TRG periodic accumulation module to obtain the accumulated signal. The accumulated signal is read by sliding and the sign bit is extracted by the sign phase correlation control module to obtain the sign bit signal; The symbol bit signal and the fixed master and slave station phase coding sequence are subjected to sliding correlation detection by a parallel phase coding search module to obtain the correlation detection results; The signal search and decision module performs peak value judgment and main / secondary station time difference judgment on the relevant detection results to identify the main and secondary station signals of the platform chain.

2. The method according to claim 1, characterized in that, The step of filtering the input AD sampling signal through a bandpass filter module to remove out-of-band noise and obtain the filtered signal also includes: The design parameters of the bandpass filter are determined based on the carrier frequency of the Loran C signal and the sampling rate of the analog-to-digital converter. Based on the design parameters, the corresponding filter coefficients are generated using filter design tools. The filter coefficients are imported into the FIR IP core in the FPGA to form a bandpass filter module.

3. The method according to claim 1, characterized in that, The downsampling process, which involves using a 100μs interval sampling module to sample the filtered signal and obtain the downsampled signal, specifically includes: The filtered signal is input to the main downsampling channel, and multiple sampling point data are continuously acquired according to the carrier period. The sign bit of multiple sampling point data is determined. When the number of positive numbers is greater than or equal to a preset threshold, the data with the largest value is selected as the main channel sampling value for the current 100μs interval. When the number of negative numbers is greater than or equal to a preset threshold, the data with the smallest value is selected as the current main channel sampling value for the 100μs interval. The filtered signal is delayed by a quarter of a carrier cycle and then input into the quadrature downsampling channel to continuously acquire multiple sampling point data according to the carrier cycle; The sign bit of multiple sampling point data is determined. When the number of positive numbers is greater than or equal to a preset threshold, the data with the largest value is selected as the positive traffic channel sampling value for the current 100μs interval. When the number of negative numbers is greater than or equal to a preset threshold, the data with the smallest value is selected as the positive traffic channel sampling value for the current 100μs interval; The main channel sample value and the positive traffic channel sample value are used together as a downsampling signal and output to the TRG period accumulation module.

4. The method according to claim 1, characterized in that, The step of accumulating the downsampled signal using the TRG periodic accumulation module to obtain the accumulated signal specifically includes: The downsampled signal is stored in RAM, and the corresponding downsampled signal data is read from RAM according to the TRG period length; The read downsampled signal data is accumulated to obtain the accumulated signal. The accumulation process is used to suppress in-band noise. The accumulated signal is output to the symbol phase correlation control module.

5. The method according to claim 1, characterized in that, The step of performing sliding readout and sign bit extraction on the accumulated signal through the sign phase correlation control module to obtain the sign bit signal specifically includes: The accumulated signal is stored in RAM. A state machine controls the sliding read operation of RAM. Each read operation acquires a preset number of data points, and the read interval between adjacent data points is 1ms. The sign bit is extracted from the read data points to obtain a 1-bit sign bit signal.

6. The method according to claim 1, characterized in that, The step of performing sliding correlation detection on the symbol bit signal and the fixed master and slave station phase coding sequence through a parallel phase coding search module to obtain the correlation detection result specifically includes: The sign bit signal is input to the main station phase encoding search window and the secondary station phase encoding search window, respectively. The main station phase encoding search window stores the main station phase encoding sequence P. M =[0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0], the secondary station phase encoding search window fixedly stores the secondary station phase encoding sequence P. S =[0 1 1 0 0 0 0 0 0 0 0 0 11 0]; In the master station phase code search window, the sign bit signal and the master station phase code sequence are subjected to a sliding XOR operation to obtain the master station phase code search result; In the secondary station phase code search window, the sign bit signal and the secondary station phase code sequence are subjected to a sliding XOR operation to obtain the secondary station phase code search result; The main station phase encoding search results and the secondary station phase encoding search results are combined as relevant detection results and output to the signal search and decision module.

7. The method according to claim 6, characterized in that, The step of performing a sliding XOR operation between the sign bit signal and the main station phase encoding sequence in the main station phase encoding search window to obtain the main station phase encoding search result specifically includes: In odd periods, the first signal point is extracted from the sign bit signal using an index of k+i*10; In even periods, the first signal point is extracted from the sign bit signal according to the index k+i*10+GRI; Where k is the sampling point obtained from the 100μs interval sampling module, i represents the index of the encoded sequence, and GRI is the repetition pulse period of the chain group; The extracted first signal point is compared with the main station phase encoding sequence P. M Perform a sliding XOR operation on [0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0] to obtain the first sliding XOR operation result; The results of the first sliding XOR operation are accumulated to obtain the main station phase encoding search result.

8. The method according to claim 7, characterized in that, In the secondary station phase encoding search window, the sign bit signal and the secondary station phase encoding sequence are subjected to a sliding XOR operation to obtain the secondary station phase encoding search result, specifically including: In odd periods, the second signal point is extracted from the sign bit signal using an index of k+i*10; In even periods, the second signal point is extracted from the sign bit signal according to the index k+i*10+GRI; The extracted second signal point is compared with the secondary station phase encoding sequence P. S Perform a sliding XOR operation on [0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0] to obtain the second sliding XOR operation result; The results of the second sliding XOR operation are accumulated to obtain the sub-station phase encoding search result.

9. The method according to claim 6, characterized in that, The step of identifying the primary and secondary station signals of the platform chain by performing peak value judgment and primary / secondary station time difference judgment on relevant detection results through the signal search and judgment module specifically includes: Peak value determination is performed on the main station phase encoding search results and the secondary station phase encoding search results of the orthogonal two-way output of the parallel phase encoding search module. When the relevant peak value of either channel exceeds the preset threshold, it is determined to pass the peak value determination. The time difference between the main station and the secondary station is calculated by using the signal position points of the main station and the secondary station that pass the peak decision. The time difference between the primary and secondary stations is compared with the standard time difference of the target station chain. When the difference is within the allowable range, the primary and secondary station signals of the target station chain are successfully identified.

10. A signal search system for a Roland C receiver based on FPGA, characterized in that, The system specifically includes: The first signal search unit is used to filter the input AD sampling signal through the bandpass filter module to remove out-of-band noise and obtain the filtered signal. The second signal search unit is used to downsample the filtered signal through a 100μs interval sampling module to obtain a downsampled signal. The third signal search unit is used to accumulate the downsampled signal through the TRG periodic accumulation module to obtain the accumulated signal. The fourth signal search unit is used to perform sliding read and sign bit extraction on the accumulated signal through the sign phase correlation control module to obtain the sign bit signal; The fifth signal search unit is used to perform sliding correlation detection on the symbol bit signal and the fixed master and slave station phase coding sequence through the parallel phase coding search module to obtain the correlation detection result; The sixth signal search unit is used to identify the main and secondary station signals of the stage chain by performing peak value judgment and main / secondary station time difference judgment on the relevant detection results through the signal search judgment module.

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