Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that a transistor structure is inconvenient to connect with other conductive structures due to size reduction. A semiconductor structure includes a transistor structure and a contact structure, the transistor structure including a gate layer and a semiconductor pillar, the gate layer coupled to at least one side of the semiconductor pillar. The contact structure and the semiconductor column are stacked in the first direction. The contact structure comprises a silicide layer and a conductive layer which are stacked in the first direction, the silicide layer is located between the semiconductor column and the conductive layer, and the silicide layer is connected with the first end face of the semiconductor column. In the second direction, the size of the silicide layer is larger than the size of the first end face. Through the arrangement, other conductive structures can be electrically connected with the first end face through the contact structure, and the problem that the transistor structure is inconvenient to connect with other conductive structures due to size reduction is solved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] In semiconductor manufacturing technology, metal silicides are widely used in the contact between semiconductor pillars and metals due to their low resistivity and good adhesion to other materials, thereby reducing the contact resistance between the semiconductor pillars and metals. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor structure and its fabrication method, a storage system, and an electronic device.

[0004] The embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor structure is provided, comprising: a transistor structure and a contact structure, wherein the transistor structure includes a gate layer and a semiconductor pillar, the semiconductor pillar extending along a first direction, and the gate layer coupled to at least one side of the semiconductor pillar; the contact structure is stacked with the semiconductor pillar in the first direction; the contact structure includes a silicide layer and a conductive layer stacked along the first direction, the silicide layer being located between the semiconductor pillar and the conductive layer, and the silicide layer being connected to a first end face of the semiconductor pillar; in a second direction, the size of the silicide layer is larger than the size of the first end face, and the second direction intersects the first direction.

[0006] In some embodiments, the semiconductor structure further includes: a doped layer located between the silicide layer and the first end face, the doped layer being in contact with the silicide layer and the first end face; the doped layer having N-type ions.

[0007] In some embodiments, in the second direction, the size of the conductive layer is the same as the size of the silicide layer.

[0008] In some embodiments, the size of the silicide layer in the first direction ranges from 5 nm to 10 nm.

[0009] In some embodiments, the number of transistor structures is multiple, the number of contact structures is multiple, and one contact structure is stacked with one semiconductor pillar of a transistor structure; in the multiple silicide layers, the difference in size between any two silicide layers in a first direction is less than 5 nm.

[0010] In some embodiments, the plurality of silicide layers have the same size in a first direction.

[0011] In some embodiments, the semiconductor structure further includes a plurality of dielectric structures, which are alternately arranged with a plurality of contact structures along the second direction, and the dielectric structures are in contact with the silicide layer adjacent to them.

[0012] In some embodiments, in two adjacent dielectric structures: one is a first dielectric structure and the other is a second dielectric structure; the first dielectric structure, the second dielectric structure, and the semiconductor pillar located between the first dielectric structure and the second dielectric structure together constitute a semiconductor assembly, wherein the difference between the distance between the first dielectric structure and the first end face and the distance between the second dielectric structure and the first end face is less than 0.3 nm.

[0013] In some embodiments, in the semiconductor component, the distance between the first dielectric structure and the first end face ranges from 1 nm to 3 nm.

[0014] In some embodiments, in the first direction, the distance between the silicide layer and the gate layer is greater than 50 nm.

[0015] In some embodiments, the transistor structure further includes an isolation structure located on at least one side of the semiconductor pillar, and in the first direction, the isolation structure is also located between the silicide layer and the gate layer.

[0016] In some embodiments, the dimension of the contact structure in the second direction ranges from 15 nm to 24 nm.

[0017] In some embodiments, the material of the silicide layer includes one or more metallic elements selected from nickel, titanium, and cobalt.

[0018] In some embodiments, the constituent material of the conductive layer includes titanium or titanium nitride.

[0019] In some embodiments, the semiconductor structure further includes a capacitor structure located on the side of the contact structure away from the semiconductor pillar and connected to the conductive layer.

[0020] On the other hand, a method for fabricating a semiconductor structure is provided, comprising: forming a transistor structure, the transistor structure including a gate layer and a semiconductor pillar, the semiconductor pillar extending along a first direction, the gate layer coupled to at least one side of the semiconductor pillar; forming a contact structure, the contact structure being stacked with the semiconductor pillar in the first direction; the contact structure including a silicide layer and a conductive layer stacked along the first direction, the silicide layer being located between the semiconductor pillar and the conductive layer, and the silicide layer contacting a first end face of the semiconductor pillar; in a second direction, the size of the silicide layer is larger than the size of the first end face, and the second direction intersects the first direction.

[0021] In some embodiments, forming the contact structure includes: removing a portion of the isolation structure of the transistor structure to form a first groove, the isolation structure being located on at least one side of the semiconductor pillar and stacked with the gate layer in the first direction; sequentially forming a first dielectric layer and a second dielectric layer in the first groove, the first dielectric layer being located between the second dielectric layer and the semiconductor pillar; removing a portion of the first dielectric layer and a portion of the semiconductor pillar to form a second groove; forming a silicide layer located at the bottom of the second groove; and forming a conductive layer located on the side of the silicide layer away from the semiconductor pillar.

[0022] In some embodiments, forming the silicide layer includes: forming a doped layer having N-type ions in the second groove; and performing a metal deposition and annealing process on the doped layer to form the silicide layer.

[0023] In some embodiments, forming a conductive layer includes depositing a conductive material within the second groove.

[0024] In another aspect, a storage system is provided, comprising: a semiconductor structure as described above and a controller, the controller being coupled to the semiconductor structure to control the semiconductor structure to store data.

[0025] In another aspect, an electronic device is provided, comprising: a motherboard and a storage system as described above, wherein the motherboard is electrically connected to the storage system. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 This is a three-dimensional structural diagram of a three-dimensional memory according to some embodiments;

[0028] Figure 2 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0029] Figure 3 for Figure 1 A schematic diagram of the structure of a storage unit in China;

[0030] Figure 4 for Figure 3 The equivalent circuit diagram of the storage cell shown;

[0031] Figure 5 This is a schematic diagram of a semiconductor structure according to some embodiments;

[0032] Figure 6 This is a schematic diagram of a semiconductor structure according to some other embodiments;

[0033] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0034] Figure 8 This is a schematic diagram of the structure after forming the transistor structure according to some embodiments;

[0035] Figure 9 This is a schematic diagram of the structure after the formation of the second dielectric layer according to some embodiments;

[0036] Figure 10 This is a schematic diagram of the structure after planarizing the transistor surface according to some embodiments;

[0037] Figure 11 This is a schematic diagram of the structure after the second groove is formed according to some embodiments;

[0038] Figure 12 This is a schematic diagram of the structure after the conductive layer is formed according to some embodiments;

[0039] Figure 13 Here is a block diagram of a storage system according to some embodiments;

[0040] Figure 14 This is a block diagram of a storage system according to some other embodiments;

[0041] Figure 15 This is a block diagram of an electronic device according to some embodiments.

[0042] Figure label:

[0043] 10. Three-dimensional memory; 20. Storage system; 30. Controller; 40. Motherboard; 50. Electronic device; 11. Semiconductor device; 12. Peripheral device; 100. Memory cell array; 110. Memory cell; T. Transistor structure; C. Capacitor structure; 120. Semiconductor pillar; 130. Gate layer; 140. Gate dielectric layer; 150. Array interconnect layer; 160. Substrate; 170. Peripheral circuit; 151. First connection portion; 171. Second connection portion; 180. Common electrode; 200. Semiconductor structure; 210. Contact structure; 211. Silicate layer; 212. Conductive layer; 121. First end face; 220. Isolation structure; 230. Dielectric structure; 240. First groove; 250. First dielectric layer; 260. Second dielectric layer; 270. Second groove; 280. Doped layer. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0047] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0048] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0049] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0050] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0051] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0052] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0053] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0054] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0055] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0056] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0057] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0058] Figure 1 This is a three-dimensional structural diagram of a three-dimensional memory according to some embodiments. Figure 2 This is a cross-sectional view of a three-dimensional memory according to some embodiments. Figure 3 for Figure 1A schematic diagram of the structure of a storage cell. Figure 4 for Figure 3 The equivalent circuit diagram of the storage cell is shown.

[0059] exist Figure 1 and Figure 2 In this disclosure, some embodiments provide a three-dimensional memory 10 located in a three-dimensional coordinate system of XYZ. The three-dimensional memory 10 extends in the YZ plane. The second direction Y and the third direction Z are, for example, two orthogonal directions in the plane where the three-dimensional memory 10 is located (e.g., the plane where the common pole 180 is located). The third direction Z is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The first direction X is perpendicular to the YZ plane.

[0060] It should be noted that the first direction X intersects with the second direction Y, and the third direction Z intersects with the XY plane. This disclosure only uses the example of the first direction X, the second direction Y, and the third direction Z being mutually perpendicular to each other to explain the structure provided in some embodiments of this disclosure.

[0061] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0062] See also Figure 1 and Figure 2 The three-dimensional memory 10 provided in some embodiments of this disclosure includes a semiconductor device 11 and a peripheral device 12. The peripheral device 12 may be disposed on one side of the semiconductor device 11.

[0063] like Figure 2 As shown, the semiconductor device 11 may include a memory cell array 100 and a common electrode 180. Peripheral devices 12 may, for example, be disposed on the side of the memory cell array 100 away from the common electrode 180.

[0064] As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of the three-dimensional memory 10 is determined relative to the peripheral device 12 of the three-dimensional memory 10 in the first direction X, when the peripheral device 12 is located in the lowest plane of the three-dimensional memory 10 in the first direction X. The same concepts are applied throughout this disclosure to describe spatial relationships.

[0065] See Figure 3 and Figure 4 The common electrode 180 can be connected to a first reference voltage, which can be ground or another voltage. The common electrode 180 can include a semiconductor material, such as single-crystal silicon, polycrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The common electrode 180 can be partially or completely doped. For example, the common electrode 180 can include a doped region doped with a p-type dopant. The common electrode 180 can also include an undoped region.

[0066] See Figure 1 and Figure 2 The storage cell array 100 includes a plurality of storage cells 110 arranged in an array along the second direction Y and the third direction Z.

[0067] Among them, such as Figure 2 , Figure 3 and Figure 4 As shown, the memory cell 110 includes a transistor structure T and a capacitor structure C. The transistor structure T can be formed by a channel structure formed by a semiconductor pillar 120 and a gate layer 130 adjacent to the channel structure. A gate dielectric layer 140 is also disposed between the semiconductor pillar 120 and the corresponding gate layer 130. The semiconductor pillar 120 has a source and a drain, which are located at opposite ends of the semiconductor pillar 120. The semiconductor pillar 120 is composed of semiconductor materials, and the materials of the source and drain can include semiconductor materials doped with P-type or N-type dopants.

[0068] It should be noted that semiconductor materials include, for example, single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. P-type dopants include boron or gallium. N-type dopants include phosphorus or arsenic.

[0069] The drain of transistor structure T is connected to bit line BL, and the source of transistor structure T is connected to one plate of capacitor structure C. The other plate of capacitor structure C can be connected to the common terminal 180. Capacitor structure C represents logic 1 and 0 by the amount of charge stored within it, or the high or low voltage difference across capacitor structure C. The gate layer 130 of transistor structure T is connected to word line WL. Thus, the transistor structure T can be turned on or off by applying a voltage to word line WL, and when transistor structure T is on, bit line BL performs read or write operations on transistor structure T.

[0070] In some embodiments, see Figure 1 and Figure 2 The semiconductor device 11 may also include an array interconnect layer 150. The array interconnect layer 150 may be coupled to the memory cell 110.

[0071] The array interconnect layer 150 may include a word line WL and a bit line BL. The word line WL may be coupled to the gate layer 130 of a transistor structure T in at least one memory cell 110. The bit line BL may be coupled to the drain of a transistor structure T in at least one memory cell 110. The gate layers 130 of a plurality of transistor structures T spaced apart along a third direction Z are coupled to the same word line WL.

[0072] In the above embodiments, as Figure 2 As shown, the peripheral device 12 coupled to the semiconductor device 11 may include a substrate 160 and peripheral circuitry 170 disposed on the substrate 160. The substrate 160 may be made of monocrystalline silicon or other suitable materials, such as silicon-germanium, germanium, or silicon-on-insulator thin film. The peripheral circuitry 170 is configured to control and sense the array device. The peripheral circuitry 170 may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for supporting the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drive circuitry (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitor structures C). The peripheral circuitry 170 may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0073] The peripheral circuit 170 can be coupled to the array interconnect layer 150, enabling coupling between the semiconductor device 11 and the peripheral device 12. Specifically, since the peripheral circuit 170 is coupled to the array interconnect layer 150, the peripheral circuit 170 in the peripheral device 12 can be coupled to the transistor structure T in the semiconductor device 11 to achieve the transmission of electrical signals between the peripheral circuit 170 and the transistor structure T. In some possible implementations, an adhesive interface can be provided between the peripheral circuit 170 and the array interconnect layer 150, through which the peripheral circuit 170 and the array interconnect layer 150 can be bonded and coupled to each other.

[0074] In the above embodiments, the semiconductor device 11 may have a first connection portion 151 located in the array interconnect layer 150 on the side near the peripheral circuit 170. The first connection portion 151 is used to connect with the transistor structure T inside the semiconductor device 11. The peripheral circuit 170 may include a second connection portion 171 and a transistor disposed on the substrate 160. The second connection portion 171 is connected to the transistor disposed on the substrate 160 and is located on the side of the transistor near the semiconductor device 11. The transistor disposed on the substrate 160 may include a complementary metal-oxide-semiconductor (CMOS). In the above embodiments, the first connection portion 151 and the second connection portion 171 are bonded together. Through the bonding between the first connection portion 151 and the second connection portion 171, the connection between the transistor structure T and the transistor disposed on the substrate 160 is realized, thereby realizing the connection between the semiconductor device 11 and the peripheral circuit 170.

[0075] Figure 5 This is a schematic diagram of a semiconductor structure according to some embodiments. Please refer to [link / reference]. Figure 1 , Figure 2 and Figure 5 Some embodiments of this disclosure provide a semiconductor structure 200, which can be a three-dimensional memory 10. For example, the semiconductor structure 200 may include a semiconductor device 11 and peripheral devices 12. Alternatively, the semiconductor structure 200 may also be a part of the three-dimensional memory 10, for example, the semiconductor structure 200 may be the semiconductor device 11 in the three-dimensional memory 10. The embodiments of this disclosure do not specifically limit this.

[0076] In some embodiments, such as Figure 5As shown, the semiconductor structure 200 includes a transistor structure T and a contact structure 210. The transistor structure T includes a gate layer 130 and a semiconductor pillar 120. The semiconductor pillar 120 extends along a first direction X, and the gate layer 130 is coupled to at least one side of the semiconductor pillar 120. Here, it can be understood that the gate layer 130 may be located on one side of the semiconductor pillar 120 along a second direction Y and coupled to the semiconductor pillar 120, or the gate layer 130 may surround the semiconductor pillar 120 and be coupled to the semiconductor pillar 120.

[0077] Contact structure 210 and semiconductor pillar 120 are stacked together in the first direction X. Contact structure 210 is conductive, allowing semiconductor pillar 120 to be electrically connected to other conductive structures (e.g., capacitor structure C) through contact structure 210. Contact structure 210 includes a silicide layer 211 and a conductive layer 212 stacked together along the first direction X. Silicate layer 211 is located between semiconductor pillar 120 and conductive layer 212, and silicide layer 211 is connected to the first end face 121 of semiconductor pillar 120. The first end face 121 of semiconductor pillar 120 is the surface of semiconductor pillar 120 closest to contact structure 210 in the first direction X. In the second direction Y, the size of silicide layer 211 is larger than the size of first end face 121.

[0078] In this embodiment, reference Figure 5 The dimension of the silicide layer 211 in the second direction Y is greater than the dimension of the first end face 121 in the second direction Y. This can be understood as the maximum width of the silicide layer 211 in the second direction Y being greater than the maximum width of the first end face 121 in the second direction. For example, when the semiconductor pillar 120 is a cylindrical structure and the contact structure 210 is also a cylindrical structure, this can be understood as the radial length of the silicide layer 211 being greater than the radial length of the first end face 121.

[0079] In some examples, in the second direction Y, both ends of the silicide layer 211 extend beyond the first end face 121. In this case, the orthographic projection of the first end face 121 in the first direction X lies within the edge of the orthographic projection of the silicide layer 211 in the first direction X. In the second direction Y, the portions of the silicide layer 211 extending beyond the first end face 121 at both ends can be equal in size. That is, the distances from both ends of the silicide layer 211 along the second direction Y to the first end face 121 are equal.

[0080] In other examples, in the second direction Y, one end of the silicide layer 211 is aligned with the edge of the first end face 121, and the other end of the silicide layer 211 extends beyond the first end face 121. In this case, the orthographic projection of the first end face 121 in the first direction X is located within the edge of the orthographic projection of the silicide layer 211 in the first direction X, and a portion of the edge of the orthographic projection of the first end face 121 in the first direction X coincides with a portion of the edge of the orthographic projection of the silicide layer 211 in the first direction X.

[0081] In other examples, along one side of the second direction Y, the first end face 121 extends beyond the silicide layer 211, and along the other side of the second direction Y, the silicide layer 211 extends beyond the first end face 121, and the dimension of the portion of the silicide layer 211 extending beyond the first end face 121 in the second direction Y is greater than the dimension of the portion of the first end face 121 extending beyond the silicide layer 211 in the second direction Y.

[0082] In the examples described above, the dimension of the silicide layer 211 in the second direction Y is larger than the dimension of the first end face 121 in the second direction Y. Therefore, in the XY plane, the silicide layer 211 is wider than the first end face 121, which is more conducive to the formation of other conductive structures on the silicide layer 211 and improves the process window for the fabrication of other conductive structures (such as capacitor structure C) that are electrically connected to the first end face 121.

[0083] In this embodiment, the transistor structure T can be connected to other conductive structures (e.g., capacitor structure C) via the contact structure 210. Compared to connecting the transistor structure T to other conductive structures via the first end face 121, the contact structure 210 is wider in the second direction Y than the first end face 121, making it easier for other conductive structures to make contact with the contact structure 210 and thus achieve electrical connection with the transistor structure T. Therefore, this arrangement helps to increase the process window for connecting other conductive structures to the first end face 121, facilitating electrical connection between other conductive structures and the transistor structure T.

[0084] In addition, the above-mentioned arrangement can improve the problem that the size of the first end face 121 of the transistor structure T is reduced due to the increase in the density of the transistor structure T, making it difficult to connect the first end face 121 to other conductive structures. This is conducive to further increasing the density of the transistor structure T in the semiconductor structure 200 and to the miniaturization of the semiconductor structure 200.

[0085] In some embodiments, such as Figure 5As shown, the silicide layer 211 can be, for example, a metal silicide layer. Exemplarily, the constituent materials of the silicide layer 211 may include one or more metallic elements such as tungsten, aluminum, copper, silver, cobalt, platinum, nickel, titanium, and tantalum. Metal silicides have low resistivity and good adhesion to other materials. Therefore, when the silicide layer 211 is a metal silicide layer, it is beneficial to reduce the contact resistance between the semiconductor pillar 120 and the conductive layer 212, and to improve the electrical signal strength between the semiconductor pillar 120 and the conductive layer 212.

[0086] For example, the constituent materials of the conductive layer 212 may include, but are not limited to, one or more combinations of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, or other suitable conductive materials.

[0087] In some embodiments, such as Figure 5 As shown, the conductive layer 212 may be composed of titanium or titanium nitride, which can further reduce the contact resistance between the contact structure 210 and the semiconductor pillar 120 and improve the electrical signal strength between the transistor structure T and the contact structure 210.

[0088] In some embodiments, such as Figure 5 As shown, the dimension of the silicide layer 211 in the second direction Y can be the same as the dimension of the conductive layer 212 in the second direction Y. This can be understood as the width of the silicide layer 211 in the second direction being the same as the width of the conductive layer 212 in the second direction Y in the XY plane. Exemplarily, the surfaces of the silicide layer 211 and the conductive layer 212 that are in contact with each other can have overlapping edges.

[0089] By making the conductive layer 212 and the silicide layer 211 have the same size in the second direction Y, and since the size of the silicide layer 211 is larger than the size of the first end face 121 in the second direction Y, the size of the conductive layer 212 is also larger than the size of the first end face 121 in the second direction Y. Compared to the transistor structure T being connected to other conductive structures through the first end face 121, the transistor structure T is connected to other conductive structures (e.g., capacitor structure C) through the silicide layer 211 and the conductive layer 212. The conductive layer 212 is wider in the second direction Y than the first end face 121, making it easier for other conductive structures to contact and connect with the conductive layer 212 to achieve electrical connection with the transistor structure T. Therefore, the above arrangement helps to increase the process window for connecting other conductive structures to the first end face 121, facilitating electrical connection between other conductive structures and the transistor structure T.

[0090] In some embodiments, such as Figure 5As shown, the dimension of the contact structure 210 in the second direction Y ranges from 15nm to 24nm. Here, the dimension of the contact structure 210 in the second direction Y can be understood as the width of the contact structure 210 in the second direction Y. For example, the dimension of the contact structure 210 in the second direction Y can be 15nm, 20nm, or 24nm. When the dimension of the contact structure 210 in the second direction Y approaches 15nm, the contact structure 210 is not too wide, which helps to prevent leakage current between the contact structure 210 and other conductive structures. When the dimension of the contact structure 210 in the second direction Y approaches 24nm, the width of the contact structure 210 in the second direction Y is more conducive to the contact connection between other conductive structures and the contact structure 210, thereby electrically connecting with the semiconductor pillar 120.

[0091] In some embodiments, such as Figure 5 As shown, the dimension of the silicide layer 211 in the first direction X ranges from 5 nm to 10 nm. Here, the dimension of the silicide layer 211 in the first direction X can be understood as the thickness of the silicide layer 211 in the first direction X. For example, the dimension of the silicide layer 211 in the first direction X can be 5 nm, 7 nm, or 10 nm.

[0092] When the size of the silicide layer 211 in the first direction X is in the range of 5nm to 10nm, the silicide layer 211 can reduce the contact resistance between the first end face 121 and the conductive layer 212. At the same time, the resistance of the silicide layer 211 itself will not be too high, which is beneficial to reduce the influence of the silicide layer 211 on the on-state current and off-state current of the semiconductor structure 200.

[0093] In some embodiments, such as Figure 5 As shown, in the first direction X, the distance between the silicide layer 211 and the gate layer 130 is greater than 50 nm. Here, it can be understood that the vertical distance between the silicide layer 211 and the gate layer 130 in the first direction X is greater than 50 nm.

[0094] In some embodiments, the silicide layer 211 and the semiconductor pillar 120 have the same width in the second direction Y, and the size of the semiconductor pillar 120 is compressed during the fabrication of the silicide layer 211, resulting in a reduction in the size of the semiconductor pillar 120 in the first direction X. This leads to the silicide layer 211 and the gate layer 130 being too close, causing leakage current. Therefore, in this embodiment, the vertical distance between the silicide layer 211 and the gate layer 130 in the first direction X is greater than 50 nm. This can improve the phenomenon of leakage current caused by the close proximity of the silicide layer 211 and the gate layer 130, and improve the storage stability of the semiconductor structure 200.

[0095] In some embodiments, such as Figure 5As shown, there are multiple transistor structures T and multiple contact structures 210. A contact structure 210 and a semiconductor pillar 120 of a transistor structure T are stacked along the first direction X. Among the multiple silicide layers 211, the difference in size between any two silicide layers 211 in the first direction X is less than 5 nm. This can be understood as the difference in thickness between any two silicide layers 211 in the first direction X being less than 5 nm.

[0096] Exemplarily, the silicide layers 211 in the multiple contact structures 210 can be disposed in the same layer, and the conductive layers 212 in the multiple contact structures 210 can be disposed in the same layer. It should be noted that "disposed in the same layer" means that multiple patterns are on the same pattern layer. A pattern layer refers to a film layer formed through a single patterning process. A patterning process refers to a process capable of forming at least one pattern with a certain shape. For example, a thin film is formed on a substrate through any of various film formation processes such as deposition, coating, and sputtering, and then the thin film is patterned to form a film layer containing at least one pattern, which is called a pattern layer. The patterning steps include: coating photoresist, exposure, development, etching, and photoresist stripping, etc. In this embodiment, the positional relationship of multiple patterns belonging to the same pattern layer is referred to as "disposed in the same layer."

[0097] The above configuration helps to ensure that the thickness of the multiple silicide layers 211 in the first direction X is nearly uniform, thus facilitating control that the thickness of each silicide layer 211 in the first direction X remains within a preset thickness range and preventing excessive resistance in each silicide layer 211. This near-uniform thickness of the multiple silicide layers 211 in the first direction X also helps to reduce the impact of the multiple silicide layers 211 on the on-state and off-state currents of the semiconductor structure 200, thereby improving the electrical performance of the semiconductor structure 200.

[0098] Furthermore, in some embodiments, such as Figure 5 As shown, the multiple silicide layers 211 have the same dimensions in the first direction X. The multiple silicide layers 211 also have the same thickness in the first direction X, which facilitates controlling the thickness of each silicide layer 211 within a preset range and preventing excessive resistance in each individual silicide layer 211. Furthermore, the uniform thickness of the multiple silicide layers 211 in the first direction X helps reduce their impact on the on-state and off-state currents of the semiconductor structure 200.

[0099] In some embodiments, such as Figure 5As shown, the transistor structure T also includes an isolation structure 220. The isolation structure 220 is located on at least one side of the semiconductor pillar 120. For example, the isolation structure 220 may be located on the side of the semiconductor pillar 120 away from the gate layer 130, or the isolation structure 220 may be located on the side of the gate layer 130 away from the semiconductor pillar, or the isolation structure 220 may be located on both sides of the semiconductor pillar 120 away from the gate layer 130. Furthermore, in the first direction X, the isolation structure 220 is also located between the silicide layer 211 and the gate layer 130.

[0100] Through the above configuration, the isolation structure 220 facilitates the isolation between multiple transistors, enabling the semiconductor structure 200 to function properly. The isolation structure 220 also helps to isolate the silicide layer 211 from the gate layer 130, preventing leakage current between the silicide layer 211 and the gate layer 130, and improving the storage stability of the semiconductor structure 200.

[0101] In some embodiments, such as Figure 5 As shown, the semiconductor structure 200 also includes a plurality of dielectric structures 230, which are alternately arranged with a plurality of contact structures 210 along the second direction Y. The dielectric structures 230 and the contact structures 210 can be stacked together in the first direction X.

[0102] For example, the constituent materials of the dielectric structure 230 may include insulating materials, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials. With the above arrangement, the dielectric structure 230 is located between two adjacent contact structures 210 along the second direction Y, which can isolate the two adjacent contact structures 210, prevent leakage current between them, and enable the semiconductor structure 200 to operate normally.

[0103] In this embodiment, the dielectric structure 230 is in contact with the adjacent contact structure 210. When the dielectric structure 230 has contact structures 210 on both sides along the second direction Y, there are two adjacent contact structures 210, and the dielectric structure 230 is in contact with both of the two adjacent contact structures 210. When the dielectric structure 230 has a contact structure 210 on one side along the second direction Y, the dielectric structure 230 is in contact with the adjacent contact structure 210.

[0104] It should be noted that adjacent dielectric structures 230 and contact structures 210 are in contact with each other. Specifically, the silicide layer 211 of the contact structure 210 is in contact with the adjacent dielectric structure 230, and the conductive layer 212 of the contact structure 210 is also in contact with the adjacent dielectric structure 230. That is, the silicide layer 211 is in contact with the adjacent contact structure 210, and the conductive layer 212 is in contact with the adjacent contact structure 210.

[0105] With the above arrangement, the multiple dielectric structures 230 and multiple contact structures 210 alternately arranged along the second direction Y are in close contact with any adjacent dielectric structures 230 and contact structures 210, which is beneficial to improving the stability of the semiconductor structure 200.

[0106] In some embodiments, such as Figure 5 As shown, in any two adjacent dielectric structures 230, one is designated as a first dielectric structure 230, and the other as a second dielectric structure 230. The first dielectric structure 230, the second dielectric structure 230, and the semiconductor pillar 120 located between the first dielectric structure 230 and the second dielectric structure 230 together constitute a semiconductor assembly. Here, the semiconductor pillar 120 located between the first dielectric structure 230 and the second dielectric structure 230 can be a portion of the semiconductor pillar 120 located between the first dielectric structure 230 and the second dielectric structure 230, for example, the first end face 121 of the semiconductor pillar 120 is located between the first dielectric structure 230 and the second dielectric structure 230.

[0107] In the same semiconductor assembly, the difference between the distance between the first dielectric structure 230 and the first end face 121 and the distance between the second dielectric structure 230 and the first end face 121 is less than 0.3 nm. Exemplarily, in the same semiconductor assembly, the distance between the first dielectric structure 230 and the first end face 121 can be the same as the distance between the second dielectric structure 230 and the first end face 121, that is, the difference between the distance between the first dielectric structure 230 and the first end face 121 and the distance between the second dielectric structure 230 and the first end face 121 is 0.

[0108] In the process of preparing the silicide layer 211 using an aligned metal silicide layer process, a silicon (semiconductor) layer can be formed between the first dielectric structure 230 and the second dielectric structure 230. Then, a deposition process is performed to form a metal layer. During the deposition process, the metal in the formed metal layer reacts with the silicon to form the silicide layer 211. The metal compound gas used in the deposition process to form the metal layer has selective deposition characteristics; the metal compound gas can only be deposited on the surface of the conductor and semiconductor and decomposes to form the metal layer. Therefore, the silicide layer 211 exhibits self-alignment characteristics during preparation.

[0109] In this embodiment, the constituent materials of the dielectric structure 230 may include, for example, nitrides (or any insulating material). The dielectric structure 230 is neither a conductor nor a semiconductor; therefore, during the fabrication of the silicide layer 211, a metal layer will not form on the surface of the dielectric structure 230. By controlling the distance between the first dielectric structure 230 and the first end face 121, and the distance between the second dielectric structure 230 and the first end face 121, it is advantageous to form self-aligned vias in the silicide layer 211, facilitating the fabrication of the silicide layer 211 using the aforementioned self-aligned metal silicide layer process.

[0110] Furthermore, within the same semiconductor component, when the difference between the distance between the first dielectric structure 230 and the first end face 121 and the distance between the second dielectric structure 230 and the first end face 121 is less than 0.3 nm, it can be approximately considered that the distances from the first end face 121 to both the first and second dielectric structures 230 are equal. This facilitates sufficient contact between the contact structure 210 located between the first and second dielectric structures 230 and the first end face 121. Moreover, in the second direction Y, both ends of the contact structure 210 extend beyond the first end face 121, which helps to improve the process window for other conductive elements to connect to the first end face 121. Furthermore, in the second direction Y, the two ends of the contact structure 210 extend beyond the first end face 121 by the same amount, which helps to improve the stability of the semiconductor structure 200.

[0111] In some embodiments, such as Figure 5 As shown, in the semiconductor component, the distance between the first dielectric structure 230 and the first end face 121 ranges from 1 nm to 3 nm.

[0112] For example, the distance between the first dielectric structure 230 and the first end face 121 can be 1 nm, 2 nm, or 3 nm. In a semiconductor assembly, when the distance between the first dielectric structure 230 and the first end face 121 approaches 1 nm, the width of the contact structure 210 located between the first dielectric structure 230 and the second dielectric structure 230 extending beyond the first end face 121 in the second direction Y approaches 1 nm. This results in a larger spacing between adjacent contact structures 210 along the second direction Y, which helps prevent leakage current between adjacent contact structures 210 and improves the storage stability of the semiconductor structure 200. In a semiconductor assembly, when the distance between the first dielectric structure 230 and the first end face 121 approaches 3 nm, the dimension of the contact structure 210 located between the first dielectric structure 230 and the second dielectric structure 230 extending beyond the first end face 121 in the second direction Y approaches 3 nm. This larger width of the contact structure 210 in the second direction Y is more conducive to other conductive structures contacting and connecting with the contact structure 210, thereby electrically connecting with the semiconductor pillar 120.

[0113] In some embodiments, such as Figure 6 As shown, the semiconductor structure 200 further includes a doped layer 280. The doped layer 280 is located between the silicide layer 211 and the first end face 121, and is arranged parallel to the silicide layer 211, in contact with both the doped layer 280 and the first end face 121. The doped layer 280 has N-type ions.

[0114] For example, the constituent material of the doped layer 280 may include silicon having N-type ions. For example, the thickness of the doped layer 280 in the first direction X may be less than the thickness of the silicide layer 211 in the first direction X.

[0115] Studies have shown that N-type ions can suppress the diffusion of metal silicide material from the silicide layer 211 into the semiconductor pillar 120. Therefore, by providing a doped layer 280 between the silicide layer 211 and the first end face 121, the aforementioned abnormal diffusion phenomenon can be avoided, which helps to reduce the influence of the silicide layer 211 on the on-state and off-state currents of the semiconductor structure 200 and improve the electrical performance of the semiconductor structure 200.

[0116] In some embodiments, reference Figure 5 The semiconductor structure 200 also includes multiple capacitor structures C. The capacitor structures C are located on the side of the contact structure 210 away from the semiconductor pillar 120 and are connected to the conductive layer 212. In the first direction X, a transistor structure T, a contact structure 210, and a capacitor structure C are sequentially stacked. The contact structure 210 is connected to a capacitor structure C and a transistor structure T at its two ends along the first direction X.

[0117] In this embodiment, a contact structure 210 is disposed between the transistor structure T and the capacitor structure C. The contact structure 210 has a conductive function, thereby electrically connecting the transistor structure T and the capacitor structure C.

[0118] As can be seen from some of the embodiments mentioned above, the gate layer 130 of the transistor structure T is connected to the word line, the drain of the transistor structure T is connected to the bit line, and the source of the transistor structure T is connected to the capacitor structure C. The voltage signal on the word line can control the transistor structure T to turn on or off, thereby reading the data information stored in the capacitor structure C through the bit line, or writing the data information into the capacitor structure C for storage through the bit line.

[0119] Figure 7 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments.

[0120] In the following text, combined with Figures 7 to 12 The preparation methods of the semiconductor structure 200 provided in some embodiments of this disclosure will be explained and described.

[0121] Some embodiments of this disclosure also provide a method for fabricating a semiconductor structure 200, such as... Figure 7 As shown, the method for fabricating the semiconductor structure 200 includes: S1 to S2.

[0122] S1. A transistor structure is formed, the transistor structure including a gate layer and a semiconductor pillar, the semiconductor pillar extending along a first direction, and the gate layer coupled to at least one side of the semiconductor pillar.

[0123] In this step, refer to Figure 8 For example, a deposition process and an etching process can be used to form the semiconductor pillar 120 and the gate layer 130. The semiconductor pillar 120 extends along the first direction X, and the gate layer 130 is coupled to at least one side of the semiconductor pillar 120. In this step, multiple semiconductor pillars 120 can be formed. An insulating material can be deposited between adjacent semiconductor pillars 120 by a deposition process to form an isolation structure 220. The isolation structure 220 is located on at least one side of the semiconductor pillar 120 and is also located between partially adjacent gate layers 130. The isolation structure 220 is stacked with the gate layer 130 in the first direction X.

[0124] For example, the insulating material may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant insulating materials, or other suitable insulating materials.

[0125] Deposition processes include, but are not limited to, one or more thin film deposition processes among Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

[0126] The etching process can be either wet etching or dry etching.

[0127] S2. A contact structure is formed, which is stacked with the semiconductor pillar in a first direction. The contact structure includes a silicide layer and a conductive layer stacked along the first direction. The silicide layer is located between the semiconductor pillar and the conductive layer, and the silicide layer is in contact with the first end face of the semiconductor pillar. In a second direction, the size of the silicide layer is larger than the size of the first end face, and the second direction intersects the first direction.

[0128] In this step, refer to Figure 8 For example, an etching process can be used to remove part of the isolation structure 220 of the transistor structure T to form the first groove 240. The etching process can be a wet etching process or a dry etching process.

[0129] After the first groove 240 is formed, a first dielectric layer 250 and a second dielectric layer 260 are formed sequentially in the first groove 240, with the first dielectric layer 250 located between the second dielectric layer 260 and the semiconductor pillar 120.

[0130] In this step, refer to Figure 8 and Figure 9 An insulating material (e.g., silicon oxide) can be deposited within the first groove 240 using an ALD process to form a first dielectric layer 250. The composition of the first dielectric layer 250 can be the same as that of the isolation structure 220. The first dielectric layer 250 at least covers the sidewalls of the first groove 240 and may also cover the bottom wall of the first groove 240. An insulating material (e.g., silicon nitride) can be further deposited within the first groove 240 using one or more thin-film deposition processes, including but not limited to PVD, CVD, and ALD, to form a second dielectric layer 260. The second dielectric layer 260 fills the remaining space of the first groove 240 and is located on the side of the first dielectric layer 250 away from the semiconductor pillar 120. In addition, in order to avoid damaging the second dielectric layer 260 when removing part of the first dielectric layer 250 in subsequent preparation steps, the composition of the second dielectric layer 260 can be different from that of the first dielectric layer 250. For example, the composition of the first dielectric layer 250 includes silicon oxide, and the composition of the second dielectric layer 260 includes silicon nitride.

[0131] refer to Figure 9 and Figure 10 After the first dielectric layer 250 and the second dielectric layer 260 are sequentially formed in the first groove 240, the surface of the transistor structure T can be planarized by chemical mechanical polishing (CMP) to make the upper surface of the first dielectric layer 250, the upper surface of the second dielectric layer 260 and the upper surface of the semiconductor pillar 120 flush.

[0132] refer to Figure 10 and Figure 11 After the first dielectric layer 250 and the second dielectric layer 260 are formed sequentially in the first groove 240, a dry etching process or a wet etching process can be used to remove part of the first dielectric layer 250 and part of the semiconductor pillar 120 to form the second groove 270.

[0133] Here, the second groove 270 is the self-aligned hole for the subsequent formation of the silicide layer 211. The width of the second groove 270 in the second direction Y is greater than the width of the first end face 121 in the second direction Y, which is beneficial to improve the process window for forming other conductive structures on the first end face 121 in the subsequent fabrication process.

[0134] refer to Figure 11 , Figure 12 and Figure 5 After the second groove 270 is formed, a silicide layer 211 can be formed, which is located at the bottom of the second groove 270.

[0135] In this step, continue to refer to Figure 11 , Figure 12 and Figure 5 A doped layer 280 with N-type ions can be formed within the second groove 270 by a deposition process. The constituent material of the doped layer 280 includes silicon. After the formation of the doped layer 280, a metal deposition and annealing process is performed on the doped layer 280 to form a silicide layer 211.

[0136] Here, the metal compound gas used in the metal deposition process has selective deposition characteristics. This metal compound gas can only adsorb onto the surface of conductors and semiconductors (e.g., metals and silicon) and decompose to form a metal layer, but cannot adsorb onto the surface of the insulating dielectric layer. Therefore, after metal deposition on the doped layer 280, a metal layer is formed only on the doped layer 280. In some embodiments, the metal compound gas may include one or more of tungsten (W), cobalt (Co), nickel (Ni), or titanium (Ti). Of course, this disclosure does not limit the specific types of metals included in the metal compound gas; any metal that can selectively adsorb onto the surface of conductors and semiconductors but not onto the surface of the insulating dielectric layer is acceptable, and may include metals with this characteristic developed according to technological advancements.

[0137] After metal deposition and annealing processes are performed on the doped layer 280, the doped layer 280 reacts with the metal to form a (metal) silicide layer 211.

[0138] Here, the N-type ions in the doped layer 280 can also suppress the diffusion of silicide generated during this process into the semiconductor pillar 120. Therefore, the thickness of the final silicide layer 211 can be controlled by controlling the thickness of the doped layer 280, which helps to avoid abnormal diffusion of the silicide layer 211. Furthermore, the above-described fabrication process is simple and saves on the amount of metal used, which helps to reduce the fabrication difficulty and cost of the semiconductor structure 200.

[0139] refer to Figure 5 and Figure 12 After the silicide layer 211 is formed, a conductive layer 212 is formed, which is located on the side of the silicide layer 211 away from the semiconductor pillar 120.

[0140] In this step, one or more thin film deposition processes, including but not limited to PVD, CVD, and ALD, can be used to deposit conductive material in the second groove 270 to form a conductive layer 212.

[0141] For example, the conductive material includes, but is not limited to, one or more combinations of titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or other suitable conductive materials.

[0142] The semiconductor structure 200 fabricated using the above-described process has a contact structure 210 that reduces the contact resistance between the first end face 121 and other conductive structures. Specifically, the silicide layer 211 has a larger dimension in the second direction Y than the first end face 121 in the second direction Y. Therefore, in the XY plane, the silicide layer 211 is wider than the first end face 121, which is more conducive to the formation of other conductive structures on the silicide layer 211, thus improving the process window for fabricating other conductive structures (such as capacitor structure C) electrically connected to the first end face 121.

[0143] Furthermore, the doped layer 280 can suppress the abnormal diffusion of the silicide layer 211, which is beneficial to improving the electrical performance of the prepared semiconductor structure 200.

[0144] This disclosure also provides a storage system in some embodiments. Please refer to... Figure 13 and Figure 14 , Figure 13 This is a block diagram of a storage system according to some embodiments. Figure 14 This is a block diagram of a storage system according to some other embodiments. For example... Figure 13 As shown, the storage system 20 includes a controller 30 and a three-dimensional memory 10 provided in some of the above embodiments. The controller 30 is coupled to the three-dimensional memory 10 and configured to control the three-dimensional memory 10 to store data.

[0145] It should be noted that the three-dimensional memory 10 can be the semiconductor structure 200 in some of the above embodiments, or the three-dimensional memory 10 includes the semiconductor structure 200 in some of the above embodiments.

[0146] The storage system 20 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 20 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device 50 containing storage.

[0147] In some embodiments, such as Figure 13 As shown, the storage system 20 includes a controller 30 and a three-dimensional memory 10, and the storage system 20 can be integrated into a memory card.

[0148] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0149] In other embodiments, such as Figure 14 As shown, the storage system 20 includes a controller 30 and multiple three-dimensional memory units 10, and the storage system 20 is integrated into a solid state drive (SSD).

[0150] In some embodiments of the storage system 20, the controller 30 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices 50 such as personal calculators, digital cameras, and mobile phones.

[0151] In other embodiments, controller 30 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0152] In some embodiments, the controller 30 may be configured to manage data stored in the 3D memory 10 and to communicate with an external device (e.g., a host). In some embodiments, the controller 30 may also be configured to control operations of the 3D memory 10, such as read, erase, and program operations. In some embodiments, the controller 30 may also be configured to manage various functions relating to data stored or to be stored in the 3D memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 30 is also configured to process error correction codes relating to data read from or written to the 3D memory 10.

[0153] Of course, the controller 30 can also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 30 can communicate with external devices (e.g., a host) through at least one of various interface protocols.

[0154] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0155] The controller 30 mentioned above may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0156] In this embodiment, since the three-dimensional memory 10 can be the semiconductor structure 200 in some of the above embodiments, or the three-dimensional memory 10 includes the semiconductor structure 200 in some of the above embodiments, the electrical performance of the memory system including the semiconductor structure in some of the above embodiments is also improved.

[0157] Some embodiments of this disclosure also provide an electronic device. Figure 15 This is a block diagram of an electronic device according to some embodiments. For example... Figure 15As shown, the electronic device 50 includes a storage system 20 and a motherboard 40 as provided in some of the above embodiments. The storage system 20 is electrically connected to the motherboard 40. In addition, the electronic device 50 may also include at least one of a central processing unit (CPU) and a cache.

[0158] For example, electronic device 50 can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0159] In this embodiment, the electronic device 50 may include the storage system 20 provided in the above embodiment, which is beneficial to improving the electrical performance of the electronic device 50 and facilitating the miniaturization of the electronic device 50.

[0160] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A transistor structure, the transistor structure including a gate layer and a semiconductor pillar, the semiconductor pillar extending along a first direction, the gate layer being coupled to at least one side of the semiconductor pillar; A contact structure is stacked with the semiconductor pillar in a first direction; the contact structure includes a silicide layer and a conductive layer stacked along the first direction, the silicide layer is located between the semiconductor pillar and the conductive layer, and the silicide layer is connected to a first end face of the semiconductor pillar; in a second direction, the size of the silicide layer is larger than the size of the first end face, and the second direction intersects the first direction.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A doped layer is located between the silicide layer and the first end face, the doped layer is in contact with the silicide layer, and the doped layer is in contact with the first end face; The doped layer has N-type ions.

3. The semiconductor structure according to claim 1, characterized in that, In the second direction, the size of the conductive layer is the same as the size of the silicide layer.

4. The semiconductor structure according to claim 1, characterized in that, The size of the silicide layer in the first direction ranges from 5 nm to 10 nm.

5. The semiconductor structure according to claim 1, characterized in that, The number of transistor structures is multiple, the number of contact structures is multiple, and one contact structure is stacked with one semiconductor pillar of the transistor structure; In the plurality of silicide layers, the difference in size between any two silicide layers in the first direction is less than 5 nm.

6. The semiconductor structure according to claim 5, characterized in that, The plurality of silicide layers have the same size in the first direction.

7. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure further includes a plurality of dielectric structures, which are alternately arranged with a plurality of contact structures along the second direction, and the dielectric structures are in contact with the silicide layer adjacent to them.

8. The semiconductor structure according to claim 7, characterized in that, Of the two adjacent dielectric structures: one is a first dielectric structure and the other is a second dielectric structure; The first dielectric structure, the second dielectric structure, and the semiconductor pillar located between the first dielectric structure and the second dielectric structure together constitute a semiconductor assembly, wherein the difference between the distance between the first dielectric structure and the first end face and the distance between the second dielectric structure and the first end face is less than 0.3 nm.

9. The semiconductor structure according to claim 8, characterized in that, In the semiconductor component: the distance between the first dielectric structure and the first end face ranges from 1 nm to 3 nm.

10. The semiconductor structure according to claim 1, characterized in that, In the first direction, the distance between the silicide layer and the gate layer is greater than 50 nm.

11. The semiconductor structure according to claim 1, characterized in that, The transistor structure further includes an isolation structure located on at least one side of the semiconductor pillar, and in the first direction, the isolation structure is also located between the silicide layer and the gate layer.

12. The semiconductor structure according to claim 1, characterized in that, The dimensions of the contact structure in the second direction range from 15 nm to 24 nm.

13. The semiconductor structure according to claim 1, characterized in that, The material of the silicide layer includes one or more metallic elements selected from nickel, titanium, and cobalt.

14. The semiconductor structure according to claim 1, characterized in that, The conductive layer is composed of materials including titanium or titanium nitride.

15. The semiconductor structure according to any one of claims 1-14, characterized in that, Also includes: A capacitor structure is located on the side of the contact structure away from the semiconductor pillar and is connected to the conductive layer.

16. A method for fabricating a semiconductor structure, characterized in that, include: A transistor structure is formed, the transistor structure including a gate layer and a semiconductor pillar, the semiconductor pillar extending along a first direction, and the gate layer coupled to at least one side of the semiconductor pillar; A contact structure is formed, wherein the contact structure and the semiconductor pillar are stacked in the first direction; the contact structure includes a silicide layer and a conductive layer stacked in the first direction, the silicide layer is located between the semiconductor pillar and the conductive layer, and the silicide layer is in contact with the first end face of the semiconductor pillar; in the second direction, the size of the silicide layer is larger than the size of the first end face, and the second direction intersects the first direction.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, The formation of the contact structure includes: A portion of the isolation structure of the transistor structure is removed to form a first recess, the isolation structure being located on at least one side of the semiconductor pillar, and the isolation structure being stacked with the gate layer in the first direction; A first dielectric layer and a second dielectric layer are sequentially formed in the first groove, with the first dielectric layer located between the second dielectric layer and the semiconductor pillar; A portion of the first dielectric layer and a portion of the semiconductor pillars are removed to form a second groove; A silicide layer is formed, the silicide layer being located at the bottom of the second groove; A conductive layer is formed on the side of the silicide layer away from the semiconductor pillar.

18. The method for preparing a semiconductor structure according to claim 17, characterized in that, The formation of the silicide layer includes: A doped layer is formed in the second groove, the doped layer having N-type ions; The doped layer is subjected to metal deposition and annealing processes to form the silicide layer.

19. The method for preparing a semiconductor structure according to claim 18, characterized in that, The formation of the conductive layer includes: Conductive material is deposited in the second groove.

20. A storage system, characterized in that, include: The semiconductor structure according to any one of claims 1-15; A controller coupled to the semiconductor structure to control the semiconductor structure to store data.

21. An electronic device, characterized in that, include: The motherboard and the storage system as described in claim 20, wherein the motherboard is electrically connected to the storage system.

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