Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device includes a substrate, a plurality of layers of transistor cells stacked on the substrate, and a word line. A plurality of layers of transistor units stacked on the substrate; each layer of transistor units comprises a plurality of transistor units which are arranged at intervals in the first direction, and each transistor unit comprises at least two transistors which are arranged at intervals in the first direction. The transistor comprises a semiconductor structure and an insulated grid electrode; the semiconductor structure extends along a second direction; in the first direction, a common grid electrode is arranged between the semiconductor structures of the adjacent transistors in each transistor unit, and respective grid electrodes are arranged between the adjacent semiconductor structures of the adjacent transistor units; the first direction and the second direction intersect and are both parallel to the substrate. The plurality of word lines extend along a third direction perpendicular to the substrate, and each word line is electrically connected with a plurality of grid electrodes which are arranged at intervals along the third direction. The performance of the semiconductor device can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of semiconductor devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect the performance of semiconductor devices.

[0003] To minimize product costs, the goal is to fabricate as many semiconductor devices as possible on a substrate with limited area. Since the advent of Moore's Law, the industry has proposed various structural designs and process optimizations for semiconductor devices to meet current product demands. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device, its manufacturing method, and an electronic device that can effectively improve the performance of the semiconductor device.

[0005] In a first aspect, embodiments of this application provide a semiconductor device, comprising:

[0006] A multilayer stacked transistor unit on a substrate; each transistor unit includes a plurality of transistor units spaced apart along a first direction, and each transistor unit includes at least two transistors spaced apart along the first direction;

[0007] The transistor includes a semiconductor structure and a phase-insulated gate; the semiconductor structure extends along a second direction; along a first direction, a common gate is provided between the semiconductor structures of adjacent transistors in each transistor unit, and a separate gate is provided between the adjacent semiconductor structures of adjacent transistor units; the first direction intersects the second direction and is parallel to the substrate.

[0008] Multiple word lines extend along a third direction perpendicular to the substrate, and each word line is electrically connected to multiple gates spaced apart along the third direction.

[0009] In some possible embodiments, it also includes:

[0010] Multiple bit lines extend along a first direction, and each bit line is electrically connected to multiple semiconductor structures spaced apart along the first direction. In some possible embodiments, the transistor further includes a gate dielectric structure disposed between the semiconductor structures and the gate along the first direction;

[0011] Semiconductor devices also include:

[0012] Multiple gate dielectric layers extend along a third direction and are electrically connected to multiple gate dielectric structures spaced apart along the third direction, and are stacked with word lines in a first direction.

[0013] In some possible embodiments, along a first direction, the first spacing between the semiconductor structures of adjacent transistors in adjacent transistor cells is greater than the second spacing between the semiconductor structures of adjacent transistors in the same transistor cell.

[0014] In some possible embodiments, along the first direction, the first spacing is equal to twice the second spacing plus the sum of the dimensions of the semiconductor structure.

[0015] Secondly, embodiments of this application also provide a method for manufacturing a semiconductor device, comprising:

[0016] A multilayer spaced semiconductor unit is formed on a substrate; each semiconductor unit includes a plurality of semiconductor units spaced apart along a first direction, and each semiconductor unit includes at least two semiconductor structures spaced apart along the first direction; the semiconductor structures extend along a second direction.

[0017] Along the first direction, a common gate and word line are fabricated between adjacent semiconductor structures in a semiconductor cell, and a separate gate and word line are fabricated between adjacent semiconductor structures in adjacent semiconductor cells to obtain the transistor cell to which the semiconductor cell belongs.

[0018] The word line extends along a third direction perpendicular to the substrate and is electrically connected to a plurality of gates spaced apart along the third direction.

[0019] In some possible embodiments, a multilayer spaced semiconductor cell is formed on the substrate, including:

[0020] A stacked structure is formed on the substrate, the stacked structure comprising alternating layers of semiconductor layers and layers of sacrificial layers;

[0021] Pattern the removal of the two ends of the overlay structure along the second direction, and create frame layers at the two ends of the overlay structure along the second direction;

[0022] The remaining stacked structure is patterned to form multiple first channels and second channels spaced apart along a first direction, exposing the substrate, such that the stacked structure between adjacent first channels forms a stacked unit, and the stacked unit is divided into at least two stacked walls by at least one second channel; both the first channel and the second channel extend along a second direction, and the frame layer is exposed at both ends of the second direction; along the first direction, the size of the first channel is larger than the size of the second channel;

[0023] By removing the sacrificial layers based on the first and second channels, a third channel is formed, thereby creating a multilayer semiconductor structure with multiple semiconductor layers separated by the third channel.

[0024] In some possible embodiments, along the first direction, the size of the first channel is equal to twice the size of the second channel plus the size of the stacked wall.

[0025] In some possible embodiments, along a first direction, a common gate and word line are formed between adjacent semiconductor structures in a semiconductor cell, and respective gates and word lines are formed between adjacent semiconductor structures in adjacent semiconductor cells, including:

[0026] A dielectric structure is fabricated on both sides of a semiconductor structure along a third direction, and an isolation wall is formed between adjacent semiconductor cells along a first direction; the isolation wall and the semiconductor cells are spaced apart;

[0027] Along the first direction, a gate dielectric material layer and a common gate material layer are sequentially fabricated between adjacent semiconductor structures and dielectric structures in a semiconductor cell, and a gate dielectric material layer and a gate material layer are sequentially fabricated between an isolation wall and the semiconductor structure and dielectric structure of an adjacent semiconductor cell.

[0028] The isolation wall, gate dielectric material layer, and gate material layer are patterned to form the isolation layer, gate dielectric structure, gate dielectric layer, gate, and word line, respectively.

[0029] In some possible embodiments, fabricating a dielectric structure located on both sides of the semiconductor structure along a third direction, and forming an isolation wall between adjacent semiconductor cells along a first direction, includes:

[0030] Dielectric layers are filled between the framework layers, and each semiconductor structure is encapsulated by the dielectric layers.

[0031] The dielectric layer is patterned to form a dielectric structure located on both sides of the semiconductor structure along a third direction, and an isolation wall located between semiconductor cells along a first direction.

[0032] In some possible embodiments, along the first direction, the distance between the isolation wall and the adjacent semiconductor cell is the same as the distance between adjacent semiconductor structures in the semiconductor cell, and the size of the isolation wall is the same as the size of the semiconductor structure.

[0033] In some possible embodiments, along a first direction, respective gate dielectric material layers and a common gate material layer are sequentially fabricated between adjacent semiconductor structures and dielectric structures in a semiconductor cell, and respective gate dielectric material layers and gate material layers are sequentially fabricated between an isolation wall and the semiconductor structure and dielectric structure of an adjacent semiconductor cell, including:

[0034] Along the first direction, gate dielectric material layers are fabricated on both sides of the semiconductor structure and the dielectric structure, as well as on both sides of the isolation wall; the gate dielectric material layers on both sides of the semiconductor structure are their respective gate dielectric material layers;

[0035] Along the first direction, a gate material layer is fabricated on the side of the gate dielectric material layer that is exposed, such that both sides of the gate material layer are in contact with the gate dielectric material layer; the gate material layers between the respective gate dielectric material layers of adjacent semiconductor structures in the semiconductor cell form a common gate material layer, and the gate material layers between the isolation wall and the adjacent semiconductor structure form their respective gate material layers.

[0036] Thirdly, embodiments of this application also provide an electronic device, including: any semiconductor device as provided in the first aspect above, or a semiconductor device manufactured by a manufacturing method of any semiconductor device as provided in the second aspect above.

[0037] The beneficial technical effects of the technical solutions provided in this application include:

[0038] In the semiconductor device provided in this application embodiment, multiple transistor units are stacked on a substrate, and each layer has multiple transistor units spaced apart along a first direction. Each transistor unit includes multiple transistors spaced apart along the first direction. The gates of the transistors along the first direction are distributed on both sides of the semiconductor structure of the transistor. Adjacent transistors in the same transistor unit share gates on opposite sides, while the outermost transistors in different transistor units use their gates separately, closer to the gates of adjacent transistor units. This application embodiment can reduce the size of the transistor units in the first direction, save substrate area, and further miniaturize the size of the semiconductor device. Moreover, this application embodiment can reduce the material required to manufacture the gates, reducing production costs.

[0039] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0040] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0041] Figure 1 This is a top view of a semiconductor device provided in an embodiment of this application;

[0042] Figure 2 for Figure 1 Schematic diagram of the cross section at point AA';

[0043] Figure 3 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application;

[0044] Figure 4This is a side view schematic diagram of the film structure after forming a stacked structure 600 on a substrate 100 in a method for manufacturing a semiconductor device according to an embodiment of this application.

[0045] Figure 5 This is a top view of the film structure after patterning removal of both ends of the stacked structure 600 along the second direction and fabrication of the frame layer 700 at both ends of the stacked structure 600 along the second direction in a semiconductor device manufacturing method provided in this application embodiment.

[0046] Figure 6 This is a side view of the film structure after patterning removal of both ends of the stacked structure 600 along the second direction and fabrication of the frame layer 700 at both ends of the stacked structure 600 along the second direction in a semiconductor device manufacturing method provided in this application embodiment.

[0047] Figure 7 This is a top view of the film structure formed by the patterning process of the remaining stacked structure 600 in a semiconductor device manufacturing method provided in this application, after forming a plurality of first channels 801 and second channels 802 spaced apart along a first direction.

[0048] Figure 8 for Figure 7 Schematic diagram of the cross section at point AA';

[0049] Figure 9 A top view schematic diagram of the film structure after removing each sacrificial layer 62 in a method for manufacturing a semiconductor device according to an embodiment of this application;

[0050] Figure 10 for Figure 9 Schematic diagram of the cross section at point AA';

[0051] Figure 11 for Figure 9 Schematic diagram of the cross section at point BB';

[0052] Figure 12 This is a top view of the film structure after the dielectric layer 901 is filled between the frame layers 700 in a method for manufacturing a semiconductor device according to an embodiment of this application.

[0053] Figure 13 for Figure 12 Schematic diagram of the cross section at point AA';

[0054] Figure 14 for Figure 12 Schematic diagram of the cross section at point BB';

[0055] Figure 15This is a top view schematic diagram of the film structure during the patterning process of the dielectric layer 901 in a semiconductor device manufacturing method provided in this application embodiment;

[0056] Figure 16 for Figure 15 Schematic diagram of the cross section at point AA';

[0057] Figure 17 for Figure 15 Schematic diagram of the cross section at point BB';

[0058] Figure 18 This is a top view of a film structure formed by fabricating dielectric structures 900 on both sides of a semiconductor structure 21 and forming isolation walls 501 between adjacent semiconductor units 211 in a semiconductor device manufacturing method provided in this application embodiment.

[0059] Figure 19 for Figure 18 Schematic diagram of the cross section at point AA';

[0060] Figure 20 for Figure 18 Schematic diagram of the cross section at point BB';

[0061] Figure 21 This is a top view of the film structure after a semiconductor device manufacturing method provided in this application is used to manufacture a common gate material layer 221 between adjacent semiconductor structures 21 and dielectric structures 900 in a semiconductor cell 211, and to manufacture respective gate material layers 221 between the isolation wall 501 and the semiconductor structures 21 and dielectric structures 900 of the adjacent semiconductor cell 211.

[0062] Figure 22 for Figure 21 Schematic diagram of the cross section at point AA';

[0063] Figure 23 for Figure 21 A schematic diagram of the cross-section at point BB'.

[0064] Figure label:

[0065] 100-substrate;

[0066] 200-transistor unit;

[0067] 20 - Transistor; 21 - Semiconductor structure; 211 - Semiconductor unit; 22 - Gate; 221 - Gate material layer; 23 - Gate dielectric structure; 231 - Gate dielectric material layer; 24 - Drain; 25 - Source;

[0068] 300 - Word line; 301 - First word line; 302 - Second word line; 303 - Third word line; 400 - Gate dielectric layer; 500 - Isolation layer; 501 - Isolation wall;

[0069] 600 - Stacked structure; 61 - Semiconductor layer; 62 - Sacrificial layer; 63 - Stacked cell; 64 - Stacked wall;

[0070] 700 - Frame layer; 801 - First channel; 802 - Second channel; 803 - Third channel;

[0071] 900 - Dielectric structure; 901 - Dielectric layer;

[0072] 101 - Mask structure; 102 - Capacitor; 103 - Bit line;

[0073] L1 - First spacing; L2 - Second spacing. Detailed Implementation

[0074] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0075] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."

[0076] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0077] The research and development approach of this application includes: As chip integration density continues to increase, the size of memory in semiconductor devices is also constantly shrinking. How to further improve the storage density of three-dimensional stacked dynamic random access memory (3D DRAM) is an important research direction in the field of 3D DRAM.

[0078] Multi-layer stacked 3D DRAM technology can effectively improve storage density. When the number of stacked layers increases to a certain extent, horizontally stacked 3D DRAM will exhibit significant performance or cost advantages.

[0079] Horizontally stacked 3D DRAM refers to structures such as transistors or memory cells stacked horizontally. Currently, multi-layer horizontally stacked 3D DRAM can be implemented using a vertical word line architecture, where the word lines are perpendicular to the substrate. However, when a dual word line structure is used for the transistors, each transistor has a separate gate on both sides of the semiconductor structure, resulting in a larger area of ​​the transistors in the horizontal direction, which in turn leads to a larger area occupied by the memory cell array in the horizontal direction.

[0080] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.

[0081] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0082] This application provides a semiconductor device, the structural schematic diagram of which is shown below. Figure 1 and Figure 2 As shown, the semiconductor device includes: transistor cells 200 and word lines 300 stacked on a substrate 100 in multiple layers.

[0083] Each transistor cell 200 includes a plurality of transistor cells 200 spaced apart along a first direction, and each transistor cell 200 includes at least two transistors 20 spaced apart along the first direction.

[0084] The transistor 20 includes a semiconductor structure 21 and a phase-insulated gate 22; the semiconductor structure 21 extends along a second direction; along a first direction, a common gate 22 is provided between the semiconductor structures 21 of adjacent transistors 20 in each transistor unit 200, and a separate gate 22 is provided between the adjacent semiconductor structures 21 of adjacent transistor units 200; the first direction intersects the second direction and is parallel to the substrate 100.

[0085] Multiple word lines 300 extend along a third direction perpendicular to the substrate 100, and each word line is electrically connected to multiple gates 22 spaced apart along the third direction.

[0086] In the semiconductor device provided in this application embodiment, multilayer transistor units 200 are stacked on a substrate 100. Each layer has multiple transistor units 200 arranged at intervals along a first direction. Each transistor unit 200 includes multiple transistors 20 arranged at intervals along the first direction. The gates 22 of the transistors 20 along the first direction are distributed on both sides of the semiconductor structure 21 of the transistor 20. In the same transistor unit 200, adjacent transistors 20 share the gates 22 on opposite sides. In different transistor units 200, the gates 22 of the outermost transistors 20 are used separately. Compared with the related art where each transistor 20 has a separate gate 22 on both sides of the semiconductor structure 21, the present application embodiment can reduce the size of the transistor unit 200 in the first direction, save the area of ​​the substrate 100, and further miniaturize the size of the semiconductor device. Moreover, the present application embodiment can reduce the material required to manufacture the gates 22, reducing production costs.

[0087] In this embodiment, each word line 300 is connected to multiple gates 22 at the same position in both the first and second directions, and can be integrally formed with the gates 22, which can reduce manufacturing difficulty and improve manufacturing efficiency.

[0088] It should be noted that in the embodiments of this application, the first direction is the arrangement direction of the transistor 20, which is parallel to the substrate 100 and can be called the horizontal direction. The plane containing the first direction and the second direction is called the horizontal plane. The horizontal position is the same, that is, the position in the first direction and the second direction is the same.

[0089] Optionally, the first direction is perpendicular to the second direction.

[0090] The operation of transistor 20 will be described in detail below with reference to the accompanying drawings.

[0091] like Figure 1 and Figure 2 As shown, in this embodiment of the application, the transistor units 200 are arranged at intervals along a first direction, and each transistor 20 has a gate 22 on both sides. In the same transistor unit 200, adjacent transistors 20 share the gate 22 located between them, and the outermost gate 22 of the outermost transistor 20 is used separately and does not need to be shared with other transistors 20.

[0092] When both gates 22 on both sides of the semiconductor structure 21 of a transistor 20 are at a high level, the channel of the semiconductor structure 21 is in the open state; when at least one of the gates 22 on both sides of the semiconductor structure 21 of a transistor 20 is at a low level, the channel of the semiconductor structure 21 is in the closed state.

[0093] For example, in the third direction, word line 300 connects multiple gates 22 at the same horizontal position. In one transistor unit 200, from left to right, there are first word line 301, second word line 302 and third word line 303. First word line 301 and third word line 303 are connected to individual gates 22, and second word line 302 is connected to a common gate 22. Figure 1 A transistor unit 200 includes two transistors 20. When the first word line 301 is low, the individual gate 22 of the semiconductor structure 21 of the left transistor 20 is low. When the second word line 302 is low, the shared gate 22 between the semiconductor structures 21 of the two transistors 20 is low. When the third word line 303 is low, the individual gate 22 of the semiconductor structure 21 of the right transistor 20 is low. At this time, both the left and right transistors 20 are in the off state.

[0094] When the first word line 301 is low, the individual gate 22 of the semiconductor structure 21 of the left transistor 20 is low. When the second word line 302 is high, the shared gate 22 between the semiconductor structures 21 of the two transistors 20 is high. When the third word line 303 is high, the individual gate 22 of the semiconductor structure 21 of the right transistor 20 is high. At this time, the left transistor 20 is in the off state, and the right transistor 20 is in the on state.

[0095] When the first word line 301 is high, the individual gate 22 of the semiconductor structure 21 of the left transistor 20 is high. When the second word line 302 is high, the shared gate 22 between the semiconductor structures 21 of the two transistors 20 is high. When the third word line 303 is high, the individual gate 22 of the semiconductor structure 21 of the right transistor 20 is high. At this time, both the left and right transistors 20 are in the on state.

[0096] When the first word line 301 is high, the individual gate 22 of the semiconductor structure 21 of the left transistor 20 is high. When the second word line 302 is high, the shared gate 22 between the semiconductor structures 21 of the two transistors 20 is high. When the third word line 303 is low, the individual gate 22 of the semiconductor structure 21 of the right transistor 20 is low. At this time, the left transistor 20 is in the on state, and the right transistor 20 is in the off state.

[0097] Unlike related technologies where each transistor 20 has two gates 22, this application embodiment forms a transistor unit 200 with multiple transistors 20 that can share a gate 22, and provides the following isolation method for the multiple transistor units 200:

[0098] In some possible embodiments, the semiconductor device further includes:

[0099] Multiple bit lines 103 extend along a first direction, and each bit line is electrically connected to multiple semiconductor structures 21 arranged at intervals along the first direction.

[0100] In this embodiment, multilayer transistor units 200 are stacked on substrate 100 along a third direction. Bit lines 103 are formed at one end of transistor 20 of transistor unit 200 along a second direction and extend along a first direction to connect semiconductor structures 21 of multiple transistors 20 disposed on the same layer.

[0101] Optionally, each transistor 20 has a drain 24 formed at the end of its semiconductor structure 21, and the bit line 103 is electrically connected to the drains 24 at the ends of the semiconductor structures 21 arranged along the first direction.

[0102] Optionally, an active electrode 25 is formed at the end of the semiconductor structure 21 of each transistor 20, and is electrically connected to the corresponding capacitor 102.

[0103] Optionally, the source 25 and the drain 24 are formed at both ends of the semiconductor structure 21.

[0104] In some possible embodiments, such as Figure 1 and Figure 2 As shown, transistor 20 also includes a gate dielectric structure 23.

[0105] The gate dielectric structure 23 is disposed between the semiconductor structure 21 and the gate 22 along the first direction.

[0106] The semiconductor device also includes a plurality of gate dielectric layers 400 extending along a third direction and electrically connected to a plurality of gate dielectric structures 23 spaced apart along the third direction, and stacked with word lines 300 in a first direction.

[0107] In this embodiment, the gate dielectric structure 23 is located between the semiconductor structure 21 and the gate 22 of each transistor 20. The gate dielectric layer 400 is connected to the gate dielectric structure 23, which is located at the same position in both the first and second directions, and can be integrally formed with the gate dielectric structure 23, thereby reducing manufacturing difficulty and improving manufacturing efficiency.

[0108] In some possible embodiments, such as Figure 1 As shown, along the first direction, the first spacing L1 between the semiconductor structures 21 of adjacent transistors 20 in adjacent transistor units 200 is greater than the second spacing L2 between the semiconductor structures 21 of adjacent transistors 20 in the same transistor unit 200.

[0109] In this embodiment, multiple gates 22 between the semiconductor structures 21 of adjacent transistors 20 in the same transistor unit 200 are designed as a common gate 22, which greatly reduces the spacing between semiconductor structures 21 and thus effectively reduces the size of semiconductor devices.

[0110] In some possible embodiments, such as Figure 1 As shown, along the first direction, the first spacing L1 is equal to twice the second spacing L2 plus the sum of the dimensions of the semiconductor structure 21.

[0111] In this embodiment, the gates 22 of transistors 20 in the same transistor unit 200 and in different transistor units 200 can be fabricated simultaneously and have the same size. Therefore, two sets of gates 22 (or a combination of gate 22 and gate dielectric structure 23) need to be provided between adjacent transistor units 200, and the first spacing L1 is not less than twice the second spacing L2.

[0112] Furthermore, an isolation layer needs to be provided between adjacent transistor units 200. The size of the isolation layer is consistent with the size of the semiconductor structure 21. Therefore, the isolation layer can be directly patterned using the mask structure 101 used to manufacture the semiconductor structure 21, which can reduce the cost of patterning.

[0113] Therefore, along the first direction, the first spacing L1 is equal to twice the second spacing L2 plus the size of the semiconductor structure 21.

[0114] Optionally, the material of the semiconductor structure 21 includes metal oxide semiconductor materials or silicon-containing materials. Among them, metal oxide semiconductor materials include IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), and IWO (Indium Wolfmium Oxide). Oxide (indium tungsten oxide), InGaO (indium gallium oxide), ZnO (zinc oxide), InO (indium oxide), InO (indium oxide), InWO (indium tungsten oxide), SnO (tin oxide), TiO (titanium oxide), InSnO (indium tin oxide), ZnON (nitrogen-doped zinc oxide), MgZnO (magnesium zinc oxide), InZnO (indium zinc oxide), InGaZnO (indium gallium zinc oxide), ZrInZnO (zinc zirconium oxide), HfInZnO (hafnium indium zinc oxide), SnInZnO (tin indium zinc oxide), AlZnO (zinc aluminum oxide), AlSnInZnO (zinc aluminum indium oxide), SiInZnO (zinc silicon oxide), ZnSnO (zinc tin oxide), AlZnSnO (zinc aluminum oxide), GaZnSnO (zinc gallium oxide), ZrZnSnO (zinc zirconium oxide), and InGaSiO (indium gallium silicon oxide), etc.

[0115] Based on the same inventive concept, embodiments of this application also provide a method for manufacturing a semiconductor device, the process flow diagram of which is shown below. Figure 3 As shown, the method includes steps S101-S102:

[0116] S101: A multilayer spaced semiconductor unit 211 is formed on the substrate 100; each semiconductor unit 211 includes a plurality of semiconductor units 211 spaced apart along a first direction, and each semiconductor unit 211 includes at least two semiconductor structures 21 spaced apart along the first direction; the semiconductor structures 21 extend along a second direction.

[0117] S102: Along a first direction, a common gate 22 and word line 300 are fabricated between adjacent semiconductor structures 21 in semiconductor cell 211, and individual gates 22 and word lines 300 are fabricated between adjacent semiconductor structures 21 of adjacent semiconductor cells 211, thereby obtaining a transistor cell 200 to which semiconductor cell 211 belongs. The word line 300 extends along a third direction perpendicular to the substrate 100 and is electrically connected to a plurality of gates 22 spaced apart along the third direction.

[0118] In this embodiment, a multilayer semiconductor unit 211 is first formed on the substrate 100. The semiconductor structures 21 of each semiconductor unit 211 are spaced apart in the first direction, the second direction, and the third direction, and do not contact each other. Then, a shared gate 22 and word line 300 are fabricated between adjacent semiconductor structures 21 in the semiconductor unit 211, and individual gates 22 and word lines 300 are fabricated between adjacent semiconductor structures 21 of adjacent semiconductor units 211, resulting in a transistor unit 200 to which the semiconductor unit 211 belongs. This embodiment can reduce the size of the transistor unit 200 in the first direction, save the area of ​​the substrate 100, and further miniaturize the size of the semiconductor device. Moreover, this embodiment can reduce the material required to fabricate the gate 22, reducing production costs.

[0119] Optionally, the gate 22 and word line 300 can be integrally formed and manufactured at the same time, which can reduce the manufacturing steps of semiconductor devices and reduce manufacturing costs.

[0120] In some possible embodiments, forming multiple spaced semiconductor cells 211 on the substrate 100 in step S101 above includes the following steps:

[0121] A stacked structure 600 is formed on the substrate 100. The stacked structure 600 includes alternating layers of semiconductor layers 61 and sacrificial layers 62. A schematic diagram of the resulting film structure is shown below. Figure 4 As shown.

[0122] Patterning is used to remove the two ends of the stacked structure 600 along the second direction. A frame layer 700 is then fabricated at both ends of the stacked structure 600 along the second direction. The resulting membrane structure is shown in the schematic diagram below. Figures 5-6 As shown.

[0123] The remaining stacked structure 600 is patterned to form multiple first channels 801 and second channels 802 spaced apart along a first direction, exposing the substrate 100. This allows the stacked structures 600 between adjacent first channels 801 to form stacked units 63, each stacked unit 63 being separated into at least two stacking walls 64 by at least one second channel 802. Both the first channels 801 and 802 extend along a second direction, exposing frame layers at both ends of the second direction. Along the first direction, the size of the first channel 801 is larger than the size of the second channel 802. A schematic diagram of the resulting film structure is shown below. Figures 7-8 As shown.

[0124] By removing the sacrificial layers 62 based on the first and second channels, a third channel 803 is formed, so that the multilayer semiconductor layers 61 of the stacked wall 64 form a multilayer semiconductor structure 21 spaced apart by the third channel 803. The schematic diagram of the resulting film structure is shown below. Figures 9-10 As shown. In each layer, at least two semiconductor structures 21 form a semiconductor unit 211.

[0125] In this embodiment, each semiconductor structure 21 is suspended in the first, second, and third directions, and fixed at both ends by a frame layer 700. Other film structures are then fabricated based on each semiconductor structure 21 to form the transistor 20 belonging to each semiconductor structure 21. This embodiment utilizes alternately stacked sacrificial layers 62 and semiconductor layers 61. Removing the sacrificial layer 62 ensures that the remaining semiconductor structures 21 of each transistor 20 are spaced apart, reducing the possibility of mutual interference between transistors 20 in the third direction.

[0126] In some possible embodiments, along the first direction, the size of the first channel 801 is equal to twice the size of the second channel 802 plus the size of the stacked wall 64.

[0127] In this embodiment, the second channel 802 is used to form a shared gate 22 (or a shared gate 22 and the respective gate dielectric structure 23 of each adjacent transistor 20) for adjacent transistors 20, and the first channel 801 is used to form a gate 22 (or a gate 22 and the corresponding gate dielectric structure 23) for the transistor 20 at the outermost edge of the transistor unit 200. The size of the first channel 801 is equal to twice the size of the second channel 802 plus the size of the stacked wall 64. The shared gate 22 (or the shared gate 22 and the respective gate dielectric structure 23 of each adjacent transistor 20) and the gate 22 (or the gate 22 and the corresponding gate dielectric structure 23) can be fabricated simultaneously in the same process, which can reduce the number of fabrication steps of the semiconductor device and improve manufacturing efficiency.

[0128] Furthermore, this embodiment can use the mask structure 101 used to manufacture the semiconductor structure 21 in the aforementioned embodiment for patterning processing, which can save costs.

[0129] In some possible embodiments, in step S102 above, a common gate 22 and word line 300 are fabricated between adjacent semiconductor structures 21 in the semiconductor cell 211 along the first direction, and a separate gate 22 and word line 300 are fabricated between adjacent semiconductor structures 21 of adjacent semiconductor cells 211, including the following steps:

[0130] A dielectric structure 900 is fabricated on both sides of the semiconductor structure 21 along a third direction, and an isolation wall 501 is formed between adjacent semiconductor cells 211 along a first direction; the isolation wall 501 and the semiconductor cells 211 are spaced apart, and the resulting film structure is shown in the schematic diagram. Figures 18-20 As shown.

[0131] Along the first direction, a gate dielectric material layer 231 and a shared gate material layer 221 are sequentially fabricated between adjacent semiconductor structures 21 and dielectric structures 900 in semiconductor cell 211. A gate dielectric material layer 231 and a gate material layer 221 are also sequentially fabricated between the isolation wall 501 and adjacent semiconductor cells 211. A schematic diagram of the resulting film structure is shown below. Figures 21-23 As shown.

[0132] The isolation wall 501, the gate dielectric material layer 231, and the gate material layer 221 are patterned to form the isolation layer, the gate dielectric layer, the gate 22, and the word line 300, respectively.

[0133] It should be noted that in the embodiments of this application, the two sides of the semiconductor structure 21 refer to the upper and lower sides of the semiconductor structure 21 in the third direction, and the two sides of the semiconductor structure 21 refer to the left and right sides of the semiconductor structure 21 in the first direction.

[0134] In this embodiment, the dielectric structure 900 and the isolation wall 501 are made of the same material and can be manufactured in one step. By filling the dielectric structure 900 between the semiconductor structures 21 along a third direction, the isolation wall 501 can be formed between adjacent semiconductor cells 211 simultaneously. Then, a gate dielectric material layer 231 and a shared gate material layer 221 can be sequentially formed between adjacent semiconductor structures 21 and dielectric structures 900 in the semiconductor cells 211, and a gate dielectric material layer 231 and a gate material layer 221 can be formed between the isolation wall 501 and the semiconductor structures 21 and dielectric structures 900 of the adjacent semiconductor cells 211.

[0135] Next, the previously manufactured isolation wall 501, gate dielectric material layer 231 and gate material layer 221 are patterned to form the isolation layer, gate 22 and word line 300, which simplifies the process steps, improves manufacturing efficiency and reduces manufacturing costs.

[0136] In some possible embodiments, the steps described above, including fabricating dielectric structures 900 on both sides of the semiconductor structure 21 along a third direction and forming isolation walls 501 between adjacent semiconductor cells 211 along a first direction, include the following steps:

[0137] A dielectric layer 901 is filled between the framework layers 700, and the dielectric layer 901 encapsulates each semiconductor structure 21. The resulting film structure is shown in the schematic diagram below. Figures 12-14 As shown.

[0138] The patterned dielectric layer 901 forms a dielectric structure 900 located on both sides of the semiconductor structure 21 along a third direction, and an isolation wall 501 located between the semiconductor cells 211 along a first direction.

[0139] In this embodiment, each semiconductor structure 21 can be enclosed by filling the space between the frame layers 700 with dielectric layers 901, and then patterning the dielectric layers 901, retaining the dielectric layers 901 on both sides of the semiconductor structure 21 and the isolation walls 501 between adjacent semiconductor units 211, that is, simultaneously manufacturing dielectric structures 900 and isolation walls 501 made of the same material. Optionally, refer to Figures 15-17 The dielectric layer 901 can be patterned using the manufactured mask structure 101.

[0140] In some possible embodiments, along the first direction, the distance between the isolation wall 501 and the adjacent semiconductor cell 211 is the same as the distance between the isolation wall 501 and the adjacent semiconductor structure 21 in the semiconductor cell 211, and the size of the isolation wall 501 is the same as the size of the semiconductor structure 21. The resulting film structure schematic diagram is shown below. Figures 18-20 As shown.

[0141] In this embodiment, a sandwich structure of gate dielectric material layer 231, gate material layer 221, and gate dielectric material layer 231 with the same size can be manufactured between the isolation wall 501 and the adjacent semiconductor unit 211, and between adjacent semiconductor structures 21 in the semiconductor unit 211, which can simplify the manufacturing steps of semiconductor devices and save costs.

[0142] In some possible embodiments, the steps described above, including sequentially fabricating respective gate dielectric material layers 231 and a common gate material layer 221 between adjacent semiconductor structures 21 and dielectric structures 900 in the semiconductor cell 211 along the first direction, and sequentially fabricating respective gate dielectric material layers 231 and gate material layers 221 between the isolation wall 501 and the semiconductor structures 21 and dielectric structures 900 of the adjacent semiconductor cell 211, further include the following steps:

[0143] like Figures 21-23 As shown, along the first direction, gate dielectric material layers 231 are fabricated on both sides of the semiconductor structure 21 and the dielectric structure 900, as well as on both sides of the isolation wall 501; the gate dielectric material layers 231 on both sides of the semiconductor structure 21 are their respective gate dielectric material layers 231.

[0144] Along the first direction, a gate material layer 221 is fabricated on the exposed side of the gate dielectric material layer 231, such that both sides of the gate material layer 221 are in contact with the gate dielectric material layer 231; the gate material layers 221 between the respective gate dielectric material layers 231 of adjacent semiconductor structures 21 in the semiconductor cell 211 form a common gate material layer 221, and the gate material layers 221 between the isolation wall 501 and the adjacent semiconductor structure 21 form their respective gate material layers 221.

[0145] In this embodiment, after the dielectric structure 900 and the isolation wall 501 are manufactured, a gate dielectric material layer 231 is formed on both sides of the semiconductor structure 21, the dielectric structure 900 and the isolation wall 501. Then, a gate material layer 221 is formed on the exposed side of the gate dielectric material layer 231. This can be easily achieved by existing deposition processes.

[0146] Optionally, after forming the gate dielectric material layer 231, a gate material layer 221 is formed on the side of the gate dielectric material layer 231. Since the gate dielectric structure 23 and the gate 22 are substantially coincident in the first direction, and the gate dielectric layer 400 and the word line 300 are substantially coincident in the first direction, the gate material layer 221 and the gate dielectric material layer 231 can be patterned simultaneously after the gate material layer 221 is formed. Thus, the gate dielectric structure 23 and the gate 22, the gate dielectric layer 400 and the word line 300 can be formed through a single patterning process, which can further improve the manufacturing efficiency of semiconductor devices.

[0147] Optionally, refer to Figure 1 The semiconductor device provided in this application is a memory.

[0148] Optionally, after forming the semiconductor structure 21, impurity ions can be doped at both ends of the semiconductor structure 21 to make the ends conductive, forming a source 25 or a drain 24, thereby completing the fabrication of the transistor 20.

[0149] Optionally, after forming the drain 24, a bit line 103 extending in a first direction can be formed at one end of the semiconductor structure 21 having the drain 24, and electrically connected to the drains 24 at the ends of a plurality of semiconductor structures 21 spaced apart in the first direction.

[0150] Optionally, after forming the source 25, a corresponding capacitor 102 is manufactured at the end of the semiconductor structure 21 having the source 25 to complete the manufacturing of the memory.

[0151] It should be noted that the framework layer 700 can always exist in memory, serving a supporting function; its specific location is not limited. Figure 1 Not shown in the diagram. For example, along the first direction, the frame layer 700 may be located between the bit line 103 and the transistor 20, or at the end of the bit line 103 facing away from the transistor 20, or between the transistor 20 and the capacitor 102, or at the end of the capacitor 102 facing away from the transistor 20, depending on the actual requirements.

[0152] Optionally, the process further includes: removing the substrate 100 to obtain, as shown in the figure. Figures 1-2 The semiconductor device shown.

[0153] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned by a patterning process to manufacture each corresponding film layer.

[0154] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.

[0155] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film of a certain material manufactured on a substrate 100 using a deposition or coating process. If the thin film does not require a patterning process or photolithography process during the entire manufacturing process, the thin film can also be called a layer. If the thin film requires a patterning process or photolithography process during the entire manufacturing process, it can be called a thin film before the patterning process and a layer after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern".

[0156] Based on the same inventive concept, this application also provides an electronic device, including: any of the semiconductor devices provided in the above embodiments, or a semiconductor device manufactured by the manufacturing method of any of the semiconductor devices provided in the above embodiments.

[0157] In this embodiment, since the electronic device uses any of the semiconductor devices provided in the foregoing embodiments or the semiconductor devices manufactured by the manufacturing methods of any of the semiconductor devices provided in the foregoing embodiments, the principles and technical effects are as described in the foregoing embodiments and will not be repeated here.

[0158] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or power bank.

[0159] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the semiconductor devices provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.

[0160] Those skilled in the art will understand that the electronic devices provided in the embodiments of this application can be specifically designed and manufactured for a desired purpose, or may include known devices in general-purpose computers. These devices have any of the semiconductor devices provided in the various embodiments described above.

[0161] By applying the embodiments of this application, at least the following beneficial effects can be achieved:

[0162] 1. In the semiconductor device provided in this application embodiment, multilayer transistor units 200 are stacked on a substrate 100. Each layer has multiple transistor units 200 arranged at intervals along a first direction. Each transistor unit 200 includes multiple transistors 20 arranged at intervals along the first direction. The gates 22 of the transistors 20 along the first direction are distributed on both sides of the semiconductor structure 21 of the transistor 20. Adjacent transistors 20 in the same transistor unit 200 share their gates 22 on opposite sides. In different transistor units 200, the outermost transistor 20 uses its gate 22 separately, close to the gate of the adjacent transistor unit 200. Compared with the related art where each transistor 20 has a separate gate 22 on both sides of the semiconductor structure 21, this application embodiment can reduce the size of the transistor unit 200 in the first direction, save the area of ​​the substrate 100, and further miniaturize the size of the semiconductor device. Moreover, this application embodiment can reduce the material required to manufacture the gate 22, reducing production costs.

[0163] 2. In some embodiments, the gate dielectric structure 23 is located between the semiconductor structure 21 and the gate 22 of each transistor 20. The gate dielectric layer 400 is connected to the gate dielectric structure 23 at the same horizontal position and can be integrally formed with the gate dielectric structure 23, which can reduce manufacturing difficulty and improve manufacturing efficiency.

[0164] 3. In some embodiments, the gates 22 of transistors 20 in the same transistor unit 200 and in different transistor units 200 can be fabricated simultaneously and have the same size. Therefore, two sets of gates 22 (or a combination of gate 22 and gate dielectric structure 23) need to be provided between adjacent transistor units 200, and the first spacing L1 is not less than twice the second spacing L2. Moreover, an isolation layer needs to be provided between adjacent transistor units 200. The size of the isolation layer is consistent with the size of the semiconductor structure 21. Therefore, the isolation layer can be directly patterned using the mask used to fabricate the semiconductor structure 21, which can reduce the cost of patterning.

[0165] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0166] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0167] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0168] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0169] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: A multilayer stacked transistor unit on a substrate; each layer of the transistor unit includes a plurality of transistor units spaced apart along a first direction, and each transistor unit includes at least two transistors spaced apart along the first direction; The transistor includes a semiconductor structure and a phase-insulated gate; the semiconductor structure extends along a second direction; along the first direction, a common gate is provided between the semiconductor structures of adjacent transistors in each transistor unit, and a separate gate is provided between the adjacent semiconductor structures of adjacent transistor units; the first direction intersects the second direction and is parallel to the substrate. Multiple word lines extend along a third direction perpendicular to the substrate, and each word line is electrically connected to multiple gates spaced apart along the third direction.

2. The semiconductor device according to claim 1, characterized in that, Also includes: Multiple bit lines extend along the first direction, and each bit line is electrically connected to multiple semiconductor structures arranged at intervals along the first direction.

3. The semiconductor device according to claim 1, characterized in that, The transistor further includes: a gate dielectric structure disposed between the semiconductor structure and the gate along the first direction; The semiconductor device further includes: Multiple gate dielectric layers extend along the third direction and are electrically connected to multiple gate dielectric structures spaced apart along the third direction, and are stacked with the word lines in the first direction.

4. The semiconductor device according to claim 1, characterized in that, Along a first direction, the first spacing between the semiconductor structures of adjacent transistors in adjacent transistor units is greater than the second spacing between the semiconductor structures of adjacent transistors in the same transistor unit.

5. The semiconductor device according to claim 4, characterized in that, Along the first direction, the first spacing is equal to twice the second spacing plus the sum of the dimensions of the semiconductor structure.

6. A method for manufacturing a semiconductor device, characterized in that, include: A multilayer spaced semiconductor unit is formed on a substrate; each semiconductor unit layer includes a plurality of semiconductor units spaced apart along a first direction, and each semiconductor unit includes at least two semiconductor structures spaced apart along the first direction; the semiconductor structures extend along a second direction. Along the first direction, a common gate and word line are formed between adjacent semiconductor structures in the semiconductor cell, and a respective gate and word line are formed between adjacent semiconductor structures of adjacent semiconductor cells to obtain the transistor cell to which the semiconductor cell belongs. The word line extends along a third direction perpendicular to the substrate and is electrically connected to a plurality of gates spaced apart along the third direction.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, Forming multiple spaced semiconductor units on a substrate, including: A stacked structure is formed on the substrate, the stacked structure comprising alternating layers of semiconductor layers and layers of sacrificial layers; Patterning is used to remove the two ends of the stacked structure along the second direction, and frame layers are created at the two ends of the stacked structure along the second direction. The remaining stacked structure is patterned to form a plurality of first channels and second channels spaced apart along the first direction, exposing the substrate, such that the stacked structure between adjacent first channels forms a stacked unit, the stacked unit being divided into at least two stacked walls by at least one second channel; both the first channel and the second channel extend along the second direction, exposing the frame layer at both ends of the second direction; along the first direction, the size of the first channel is larger than the size of the second channel; By removing each of the sacrificial layers based on the first and second channels, a third channel is formed, such that the multilayer semiconductor layers of the stacked wall form a multilayer semiconductor structure spaced apart by the third channel.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, Along the first direction, the size of the first channel is equal to twice the size of the second channel plus the size of the stacked wall.

9. The method for manufacturing a semiconductor device according to claim 6, characterized in that, Along the first direction, a common gate and word line are fabricated between adjacent semiconductor structures in the semiconductor cell, and respective gates and word lines are fabricated between adjacent semiconductor structures of adjacent semiconductor cells, including: A dielectric structure is fabricated on both sides of the semiconductor structure along the third direction, and an isolation wall is formed between adjacent semiconductor cells along the first direction; the isolation wall is spaced from the semiconductor cells; Along the first direction, a respective gate dielectric material layer and a common gate material layer are sequentially fabricated between adjacent semiconductor structures and dielectric structures in the semiconductor unit, and a respective gate dielectric material layer and a gate material layer are sequentially fabricated between the isolation wall and the semiconductor structure and dielectric structure of the adjacent semiconductor unit. The isolation wall, the gate dielectric material layer, and the gate material layer are patterned to form an isolation layer, a gate dielectric structure and a gate dielectric layer, the gate and the word line, respectively.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, Fabricating a dielectric structure located on both sides of the semiconductor structure along a third direction, and forming an isolation wall between adjacent semiconductor cells along the first direction, includes: The space between the framework layers is filled with dielectric layers, which encapsulate each of the semiconductor structures. The dielectric layer is patterned to form the dielectric structure located on both sides of the semiconductor structure along a third direction, and an isolation wall located between the semiconductor cells along a first direction.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, Along the first direction, the distance between the isolation wall and the adjacent semiconductor unit is the same as the distance between the isolation wall and the adjacent semiconductor structure in the semiconductor unit, and the size of the isolation wall is the same as the size of the semiconductor structure.

12. The method for manufacturing a semiconductor device according to claim 9, characterized in that, Along the first direction, respective gate dielectric material layers and a common gate material layer are sequentially fabricated between adjacent semiconductor structures and dielectric structures in the semiconductor cell, and respective gate dielectric material layers and gate material layers are sequentially fabricated between the isolation wall and the semiconductor structures and dielectric structures of the adjacent semiconductor cell, including: Along the first direction, gate dielectric material layers are fabricated on both sides of the semiconductor structure and the dielectric structure, as well as on both sides of the isolation wall; the gate dielectric material layers on both sides of the semiconductor structure are their respective gate dielectric material layers. Along the first direction, a gate material layer is fabricated on the exposed side of the gate dielectric material layer, such that both sides of the gate material layer are in contact with the gate dielectric material layer; the gate material layers between the respective gate dielectric material layers of adjacent semiconductor structures in the semiconductor cell form a common gate material layer, and the gate material layers between the isolation wall and the adjacent semiconductor structure form their respective gate material layers.

13. An electronic device, characterized in that, include: The semiconductor device as described in any of claims 1-5 above, or the semiconductor device manufactured by the manufacturing method of any of claims 6-12 above.

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