Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. A plurality of carriers are stored in an electric floating body of a metal semiconductor insulating film electric field effect transistor to store data. The erase operation of the majority carriers is performed together along the word lines by applying a voltage to the board lines by separating the board lines capacitively coupled to the floating body from each word line and wiring the board lines parallel to the word lines. Renew operation of the semiconductor memory device by separating the bit line from the sense amplifier after reading and latching data along the select word line to the sense amplifier and simultaneously erasing majority carriers from the floating bodies of the cells on the select word line, and then rewriting the bit line to the sense amplifier according to the state of the sense amplifier. And injecting the majority carriers into the unit which originally stores more majority carriers. In a write operation, in addition to adding an operation of writing data to the sense amplifier from the outside while simultaneously erasing the majority carriers from the selection unit, the write operation can be performed in the same principle as a re-new operation.

Description

Technical Field

[0001] This invention relates to a storage device using semiconductor elements. Background Technology

[0002] In recent years, in the development of Large Scale Integration (LSI) technology, memory devices that can be mounted on logic circuits using semiconductor components have been required to be highly integrated, high-performance, low-power-consumption, and highly functional.

[0003] Dynamic Random Access Memory (DRAM) is widely used in integrated circuit memory. To increase DRAM memory density, there are DRAMs (e.g., see Non-Patent Document 1) using an SGT structure extending perpendicularly to the upper surface of the semiconductor substrate (see Non-Patent Document 2) or DRAM memory cells consisting of only a single MOS transistor without capacitors (see Non-Patent Documents 3 to 6). The latter is commonly referred to as "1TDRAM". For example, by using the current between the source and drain of an n-channel MOS transistor, some or all of the holes generated by the impact ionization phenomenon are retained within the channel to write logic data "1". Conversely, the holes are removed from the channel to write logic data "0".

[0004] These methods, for example, utilize the source-drain current of an n-channel MOS transistor formed on an SOI (Silicon On Insulator) to retain some or all of the holes generated by the impact ionization phenomenon within the channel in a floating body, thus enabling the writing of logic data "1" (a state with a lower threshold voltage). Conversely, the holes are removed from the floating body to write logic data "0" (a state with a higher threshold voltage). Initially, "0" writing is achieved by increasing the gate voltage of the cell connected to the character line and then setting the potential of the bit line connected to the drain of the cell to a negative potential (defining the source potential of the cell as 0V). However, in this method, the non-selected character line must be set to a negative potential to reduce the floating body voltage of the non-selected cell to a sufficiently low voltage to prevent holes from being removed from the floating bodies of other elements connected to the same bit line. Therefore, when writing a "1" by raising the bit line potential, the gate voltage seen from the drain becomes a negative value with a large absolute value. This causes holes to flow into the floating body of the "0" data cell due to gate-induced drain leakage current (GIDL), which in turn changes the "0" state cell to the "1" state (bit line interference).

[0005] To address this issue, a method for writing "0" has been proposed, which removes holes from the floating body by increasing the voltage of the plate coupled to the floating body capacitor. For example, a cell called Key Shaped Floating Body Memory (KFBM) is constructed with a structure where a high-silicon pillar is squarely separated by a thin insulating film and covered by plate electrodes (see Patent Document 1, Non-Patent Document 7). When writing "0" data, by setting this plate electrode to a high value, holes can be removed from the floating bodies of all cells within the element array. This "0" writing does not require selectivity, therefore, it is not necessary to set the character line to a negative potential during "0" writing; it can be set to 0V. Therefore, when performing "1" writing, the bit line interference problem, which was originally a problem in the original cell, is significantly improved.

[0006] However, in storage devices using this storage element, the methods for implementing write and rewrite operations remain unclear.

[0007] [Existing Technical Documents]

[0008] [Patent Literature]

[0009] Patent Document 1: US2023 / 0077140A1

[0010] Patent Document 2: US11,823,727B2

[0011] 1: Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka:IEEE Transactionon Electron Devices,Vol.38,No.3,pp.573-578(1991)

[0012] Materials 2: H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J. Kim, YCOh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM Cell with Vertical Pillar Transistor(VPT),” 2011 Proceeding of the European Solid-State Device ResearchConference,(2011)

[0013] Paper 3: T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asano, and K. Sunouchi, “Memory Design Using a One-Transistor Gain Cell on SOI.” IEEEJournal of Solid State Circuits,Vol.37,No.11,pp.1510-1522(2002)

[0014] Paper 4: J. Wan, L. Roger, A. Zaslavsky, and S. Critoloveanu:“A CompactCapacitor-Less High-Speed ​​DRAM Using Field Effect-Controlled ChargeRegeneration,”Electron Device Letters,Vol.35,No.2,pp.179-181(2012)

[0015] Non-patent document 5: T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y.Watanabe,Y.Minami,A.Sakamoto,J.Nishimura,H.Nakajima,M.Morikado,K.Inoh,T.Hamamoto,A.Nitayama: "Floating BodyRAM Technology and its Scalability to 32nm Node and Beyond,” IEEE IEDM (2006).

[0016] Non-patent document 6: E. Yoshida: "A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed ​​EmbeddedMemory," IEEE IEDM (2006).

[0017] Patent document 7: M.Kakumu, Y.Li, K.Sakui, N.Harada, "Fully bulk CMOS compatibleKey Shape Floating Body Memory (KFBM)," Memories-Materials, Devices, Circuits and Systems, 4 (2023) 100061. Summary of the Invention

[0018] [The problem that the invention aims to solve]

[0019] The purpose of this invention is to provide a novel write and rewrite operation, and a circuit and driving method for implementing these operations, so as to realize random access memory.

[0020] [Methods used to solve problems]

[0021] To solve the above problems, the memory device using semiconductor elements of the present invention has a configuration in which board lines are arranged parallel to character lines in a cell belonging to a page selected by the character lines, and the board lines are connected to electrodes formed by capacitive coupling to the floating bodies of the MOSFETs forming the memory cells. Then, after activating the character lines to read and latch the data stored in the memory cell belonging to that page using a sense amplifier, the bit lines are separated from the sense amplifier, and the board lines belonging to that page are activated to remove majority carriers from the floating bodies of the memory cell belonging to that page. Simultaneously, the latch state of the sense amplifier is optionally reversed using data input from the data lines. Then, based on the new latch state of the sense amplifier, the cell belonging to that page is programmed (majority carriers are injected), thereby achieving writing. Alternatively, the same operation can be performed except for the operation of "optionally reversing the latch state of the sense amplifier using data input from the data lines."

[0022] One embodiment of the present invention is a semiconductor memory device, which is constructed on a substrate (14 in FIG. 17 is an example) by means of a first direction in top view ( Figure 1 (Taking the direction of WL as an example) Multiple storage units arranged in an array form a page. Figure 1 (Taking a group of units connected to a shared WL as an example);

[0023] Each of the aforementioned storage units possesses:

[0024] Electrically floating semiconductor substrate (Figure 17, 8 is an example);

[0025] The first impurity region (9 in Figure 17 is an example) is connected to one side of the aforementioned semiconductor substrate and to the source line;

[0026] The second impurity region (19 in Figure 17 is an example) is connected to the other side of the aforementioned semiconductor substrate and to the bit line;

[0027] The gate insulating film (15 in Figure 17 is an example) is in contact with the aforementioned semiconductor substrate;

[0028] The first gate conductor layer (1 in Figure 17 is an example) together with the aforementioned semiconductor substrate, the aforementioned first impurity region, and the aforementioned second impurity region forms a transistor, and is connected to the aforementioned gate insulating film and connected to the character line ( Figure 1 (WL is an example) connected; and

[0029] The second gate conductor layer (3 in Figure 17 is an example) is connected to the aforementioned gate insulating film at a different position than the aforementioned first gate conductor layer and is connected to the plate line ( Figure 1 (PL is one example) connected;

[0030] The aforementioned storage device also has:

[0031] Sensing amplifier circuit ( Figure 4 Taking the current load circuit and latching circuit as an example, the current will be transferred from the first switching circuit ( Figure 4 SW3 j SW4 j SW3 j+1 SW4 j+1 (As an example) The signal read from the aforementioned storage unit connected to the aforementioned bit line is amplified and latched; and

[0032] Data cable ( Figure 4 DQ and / DQ are examples), via the second switching circuit ( Figure 4 SW1 j SW2 j SW1 j+1 SW2 j+1 (e.g., one example) is connected to the aforementioned sensing amplifier circuit;

[0033] During a write operation, the aforementioned character line is activated, and the first switch circuit is turned on for the data stored in the aforementioned memory cell. After the signal is amplified and latched by the aforementioned sensing amplifier circuit, the first switch circuit is turned off, and the aforementioned board line is selected and the aforementioned memory cell is erased. At the same time, the aforementioned second switch circuit is turned on, and data is input from the data line to the aforementioned sensing amplifier circuit, causing the latch state of the aforementioned sensing amplifier circuit to change. Then, based on the latch state of the aforementioned sensing amplifier circuit, the aforementioned memory cell is programmed. Figure 13 (A timing diagram is shown as an example).

[0034] In the aforementioned semiconductor memory devices, a preferred option is...

[0035] Upon reactivation, after activating the aforementioned character lines and turning on the aforementioned first switch circuit to amplify and latch the signal through the aforementioned sensing amplifier circuit, the data stored in the aforementioned memory unit is re-entered.

[0036] The aforementioned first switch circuit is blocked, and the aforementioned board line is selected to erase the aforementioned memory cell.

[0037] Subsequently, the aforementioned memory cell is programmed according to the latch state of the aforementioned sensing amplifier circuit. Figure 13 (A timing diagram is shown as an example).

[0038] In the aforementioned semiconductor memory devices, a preferred option is...

[0039] In a top view, the character line driving circuit is connected to one end of the aforementioned character line extending along the first direction. Figure 16 Taking WL drivers as an example, the row address selection circuit ( Figure 16(Taking the Row decoder as an example) is selectively activated.

[0040] The board line drive circuit connected to one end of the aforementioned board line ( Figure 16 (Taking PL drivers as an example) is located in the opposite direction of the aforementioned character line driver circuit relative to the aforementioned first direction in the memory cell array.

[0041] The aforementioned board line driving circuit is selectively activated through the aforementioned character lines.

[0042] In the aforementioned semiconductor memory devices, a preferred option is...

[0043] The aforementioned sensing amplifier circuit ( Figure 4 (taking S / Aj as an example) has:

[0044] First sensing node ( Figure 4 Taking SNLj as an example), separated by the first switching element ( Figure 4 (taking SW3j as an example) and the first element line ( Figure 4 (BLLj is an example) separation;

[0045] Second sensing node ( Figure 4 Taking SNRj as an example), separated by a second switching element ( Figure 4 SW4 j (as one example) and another second bit line ( Figure 4 (BLRj is an example) separated, the other second bit line is located at the aforementioned first bit line ( Figure 4 (taking BLLj as an example) relative to the aforementioned sensing amplifier ( Figure 4 (S / Aj is an example) The opposite side or adjacent to the aforementioned first element line;

[0046] Current load circuit ( Figure 4 S / A j (The “current load circuit” is an example) Current flows through the first and second sensing nodes and the first and second switching elements mentioned above.

[0047] latch circuit ( Figure 4 S / A j (The "latch circuit" in the text is an example) amplifies and latches the potential difference between the aforementioned first and second sensing nodes;

[0048] First programming circuit ( Figure 4 and BLL j (The connected "programming circuit" is one example), a voltage is applied to the aforementioned first element line;

[0049] Second programming circuit ( Figure 4 With BLR j(The connected "programming circuit" is one example), a voltage is applied to the aforementioned second bit line;

[0050] Third switching element ( Figure 4 SW5 j (As an example), the aforementioned first element line is lowered to the ground potential;

[0051] Fourth switching element ( Figure 4 SW6 j (As an example), the aforementioned second bit line is lowered to ground potential;

[0052] Fifth switching element ( Figure 4 Taking SW1j as an example, the aforementioned first sensing node is connected to one side of the shared data line ( Figure 4 (DQ is one example);

[0053] Sixth switching element ( Figure 4 SW2 j (As an example), the aforementioned second sensing node is connected to the other side of the aforementioned shared data line ( Figure 4 (DQ is an example).

[0054] In the aforementioned semiconductor memory devices, a preferred option is...

[0055] The aforementioned current load circuit is the same as the aforementioned latch circuit. Figure 15 TR20 j To TR28 j The circuit formed is an example.

[0056] In the aforementioned semiconductor memory devices, a preferred option is...

[0057] In addition to the aforementioned sensing amplifier circuit, a second sensing amplifier is provided, which includes:

[0058] Third sensing node ( Figure 4 SNL j+1 For example, separated by the seventh switching element ( Figure 4 SW3 j+1 (as an example) and the third bit line ( Figure 4 BLL j+1 (For example) separation;

[0059] Fourth sensing node ( Figure 4 SNR j+1 As an example, separated by the eighth switching element ( Figure 4 SW4 j+1 (as one example) and another fourth bit line ( Figure 4 BLR j+1 (As an example) Separation, the other fourth bit line ( Figure 4 BLRj+1 (As an example) located in the aforementioned third bit line ( Figure 4 BLL j+1 For example, relative to the aforementioned second sensing amplifier ( Figure 4 S / A j+1 (For example) the opposite side, or adjacent to the aforementioned third bit line;

[0060] Current load circuit ( Figure 4 S / A j+1 (The “current load circuit” is an example) Current flows through the aforementioned third and fourth sensing nodes and the aforementioned seventh and eighth switching elements.

[0061] latch circuit ( Figure 4 S / A j+1 (The "latch circuit" is one example) amplifies and latches the potential difference between the aforementioned third and fourth sensing nodes;

[0062] Third programming circuit ( Figure 4 and BLL j+1 (The connected "programming circuit" is one example) applies a voltage to the aforementioned third bit line;

[0063] Fourth programming circuit ( Figure 4 With BLR j+1 (The connected "programming circuit" is one example) a voltage is applied to the aforementioned fourth bit line;

[0064] Ninth switching element ( Figure 4 SW5 j+1 (As an example), the aforementioned third bit line is lowered to ground potential;

[0065] Tenth switching element ( Figure 4 SW6 j+1 (As an example), the aforementioned fourth bit line is lowered to ground potential;

[0066] Eleventh Switching Element ( Figure 4 SW1 j+1 For example, the aforementioned third sensing node is connected to one side of the aforementioned shared data line. Figure 4 (DQ is one example); and

[0067] The twelfth switching element ( Figure 4 SW2 j+1 For example, the aforementioned fourth sensing node is connected to the other side of the aforementioned shared data line. Figure 4 (DQ is one example);

[0068] The aforementioned first sensing node of the aforementioned sensing amplifier circuit and the aforementioned third sensing node of the aforementioned second sensing amplifier are connected by a thirteenth switching circuit. Figure 4 SW7 j,j+1 (As an example) an electrical short circuit;

[0069] Alternatively, the aforementioned second sensing node of the aforementioned sensing amplifier circuit and the aforementioned fourth sensing node of the aforementioned second sensing amplifier are connected by a fourteenth switching circuit. Figure 4 SW8 j,j+1 (As an example) and electrical short circuit.

[0070] In the aforementioned semiconductor memory devices, a preferred option is...

[0071] The first virtual cell is constructed with the same structure as the aforementioned storage cell. Figure 4 (DCLj is an example) is connected to the aforementioned first bit line and the first dummy character line ( Figure 4 (The DWLL is an example);

[0072] A second virtual unit with the same structure as the aforementioned storage unit is created. Figure 4 (DCRj is an example) is connected to the aforementioned second bit line and the second dummy character line ( Figure 4 (The DWLR is an example);

[0073] A third virtual unit with the same structure as the aforementioned storage unit is created. Figure 4 DCL j+1 (As an example) Connect the aforementioned third bit line and the first dummy character line;

[0074] A fourth virtual unit with the same structure as the aforementioned storage unit is created. Figure 4 DCR j+1 (As an example) Connect the aforementioned fourth bit line and the second dummy character line;

[0075] The state of the first virtual unit is the opposite of that of the third virtual unit;

[0076] The state stored in the aforementioned second virtual unit is the opposite of that in the aforementioned fourth virtual unit.

[0077] In the aforementioned semiconductor memory devices, a preferred option is...

[0078] The aforementioned semiconductor substrate extends vertically in a columnar shape from the surface of the aforementioned substrate and is in an electrically floating state. The first semiconductor region of the first conductivity type (8 in Figure 17 is an example).

[0079] The aforementioned first gate conductor layer is connected to the top surface of the aforementioned first semiconductor region via a gate insulating film (15 in Figure 17 is an example);

[0080] The aforementioned second gate conductor layer (3 in Figure 17 is an example) is connected to the pillar portion of the aforementioned first semiconductor region via the aforementioned gate insulating film;

[0081] The aforementioned first impurity region and the aforementioned second impurity region are connected to the upper side of the aforementioned first semiconductor region and located on both sides of it in the horizontal direction, and are second semiconductor regions of the second conductivity type (9 and 19 in FIG17 are an example).

[0082] An active electrode line is connected to the second semiconductor region corresponding to the first impurity region (9 in Figure 17 is an example) as a first metal wiring layer (4 in Figure 17 is an example). A bit line is connected to the second semiconductor region corresponding to the second impurity region (19 in Figure 17 is an example) as a second metal wiring layer (2 in Figure 17 is an example). A character line is connected to the first gate conductor layer, and a board line is connected to the second gate conductor layer. The characters are separated and wired to be parallel to each character line. Attached Figure Description

[0083] Figure 1 This is an equivalent circuit diagram of a storage device using semiconductor elements according to the first embodiment.

[0084] Figure 2 This is the operating principle of writing (programming) "1" to a storage device using semiconductor elements in the first embodiment.

[0085] Figure 3 This is the operating principle of writing (erasing) "0" in the storage device using semiconductor elements in the first embodiment.

[0086] Figure 4 This is a block diagram of the sense amplifier circuit of the storage device using semiconductor elements according to the first embodiment.

[0087] Figure 5 This is an example of a sense amplifier circuit diagram for a storage device using semiconductor elements according to the first embodiment.

[0088] Figure 6 The attached diagram shows the transistors related to the basic operation of data sensing in the sensing amplifier circuit of the storage device using semiconductor elements according to the first embodiment.

[0089] Figure 7 The attached diagram shows the transistors related to the basic latching operation in the sense amplifier circuit of the memory device using semiconductor elements according to the first embodiment.

[0090] Figure 8 The attached diagram shows the transistors related to the basic programming operations in the sense amplifier circuit of the memory device using semiconductor elements in the first embodiment.

[0091] Figure 9The attached diagram shows the transistors in the sense amplifier circuit of the memory device using semiconductor elements in the first embodiment, emphasizing the basic operation of clearing (erasing).

[0092] Figure 10 The accompanying drawing shows the transistors in the sense amplifier circuit of the memory device using semiconductor elements in the first embodiment, emphasizing the basic operation related to reading from the sense amplifier.

[0093] Figure 11 The attached diagram shows the transistors in the sense amplifier circuit of the memory device using semiconductor elements in the first embodiment, emphasizing their relationship to the basic operation of writing to the sense amplifier.

[0094] Figure 12 This is a drawing illustrating the read operation of a storage device using semiconductor elements according to the first embodiment.

[0095] Figure 13 This is a drawing illustrating the write operation of a storage device using semiconductor elements according to the first embodiment.

[0096] Figure 14 The accompanying drawing illustrates the reoperation of a storage device using semiconductor elements according to the first embodiment.

[0097] Figure 15 This is another example of a sense amplifier circuit diagram for a storage device using semiconductor elements according to the first embodiment.

[0098] Figure 16 The accompanying drawings illustrate the row decoder, character line driving circuit, and board line driving circuit of the storage device using semiconductor elements according to the first embodiment.

[0099] Figure 17A This is a top view of a storage device using semiconductor elements according to a first embodiment.

[0100] Figure 17B It is along Figure 17A A cross-sectional view of the AA' wire cut.

[0101] Figure 17C It is along Figure 17A A cross-sectional view of BB' wire cutting.

[0102] Figure 17D It is along Figure 17A A cross-sectional view of the CC' wire cutting.

[0103] Figure 17E It is along Figure 17A A cross-sectional view of the DD' wire cut.

[0104] Figure 17F It is along Figure 17AA cross-sectional view of the EE' wire cut.

[0105] Figure 18A This is a top view of a storage device using semiconductor elements according to a second embodiment.

[0106] Figure 18B It is along Figure 18A A cross-sectional view of the AA' wire cut.

[0107] Figure 18C It is along Figure 18A A cross-sectional view of BB' wire cutting.

[0108] Figure 18D It is along Figure 18A A cross-sectional view of the CC' wire cutting.

[0109] Figure 18E It is along Figure 18A A cross-sectional view of the DD' wire cut.

[0110] Figure 18F It is along Figure 18A A cross-sectional view of the EE' wire cut.

[0111] Figure 19 This is an equivalent circuit diagram of a storage device using semiconductor elements according to the second embodiment.

[0112] Explanation of reference numerals in the attached figures

[0113] 1. First gate conductor layer (character line)

[0114] 2. Second metal wiring layer (bit line)

[0115] 3. Second gate conductor layer (plate line)

[0116] 4 First metal wiring layer (source line)

[0117] 5. Buffer layer (same as the first metal wiring layer)

[0118] 6. Contact hole (for connecting the silicon layer to the first metal wiring layer)

[0119] 7. Through-hole (for connection between the first and second metal wiring layers)

[0120] 8 First Semiconductor Region

[0121] 9. Second semiconductor region (source line side)

[0122] 10 Third Semiconductor Region

[0123] 11 First Insulation Layer

[0124] 12 Second Insulation Layer

[0125] 13 Third Insulation Layer

[0126] 14 substrate

[0127] 15 Gate insulating film

[0128] 19 Second semiconductor region (bit line side)

[0129] A 0C ~A 9C , / A 0C ~ / A 9C column address

[0130] A 0R ~A 9R , / A 0R ~ / A 9R line address

[0131] BL0~BL 1023 Bitline

[0132] BLL j ,BLL j+1 ,BLR j ,BLR j+1 Bitline

[0133] Cell array

[0134] Column decoder

[0135] CSL drivers column select line drive circuit

[0136] CSL j CSL j+1 Column selection line

[0137] DCL j DCL j+1 DCR j DCR j+1 virtual unit

[0138] MC ij (i = 0 ~ 1023, j = 0 ~ 1023) storage unit

[0139] MCL i,j MCR i,j storage unit

[0140] MCL0 j ,MCL0 j+1 ,MCR0 j ,MCR0 j+1 storage unit

[0141] PL decoder board-line decoder

[0142] PL drivers board-line drive circuit

[0143] Row decoder

[0144] S / A j S / A j+1 Sensing amplifier

[0145] Sense amplifier

[0146] SL source line

[0147] SNL j SNL j+1 SNR j SNR j+1 Sensing Nodes

[0148] SW1 j ~SW6 j Switching circuit

[0149] SW1 j+1 ~SW6 j+1 Switching circuit

[0150] SW7 j,j+1 SW8 j,j+1 Switching circuit

[0151] TR1 j ~TR7 j TR10 j ~TR13 j p-type MOSFET

[0152] TR1 j+1 ~TR7 j+1 TR10 j+1 ~TR13 j+1 p-type MOSFET

[0153] TR8 j TR9 j TR14 j ~TR19 j n-type MOSFET

[0154] TR8 j+1 TR9 j+1 TR14 j+1 ~TR19 j+1 n-type MOSFET

[0155] TR20, TR21 n-type MOSFETs

[0156] TR20 j TR21 j TR24 j p-type MOSFET

[0157] TR20 j+1 TR21 j+1 TR24 j+1 p-type MOSFET

[0158] TR22 j TR23 j TR25 j ~TR28 j n-type MOSFET

[0159] TR22 j+1 TR23 j+1 TR25 j+1 ~TR28 j+1 n-type MOSFET

[0160] WL0~WL 1023 character lines

[0161] WLL i ,WLL i+1 ,WLL i+2 WLR i WLR i+1 WLR i+2 character lines

[0162] WL drivers are character line driver circuits. Detailed Implementation

[0163] The following description, with reference to the accompanying drawings, illustrates a storage device using semiconductor elements according to embodiments of the present invention.

[0164] (First Implementation)

[0165] use Figure 1 The equivalent circuit of the storage cell and sense amplifier of the storage device using semiconductor elements in this embodiment will be explained. Figure 1 This shows the multiple memory cells (MCL) i,j MCL i+1,j MCL i+2,j MCL i,j+1 MCL i+1,j+1 MCL i+2,j+1 MCR i,j MCR i+1,j MCR i+2,j MCR i,j+1 MCRi+1,j+1 MCR i+2,j+1 The row direction of the matrix-like cell array (parallel to the character line group WLL) i or WLR i A sensing amplifier (S / A) is formed on the center part of the direction. j In this embodiment, the memory cell is formed by a well-known n-type MOSFET with an electrically floating body (see Patent Documents 1 and 2). Its source or drain is connected to a bit line BLL. j / BLR j Or source line SL. Additionally, its float is connected to the plate line PLL via electrostatic capacitance. i or PLR i This storage unit is a type of unit that stores data by storing majority carriers in a floating body. When the state with more majority carriers is defined as "1" and the state with fewer majority carriers is defined as "0", the threshold voltage of the storage unit in the "1" state becomes lower than that in the "0" state. When reading under the same voltage conditions, the "1" unit will have more current flowing than the "0" unit, and the data can be identified.

[0166] Here, an example of the structure of the memory cell in this embodiment will be specifically described. The aforementioned memory cell includes: an electrically floating semiconductor substrate; a first impurity region connected to source lines that are connected to both ends of the aforementioned semiconductor substrate; a second impurity region connected to bit lines; a gate insulating film in contact with the aforementioned semiconductor substrate; a first gate conductor layer connected to the aforementioned gate insulating film and connected to character lines; and a second gate conductor layer connected to the aforementioned gate insulating film and connected to board lines. This is an example of a memory cell.

[0167] At Figure 1 In the middle, the sensor amplifier circuit (S / A) will be located in the middle. j The character group on the left of ) is marked as WLL i The character line group on the right is marked WLR i Here, i is a natural number representing the character line number (1≤i≤M). Similarly, the signal located in the sensing amplifier circuit (S / A) will be... j The bit line group to the left of ) is labeled BLL j The bit line group on the right is labeled BLR j Here, j is a natural number representing the bit line number (1≤j≤N). Figure 1 The text only displays six character lines (WLL) – three on the left and three on the right. i WLL i+1 WLL i+2 WLR i WLR i+1 WLR i+2And two on each side, for a total of four bit lines (BLL) j BLL j+1 BLR j BLR j+1 In addition, only six PLL lines, three on each side, were displayed. i PLL i+1 PLL i+2 PLR i PLR i+1 PLR i+2 Here, character lines, source lines, and board lines are all wired in parallel, while bit lines are wired perpendicular to these lines. Furthermore, the j-th sense amplifier circuit S / A... j BLL connected to the j-th left-hand bit line j and the j-th rightmost bit line BLR j Here, the bit line BLL located on the left will be connected. j With character line WLL i WLL i+1 and WLL i+2 The storage cells are respectively labeled as MCL i,j MCL i+1,j and MCL i+2,j Connect the bit line BLL located on the left. j+1 With character line WLL i WLL i+1 WLL i+2 The storage cells are respectively labeled as MCL i,j+1 MCL i+1,j+1 MCL i+2,j+1 Similarly, the bit line BLR located on the right side will be connected. j With character line WLR i WLR i+1 WLR i+2 The storage units are respectively labeled as MCR i,j MCR i+1,j MCR i+2,j Connect to the bit line BLR located on the right. j+1 With character line WLR i WLR i+1 WLR i+2 The storage units are respectively labeled as MCR i,j+1 MCR i+1,j+1 and MCR i+2,j+1 .

[0168] use Figure 2This embodiment describes the write operation of storing holes, which are the majority carriers, in the floating body of the memory cell of a memory device using semiconductor elements. When the MOSFET of the memory cell is saturated by applying a positive voltage to both the character line and the bit line, the area near the drain of the MOSFET (the node connected to the bit line) becomes a pinch-off state. Electrons flowing in the channel are accelerated by a high electric field, and these collide with silicon atoms, thereby generating a large number of electron-hole pairs (collision ionization). Electrons flow into the bit line, while holes flow into the floating body. Thus, holes are stored in the floating body, achieving a state where a large number of holes are stored in the floating body. This state is defined as "1". Similarly, using... Figure 3 The operation of removing holes from the float of the memory cell in the memory device using semiconductor elements of this embodiment will be explained. Starting from a state where both the gate (character line) and drain (bit line) of the MOSFET of the memory cell are set to 0V, the plate line (PL) is raised to a positive potential. Accordingly, a large number of holes stored in the float flow from the p-type silicon float to the n-type silicon layer (source line or bit line, etc.), resulting in a reduction in the number of holes stored in the float. This state is defined as "0". Furthermore, the method for achieving the "1" state and the method described above for achieving the "0" state are only examples; other methods may also be used.

[0169] use Figure 4 First, the configuration of the memory cell array and the sensing amplifier circuit will be explained. The j-th sensing amplifier S / Aj will be described in detail. It includes: a sensing amplifier circuit S / Aj. j (An example of the sensing amplifier circuit in request item 1) has: sensing node pair SNL j SNR j SW3 through the first switching element j SW4 j (An example of the first switching circuit in request item 1) with bit line pair BLL j BLR j (An example of the bit line in request item 1) separation; current load circuit, via the aforementioned sensing node to SNL j SNRj and the first switching element SW3 j SW4 j This allows current to flow through the aforementioned bit line pair BLL j BLR j The latch circuit amplifies and latches the aforementioned sensing node pair SNL. j SNR j The potential difference; programming circuit pair, for the aforementioned bit line pair BLL j BLR j Apply voltage; the second switching element to SW5 j SW6j The aforementioned bit line is paired with BLL j BLR j The voltage drops to ground potential; and the third switching element is connected to SW1. j SW2 j (An example of the second switching circuit in Request 1) connects the aforementioned sensing node pair to a common data line pair (an example of the data line in Request 1); memory cell MCL0 j MCR0 j (An example of a memory cell in request item 1), the drain or source is connected to the aforementioned bit line pair BLL. j BLR j The floating body is composed of a floating metal-insulator-semiconductor field-effect transistor; the board lines PLL0 and PLR0 (an example of the board lines in claim 1) are connected to the aforementioned memory cell MCL0. j MCR0 j The floating capacitor coupling; and the character lines WLL0 and WLR0 (an example of the character lines in request item 1), connected to the aforementioned memory cell MCL0. j MCR0 j The gates are connected; the aforementioned board lines PLL0 and PLR0 are wired in a one-to-one correspondence with the aforementioned character lines WLL0 and WLR0. Although not in Figure 4 As shown, there are M character lines on each side of the sensing amplifier. In addition to these, there is another special character line on each side, for example, closest to the sensing amplifier. However, their location is irrelevant. These dummy character lines, DWLL and DWLR, are input to the gate of special memory cells. These special cells are called dummy cells, DCL. j DCL j+1 DCR j DCR j+1 Each bit line is pre-written with a state of "1" or "0". That is, DCL (Digital Channel Logical Array). j Write a "1", DCL j+1 Writing a "0" or vice versa is fine. Similarly, DCR j Write a "1", DCR j+1 It doesn't matter if you write "0" or the opposite.

[0170] Here, an example of the structure of the memory cell in this embodiment will be specifically described. The aforementioned memory cell includes: an electrically floating semiconductor substrate; a first impurity region connected to source lines at both ends of the aforementioned semiconductor substrate; a second impurity region connected to bit lines; a gate insulating film connected to the aforementioned semiconductor substrate; a first gate conductor layer connected to the aforementioned gate insulating film and connected to character lines; and a second gate conductor layer connected to the aforementioned gate insulating film and connected to board lines. This is an example of a memory cell.

[0171] Next, use Figure 4 The configuration of the sense amplifier circuit of the memory device using semiconductor components in this embodiment is illustrated by a circuit block diagram. Figure 4 In the diagram, the portions enclosed by dashed lines represent the sensing amplifiers S / A. j S / A j+1 Since all components are identical, the sensor amplifier circuit S / A will be explained. j Sensing amplifier circuit S / A j The central section contains a current load circuit and a latching circuit. These are controlled by the Read signal and the LTC signal, respectively. They share the sensing node SNL on the left side. j and the SNR of the sensing node on the right. j The sensing node SNL on the left. j via switching element SW3 j BLL connected to the left side j SNR of the sensing node on the right j via switching element SW4 j BLR connected to the right bit line j These switching elements SW3 j and SW4 j All are controlled via the CLMP signal. The sensing node SNL on the left... j The input is fed to the programming circuit on the left, and the output of the programming circuit on the left is connected to the bit line BLL on the left. j The programming circuit on the left is controlled by the signal PRGL. Similarly, the sensing node SNR on the right... j The input is fed to the programming circuit on the right, and the output of the programming circuit on the right is connected to the bit line BLR on the right. j The programming circuit on the right is controlled by the signal PRGR. The sensing node on the left is SNL. j The switching element SW1 is controlled by the selection line CSLj of the j-th column. j Connect to the DQ side of the shared input / output pair DQ / / DQ. The sensing node SNR on the right... j The switching element SW2j, controlled by the j-th column select line CSLj, is connected to the / DQ side of the common input / output pair DQ, / DQ. The left and right bit lines BLL... j and BLR j Each is controlled by a switching element SW5 controlled by signal PRCH. j and SW6 j Grounded (0V). Additionally, the sensing node SNL to the left of the j-th sensing amplifier circuit S / Aj. j With the (j+1)th sense amplifier circuit S / A j+1Left sensing node SNL j+1 via the switching element SW7 controlled by the signal DCAVL j,j+1 Short circuit. Similarly, the j-th sensing amplifier circuit S / A j SNR of the sensing node on the right j With the (j+1)th sense amplifier circuit S / A j+1 SNR of the sensing node on the right j+1 via the switching element SW8 controlled by the signal DCAVR j,j+1 Short circuit. Additionally, the current load circuit and the latching circuit are... Figure 4 The circuits can be separated into different circuits, but it is also fine to combine them into a single circuit block.

[0172] illustrate Figure 4 The block diagram of the memory cell array and sense amplifier circuit shown represents the standby state. This is the state before any basic operation begins or after any basic operation ends. First, the source lines are always grounded. In standby mode, all character lines and dummy character lines are grounded, and all board lines are set to a negative potential (V). PLH The CLMP signal controls all switching elements SW3. j SW3 j+1 SW4 j SW4 j+1 In the on state (set to a positive voltage V) CLMP The PRCH signal controls all switching elements SW5. j SW5 j+1 SW6 j SW6 j+1 In the ON state, and BLL all bit lines j BLL j+1 BLR j BLR j+1 and all sensing nodes SNL j SNL j+1 SNR j SNR j+1 Grounding. Column Select Line (CSL) j CSL j+1 In the non-selection state, the switching element SW1 j SW1 j+1 SW2 j SW2 j+1The circuit is in the off state. The Read signal keeps the current-load circuit in a state where no load current flows, and the LTC signal deactivates the latch circuit. The left and right programming circuits are respectively set to not output to the left and right bit lines via the PRGL and PRGR signals. Furthermore, the DCAVL and DCAVR signals control SW7 respectively. j,j+1 SW8 j,j+1 It is in the disconnected state. This state is the standby state.

[0173] use Figure 4 This embodiment will explain the basic operation of the storage cell and sense amplifier of the storage device using semiconductor elements.

[0174] First, the basic operation of "data sensing" of the memory cell and sense amplifier of the memory device using semiconductor elements in this embodiment will be explained. Assume that the cell MCL0 is located on the left side of the sense amplifier. j MCL0 j+1 The data stored in (assuming they are in MCL0) j Stored data with "0", in MCL0 j+1 The data (containing "1" data) is sensed by the corresponding sensing amplifiers S / Aj and S / Aj+1, respectively. Operation begins from standby mode. First, the grounding operation of all bit lines is stopped via the PRCH signal, causing the bit lines to float at 0V. Then, the character line WLL0 selected by the address in the left-hand cell array is raised from the ground level to the positive voltage V used for reading. WLR At the same time, the dummy character line DWLR in the cell array on the right is raised from the ground level to the positive voltage V used for reading. WLR Then, the current load circuit is activated via the Read signal, drawing power from the supply voltage V. dd Current flows through the memory cell MCL0 via the bit lines. j MCL0 j+1 and DCR (Dual Unit) j DCR j+1 The current is drawn into the source line SL, which is at the ground level, via the storage cell and the dummy cell. At this time, the sensing node SNR on the right... j With SNR j+1 Through the switching element SW8 j,j+1 Electrical short circuit (by activating the DCAVR signal). Due to the dummy unit DCR. j With DCR j+1 Since data that is opposite to each other is pre-written, this electrical short circuit will cause a short circuit on the right-hand bit line BLR. j With BLR j+1The reference current I is obtained by averaging the read current of the cell storing "1" and the read current of the cell storing "0". ref (If the read currents of units "0" and "1" are recorded as I0 and I1 respectively, then I ref =1 / 2 (I0 and I1)). On the other hand, based on the above assumptions, the left-side bit line BLL j With BLL j+1 Then I0 and I1 flow respectively. In this case, the SNL of the sensing node pair of the sensing amplifier S / Aj j With SNR j SNL j Compared to SNR j Faster to power supply voltage V dd The signal is developed by increasing the voltage in the direction of the direction. Furthermore, the sensing amplifier circuit S / A... j+1 SNL of sensing node pairs j+1 With SNR j+1 , with SNR j+1 Compared to SNL j+1 Faster to power supply voltage V dd The signal is generated by increasing the voltage in the direction of the signal. This is the basic operation of "data sensing" in the memory cell and sensing amplifier of the memory device using semiconductor elements in this embodiment.

[0175] Next, the basic operation of "latching" of the memory cell and sense amplifier in the memory device using semiconductor elements in this embodiment will be explained. The basic "latching" operation begins when the basic "data sensing" operation is completed. When the voltage difference between the sensing nodes of these sense amplifiers develops to a certain level, if the signal CLMP is transferred from V... CLMP The potential drops to ground potential, i.e., it separates from the sensing node pair and bit line of the sensing amplifier. Then, by activating the signal LTC, the sensing node pair is amplified to ground potential and the supply voltage Vdd level and latched. Under the above assumptions, SNL j Latched as power supply voltage V The dd level is latched as the access level, and SNRj is latched as the connection level. Additionally, SNL... j+1 To become the standard for receiving positions, SNR j+1 It is latched at the power supply voltage Vdd level. The above is the basic operation of "latching" of the memory cell and sense amplifier of the memory device using semiconductor elements in this embodiment.

[0176] Next, the basic "erasure" operation of the memory cell and sense amplifier of the memory device using semiconductor elements in this embodiment will be explained. The basic "erasure" operation sets the storage state of all memory cells selected by the character line to "0". That is, it is a basic operation that removes the majority carrier holes from the floating body of the memory cell, reducing the number of holes present there. The basic "erasure" operation begins from the time when the basic "latch" operation is completed or from the standby state. When entering the basic "erasure" operation from the standby state, the signal CLMP is changed from V CLMP The bit level drops to the contact level, separating the sensing node from the bit line of the sensing amplifier. When entering the erase basic operation after the latching basic operation, the CLMP signal has dropped to the contact level. Simultaneously, when the previous cycle is the data sensing basic operation, the PRCH signal is restored to the power supply voltage V. dd This grounds the bit lines. Furthermore, during the basic "data sensing" operation of the previous cycle, the selected character lines are restored to the ground level. However, it is also possible to maintain the positive voltage V used for reading without restoring it. WLR Or set to a positive voltage V for programming. WLW From this state, the board line PLL0 corresponding to the selected character line WLL0 will be moved from V... PLH Rise to a positive potential V PLE Therefore, as follows: Figure 3 As explained, holes are removed from the float of the selected memory cell, making the storage state of these cells "0". This is the basic operation of "erasing" the memory cell and sense amplifier of the memory device using semiconductor elements in this embodiment.

[0177] Next, the basic operation of "programming" the memory cell and sense amplifier of the memory device using semiconductor elements in this embodiment will be explained. The basic operation of "programming" sets the memory cell specified by the sense amplifier to a "1" storage state from all memory cells with a "0" storage state selected by the character line. That is, it is a basic operation that injects majority carrier holes into the floating body of the memory cell, increasing the number of holes present at that location. The basic operation of "programming" begins after the basic operation of "latching" and the basic operation of "erasing" are completed. First, the grounded bit line is set to a floating 0V (the signal PRCH is lowered to the ground level). Simultaneously, the character line is set to a positive voltage V for programming. WLW Next, the cell array side corresponding to the selected character line is activated. Currently, the programming signal PRGL on the left is activated, and the bit line is set to a positive programming voltage V via the programming circuit. BLW However, the programming circuit input has a sensing node with a sensing amplifier that latches the voltage SNL. j SNLj+1 SNR j SNR j+1 Furthermore, the basic operation of "programming" is selectively performed based on this voltage. The above describes the basic operation of "programming" the memory cell and sense amplifier of the memory device using semiconductor elements in this embodiment.

[0178] Next, the basic operation of "reading from the sense amplifier" of the memory cell and sense amplifier of the memory device using semiconductor elements in this embodiment will be explained. The basic operation of "reading from the sense amplifier" begins from the state after the basic operation of "latching" is completed. The column selection line CSL selected by the address is... j From ground level up to power supply voltage V dd Position level. Based on this, the switching element SW1 is... j SW2 j Turn on, and enable the selected sense amplifier circuit S / A j Sensing nodes for SNL j SNR j Connect them to the common input / output pairs DQ and / DQ respectively. Based on this, the selected sense amplifier circuit S / A... j Sensing nodes for SNL j SNR j The latched information is transmitted to the common input / output pair DQ, / DQ, and read to the external circuit. This is the basic operation of "reading from the sense amplifier" of the memory cell and sense amplifier in the memory device using semiconductor elements according to this embodiment.

[0179] Next, the basic operation of "writing to the sense amplifier" for the memory cell and sense amplifier of the memory device using semiconductor elements in this embodiment will be explained. The basic operation of "writing to the sense amplifier" starts from the state after the basic operation of "latching" is completed. The column select line CSL selected by address selection is then used. j From ground level up to power supply voltage V dd Position level. Based on this, the switching element SW1 is... j SW2 j Turn on, and enable the selected sense amplifier circuit S / A j Sensing nodes for SNL j SNR j Connect to the common input / output pairs DQ and / DQ respectively. Meanwhile, via... Figure 4 The undisplayed external write circuitry writes data to the DQ and / DQ inputs via the common input / output lines. This data is written when its polarity differs from the originally latched S / A input. j Sensing nodes for SNL j SNR jWhen the polarities are opposite, the polarity of the sensing node is reversed. Therefore, write data from external circuitry can be reflected on the column select line (CSL). j The selected sense amplifier circuit S / Aj data. The above describes the basic operation of "writing to sense amplifier" for the memory cell and sense amplifier of the memory device using semiconductor elements in this embodiment.

[0180] use Figure 5 This section will describe a more specific circuit configuration of the storage cell and sense amplifier of the storage device using semiconductor elements in this embodiment. Figure 5 In the middle, the sensing amplifier circuit S / A j By TR1 j To TR19 j The sense amplifier circuit S / Aj+1 is composed of 19 MOSFETs and consists of TR1. j+1 To TR19 j+1 It consists of 19 MOSFETs. In addition to these MOSFETs, there is also a TR20, which is a MOSFET used to control the S / A... j The sensing node SNL on the left j With S / A j+1 The sensing node SNL on the left j+1 Electrical short circuit between; and TR21, which belongs to the MOSFET, is used to enable S / A j SNR of the sensing node on the right j With S / A j+1 SNR of the sensing node on the right j+1 An electrical short circuit occurred between them. Figure 5 In the middle, TR1 j To TR5 j Equivalent to Figure 4 S / A j The current load circuit, TR1 j+1 To TR5 j+1 Equivalent to Figure 4 S / A j+1 The current-loaded circuit. Furthermore, in Figure 5 In the middle, the TR6 of the n-type MOSFET j To TR9 j Equivalent to Figure 4 S / A j The latching circuit, the TR6 of the n-type MOSFET j+1 To TR9 j+1 Equivalent to Figure 4 S / A j+1 The latching circuit. Furthermore, in Figure 5 In the middle, the TR10 of the n-type MOSFET j To TR13 j Equivalent to Figure 4 S / A j The programming circuit, the TR10 of the n-type MOSFET j+1 To TR13 j+1 Equivalent to Figure 4 S / A j+1 The programming circuit. Furthermore, in Figure 5 In the middle, the TTR14 of n-type MOSFE j To TR19 j They are respectively equivalent to Figure 4 S / A j Switching element SW3 j SW4 j SW5 j SW6 j SW1 j SW2 j TR14 of n-type MOSFET j+1 To TR19 j+1 They are respectively equivalent to Figure 4 S / A j+1 Switching element SW3 j+1 SW4 j+1 SW5 j+1 SW6 j+1 SW1 j+1 SW2 j+1 .also, Figure 5 The TR20 and TR21 of the n-type MOSFET are respectively equivalent to Figure 4 SW7 j,j+1 SW8 j,j+1 .in addition, Figure 4 The Read signal, used to transmit load current to memory cells and dummy cells, is... Figure 5 The value was changed to / Read to indicate timely activation when the gate of the p-type MOSFET drops to a low bit position to control it. The same change was implemented in PRGL and PRGR. Furthermore, Figure 4 The signal LTC controlling the latch circuit is at Figure 5 The circuit is divided into two types: a p-type cross-coupled MOSFET LTC and an n-type cross-coupled MOSFET / LTC. Furthermore, although the current load circuit is configured with a current mirror connection via a p-type MOSFET, the current mirror connection needs to be reversed depending on which of the left or right sensing nodes the dummy unit is connected to. Therefore, the circuit configuration can be changed via the signals / CML and / CMR.

[0181] use Figures 5 to 11 The basic operation of the storage cell and sense amplifier of the storage device using semiconductor elements in this embodiment will be explained based on a more specific circuit.

[0182] use Figure 5 and Figure 6 This embodiment will explain the basic operation of "data sensing" in the storage cell and sensing amplifier circuit of the storage device using semiconductor elements. Figure 5 In the MOSFET shown, there is a Figure 6 The MOSFETs, marked in black, operate in conjunction with the basic data sensing operations. The state before operation begins is standby. In standby mode, / Read, PRCH, / LTC, / PRGL, / PRGR, DQ, and / DQ all represent the supply voltage (V). dd Level, SNL j SNR j SNL j+1 SNR j+1 BLL j BLR j BLL j+1 BLR j+1 / CML, / CMR, CSL j CSL j+1 DCAVL, DCAVR, WLL0, WLR0, DWLL, and DWLR are all grounding levels; PLL0, PLR0, DPLL, and DPLR are all negative fixed voltage levels VPLH; and CLMP is a positive fixed voltage level V. CLMP The status. Additionally, SL is always the receiving position standard. Figure 5 This explains the basic operation of data sensing. First, the selected character line WLL0 is raised from the ground level to a positive voltage V. WLR Here, it is assumed that the character line within the unit array located to the left of the sensing amplifier has been selected. Accordingly, in Figure 4 Within the range, select two storage units CL j and CL j+1 ( Figure 10 Although not illustrated, all units actually connected to the character line are selected. Meanwhile, the dummy character line DWLR, located to the right of the sensing amplifier, also rises from the ground level to a positive voltage V. WLR Therefore, in Figure 5 Within the range, select two dummy units DCR j and DCR j+1 ( Figure 10 Although not illustrated, this actually involves selecting all dummy units connected to the character lines. The structure of a dummy unit is the same as that of a memory unit. However, unlike a memory unit, a dummy unit is pre-written with a state of "1" or "0". In this embodiment, it is assumed that the j-th bit line BLR... j Connected dummy unit DCR j Write a "1" and the (j+1)th bit line BLRj+1 Connected dummy unit DCR j+1 A "0" is written. In other words, the opposite data is written to each dummy cell. Here, the polarity of "1" and "0" is not critical. After selecting a dummy cell, the DCAVR rises from the ground level to the supply voltage V. dd Level. Based on this, the SNR of the sensing node on the right side of the two adjacent bit lines is adjusted. j With SNR j+1 The MOSFET of TR21 is electrically short-circuited. Therefore, the intermediate current flowing through the cells of "1" and "0" will flow through the inductive node SNR on the right side. j With SNR j+1 In addition, at the same time, Figure 5 As shown, / CML rises from the ground level to the power supply voltage level V. dd Based on this, TR5 j TR5 j+1 The MOSFET will remain in the on state, but TR4 j TR4 j+1 The MOSFET is turned off, and the current mirror circuit becomes the sensing node SNR on the right. j SNR j+1 The input reference current is configured. Then, / Read reads the power supply voltage V. dd The level drops to the ground level, and based on this, the current mirror circuit is adjusted from the power supply voltage V. dd Supply current, and at the sensing node, the SNR is... j With SNL j Between and SNR j+1 With SNL j+1 A voltage signal is generated between them. The above is the basic operation of "data sensing" of the storage cell and sensing amplifier circuit of the storage device using semiconductor elements in this embodiment.

[0183] use Figure 5 and Figure 7 This embodiment will explain the basic operation of "latching" of the storage cell and sense amplifier circuit of the storage device using semiconductor elements. Figure 5 In the MOSFET shown, there is a Figure 7 The MOSFETs, marked in black, operate in association with the basic "latch" operation. The state before the operation begins is the same as the state at the end of the basic "data sensing" operation. That is, it corresponds to the SNR at the sensing node. j With SNL j Between and sensing nodes to SNR j+1 With SNL j+1There is already a voltage signal in between. The basic operation of waiting for these voltage signals to develop to a certain extent before initiating "latching" depends on the constituent elements of the signal. Figure 7 TR6 of the MOSFET in the latch circuit shown in black. j TR7 j TR8 j TR9 j and TR6 j+1 TR7 j+1 TR8 j+1 TR9 j+1 The degree of variation in the threshold voltage during manufacturing. Generally, a sufficiently large voltage signal needs to be developed at the sensing node to allow the latching circuit to correctly perform the basic "latch" operation, relative to the SNR. j With SNL j Between and sensing nodes to SNR j+1 With SNL j+1 After this, the basic "latch" operation begins. At this point, the LTC rises from the ground level to the supply voltage V. dd Level, / LTC from supply voltage V dd The level is lowered to the contact level, thereby enabling the sensing node developed in the basic operation of "data sensing" to achieve SNR. j With SNL j Between and sensing nodes to SNR j+1 With SNL j+1 The signal amplification between the ground level and the power supply voltage V dd The latching occurs between levels. This is the basic operation of "latching" in the memory cell and sense amplifier circuit of the memory device using semiconductor elements in this embodiment.

[0184] use Figure 5 and Figure 8 This embodiment will explain the basic "erasure" operation in the memory cell and sense amplifier circuit of a memory device using semiconductor elements. Figure 5 In the MOSFET shown, Figure 8 The MOSFETs, marked in black, operate in association with the "erase" basic operation. The state prior to the start of this operation is the state at the end of the "latch" basic operation or a standby state. During the "erase" basic operation, the bit lines must be disconnected from the sense amplifier. Therefore, CLMP needs to be switched from V... CLMP The voltage is reduced to the ground level. Additionally, the bit lines need to be set to the ground level, and PRCH needs to be raised to the supply voltage V. dd Position. For example Figure 8 As shown, with the character line lowered to the contact level, the board line PLL0 is moved from V... PLH The negative potential rises to a positive potential V PLEThus from unit CL0 j CL0 j+1 The floating body removes the hole. In this embodiment's description, only the two memory cells MCL0 located in the cell array to the left of the sensing amplifier are mentioned. j MCL0 j+1 However, in practice, holes can be removed simultaneously from the floating bodies of all memory cells along a character line within the cell array to the left of the sensing amplifier. This is the basic "erasure" operation in the memory cell and sensing amplifier circuit of the memory device using semiconductor elements in this embodiment. Furthermore, the basic "erasure" operation assumes that the character line WLL0 has been activated to a high voltage.

[0185] use Figure 5 and Figure 9 This embodiment will explain the basic operation of "programming" in the memory cell and sense amplifier circuit of the memory device using semiconductor elements. Figure 5 In the MOSFET shown, there is a Figure 9 The MOSFETs, marked in black, operate in association with the basic "programming" operation. The state before the operation begins is the state at the end of the basic "latch" operation, which is the state of the sensing node relative to SNR. j With SNL j Between and sensing nodes to SNR j+1 With SNL j+1 The power supply voltage V is latched between them. dd The state of the voltage signal at the ground level, and the point in time when the basic "erase" operation has been completed. In this description, it is assumed that the sensing node SNR... j To establish the grounding level and sense the SNL node j Power supply voltage V dd Similarly, assuming the sensing node SNR j+1 Power supply voltage V dd And sensing node SNL j+1 To establish the connection level. The basic operation of "programming" involves raising the character line WLL0 connected to the memory cell to be programmed to the V level of the character line at the time of programming. WLW The value begins. Furthermore, the latching basic operation must also be continuously performed during this programming basic operation. In this case, the programming signal / PRGL, which selects the cell array side of the character line (the cell array side to the left of the sense amplifier in this description), is drawn from the power supply voltage V. dd The level is lowered to the contact level. Therefore, TR10 is... j and TR10 j+1 The p-type MOSFET is turned on. On the other hand, based on the above assumption, SNL j Power supply voltage V dd Level, SNLj+1 For accurate positioning, therefore TR11 j TR11 is in the disconnected state. j+1 It is in the ON state. Therefore, the bit line BLL... j Through storage unit MCL0 j It is maintained as the receiving standard, in contrast to the bit line BLL. j+1 Rise to power supply voltage V dd Accordingly, memory cell MCL0 j Although no current flows, the memory cell MCL0 j+1 Because the bias voltage is in a saturated state, impact ionization occurs, and holes are stored in the float. Based on this, the memory cell MCL0 can be... j+1 Programming is then performed. Whether or not programming is required depends on the latching state of the sense amplifier. This is the basic operation of "programming" in the memory cell and sense amplifier circuit of the memory device using semiconductor elements in this embodiment. Other methods of programming may also be considered; the method described here is merely one example.

[0186] use Figure 5 and Figure 10 This embodiment will explain the basic operation of "reading from the sense amplifier" in the memory cell and sense amplifier circuit of the memory device using semiconductor elements. Figure 5 In the MOSFET shown, there is a Figure 10 The MOSFETs, marked in black, operate in association with the basic "read from sense amplifier" operation. The state before the operation begins is the same as the state at the end of the basic "latch" operation. That is, at the sense node, the SNR... j With SNL j Between and sensor nodes to SNR j+1 With SNL j+1 The power supply voltage V has been latched between them. dd The state of the voltage signal relative to the ground level. In this description, it is assumed that the sensing node is in sync with the SNR. j To meet the standards, and SNL j Power supply voltage V dd Similarly, assuming the sensing node has a SNR... j+1 Power supply voltage V dd Level, and SNL j+1 For proper positioning. In the basic operation of reading from the sense amplifier, the sense amplifier must be decoupled from the bit line. Therefore, CLMP needs to be read from V CLMP The voltage drops to the contact level. The selected column selection line CSL... j From ground level up to power supply voltage V dd Level, and by making TR18 j TR19j The MOSFET is in the ON state to precharge to the supply voltage V. dd The common data input / output lines for the level are DQ, / DQ and the selected sense amplifier S / A. j Sensing nodes for SNL j SNR j There is an electrical short circuit between them. Therefore, DQ maintains the power supply voltage V. dd Level, but / DQ via TR9 j The MOSFET is powered by the supply voltage V dd The voltage level drops to a lower level. Therefore, a voltage difference is generated between the common data input / output lines DQ and / DQ. This is then transmitted via... Figure 4 and Figure 9 External circuitry, such as the undisplayed secondary sense amplifier, amplifies the signal, thereby storing it in memory cell MCL0. j The data is read from the memory and then sent to the external device. This is the basic operation of "reading from the sense amplifier" in the memory cell and sense amplifier circuit of the memory device using semiconductor components in this embodiment.

[0187] use Figure 5 and Figure 11 This embodiment will explain the basic operation of "writing to the sense amplifier" in the memory cell and sense amplifier circuit of the memory device using semiconductor elements. Figure 5 In the MOSFET shown, there is a Figure 11 The MOSFETs, marked in black, operate in association with the basic operation of writing to the sense amplifier. The state before the operation begins is the state at the end of the basic "latch" operation. That is, at the sense node, the SNR... j With SNL j Between and sensing nodes to SNR j+1 With SNL j+1 The power supply voltage V has been latched between them. dd The voltage signal corresponding to the ground level. In this description, it is assumed that the sensing node is in sync with the SNR. j To meet the standards, and SNL j Power supply voltage V dd Similarly, assuming the sensing node has a SNR... j+1 The power supply voltage Vdd level is set, and SNL is... j+1 For proper grounding. In the basic operation of writing to the sense amplifier, the sense amplifier must be disconnected from the bit line. Therefore, CLMP needs to be applied from V... CLMP The voltage drops to the contact level. The selected column selection line CSL... j From ground level up to power supply voltage V dd Level, and by making TR18 j TR19j The MOSFET is in the ON state, which enables the shared data input / output lines DQ and / DQ to connect with the selected sense amplifier circuit S / A. j Sensing nodes for SNL j SNR j There is an electrical short circuit between them. In this state, if from... Figure 4 or Figure 10 The write circuits not shown in the diagram drive DQ to the ground level and drive / DQ to the power supply voltage V. dd Level, then the sensing amplifier circuit S / A j Internal latch circuit (TR6) j TR7 j TR8 j TR9 j From the sensing node SNR j Latch as access level, SNL j Latched to power supply voltage V dd The level state is inverted into the SNR of the sensing node. j Latched to power supply voltage V dd Level, SNL j The latch is the opposite state to the ground level. Based on this, a basic write operation to the sense amplifier is performed. The above describes the basic "write to sense amplifier" operation in the memory cell and sense amplifier circuit of the semiconductor-based memory device of this embodiment.

[0188] use Figure 12 This embodiment describes the read operation of a memory device using semiconductor elements. This can be implemented by combining several basic operations of the sense amplifier circuit of the memory device using semiconductor elements in this embodiment. The read operation of the memory device using semiconductor elements in this embodiment includes three basic operations of the sense amplifier circuit of the memory device using semiconductor elements in this embodiment: "data sensing," "latching," and "reading from the sense amplifier." First, the basic operation of "data sensing" is initiated, moving from the standby state. Then, the basic operation of "latching" is initiated. While the data is latched, the data is read from the CSL (Content Storage Layer). j The data from the selected sense amplifier S / Aj is read externally via the common data line DQ, / DQ. In other words, data is read externally by reading from the sense amplifier.

[0189] use Figure 13This embodiment describes the write operation of the memory device using semiconductor elements. This can be implemented by combining several basic operations of the sense amplifier circuit of the memory device using semiconductor elements in this embodiment. The read operation of the memory device using semiconductor elements in this embodiment includes five basic operations of the sense amplifier circuit of the memory device using semiconductor elements in this embodiment: "data sensing," "latching," "writing to sense amplifier," "erasing," and "programming." First, the basic operation of "data sensing" is performed, moving from standby state. Then, the basic operation of "latching" is performed. Up to this point, it is the same as the read operation. Next, CLMP is transferred from V... CLMP The sensor is lowered to the contact level, separating it from the bit line. A basic "write to sensor" operation is performed on the sensor amplifier side, simultaneously erasing holes stored in the floats of all memory cells connected to the selected character line. In other words, an "erase" operation is performed. Afterwards, with both separated, a "program" operation is performed on the memory cell based on the data written to the sensor amplifier. Furthermore, during the "erase" operation, the character line activated during the "data sensing" operation maintains the voltage V during the "data sensing" operation. WLR It can also be set as the voltage V in the basic operations of subsequent "programming". WLW Either of them.

[0190] use Figure 14 This embodiment describes the restart operation of a memory device using semiconductor elements. This can be achieved by incorporating several basic operations of the sense amplifier circuit of the memory device using semiconductor elements in this embodiment. The restart operation of the memory device using semiconductor elements in this embodiment includes four basic operations of the sense amplifier circuit of the memory device using semiconductor elements in this embodiment: "data sensing," "latching," "erasing," and "programming." First, the basic operation of "data sensing" is entered from standby state. Then, the basic operation of "latching" is entered. Up to this point, it is the same as the read operation. Next, CLMP is transferred from V... CLMP The sensor amplifier is de-energized and disconnected from the bit line. Holes stored in the floats of all memory cells connected to the selected character line are erased (the basic operation of "erasing"). Then, with both separated, the basic operation of "programming" is performed on the memory cells based on the data latched in the sensor amplifier. The reprogramming operation of the semiconductor-based memory device in this embodiment is the same as the write operation of the semiconductor-based memory device in this embodiment, except that it lacks the basic operation of "writing to the sensor amplifier" in the sensor amplifier circuit of the semiconductor-based memory device of this embodiment.

[0191] use Figure 15 To illustrate a more specific circuit configuration of the storage cell and sense amplifier of the storage device using semiconductor elements in this embodiment, we will now describe another specific embodiment. This is equivalent to... Figure 4 This is a specific example of a sense amplifier that combines the current load circuit block and the latch circuit block. When / Read is lowered to the contact level, current begins to flow through the memory cell and the dummy cell. At this time, the signal / Release is still at the power supply voltage V. dd Level, Sensing Node SNL j SNR j SNL j+1 SNR j+1 Both stabilize at the same level (0V and V). dd (between). Then, when / Release is lowered to the contact level, positive feedback is generated between the cross-coupled inverters, at the sensing node to SNL. j SNR j and SNL j+1 SNR j+1 A potential difference is developed and latched between them. Other basic operations such as "erase," "program," "read from sense amplifier," and "write to sense amplifier" are also supported. Figure 4 Same as shown.

[0192] use Figure 16 This embodiment describes a board line PL driver circuit for a 1 Mbit (1024 × 1024 bit) memory device using semiconductor elements. The PL activated during data erasure is the board line PL belonging to the selected character line WL. Therefore, it can be driven by the same row decoder as the character line WL driver circuit. However, this row decoder is the same circuit as the row decoder selected for character line WL driving, resulting in wasted circuit area. Therefore, as... Figure 16 As shown, by utilizing the character line WL itself as a selection signal, circuit repetition can be avoided. That is, as... Figure 16 As shown, a more streamlined storage device can be provided by driving the board line PL using the logic AND of the signal PDRV, which specifies the timing of boosting the board line PL when the character line WL is erased with specified data. Of course, the voltage of the character line and the board line are usually different, so a voltage conversion circuit is needed between the character line input and the board line PL drive circuit. Figure 16 The text is omitted. Furthermore, in... Figure 16 The dummy character lines, the dummy units connected to them, the selection circuits and drive circuits of the dummy character lines, and the board lines of the dummy units and their selection circuits and drive circuits are omitted.

[0193] use Figures 17A to 17FThis embodiment will explain the device structure of the memory cell of the memory device using semiconductor elements. Figure 17A This is a top view showing the cell structure of the memory device using semiconductor elements according to this embodiment. The figure shows a region of six memory cells corresponding to three character lines and two bit lines in a cell array where the memory cells are arranged in a matrix. These correspond to... Figure 1 The array on the left or right side of the sensing amplifier in the image shows six memory cells with equivalent circuitry. Figure 17B It means in Figure 17A A cross-sectional view taken from above, cut along line segment AA'. Figure 17C It means in Figure 17A A cross-sectional view taken from above, cut along line segment BB'. Figure 17D It means in Figure 17A A cross-sectional view taken from above, cut along line segment CC'. Figure 17E It means in Figure 17A A cross-sectional view cut along line segment DD' from a top view. Figure 17F It means in Figure 17A A cross-sectional view cut along line segment EE' from a top view.

[0194] Depend on Figure 17A , Figure 17B and Figure 17E It is understood that the first semiconductor region 8 (an example of the semiconductor substrate in the claim) corresponding to each memory cell is arranged in a two-dimensional array on the second semiconductor region 10, which is composed of n-type silicon located on the p-type silane plate 14 (an example of the substrate in the claim) and above it. The first semiconductor region 8 is ion-implanted with impurity atoms (e.g., boron atoms) to become p-type silicon. Furthermore, n-type first impurity regions 9 (an example of one of the n-type second impurity regions in the claim) and 19 (an example of the other n-type second impurity region in the claim) are connected to the upper part of the first semiconductor region 8. Figure 1 They are arranged on both sides of the first semiconductor region 8 in the left-right direction. If it is to be an n-type silicon, it can be achieved by ion implantation of phosphorus atoms.

[0195] Depend on Figures 17A to 17F It can be seen that the second gate conductor layer (plate line) 3 is along... Figure 17A The semiconductor regions 8 are arranged in a vertical direction and separated by a thin gate insulating film 15 (the gate insulating film in the claim is an example). The region from below the top surface of the n-type first impurity region 9 to above the n-type second semiconductor region 10 is filled with the first insulating layer 11, except for the first semiconductor region 8, the second gate conductor layer (plate line) 3 and the gate insulating film 15 between them.

[0196] Depend on Figure 17A and Figure 17BIt can be seen that, in the upper part of the first semiconductor region 8, the first gate conductor layer (character line) 1 is separated from the gate insulating film 15 along... Figure 17A The components are arranged vertically to form an n-type metal oxide semiconductor field-effect transistor (MOSFET), with n-type first impurity regions 9 and 19 as the source or drain, a first semiconductor region 8 as the float, and a first gate conductor layer as the gate. As described above, the gate insulating film 15 is disposed on the upper part (top surface) of the first semiconductor region 8 and functions to electrically insulate the upper part of the first semiconductor region 8 from the first gate conductor layer (character line) 1. It is also disposed to cover the side surface of the first semiconductor region 8 and functions to electrically insulate the second gate conductor layer (plate line) 3 from the first semiconductor region 8. These gate insulating films 15 can be continuously and integrally disposed on the side surface and the upper part (top surface) of the first semiconductor region 8, or they can be disposed separately. One of the source or drain is connected to the first metal wiring layer (source line) 4 through the contact hole 6, and the first metal wiring layer (source line) 4 is along... Figure 17A The source or drain is arranged vertically. On the other hand, the other side of the source or drain is connected to the second metal wiring layer (bit line) via contact hole 6, a buffer layer 5 formed in the same layer as the first metal wiring layer, and via 7. The second metal wiring layer (bit line) is arranged vertically. Figure 17A The wiring is arranged in a left-right direction. The area below the top surface of the second metal wiring layer (bit line) and above the top surface of the n-type first impurity regions 9 and 19, excluding the first gate conductor layer (character line) 1 and the gate insulating film 15, contact hole 6, first metal wiring layer (source line), buffer layer 5, via 7, and second metal wiring layer (bit line) located below it, is filled by the second insulating layer 12. Furthermore, the area above the top surface of the second metal wiring layer (bit line) is covered by the third insulating layer 13.

[0197] The first embodiment of the present invention has the following features.

[0198] (Feature 1)

[0199] like Figure 4 As described, the first embodiment of the present invention uses a semiconductor element-based memory device, which separates the board lines according to each character line and arranges them parallel to the character lines, enabling the removal of holes from the floats of all memory cells along the selected character lines. Although it is a non-selective erase operation, the memory device of this embodiment can still perform random write and rewrite operations. The advantage of this non-selective erase is that it does not require setting the character lines to a negative potential. That is, it can alleviate the problem of "1" interference on the bit lines, thereby improving the data retention characteristics of the cells.

[0200] (Feature 2)

[0201] like Figure 4As explained, when the sense amplifier and bit line are separated, the basic operation of clearing the memory cell and the basic operation of writing to the sense amplifier can be performed simultaneously, thus shortening the cycle time of the write operation.

[0202] (Feature 3)

[0203] like Figure 16 As explained, in the memory device using semiconductor elements according to the first embodiment of the present invention, the board line driving circuit can be configured on the opposite side of the character line driving circuit relative to the cell array. Accordingly, a semiconductor memory device with a smaller chip area can be realized.

[0204] (Second Implementation)

[0205] use Figures 18A to 18F and Figure 19 The structure of the storage device using semiconductor elements in this embodiment will be explained. Figure 18A This is a top view showing the cell structure of the memory device using semiconductor elements in this embodiment. Figure 18B It means in Figure 18A From an overhead view along Figure 18A A cross-sectional view of the AA' line segment. Figure 18C It means in Figure 18A A cross-sectional view taken from above, cut along line segment BB'. Figure 18D It means in Figure 18A A cross-sectional view taken from above, cut along line segment CC'. Figure 18E It means in Figure 18A A cross-sectional view cut along line segment DD' from a top view. Figure 18F It means in Figure 18A A top-down view of a cross-section cut along line segment EE'. Figure 19 This represents the equivalent circuit of the cell array of the memory device using semiconductor elements in this embodiment.

[0206] Figures 18A to 18F The cell structure of the memory device using semiconductor elements shown in this embodiment is the same as that of the memory device using semiconductor elements in the first embodiment, except for the structure of the second gate conductor layer (plate line) 3. Figures 17A to 17F In the cell structure of the memory device using semiconductor elements shown in the first embodiment, although the second gate conductor layer (plate line) 3 is arranged separately for each first gate conductor layer (character line) 1, Figures 18A to 18FIn the cell structure of the memory device using semiconductor elements shown in this embodiment, the second gate conductor layer (plate line) 3 is arranged separately for each adjacent two first gate conductor layers (character lines) 1. Apart from this difference, the cell structure of the memory device using semiconductor elements in this embodiment is the same as that in the memory device using semiconductor elements in the first embodiment.

[0207] Figure 19 This embodiment shows the equivalent circuit of the cell array of a memory device using semiconductor elements and its relationship to a sense amplifier. Figure 19 In the middle, at the two adjacent bit lines BL j and BL j+1 Each of them is equipped with a sensing amplifier S / AL at both ends. j S / AR j S / AL j+1 and S / AR j+1 Furthermore, a dummy bit line DBLL is positioned to the left of the sensing amplifier on the left side. j DBLL j+1 And in these connections there are dummy cells DCL selected by the dummy character line DWLL and driven by the dummy board line DPLL. j DCL j+1 Similarly, a dummy bit line DBLR is configured to the right of the sensing amplifier on the right side. j DBLR j+1 And in these connections there are dummy units DCR selected by the dummy character line DWLR and driven by the dummy board line DPLR. j DCR j+1 The sensing amplifier circuit itself and Figure 4 or Figure 5 The same as shown. However, TR4 j TR5 j TR4 j+1 TR5 j+1 No longer needed, and TR2 j With TR3 j or TR2 j+1 With TR3 j+1 The common gate node is directly connected to SNL j SNR j SNL j+1 or SNR j+1 Specifically, the sensing amplifier on the left is connected to the SNL, and the sensing amplifier on the right is connected to the SNR. Furthermore, Figure 5 Only one of the transistors TR20 and TR21 shown is required. Specifically, the sense amplifier on the left does not require TR21, and the sense amplifier on the right does not require TR20.

[0208] The basic operations of data sensing and latching for each sensing amplifier are described below. Assuming an odd-numbered character line is selected, then the left-hand sensing amplifier S / AL... j and S / AL j+1 Data sensing and latching of the data from the unit connected to the character line are performed. At this time, DWLL is activated, reading data from the dummy unit DCL. j and DCL j+1 Data. Dummy unit DCL j With DCL j+1 The data stored in it becomes the opposite of each other, through Figure 19 The undisplayed transistor will S / AL j and S / AL j+1 The sensing nodes on the left are electrically short-circuited, thereby causing a current flowing through these nodes that is precisely between the current flowing through the "1" data cell and the current flowing through the "0" memory cell. Referring to these currents, the data of the memory cell selected by the odd-numbered character line is sensed. Subsequently, the even-numbered character line sharing the source line with the selected character line is activated, and the data stored in the cell connected to it is sensed by the sensing amplifier S / AR on the right. j and S / AR j+1 Data sensing and latching are performed. At this time, the DWLR is activated, reading from the dummy unit DCR. j and DCR j+1 Data. Dummy unit DCR j With DCR j+1 The data stored therein becomes the opposite of each other, through Figure 19 The undisplayed transistors will S / AR j and S / AR j+1 The sensing nodes on the right are electrically short-circuited, thereby causing a current to flow through these nodes that is exactly between the current flowing through the "1" data cell and the current flowing through the "0" data cell. The data of the memory cell selected by the even-numbered character line is sensed in reference to these currents. Therefore, when the even-numbered character line is selected, the same operation is performed in reverse order as described above.

[0209] The basic programming operation starts the odd-numbered character line, based on the sense amplifier S / AL latched on the left. j and S / AL j+1 The state is programmed. Then, the even-numbered character line is activated, based on the sense amplifier S / AR latched on the right. j and S / AR j+1 Programming based on the state.

[0210] The basic operation of clearing (erasing) will raise the board line, which is configured to be shared by the odd-numbered and even-numbered character lines mentioned above, to a positive voltage V. PLE Holes are removed from the floating bodies of all memory cells selected by these two character lines.

[0211] Read from the sense amplifier via the active column selection line CSL j or CSL j+1 Therefore, S / AL is selected. j with S / AR j or S / AL j+1 with S / AR j+1 Then, depending on whether the WL selected by the address is the odd-numbered or even-numbered one, from S / AL j with S / AR j or S / AL j+1 with S / AR j+1 The sense amplifier reads data to the common data line pair DQ, / DQ.

[0212] The write to the sense amplifier is performed via the activated column select line CSL. j or CSL j+1 Therefore, S / AL is selected. j with S / AR j or S / AL j+1 with S / AR j+1 Then, depending on whether the WL selected by the address is the odd-numbered or even-numbered one, the data is transferred from the shared data line pair DQ, / DQ to S / AL. j with S / AR j or S / AL j+1 with S / AR j+1 The sensing amplifier writes data.

[0213] The read, write, and rewrite operations of the storage device using semiconductor elements in this embodiment are performed in the same way as the basic operations, so detailed descriptions are omitted here.

[0214] exist Figures 18A to 18F and Figure 19 In this context, although the two memory cells of the board line (PL) are shared relative to the shared source line SL, it is also acceptable to share the two memory cells of the board line (PL) relative to the shared bit line BL.

[0215] The second embodiment of the present invention has the following features.

[0216] (Feature 1)

[0217] The second embodiment of the memory device using semiconductor elements of the present invention separates the board lines into two character lines and arranges them parallel to the character lines, enabling the removal of holes from the floats of all memory cells along the selected character line and its adjacent character lines. Accordingly, read operations, write operations, and rewrite operations can be performed. By employing this structure, the memory device using semiconductor elements of the second embodiment of the present invention provides a narrower distance between two memory cells along a bit line compared to the first embodiment, thereby enabling a semiconductor memory device with further reduced bit costs.

[0218] (Feature 2)

[0219] The second embodiment of the present invention uses a semiconductor element-based memory device where the relative positions of the dummy cells and the sensing node pair are predetermined. Therefore, it is unnecessary to switch the transistors connected to the current mirror of the sensing amplifier. Furthermore, in the circuit that averages the cell current to generate the reference current, the dummy cell side is also fixed relative to the sensing amplifier, thus eliminating the need for an averaging circuit on one side. As a result, the size of the sensing amplifier circuit can be smaller than that of the first embodiment, and a semiconductor memory device that further reduces bit costs can be provided.

[0220] [Potential for Industrial Applications]

[0221] According to the present invention, a more well-known semiconductor memory device with higher density, higher speed and higher operating margin can be provided.

Claims

1. A semiconductor memory device comprising: Multiple memory cells, a sense amplifier circuit, and data lines; among which, The aforementioned multiple storage cells are arranged along a first direction on a substrate to form a page when viewed from above; Each of the aforementioned storage units possesses: Electrically floating semiconductor substrate; The first impurity region is connected to one side of the aforementioned semiconductor substrate and to the source line; The second impurity region is connected to the other side of the aforementioned semiconductor substrate and to the bit line; The gate insulating film is in contact with the aforementioned semiconductor substrate; A first gate conductor layer, together with the aforementioned semiconductor substrate, the aforementioned first impurity region, and the aforementioned second impurity region, forms a transistor, and is connected to the aforementioned gate insulating film and to the character line; and The second gate conductor layer is connected to the gate insulating film and the board line at a different position than the first gate conductor layer. The aforementioned sensing amplifier circuit amplifies and latches the signal read from the aforementioned storage unit connected to the aforementioned bit line via the first switching circuit; The aforementioned data line is connected to the aforementioned sensing amplifier circuit via a second switching circuit; During writing, the aforementioned character line is activated, turning on the aforementioned first switch circuit. This amplifies and latches the data stored in the aforementioned memory cell using the aforementioned sensing amplifier circuit. Then, the aforementioned first switch circuit is blocked, and the aforementioned board line is selected to erase the aforementioned memory cell. Simultaneously, the aforementioned second switch circuit is turned on to input data from the data line to the aforementioned sensing amplifier circuit, causing the latch state of the aforementioned sensing amplifier circuit to change. Afterward, the aforementioned memory cell is programmed according to the latch state of the aforementioned sensing amplifier circuit.

2. The semiconductor memory device according to claim 1, wherein, Upon reactivation, after activating the aforementioned character line and turning on the aforementioned first switch circuit to amplify and latch the signal through the aforementioned sensing amplifier circuit, the data stored in the aforementioned memory unit is then processed. The aforementioned first switch circuit is blocked, and the aforementioned board line is selected to erase the aforementioned memory cell. Then, the aforementioned memory cell is programmed according to the latching state of the aforementioned sensing amplifier circuit.

3. The semiconductor memory device according to claim 1, wherein, In a top view, the character line driving circuit connected to one end of the aforementioned character line extending along the first direction is selectively activated by the row address selection circuit. The board line driving circuit connected to one end of the aforementioned board line is located in the opposite direction of the aforementioned character line driving circuit in the memory cell array in the aforementioned first direction. The aforementioned board line driving circuit is selectively activated through the aforementioned character lines.

4. The semiconductor memory device according to claim 1, wherein, The aforementioned sensing amplifier circuit has: The first sensing node is separated from the first element line by the first switching element; The second sensing node is separated from another second bit line by a second switching element. This other second bit line is located on the opposite side of the aforementioned first bit line relative to the aforementioned sensing amplifier, or adjacent to the aforementioned first bit line. The current load circuit allows current to flow through the first and second bit lines via the first and second sensing nodes and the first and second switching elements. The latching circuit amplifies and latches the potential difference between the aforementioned first and second sensing nodes; The first programming circuit applies a voltage to the aforementioned first bit line; The second programming circuit applies a voltage to the aforementioned second bit line; The third switching element lowers the aforementioned first element line to ground potential; The fourth switching element lowers the aforementioned second bit line to ground potential; The fifth switching element connects the aforementioned first sensing node to one side of the shared data line; as well as The sixth switching element connects the aforementioned second sensing node to the other side of the aforementioned shared data line.

5. The semiconductor memory device according to claim 4, wherein, The aforementioned current load circuit and the aforementioned latch circuit are the same circuit.

6. The semiconductor memory device according to claim 4, in addition to the aforementioned sensing amplifier circuit, further comprising a second sensing amplifier, the second sensing amplifier comprising: The third sensing node is separated from the third bit line by the seventh switching element; The fourth sensing node is separated from another fourth bit line by the eighth switching element. This other fourth bit line is located on the opposite side of the aforementioned third bit line relative to the aforementioned second sensing amplifier, or adjacent to the aforementioned third bit line. The current load circuit allows current to flow through the aforementioned third and fourth bit lines via the aforementioned third and fourth sensing nodes and the aforementioned seventh and eighth switching elements; The latching circuit amplifies and latches the potential difference between the aforementioned third and fourth sensing nodes; The third programming circuit applies a voltage to the aforementioned third bit line; The fourth programming circuit applies a voltage to the aforementioned fourth bit line; The ninth switching element lowers the aforementioned third bit line to ground potential; The tenth switching element lowers the aforementioned fourth bit line to ground potential; The eleventh switching element connects the aforementioned third sensing node to one side of the aforementioned shared data line; and The twelfth switching element connects the aforementioned fourth sensing node to the other side of the aforementioned shared data line; The aforementioned first sensing node of the aforementioned sensing amplifier circuit and the aforementioned third sensing node of the aforementioned second sensing amplifier are electrically short-circuited through the thirteenth switching circuit. Alternatively, the aforementioned second sensing node of the aforementioned sensing amplifier circuit and the aforementioned fourth sensing node of the aforementioned second sensing amplifier are electrically short-circuited through the fourteenth switching circuit.

7. The semiconductor memory device according to claim 6, wherein, A first dummy unit with the same structure as the aforementioned storage unit is connected to the aforementioned first bit line and the first dummy character line; A second dummy unit with the same structure as the aforementioned storage unit is connected to the aforementioned second bit line and second dummy character line; A third dummy unit with the same structure as the aforementioned storage unit is connected to the aforementioned third bit line and the first dummy character line; A fourth dummy unit, which has the same structure as the aforementioned storage unit, is connected to the aforementioned fourth bit line and the second dummy character line; The state stored in the aforementioned first virtual unit is the opposite of that in the aforementioned third virtual unit; The state stored in the aforementioned second virtual unit is the opposite of that in the aforementioned fourth virtual unit.

8. The semiconductor memory device according to claim 1, wherein, The aforementioned semiconductor substrate is a first semiconductor region of a first conductivity type that extends vertically in a columnar shape from the surface of the aforementioned substrate and is in an electrically floating state. The aforementioned first gate conductor layer is connected to the top surface of the aforementioned first semiconductor region through a gate insulating film; The aforementioned second gate conductor layer is connected to the pillar portion of the aforementioned first semiconductor region via the aforementioned gate insulating film; The aforementioned first impurity region and the aforementioned second impurity region are second semiconductor regions of the second conductivity type that are connected to the upper side of the aforementioned first semiconductor region and located on both sides of it in the horizontal direction. The aforementioned second semiconductor region corresponding to the aforementioned first impurity region is connected to an active electrode line as a first metal wiring layer. The aforementioned second semiconductor region corresponding to the aforementioned second impurity region is connected to a bit line as a second metal wiring layer. The aforementioned first gate conductor layer is connected to a character line. The aforementioned second gate conductor layer is connected to a board line. The aforementioned character lines are separated and wired to be parallel to the aforementioned character lines.

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