Semiconductor structure, forming method, semiconductor device and storage system

Abstract

The invention provides a semiconductor structure, a method for forming the semiconductor structure, a semiconductor device and a storage system, and relates to the technical field of semiconductors. The semiconductor structure comprises a first stacking structure and a second stacking structure, wherein the first stacking structure comprises conductive layers and first dielectric layers which are alternately stacked along a first direction; comprising second dielectric layers and first dielectric layers which are alternately stacked in the first direction; the blocking structure is arranged between the first stacking structure and the second stacking structure in the first direction and extends in the second direction perpendicular to the first direction; the at least two rows of contact structures at least partially penetrate through the second stacking structure in the first direction, and the at least two rows of contact structures are arranged in the second direction; the connecting structure penetrates through the barrier structure in the third direction, the connecting structure is connected with the contact structure and the corresponding conductive layer in the first stacking structure, and the third direction is perpendicular to the first direction and the second direction. The semiconductor structure reduces the area of the region of the second stack structure for setting the contact structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for forming a semiconductor structure, a semiconductor device, and a memory system. Background Technology

[0002] With the development of semiconductor technology, the feature size of semiconductor devices is shrinking and the integration density is increasing. The process and manufacturing technology of planar memory cells have become challenging and costly, leading to the emergence of three-dimensional semiconductor structures. Three-dimensional semiconductor structures stack memory cells in a three-dimensional manner, which can multiply the integration density on a unit area of ​​wafer and reduce costs.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor structure, a method for forming a semiconductor structure, a semiconductor device, and a memory system.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a first stacked structure including a conductive layer and a first dielectric layer alternately stacked along a first direction; a second stacked structure including a second dielectric layer and a first dielectric layer alternately stacked along the first direction; a barrier structure disposed between the first stacked structure and the second stacked structure along the first direction, the barrier structure extending along a second direction perpendicular to the first direction; at least two rows of contact structures, the contact structures at least partially penetrating the second stacked structure along the first direction, the at least two rows of contact structures being arranged along the second direction; and a connecting structure penetrating the barrier structure along a third direction, the connecting structure connecting the contact structures to corresponding conductive layers in the first stacked structure, the third direction being perpendicular to both the first direction and the second direction.

[0007] According to one embodiment of this disclosure, the at least two rows of contact structures are staggered in the third direction.

[0008] According to one embodiment of the present disclosure, the semiconductor structure includes a stacked structure, the stacked structure being divided into a plurality of memory blocks along the third direction, the memory blocks including a first stacked structure, a second stacked structure, the barrier structure, the at least two rows of contact structures, and the connection structure.

[0009] According to one embodiment of the present disclosure, the plurality of memory blocks include a first memory block and a second memory block adjacent thereto; the semiconductor structure further includes a first gate line slot structure that at least partially penetrates the stacked structure along the first direction, the first gate line slot structure being disposed between the first memory block and the second memory block and extending along the second direction to isolate the first memory block and the second memory block.

[0010] According to one embodiment of this disclosure, the plurality of memory blocks further includes a third memory block adjacent to the first memory block, the second stacking structure of the third memory block being connected to a layer corresponding to the second stacking structure of the first memory block; the barrier structure is a first barrier structure; the semiconductor structure further includes a second gate line gap structure and a second barrier structure that at least partially penetrate the stacking structure along the first direction, the first gate line gap structure and the second barrier structure being disposed between the first memory block and the third memory block and extending along the second direction to isolate the first stacking structure of the first memory block and the first stacking structure of the third memory block.

[0011] According to one embodiment of the present disclosure, the contact structure includes a first portion and a second portion connected together, the first portion of the contact structure extending at least through a portion of the second stacked structure along the first direction, and the second portion of the contact structure extending along the third direction to connect with the connection structure.

[0012] According to one embodiment of the present disclosure, the semiconductor structure further includes a first channel structure and a second channel structure that at least partially penetrate the first stacked structure along the first direction, wherein: the conductive layer of the portion of the first channel structure in the first stacked structure is correspondingly connected to the conductive layer of the portion of the second channel structure, and the connection structure connects the contact structure to the corresponding conductive layer of the portion of the second channel structure in the first stacked structure.

[0013] According to another aspect of this disclosure, a semiconductor structure is provided, comprising: a first stacked structure including a conductive layer and a first dielectric layer alternately stacked along a first direction; a second stacked structure including a second dielectric layer and a first dielectric layer alternately stacked along the first direction; at least one row of contact structures, the contact structures at least partially penetrating the second stacked structure along the first direction, the at least one row of contact structures being arranged along a second direction perpendicular to the first direction; a barrier structure disposed between the first stacked structure and the second stacked structure along the first direction, the barrier structure being at least located on both sides of the at least one row of contact structures along a third direction and extending along the second direction, the third direction being perpendicular to both the first direction and the second direction; and a connection structure penetrating the barrier structure along the third direction, the connection structure connecting the contact structures to corresponding conductive layers in the first stacked structure.

[0014] According to one embodiment of this disclosure, the at least one row of contact structures is aligned and arranged along the second direction.

[0015] According to one embodiment of this disclosure, the at least one row of contact structures is arranged in a serpentine pattern along the second direction.

[0016] According to one embodiment of the present disclosure, the semiconductor structure includes a stacked structure, the stacked structure being divided into a plurality of memory blocks along the third direction, the memory blocks including a first stacked structure, a second stacked structure, the at least one row of contact structures, the barrier structure, and the connection structure.

[0017] According to one embodiment of the present disclosure, the plurality of memory blocks include a first memory block and a second memory block adjacent thereto; the semiconductor structure further includes a gate line slot structure that at least partially penetrates the stacked structure along the first direction, the gate line slot structure being disposed between the first memory block and the second memory block and extending along the second direction to isolate the first memory block and the second memory block.

[0018] According to one embodiment of the present disclosure, the contact structure includes a first portion and a second portion connected together, the first portion of the contact structure extending at least through a portion of the second stacked structure along the first direction, and the second portion of the contact structure extending along the third direction to connect with the connection structure.

[0019] According to one embodiment of the present disclosure, the semiconductor structure further includes a first channel structure and a second channel structure that at least partially penetrate the first stacked structure along the first direction, wherein: the conductive layer of the portion of the first channel structure in the first stacked structure is correspondingly connected to the conductive layer of the portion of the second channel structure, and the connection structure connects the contact structure to the corresponding conductive layer of the portion of the second channel structure in the first stacked structure.

[0020] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a stacked structure, the stacked structure including a first stacked structure comprising a conductive layer and a first dielectric layer alternately stacked along a first direction and a second stacked structure comprising a second dielectric layer and a first dielectric layer alternately stacked along the first direction; forming a barrier structure extending between the first stacked structure and the second stacked structure along the first direction and a second direction, the second direction being perpendicular to the first direction; forming at least two rows of contact structures that at least partially penetrate the second stacked structure along the first direction and a connection structure that penetrates the barrier structure along a third direction and connects the contact structures to corresponding conductive layers in the first stacked structure, the at least two rows of contact structures being arranged along the second direction, the third direction being perpendicular to both the first direction and the second direction.

[0021] According to one embodiment of this disclosure, forming a stacked structure includes: alternately stacking a second dielectric layer and a first dielectric layer along a first direction to form an initial stacked structure; the method further includes: forming a plurality of channel holes along the first direction at least partially penetrating the initial stacked structure, the plurality of channel holes including a plurality of barrier holes arranged along a second direction; forming a sacrificial structure in the plurality of channel holes; forming a barrier structure extending along the first direction and a second direction between the first stacked structure and the second stacked structure, including: removing the sacrificial structure in the plurality of barrier holes; removing the second dielectric layer and the first dielectric layer between a portion of the barrier holes adjacent along the second direction in the plurality of barrier holes to form a merged barrier hole; removing a portion of the second dielectric layer from the merged barrier hole and filling it with a barrier layer; removing the barrier layer from the sidewall of the merged barrier hole and depositing the first dielectric layer on the sidewall surface after removing the barrier layer; forming a sacrificial structure on the surface of the first dielectric layer in the merged barrier hole.

[0022] According to one embodiment of the present disclosure, the plurality of channel holes further includes a plurality of gate line slot holes arranged along the second direction; the method further includes: removing the sacrificial structure in the plurality of gate line slot holes; removing the second dielectric layer and the first dielectric layer between adjacent gate line slot holes along the second direction in the plurality of gate line slot holes to form a gate line slot.

[0023] According to one embodiment of the present disclosure, the method further includes: removing a portion of the second dielectric layer of the initial stacked structure from the gate line gap; forming the stacked structure, further including: forming the conductive layer in the gate line gap to form the stacked structure.

[0024] According to one embodiment of this disclosure, forming at least two rows of contact structures that at least partially penetrate the second stacked structure along a first direction and a connection structure that penetrates the barrier structure along a third direction and connects the contact structures to corresponding conductive layers in the first stacked structure includes: forming at least two rows of contact holes arranged along the second direction by penetrating the second stacked structure at least partially along the first direction; removing a second dielectric layer of the second stacked structure from the contact holes to expose the barrier layer, forming a first contact path; removing the barrier layer from the first contact path along the third direction to expose a corresponding conductive layer, forming a second contact path; and forming conductive layers in the contact holes, the first contact path, and the second contact path to form the contact structure and the connection structure.

[0025] According to one embodiment of the present disclosure, the method further includes: removing a conductive layer on the sidewall of the gate line gap; and forming a gate line gap structure in the gate line gap.

[0026] According to one embodiment of the present disclosure, a barrier structure extending along the first direction and the second direction is formed between the first stacked structure and the second stacked structure, and the method further includes: removing the sacrificial structure in the merged barrier hole; removing the second dielectric layer from the sidewall of the merged barrier hole; removing the filled barrier layer from the merged barrier hole; and forming the barrier structure in the merged barrier hole.

[0027] According to one embodiment of the present disclosure, the plurality of channel holes further includes a plurality of channel holes arranged along the second direction; the method further includes: removing the sacrificial structure in the plurality of channel holes; and forming a channel structure in the plurality of channel holes that at least partially penetrates the first stacked structure along the first direction.

[0028] According to another aspect of this disclosure, a semiconductor device is provided, comprising the semiconductor structure of any of the claims above.

[0029] According to another aspect of this disclosure, a storage system is provided, including a semiconductor device as described above and a controller coupled to the semiconductor device.

[0030] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0031] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0032] Figure 1 A block diagram of an exemplary system with a memory is shown in an embodiment of this disclosure.

[0033] Figure 2A A block diagram of a memory system is shown as an example.

[0034] Figure 2B A block diagram of another memory system is shown as an example.

[0035] Figure 3 A schematic circuit diagram of a memory 300 including peripheral circuitry provided for an embodiment of this disclosure.

[0036] Figure 4 This is a schematic diagram of a peripheral circuit provided in an embodiment of the present disclosure.

[0037] Figure 5A A schematic cross-sectional view of a semiconductor structure is shown according to an exemplary embodiment.

[0038] Figure 5B It shows Figure 5A An exemplary embodiment of the channel hole arrangement of the semiconductor structure.

[0039] Figure 5C It shows Figure 5A A schematic diagram of a cross-section of a semiconductor structure in another direction.

[0040] Figure 6A It shows Figure 5A Another diagram showing the cross-section of the semiconductor structure.

[0041] Figure 6B It shows Figure 5C Another diagram showing the cross-section of the semiconductor structure.

[0042] Figure 7A A cross-sectional schematic diagram of another semiconductor structure is shown according to an exemplary embodiment.

[0043] Figure 7B It shows Figure 7A An exemplary implementation of the channel hole arrangement in a semiconductor structure.

[0044] Figure 7C It shows Figure 7A A schematic diagram of a cross-section of a semiconductor structure in another direction.

[0045] Figure 8 It shows Figure 7AAnother exemplary implementation of the channel hole arrangement of the semiconductor structure.

[0046] Figure 9A It shows Figure 7A Another diagram showing the cross-section of the semiconductor structure.

[0047] Figure 9B It shows Figure 7C Another diagram showing the cross-section of the semiconductor structure.

[0048] Figure 10 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0049] Figure 11 This is a flowchart illustrating another method for forming a semiconductor structure according to an exemplary embodiment.

[0050] Figure 12 It shows Figure 10 The step S1004 shown is a schematic diagram of the processing procedure in one embodiment.

[0051] Figure 13 This is a flowchart illustrating another method for forming a semiconductor structure according to an exemplary embodiment.

[0052] Figure 14 It shows Figure 10 The step S1002 shown is a schematic diagram of the processing procedure in one embodiment.

[0053] Figure 15 This is a flowchart illustrating yet another method for forming a semiconductor structure according to an exemplary embodiment.

[0054] Figure 16 It shows Figure 10 The step S1006 shown is a schematic diagram of the processing procedure in one embodiment.

[0055] Figure 17 It shows Figure 10 The step S1004 shown is a schematic diagram of the processing procedure in another embodiment.

[0056] Figure 18A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after a sacrificial structure has been formed in a plurality of channel holes.

[0057] Figure 18B It is based on Figure 18A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0058] Figure 19A An exemplary embodiment shows a schematic XY cross-sectional view of a semiconductor structure after the formation of a channel structure.

[0059] Figure 19B It is based on Figure 19A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0060] Figure 20A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after removing the sacrificial structure in the barrier via.

[0061] Figure 20B It is based on Figure 20A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0062] Figure 21A An exemplary embodiment shows a schematic XY cross-sectional view of a semiconductor structure forming merged barrier holes.

[0063] Figure 21B It is based on Figure 21A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0064] Figure 22A An exemplary embodiment illustrates an XY cross-sectional schematic diagram of a semiconductor structure after removing a portion of the second dielectric layer from a self-merged barrier aperture.

[0065] Figure 22B It is based on Figure 22A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0066] Figure 23A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the barrier layer has been filled.

[0067] Figure 23B It is based on Figure 23A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0068] Figure 24A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after depositing a first dielectric layer on the sidewall surface of a barrier hole after the barrier layer has been removed.

[0069] Figure 24B It is based on Figure 24A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0070] Figure 25A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after a sacrificial structure is formed on the surface of a first dielectric layer in a merged barrier hole.

[0071] Figure 25B It is based on Figure 25A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0072] Figure 26A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after removing the sacrificial structure in the gate line slot via.

[0073] Figure 26B It is based on Figure 26A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0074] Figure 27A An exemplary embodiment shows a schematic XY cross-sectional view of a semiconductor structure forming a gate line gap.

[0075] Figure 27B It is based on Figure 27A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0076] Figure 28A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after a portion of the second dielectric layer has been removed from the gate line gap.

[0077] Figure 28B It is based on Figure 28A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0078] Figure 29A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the formation of a conductive layer.

[0079] Figure 29B It is based on Figure 29A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0080] Figure 30A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the gate line gap structure has been formed.

[0081] Figure 30B It is based on Figure 30A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0082] Figure 31A An exemplary embodiment shows a schematic XY cross-sectional view of a semiconductor structure after the formation of a contact hole.

[0083] Figure 31B It is based on Figure 31A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0084] Figure 32A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the formation of a first contact path.

[0085] Figure 32B It is based on Figure 32A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0086] Figure 33A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the formation of a second contact path.

[0087] Figure 33B It is based on Figure 33A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0088] Figure 34A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after the formation of contact and connection structures.

[0089] Figure 34B It is based on Figure 34A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0090] Figure 35A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after removing the sacrificial structure in the merged barrier via.

[0091] Figure 35B It is based on Figure 35A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0092] Figure 36A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after removing the sacrificial structure in the merged barrier via.

[0093] Figure 36B It is based on Figure 36A The diagram shows a schematic YZ cross-section of the semiconductor structure.

[0094] Figure 37A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after removing the sacrificial structure in the merged barrier via.

[0095] Figure 37B It is based on Figure 37A The diagram shows a schematic YZ cross-section of the semiconductor structure. Detailed Implementation

[0096] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0097] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0098] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0099] In this disclosure, unless otherwise expressly specified and limited, the term "connection" and similar terms should be interpreted broadly, for example, it can refer to an electrical connection or the ability to communicate with each other; it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0100] Figure 1 A block diagram of an exemplary system with memory is shown according to an embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having memory therein.

[0101] like Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor) of an electronic device. The host 108 may be configured to send data to or receive data from the memory 104.

[0102] Memory 104 can be any memory disclosed herein, such as non-volatile memory. Non-volatile memory can be NAND flash memory (e.g., three-dimensional (3D) NAND flash memory). The semiconductor device provided in the embodiments of this disclosure can be implemented as memory 104.

[0103] In some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108.

[0104] In some embodiments, the memory controller 106 is configured to send commands to the memory 104 to cause the memory 104 to perform the memory operation methods provided in the embodiments of this disclosure.

[0105] In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0106] In some embodiments, the memory controller 106 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which can be used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to send commands to the memory 104 to cause the memory 104 to perform operations, such as read, erase, and program operations.

[0107] The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0108] In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0109] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0110] Figure 2A A block diagram of a memory system is shown as an example. Figure 2A As shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (also known as a PCMCIA card, Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC card, RS-MMC card, MMCmicro card, etc.), an SD card (e.g., SD card, miniSD card, microSD card, SDHC card, etc.), a UFS card, etc. The memory card 202 may also include a connector for connecting the memory card 202 to a host computer (e.g., ...). Figure 1 The memory card connector 204 is coupled to the host 108.

[0111] Figure 2B A block diagram of another memory system is shown as an example. Figure 2B As shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0112] Figure 3A schematic circuit diagram of a memory 300 including peripheral circuitry provided for embodiments of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of memory strings 308 of NAND flash memory, each memory string 308 extending vertically above a substrate (not shown).

[0113] In some embodiments, the peripheral circuit 302 is configured to perform the operation methods provided in the embodiments of this disclosure. It is understood that the peripheral circuit 302 may be configured to perform the operation methods provided in the embodiments of this disclosure according to instructions received from the memory controller 106.

[0114] In some embodiments, each memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0115] In some embodiments, each storage unit 306 may store 1 bit of data, 2 bits of data, or more bits of data, i.e., it may be a single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), quad-level cell (QLC), or a higher-level type.

[0116] like Figure 3 As shown, each memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. SSG 310 and DSG 312 may be configured to activate the selected memory string 308 during read and program operations.

[0117] In some embodiments, the sources of memory strings 308 within the same block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). For example, all memory strings 308 within the same block 304 have an array common source (ACS). Figure 3 As shown, the storage string 308 can be organized into multiple blocks 304. In some embodiments, each of the multiple blocks 304 may have a common source pole line 314 (e.g., coupled to ground); in other embodiments, the multiple blocks 304 may be divided into storage block groups, with the array common source of different storage blocks in each storage block group being isolated from each other. Specific implementation details can be found in [reference needed]. Figure 8 In some embodiments, each block 304 is the basic data unit for the erase operation, that is, all storage units 306 on the same block 304 are erased simultaneously.

[0118] In some embodiments, the transistor of the DSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). Each memory string 308 can be configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0119] like Figure 3 As shown, the memory cells 306 of the memory string 308 can be coupled via word lines (WL) 318, which selects which row of memory cells 306 is affected by read and program operations. Peripheral circuitry 302 can be coupled to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each memory cell 306 targeted for operation via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313, and by sensing voltage and / or current signals from each memory cell 306 targeted for operation. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0120] Figure 4 This is a schematic diagram of a peripheral circuit provided in an embodiment of this disclosure. (See diagram below.) Figure 4As shown, the peripheral circuitry 302 may include a page buffer circuit / sensor amplifier 404, a column decoder / BL driver 406, a row decoder / WL driver 408, a voltage generator 410, a control logic unit 412, a register 414, input / output (I / O) circuitry 416, and a data bus 418. It should be understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0121] In some embodiments, the page buffer circuit / sensor amplifier 404 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic unit 412. For example, the page buffer circuit / sensor amplifier 404 can store a page of programming data (write data) to be programmed into the memory cell array 301. As another example, the page buffer circuit / sensor amplifier 404 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. The column decoder / BL driver 406 can be configured to be controlled by the control logic unit 412 and to select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 410.

[0122] The row decoder / WL driver 408 can be configured to be controlled by the control logic unit 412 and to select / deselect block 304 of the memory cell array 301 and select / deselect word line 318 of block 304. The row decoder / WL driver 408 can also be configured to drive word line 318 using word line voltages generated from the voltage generator 410. In some embodiments, the row decoder / WL driver 408 can also select / deselect and drive SSG line 314 and DSG line 313. The voltage generator 410 can be configured to be controlled by the control logic unit 412 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages, etc., to be supplied to the memory cell array 301.

[0123] Control logic unit 412 can be coupled to each part of peripheral circuitry 302 and is configured to control the operation of each part. Register 414 can be coupled to control logic unit 412 and may include a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuitry 416 can be coupled to control logic unit 412 and acts as a control buffer to buffer inputs from the host (…). Figure 4The input / output circuit 416 receives control commands (not shown) and relays them to the control logic unit 412, and buffers status information received from the control logic unit 412 and relays it to the host. The input / output circuit 416 can also be coupled to the column decoder / bit line driver 406 via the data bus 418, and acts as a data I / O interface and data buffer to buffer data and relay it to or from the memory cell array 301.

[0124] The semiconductor structure in the memory uses a stacked structure to provide the gate conductive layer of the transistor (including the select gate and word line), a channel structure that runs through the stacked structure to provide the channel layer of the transistor, and a contact structure that runs through the stacked structure to realize the conductive channel connecting the gate conductive layer that runs through the channel structure to the external circuit. Figure 5A A schematic cross-sectional view of a semiconductor structure is shown according to an exemplary embodiment. Figure 5A The semiconductor structure shown may include a first stacked structure 5002, a second stacked structure 5004, a barrier structure 502, a contact structure 504, and a connection structure 506.

[0125] Figure 5C It shows Figure 5A A schematic diagram of a cross-section of a semiconductor structure in another direction. (See diagram below.) Figure 5A and Figure 5C As shown, the first stack structure 5002 may include a conductive layer 50022 and a first dielectric layer 5006 alternately stacked along a first direction (e.g., the Z direction in the figure), wherein the conductive layer 5022 may be a word line 318 of the memory cell array 301. The second stack structure 5004 may include a second dielectric layer 50042 and a first dielectric layer 5006 alternately stacked along the first direction. A barrier structure 502 may be disposed between the first stack structure 5002 and the second stack structure 5004 along the first direction and extend along a second direction perpendicular to the first direction (e.g., the X direction in the figure) to separate the first stack structure 5002 and the second stack structure 5004. At least two rows of contact structures 504 arranged along the second direction may be provided, and the contact structures 504 may at least partially penetrate the second stack structure 5004 along the first direction. The connecting structure 506 can penetrate the barrier structure 502 along a third direction (e.g., the Y direction in the figure) that is perpendicular to the first direction and the second direction. The connecting structure 506 connects the contact structure 504 to the corresponding conductive layer in the first stacked structure 5002.

[0126] In some embodiments, Figure 5A The semiconductor structure shown may include a stacked structure 500, which may be divided into multiple memory blocks along a third direction. Each memory block may include a first stacked structure, a second stacked structure, a barrier structure, at least two rows of contact structures, and connection structures, for example... Figure 5A The diagram shows that the stacked structure 500 is divided into storage block 1 and storage block 2 along the Y direction. Storage block 1 includes a first stacked structure 5002, a second stacked structure 5004, a barrier structure 502, a contact structure 504, and a connection structure 506.

[0127] In some embodiments, at least two rows of contact structures arranged in an upward staggered manner may be provided in the second stacking structure region of each storage block. Figure 5B It shows Figure 5A An exemplary embodiment of the channel hole arrangement of the semiconductor structure. Figure 5B In this context, the X' and Y' directions can be two directions parallel to the X and Y directions, respectively. For example... Figure 5B As shown, the second stacking structure regions of storage block 1 and storage block 2 are each provided with two rows of contact structures 504 that are staggered in the Y' direction and arranged along the X' direction.

[0128] According to the semiconductor structure provided in the embodiments of this disclosure, a first stacked structure comprising alternating conductive layers and a first dielectric layer along a first direction, and a second stacked structure comprising alternating second dielectric layers and a first dielectric layer along the first direction, a connection structure connecting a contact structure to a corresponding conductive layer in the first stacked structure is provided through a barrier structure disposed between the first and second stacked structures along the first direction and extending along the second direction in a third direction perpendicular to both the first and second directions. This reduces the limitation on the distance for removing the second dielectric layer during the formation of the contact structure. Thus, by providing at least two rows of contact structures that at least partially penetrate the second stacked structure along the first direction and are arranged in a second direction perpendicular to the first direction, the length of the second stacked structure region required to provide a certain number of contact structures corresponding to the number of conductive layers in the second direction is shortened. This reduces the area of ​​the second stacked structure used to provide the contact structures, and minimizes the limitation on the increase in the number of stacked structure layers caused by the increased chip area occupied by the contact structures, thereby improving the speed of increasing storage density.

[0129] Figure 6A It shows Figure 5A Another diagram showing the cross-section of the semiconductor structure. Figure 6B It shows Figure 5C Another diagram illustrating the cross-section of the semiconductor structure in the image. Figure 6B for Figure 6A A view of the semiconductor structure in another direction. (e.g.) Figure 6A and Figure 6BAs shown, the semiconductor structure also includes a first channel structure 6082 and a second channel structure 6084 that at least partially penetrate the first stacked structure 5002 along a first direction, wherein the conductive layer of the portion of the first channel structure 6082 in the first stacked structure 5002 is correspondingly connected to the conductive layer of the portion of the second channel structure 6084, and the connection structure 506 connects the contact structure 504 to the corresponding conductive layer of the portion of the second channel structure 6084 in the first stacked structure 5002.

[0130] In some embodiments, the second channel structure 6084 can be a virtual channel structure, and the conductive layer of the portion where the second channel structure 6084 is located serves as a "high-speed path" (through the connection structure 506) to connect the conductive layer of the portion where the contact structure 504 is located with the conductive layer of the portion where the first channel structure 6082 is located.

[0131] In some embodiments, the first stacked structure 5002 may have only one "high-speed path," and correspondingly, a barrier structure 502 may be provided on only one side of the second stacked structure 5004. That is, the contact structure 504 is connected to the corresponding conductive layer of the first stacked structure 5002, which is separated from the second stacked structure 5004 by the barrier structure 502 in the Y direction. This allows for increasing the length of the chip step region where the contact structure 504 is located in the Y direction, given a fixed area of ​​the chip core region where the first channel structure 6082 is located, so that two rows of contact structures 504 arranged in the X direction and staggered in the Y direction can be provided. In this case, the separation method between a memory block and the memory block adjacent in the forward direction along the Y direction and the memory block adjacent in the reverse direction along the Y direction can be different.

[0132] In some embodiments, the plurality of memory blocks may include a first memory block and second and third memory blocks adjacent to it on two sides in a third-direction orientation. The second memory block is separated from the first memory block by a gate line gap structure; the first stacked structure of the third memory block is separated from the first stacked structure of the first memory block by a gate line gap structure, and the second stacked structure of the third memory block is connected to the corresponding layer of the second stacked structure of the first memory block. (Refer to...) Figure 6A and Figure 6B Taking memory block 1 as the first memory block in the figure as an example, memory block 2 is the third memory block, and memory block 2 is the memory block that is adjacent to memory block 1 in the opposite direction in the Y direction. Memory block 1 can be adjacent to a second memory block (not shown in the figure) in the positive direction in the Y direction. Memory block 1 and the second memory block are separated by a first gate line slot structure 602 that at least partially penetrates the stacked structure 500 along the Z direction. The first gate line slot structure 602 extends along the X direction. Figure 6AIn order to distinguish the first stacked structures of memory block 1 and memory block 2, the first stacked structure of memory block 1 is designated as 60021, and the first stacked structure of memory block 2 is designated as 60022. The first stacked structure 60021 of memory block 1 has a "high-speed path" on one side adjacent to the first gate line gap structure 602, and the barrier structure 502 provided between the "high-speed path" and the second stacked structure 5004 can be the first barrier structure.

[0133] The second stacking structure of storage block 1 and the second stacking structure of storage block 2 (both in Figures 5A to 6B The layers corresponding to the 5004 are connected. The first stacked structure 60021 of memory block 1 and the first stacked structure 60022 of memory block 2 are separated by a second gate line gap structure 604 and a second barrier structure 606 that at least partially penetrate the stacked structure 500 along the Z direction. The first gate line gap structure 604 and the second barrier structure 606 are sequentially disposed between the first stacked structure 60021 and the first stacked structure 60022 along the X direction and extend along the X direction.

[0134] Refer again Figure 6A and Figure 6B In some embodiments, the contact structure 504 may include a first portion 5042 and a second portion 5044 connected together, the first portion 5042 of the contact structure extending at least through a portion of the second stacked structure 5004 along the Z direction, and the second portion 5044 of the contact structure extending along the Y direction to be connected to the connection structure 506.

[0135] According to the semiconductor structure provided in the embodiments of this disclosure, by setting only one "high-speed path" for the first stacked structure, the contact structure is connected to the conductive layer on only one side of the second stacked structure. This allows for increasing the length of the chip step area where the contact structure is located in the third direction, given that the area of ​​the chip core region where the first channel structure is located is fixed. This enables the setting of two rows of contact structures arranged along the second direction and staggered in the third direction.

[0136] Figure 7A A cross-sectional schematic diagram of another semiconductor structure is shown according to an exemplary embodiment. Figure 5A The semiconductor structure shown may include a first stacked structure 7002, a second stacked structure 7004, a barrier structure 702, a contact structure 704, and a connection structure 706.

[0137] Figure 7C It shows Figure 7A A schematic diagram of a cross-section of a semiconductor structure in another direction. (See diagram below.) Figure 7A and Figure 7CAs shown, the first stacked structure 7002 may include a conductive layer 70022 and a first dielectric layer 7006 alternately stacked along the Z direction, wherein the conductive layer 7022 may be a word line 318 of the memory cell array 301. The second stacked structure 7004 may include a second dielectric layer 70042 and a first dielectric layer 7006 alternately stacked along the Z direction. A barrier structure 702 may be disposed along the Z direction between the first stacked structure 7002 and the second stacked structure 7004 and extend along the X direction to separate the first stacked structure 7002 and the second stacked structure 7004. At least one row of contact structures 704 arranged along the X direction may be provided, and the contact structures 704 may at least partially penetrate the second stacked structure 7004 along the Z direction. The barrier structure 702 is located at least on both sides of the contact structures 704 in the Y direction. A connection structure 706 may penetrate the barrier structure 702 along the Y direction, and the connection structure 706 connects the contact structures 704 to the corresponding conductive layers in the first stacked structure 7002.

[0138] In some embodiments, Figure 7A The semiconductor structure shown may include a stacked structure 700, which may be divided into multiple memory blocks along a third direction. Each memory block may include a first stacked structure, a second stacked structure, a barrier structure, at least one row of contact structures, and connection structures, for example... Figure 7A The diagram shows that the stacked structure 700 is divided into storage block 1' and storage block 2' along the Y direction. Storage block 1' includes a first stacked structure 7002, a second stacked structure 7004, a barrier structure 702, a contact structure 704, and a connection structure 706.

[0139] In some embodiments, at least one row of contact structures aligned along a second direction may be provided in the second stacking structure region of each storage block. Figure 7B It shows Figure 7A An exemplary embodiment of the channel hole arrangement in a semiconductor structure. For example... Figure 7B As shown, the second stacking structure regions of storage block 1' and storage block 2' are each provided with a row of contact structures 704 aligned along the X' direction.

[0140] In other embodiments, at least one row of contact structures arranged in a serpentine pattern along a second direction may be provided in the second stacking structure region of each storage block. Figure 8 It shows Figure 7A Another exemplary implementation of the channel hole arrangement in the semiconductor structure. For example... Figure 7B As shown, the second stacking structure regions of storage block 1” and storage block 2” are each provided with a row of contact structures 704 arranged in a serpentine pattern along the X' direction.

[0141] According to the semiconductor structure provided in the embodiments of this disclosure, a first stacked structure comprising a conductive layer and a first dielectric layer alternately stacked along a first direction and a second stacked structure comprising a second dielectric layer and a first dielectric layer alternately stacked along a first direction are provided. By providing a connection structure that penetrates the barrier structure along a third direction on both sides of at least one row of contact structures in the second stacked structure, the connection contact structure can be connected to the "high-speed path" of the first stacked structure on both sides of the second stacked structure, thereby increasing the redundant path, reducing the WL resistance, and thus improving the performance of the chip product.

[0142] Figure 9A It shows Figure 7A Another diagram showing the cross-section of the semiconductor structure. Figure 9B It shows Figure 7C Another diagram illustrating the cross-section of the semiconductor structure in the image. Figure 9B for Figure 9A A view of the semiconductor structure in another direction. (e.g.) Figure 9A and Figure 9B As shown, the semiconductor structure also includes a first channel structure 9042 and a second channel structure 9044 that at least partially penetrate the first stacked structure 7002 along the Z direction. The conductive layer of the portion of the first channel structure 9042 in the first stacked structure 7002 is correspondingly connected to the conductive layer of the portion of the second channel structure 9044. The connection structure 706 connects the contact structure 704 to the corresponding conductive layer of the portion of the second channel structure 7044 in the first stacked structure 7002.

[0143] In some embodiments, the second channel structure 9044 can be a virtual channel structure, and the conductive layer of the portion where the second channel structure 9044 is located serves as a "high-speed path" (through the connection structure 706) to connect the conductive layer of the portion where the contact structure 704 is located with the conductive layer of the portion where the first channel structure 9042 is located.

[0144] In some embodiments, the first stacking structure 7002 may have a "high-speed path" on each side of the second stacking structure 7004 in the Y direction, and correspondingly, barrier structures 702 are provided on both sides of the second stacking structure 7004. That is, the contact structure 704 is connected to the corresponding conductive layer of the first stacking structure 7002 separated by the barrier structures 702 on both sides of the second stacking structure 7004 in the Y direction. In this case, the separation method of a memory block and its positively adjacent memory block and its negatively adjacent memory block in the Y direction can be the same.

[0145] In some embodiments, the plurality of memory blocks may include a first memory block and a second memory block adjacent to it in a third direction, the second memory block being separated from the first memory block by a gate line gap structure. (Refer to...) Figure 9A and Figure 9BTaking memory block 1' as the first memory block and memory block 2' as the second memory block in the figure, memory block 1' and memory block 2' are separated by a gate line slot structure 902 that at least partially penetrates the stacked structure 700 along the Z direction. The gate line slot structure 902 extends along the X direction. The first stacked structure 9002 of memory block 1' has a "high-speed path" near the gate line slot structures 902 on both sides. A barrier structure 702 is provided between each of these two "high-speed paths" and the second stacked structure 7004.

[0146] Refer again Figure 9A and Figure 9B In some embodiments, the contact structure 704 may include a first portion 7042 and a second portion 7044 connected together, the first portion 7042 of the contact structure extending at least through a portion of the second stacked structure 7004 along the Z direction, and the second portion 7044 of the contact structure extending along the Y direction (forward or reverse) to be connected to the connection structure 706.

[0147] According to the semiconductor structure provided in the embodiments of this disclosure, by setting two "high-speed paths" for the first stacked structure, the contact structure is connected to the conductive layers on both sides of the second stacked structure, which increases the redundancy path, reduces the WL resistance, and thus improves the performance of the chip product.

[0148] Figure 10 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 10 The methods shown may include, for example, forming Figures 5A to 6B The overall steps of the semiconductor structure are shown. (Refer to...) Figure 10 The method 100 provided in this embodiment may include the following steps S1002 to S1006.

[0149] In step S1002, a stacked structure is formed, the stacked structure including a first stacked structure of conductive layers and a first dielectric layer alternately stacked along a first direction and a second stacked structure including a second dielectric layer and a first dielectric layer alternately stacked along the first direction.

[0150] In some embodiments, after an initial stacked structure is formed by alternately stacking the second dielectric layer and the first dielectric layer along a first direction, a portion of the second dielectric layer is replaced with a conductive layer in a subsequent process to form the stacked structure. Implementations of forming the initial stacked structure in some exemplary embodiments can be found in step S1102. Implementations of replacing a portion of the second dielectric layer with a conductive layer in some exemplary embodiments can be found in… Figure 14 .

[0151] In step S1004, a barrier structure is formed extending along a first direction and a second direction between the first stacked structure and the second stacked structure, wherein the second direction is perpendicular to the first direction.

[0152] A barrier layer can be formed between the virtual channel structure region and the step region using self-blocking vias to block the step region when forming the conductive layer between the core region and the virtual channel structure region. Implementation methods for forming the barrier structure in some embodiments are described below. Figure 11 .

[0153] In step S1006, at least two rows of contact structures are formed that at least partially penetrate the second stacked structure along the first direction, and a connection structure is formed that penetrates the barrier structure along the third direction and connects the contact structures to the corresponding conductive layers in the first stacked structure. The at least two rows of contact structures are arranged along the second direction, and the third direction is perpendicular to both the first and second directions.

[0154] In some exemplary embodiments forming contact and connection structures, refer to Figure 16 .

[0155] Figure 11 This is a flowchart illustrating another method for forming a semiconductor structure according to an exemplary embodiment. Figure 11 The methods shown may include, for example, forming Figures 5A to 9B The process of forming a channel structure during the stacking of the semiconductor structure shown is illustrated. (Reference) Figure 11 The method 110 provided in this embodiment may include the following steps S1102 to S1110.

[0156] In step S1102, the second dielectric layer and the first dielectric layer are alternately stacked along the first direction to form an initial stacked structure.

[0157] In some embodiments, the first dielectric layer may be a silicon oxide (OX material) layer, and the second dielectric layer may be a silicon nitride (e.g., Si3N4) layer. The silicon oxide and silicon nitride layers can be alternately stacked using multilayer thin-film deposition techniques to form the initial stacked structure.

[0158] In other embodiments, the second dielectric layer may also be a polysilicon layer.

[0159] In the embodiments disclosed herein, the scheme of alternating stacking of silicon oxide layer and silicon nitride layer is used as an example for illustration, but it is not limited thereto.

[0160] In step S1104, at least partially penetrating the initial stacked structure along the first direction, a plurality of channel holes are formed along the second direction, the plurality of channel holes including a plurality of channel holes, a plurality of barrier holes and a plurality of gate line slot holes.

[0161] In some embodiments, multiple channel holes can be formed on the surface of the region corresponding to the initial stacked structure by patterning and etching the upper surface layer and the underlying silicon oxide-silicon nitride layer of the initial stacked structure sequentially using photolithography and etching processes. For example, a photolithography process can be performed to pattern the openings of the contact holes using an etching mask (e.g., a photoresist mask), and one or more dry etching and / or wet etching processes (e.g., reactive ion etching (RIE)) can be performed to penetrate the silicon oxide-silicon nitride layer.

[0162] In step S1106, a sacrificial structure is formed in the plurality of channel holes.

[0163] In some embodiments, the sacrificial structure can be made of carbon material, and a carbon material layer can be deposited in multiple channel pores to form the sacrificial structure. The sacrificial structures mentioned in the embodiments of this disclosure can all be made of carbon material as exemplary implementations, but are not limited thereto.

[0164] Figure 18A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after a sacrificial structure has been formed in a plurality of channel holes. Figure 18B It is based on Figure 18A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 18A and Figure 18B As shown, a plurality of channel holes are formed along the Z direction, at least partially penetrating the initial stacked structure 1802, and a sacrificial structure is formed therein, resulting in a plurality of first channel holes 18042, a plurality of second channel holes 18044, a plurality of barrier holes 18046 and a plurality of gate line slot holes 18048 filled with the sacrificial structure.

[0165] Figure 18A and Figure 18B correspond Figure 5B Semiconductor structure. Figure 7B and Figure 8 semiconductor structure and Figure 5B In contrast, the arrangement of barrier vias and gate line slot vias in multiple channel vias differs. The specific arrangement can be set according to actual needs, and can also be adopted. Figures 11 to 17 The implementation methods shown are not described in detail here.

[0166] In step S1108, the sacrificial structures in the multiple channel holes are removed.

[0167] In step S1110, a channel structure is formed in the plurality of channel holes.

[0168] In some embodiments, the sacrificial structures in multiple channel holes can be removed by etching or other processes, and then a channel gate dielectric layer, a channel conductive layer, and a channel insulating layer can be sequentially deposited in the channel holes to form the first channel structure and the second channel structure described above.

[0169] Figure 19A An exemplary embodiment shows a schematic XY cross-sectional view of a semiconductor structure after the formation of a channel structure. Figure 19B It is based on Figure 19A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 19A and Figure 19B As shown, after removing the sacrificial structure from the multiple channel holes (18042, 18044), a channel structure 1902 can be formed in the multiple channel holes. The channel structure 1902 may include, for example, [missing information - likely related to channel structure 1902]. Figure 6A The first channel structure 6082 and the second channel structure 6084 (or Figure 9A The first channel structure 9042 and the second channel structure 9044 in the middle.

[0170] Figure 12 It shows Figure 10 The step S1004 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 12 As shown in the embodiments of this disclosure, step S1004 may further include steps S1202 to S1210, for example, in the following steps: Figure 11 Execute the method shown below.

[0171] Step S1202: Remove the sacrificial structure from the multiple barrier holes.

[0172] Figure 20A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after removing the sacrificial structure in the barrier via. Figure 20B It is based on Figure 20A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 20A and Figure 20B As shown, the sacrificial structure in multiple barrier holes can be removed by etching and other processes to expose barrier holes 2002.

[0173] Step S1204: Remove the second dielectric layer and the first dielectric layer between some of the adjacent barrier holes along the second direction in the plurality of barrier holes to form a merged barrier hole.

[0174] Figure 21A An exemplary embodiment shows a schematic XY cross-sectional view of a semiconductor structure forming merged barrier holes. Figure 21B It is based on Figure 21A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 21A and Figure 21BAs shown, a predetermined number of adjacent barrier holes along the X direction can be merged, for example, by removing the first dielectric layer and the second dielectric layer of the initial stacked structure between two and / or three adjacent barrier holes along the X direction through processes such as etching, to form merged barrier holes 2102.

[0175] Step S1206: Remove a portion of the second dielectric layer from the merged barrier holes and fill with a barrier layer.

[0176] Figure 22A An exemplary embodiment illustrates an XY cross-sectional schematic diagram of a semiconductor structure after removing a portion of the second dielectric layer from a self-merged barrier aperture. Figure 22B It is based on Figure 22A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 22A and Figure 22B As shown, the second dielectric layer of the initial stacked structure can be removed from the merged barrier holes (in the forward and reverse directions of the Y direction) by etching or other processes, exposing the gap 2202 between the adjacent first dielectric layers extending in the forward and reverse directions of the Y direction from the sidewall of the merged barrier holes.

[0177] In some embodiments, the barrier layer may be, for example, a polycrystalline silicon material layer.

[0178] Figure 23A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the barrier layer has been filled. Figure 23B It is based on Figure 23A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. (Refer to...) Figure 22A and Figure 22B Polycrystalline silicon can be deposited on the surface of the exposed first dielectric layer and on the sidewalls of the merged barrier holes through the slit 2202 that communicates with the merged barrier holes, forming a structure like... Figure 23A and Figure 23B The barrier layer 2302 shown.

[0179] Step S1208: Remove the barrier layer from the sidewall of the merged barrier hole and deposit a first dielectric layer on the sidewall surface after the barrier layer is removed.

[0180] Figure 24A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after depositing a first dielectric layer on the sidewall surface of a barrier hole after the barrier layer has been removed. Figure 24B It is based on Figure 24A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. (Refer to...) Figure 23A and Figure 23B The combined barrier hole sidewall of the barrier layer 2402 can be removed by etching or other processes to expose the combined barrier hole sidewall, and then a layer such as... can be deposited on the exposed combined barrier hole sidewall. Figure 24A and Figure 24BThe first dielectric layer 2402 is shown.

[0181] Step S1210: A sacrificial structure is formed on the surface of the first dielectric layer in the merged barrier holes.

[0182] Figure 25A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after a sacrificial structure is formed on the surface of a first dielectric layer in a merged barrier hole. Figure 25B It is based on Figure 25A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 25A and Figure 25B As shown, a sacrificial structure 2502 can be deposited on the surface of the first dielectric layer of the merged barrier hole sidewalls, and then the upper surface of the entire initial stacked structure 1802 (along the Y direction) can be chemically mechanically polished (CMP) to remove the sacrificial structure (e.g., carbon material) on the upper surface, and then the first dielectric layer 2504 can be deposited on the upper surface.

[0183] Figure 13 This is a flowchart illustrating another method for forming a semiconductor structure according to an exemplary embodiment. Figure 13 The method shown can, for example, be used in... Figure 12 The method shown is then executed to form the gate line gap. (See reference...) Figure 13 The method 130 provided in this embodiment may include the following steps S1302 to S1304.

[0184] In step S1302, the sacrificial structures in the multiple gate line slot holes are removed.

[0185] Figure 26A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after removing the sacrificial structure in the gate line slot via. Figure 26B It is based on Figure 26A The diagram shows a YZ cross-section of the semiconductor structure. As shown in 26A and 26B, the sacrificial structures in the multiple gate line slot holes can be removed by processes such as etching to expose the gate line slot holes 2602.

[0186] In step S1304, the second dielectric layer and the first dielectric layer between adjacent gate line slot holes along the second direction in a plurality of gate line slot holes are removed to form a gate line slot.

[0187] Figure 27A An exemplary embodiment shows a schematic XY cross-sectional view of a semiconductor structure forming a gate line gap. Figure 27B It is based on Figure 27A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 27A and Figure 27B As shown, all adjacent gate line slots along the X direction can be merged. For example, the first dielectric layer and the second dielectric layer of the initial stacked structure between adjacent gate line slots along the X direction can be removed by etching or other processes to form gate line slot 2702.

[0188] Figure 14 It shows Figure 10 The step S1002 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 14 The method shown can, for example, be used in... Figure 13 The method shown is then executed to form the conductive layer of the stacked structure. For example... Figure 14 As shown in the present embodiment, step S1002 may further include steps S1402 and S1404.

[0189] Step S1402: Remove a portion of the second dielectric layer of the initial stacked structure from the gate line gap.

[0190] Figure 28A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after a portion of the second dielectric layer has been removed from the gate line gap. Figure 28B It is based on Figure 28A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 28A and Figure 28B As shown, the second dielectric layer of the initial stacked structure around the channel structure and the virtual channel structure can be removed from the gate line gap in the forward (or reverse) direction of the Y direction by etching or other processes, exposing the gap 2802 between the adjacent first dielectric layers around the channel structure and the virtual channel structure.

[0191] Step S1404: A conductive layer is formed in the gate line gap to form a stacked structure.

[0192] In some embodiments, the conductive layer may include a high dielectric constant dielectric layer and a tungsten metal layer, which may be sequentially deposited from the gate line gap onto the exposed surface of an adjacent first dielectric layer to form the conductive layer.

[0193] Figure 29A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the formation of a conductive layer. Figure 29B It is based on Figure 29A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 29A and Figure 29B As shown, a conductive layer 2902 can be deposited on the exposed adjacent first dielectric layer surface from the gap between the gate line and the gate line.

[0194] According to the method for forming a semiconductor structure provided in the embodiments of this disclosure, a barrier layer is formed between the region where the virtual channel structure is located and the step region by a self-blocking via, so as to block the step region when forming the conductive layer between the core region and the region where the virtual channel structure is located from the gate line gap. This can reduce the number of cycles required to avoid extending to the step region during the formation of the conductive layer, and simplify the process flow.

[0195] Figure 15 This is a flowchart illustrating yet another method for forming a semiconductor structure according to an exemplary embodiment. For example... Figure 15 The method shown can, for example, be used in... Figure 14 The method shown is then executed to form the gate line gap structure. (See reference...) Figure 15 The method 150 provided in this embodiment may include the following steps S1502 and S1504.

[0196] In step S1502, the conductive layer on the sidewall of the gate line gap is removed.

[0197] In step S1504, a gate line gap structure is formed in the gate line gap.

[0198] Figure 30A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the gate line gap structure has been formed. Figure 30B It is based on Figure 30A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 30A and Figure 30B As shown, the conductive layer on the sidewall of the gate line gap can be removed by etching or other processes to expose the sidewall of the gate line gap. Then, a first dielectric layer is deposited on the exposed sidewall of the gate line gap, followed by the deposition of polysilicon to form the gate line gap structure 3002.

[0199] Figure 16 It shows Figure 10 The step S1006 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 16 As shown in the present embodiment, step S1006 may further include steps S1602 to S1608.

[0200] Step S1602: At least partially penetrating the second stacked structure along the first direction to form contact holes arranged along the second direction.

[0201] In some embodiments, contact holes can be formed by patterning and etching the upper surface layer of the second stacked structure (in the forward or reverse direction along the Z direction) and the underlying silicon oxide-silicon nitride layer, etc., using photolithography and etching processes. For example, a photolithography process can be performed to pattern the opening of the contact hole using an etching mask (e.g., a photoresist mask), and one or more dry etching and / or wet etching processes can be performed to penetrate the silicon oxide-silicon nitride layer to stop at a designated silicon nitride layer, which is in the same layer as the conductive layers corresponding to the first stacked structure and the second stacked structure.

[0202] Figure 31A An exemplary embodiment shows a schematic XY cross-sectional view of a semiconductor structure after the formation of a contact hole. Figure 31B It is based on Figure 31A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 31A and Figure 31B As shown, contact holes 3102 can be formed by etching or other processes through the silicon oxide layer (first dielectric layer) and the silicon nitride layer (second dielectric layer) to the designated silicon nitride layer.

[0203] Step S1604: Remove the second dielectric layer of the second stacked structure from the contact hole to expose the barrier layer, forming a first contact path.

[0204] Figure 32A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the formation of a first contact path. Figure 32B It is based on Figure 32A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 32A and Figure 32B As shown, the second dielectric layer of the second stacked structure can be removed from the contact hole in all directions from the XY plane by etching or other processes, forming a first contact path 3202 that is in the same layer as the corresponding conductive layer.

[0205] Step S1606: Remove the barrier layer from the first contact path along a third direction to expose the corresponding conductive layer, forming a second contact path.

[0206] Figure 33A An exemplary embodiment shows a schematic XY cross-section of a semiconductor structure after the formation of a second contact path. Figure 33B It is based on Figure 33A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 33A and Figure 33B As shown, the barrier layer of the first contact passage 3202 can be removed along the Y direction (forward or reverse) through etching or other processes to expose the corresponding conductive layer that contacts the virtual channel structure 1902, forming a second contact passage 3302 that is connected to the first contact passage 3202.

[0207] Step S1608: A conductive layer is formed in the contact hole, the first contact path, and the second contact path to form a contact structure and a connection structure.

[0208] Figure 34A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after the formation of contact and connection structures. Figure 34B It is based on Figure 34A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. Figure 34A and Figure 34B As shown, after forming the second contact path 3302, the high dielectric constant layer of the corresponding conductive layer can be removed, and then a conductive layer 3402 can be deposited from the contact hole on the surface of the first and second contact paths communicating with it to form a contact structure and a connection structure. Then, the upper surface of the entire stacked structure 1802 (along the Y direction) can be chemically mechanically polished to remove the oxide layer deposited on the upper surface when forming the contact structure.

[0209] According to the method for forming a semiconductor structure provided in the embodiments of this disclosure, a barrier layer is formed between the region where the virtual channel structure is located and the step region by a self-blocking via, so that the conductive layer in the region where the virtual channel structure is located is blocked when the self-contact via forms a contact structure in the step region. This reduces the number of cycles required to avoid extending to the region where the virtual channel structure is located during the formation of the contact structure, and simplifies the process flow.

[0210] Figure 17 It shows Figure 10 The illustrated step S1004 is a process diagram in another embodiment. (See diagram below.) Figure 17 As shown in the embodiments of this disclosure, step S1004 may further include steps S1702 to S1708. For example... Figure 17 The method shown can, for example, be used in... Figure 16 The method shown is executed afterward to form a barrier structure.

[0211] Step S1702: Remove the sacrificial structure from the merged barrier holes.

[0212] Figure 35A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after removing the sacrificial structure in the merged barrier via. Figure 35B It is based on Figure 35A The diagram shows a YZ cross-section of the semiconductor structure. As shown in 35A and 35B, the sacrificial structure in the merged barrier vias can be removed by processes such as etching, exposing the merged barrier vias 3502.

[0213] Step S1704: Remove the second dielectric layer from the merged barrier hole sidewalls.

[0214] Step S1706: Remove the filled barrier layer from the self-merged barrier holes.

[0215] Figure 36A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after removing the sacrificial structure in the merged barrier via. Figure 36B It is based on Figure 36A The diagram shows a YZ cross-section of the semiconductor structure. As shown in 36A and 36B, the second dielectric layer of the merged barrier hole sidewall can be removed by processes such as etching, and then the previously filled barrier layer can be removed to expose the merged barrier hole sidewall and the gap 3602 between the adjacent first dielectric layers extending in the forward and reverse directions in the Y direction.

[0216] Step S1708: Form a barrier structure in the merged barrier holes.

[0217] Figure 37A An exemplary embodiment shows an XY cross-sectional schematic diagram of a semiconductor structure after removing the sacrificial structure in the merged barrier via. Figure 37B It is based on Figure 37A A schematic diagram of the YZ cross-section of the semiconductor structure is shown. (Refer to...) Figure 36A and Figure 36B Oxides can be deposited on the surface of the gap 3602 between the exposed and merged barrier hole sidewalls and the adjacent first dielectric layers extending in the forward and reverse directions in the Y direction to fill the merged barrier holes and form a barrier structure 3702 as shown in 37A and 37B.

[0218] Figures 18A to 37B The main processes for forming the semiconductor structures in the embodiments of this disclosure are illustrated, and have been associated with Figures 11 to 17 The steps described in the text are not repeated here.

[0219] Exemplary embodiments of this disclosure have been specifically shown and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementations described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A first stacked structure comprising a conductive layer and a first dielectric layer alternately stacked along a first direction; It includes a second stacked structure of a second dielectric layer and a first dielectric layer that are alternately stacked along the first direction; A barrier structure is disposed between the first stacked structure and the second stacked structure along the first direction, the barrier structure extending along a second direction, the second direction being perpendicular to the first direction; At least two rows of contact structures, wherein the contact structures at least partially penetrate the second stacked structure along the first direction, and the at least two rows of contact structures are arranged along the second direction; A connecting structure extending through the barrier structure along a third direction, the connecting structure connecting the contact structure and the corresponding conductive layer in the first stacked structure, the third direction being perpendicular to the first direction and perpendicular to the second direction.

2. The semiconductor structure according to claim 1, characterized in that, The at least two rows of contact structures are staggered in the third direction.

3. The semiconductor structure according to claim 1 or 2, characterized in that, It includes a stacked structure, which is divided into multiple storage blocks along the third direction. The storage blocks include a first stacked structure, a second stacked structure, a barrier structure, at least two rows of contact structures, and a connection structure.

4. The semiconductor structure according to claim 3, characterized in that, The plurality of storage blocks includes a first storage block and a second storage block adjacent to it; The semiconductor structure further includes a first gate line slot structure that at least partially penetrates the stacked structure along the first direction. The first gate line slot structure is disposed between the first memory block and the second memory block and extends along the second direction to isolate the first memory block and the second memory block.

5. The semiconductor structure according to claim 4, characterized in that, The plurality of storage blocks also includes a third storage block adjacent to the first storage block, wherein the second stacking structure of the third storage block is connected to the layer corresponding to the second stacking structure of the first storage block; The barrier structure is a first barrier structure; The semiconductor structure further includes a second gate line gap structure and a second barrier structure that at least partially penetrate the stacked structure along the first direction. The first gate line gap structure and the second barrier structure are disposed between the first memory block and the third memory block and extend along the second direction to isolate the first stacked structure of the first memory block and the first stacked structure of the third memory block.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that, The contact structure includes a first part and a second part connected to each other. The first part of the contact structure penetrates at least a portion of the second stacked structure along the first direction, and the second part of the contact structure extends along the third direction to connect with the connection structure.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, It also includes a first channel structure and a second channel structure that at least partially penetrate the first stacked structure along the first direction, wherein: In the first stacked structure, the conductive layer of the portion containing the first channel structure is connected to the conductive layer of the portion containing the second channel structure, and the connection structure connects the contact structure to the corresponding conductive layer of the portion containing the second channel structure in the first stacked structure.

8. A semiconductor structure, characterized in that, include: A first stacked structure comprising a conductive layer and a first dielectric layer alternately stacked along a first direction; It includes a second stacked structure of a second dielectric layer and a first dielectric layer that are alternately stacked along the first direction; At least one row of contact structures, the contact structures at least partially penetrating the second stacked structure along the first direction, the at least one row of contact structures being arranged along a second direction, the second direction being perpendicular to the first direction; A barrier structure is disposed between the first stacked structure and the second stacked structure along the first direction, the barrier structure being located at least on both sides of the at least one row of contact structures along a third direction and extending along the second direction, the third direction being perpendicular to the first direction and perpendicular to the second direction; A connecting structure extending through the barrier structure along the third direction connects the contact structure to the corresponding conductive layer in the first stacked structure.

9. The semiconductor structure according to claim 8, characterized in that, The at least one row of contact structures is aligned and arranged along the second direction.

10. The semiconductor structure according to claim 8, characterized in that, The at least one row of contact structures is arranged in a serpentine pattern along the second direction.

11. The semiconductor structure according to any one of claims 8 to 10, characterized in that, It includes a stacked structure, which is divided into multiple storage blocks along the third direction. The storage blocks include a first stacked structure, a second stacked structure, at least one row of contact structures, a barrier structure, and a connection structure.

12. The semiconductor structure according to claim 11, characterized in that, The plurality of storage blocks includes a first storage block and a second storage block adjacent to it; The semiconductor structure further includes a gate line slot structure that at least partially penetrates the stacked structure along the first direction. The gate line slot structure is disposed between the first memory block and the second memory block and extends along the second direction to isolate the first memory block and the second memory block.

13. The semiconductor structure according to any one of claims 8 to 12, characterized in that, The contact structure includes a first part and a second part connected to each other. The first part of the contact structure penetrates at least a portion of the second stacked structure along the first direction, and the second part of the contact structure extends along the third direction to connect with the connection structure.

14. The semiconductor structure according to any one of claims 8 to 13, characterized in that, It also includes a first channel structure and a second channel structure that at least partially penetrate the first stacked structure along the first direction, wherein: In the first stacked structure, the conductive layer of the portion containing the first channel structure is connected to the conductive layer of the portion containing the second channel structure, and the connection structure connects the contact structure to the corresponding conductive layer of the portion containing the second channel structure in the first stacked structure.

15. A method for forming a semiconductor structure, characterized in that, include: A stacked structure is formed, the stacked structure including a first stacked structure of conductive layers and a first dielectric layer alternately stacked along a first direction and a second stacked structure including a second dielectric layer and a first dielectric layer alternately stacked along the first direction; A barrier structure is formed between the first stacked structure and the second stacked structure, extending along the first direction and the second direction, wherein the second direction is perpendicular to the first direction; At least two rows of contact structures are formed that at least partially penetrate the second stacked structure along the first direction, and a connection structure is formed that penetrates the barrier structure along a third direction and connects the contact structures to the corresponding conductive layers in the first stacked structure. The at least two rows of contact structures are arranged along the second direction, and the third direction is perpendicular to both the first and second directions.

16. The method according to claim 15, characterized in that, Forming a stacked structure, including: The second dielectric layer and the first dielectric layer are alternately stacked along the first direction to form an initial stacked structure; The method further includes: The initial stacked structure is at least partially penetrated along the first direction to form a plurality of channel holes, the plurality of channel holes including a plurality of barrier holes arranged along the second direction; A sacrificial structure is formed in the plurality of channel holes; A barrier structure extending along the first and second directions between the first stacked structure and the second stacked structure includes: Remove the sacrificial structures from the plurality of barrier holes; Remove the second dielectric layer and the first dielectric layer between some of the adjacent barrier holes along the second direction in the plurality of barrier holes to form a merged barrier hole; Remove part of the second dielectric layer from the merged barrier holes and fill with the barrier layer; Remove the barrier layer from the sidewall of the merged barrier hole, and deposit the first dielectric layer on the sidewall surface after removing the barrier layer; A sacrificial structure is formed on the surface of the first dielectric layer in the merged barrier holes.

17. The method according to claim 16, characterized in that, The plurality of channel holes also includes a plurality of gate line slot holes arranged along the second direction; The method further includes: Remove the sacrificial structures from the plurality of gate line slot holes; The second dielectric layer and the first dielectric layer between adjacent gate line slots along the second direction in the plurality of gate line slot holes are removed to form a gate line slot.

18. The method according to claim 17, characterized in that, Also includes: Remove a portion of the second dielectric layer of the initial stacked structure from the gate line gap; The formation of a stacked structure also includes: The conductive layer is formed in the gate line gap to form the stacked structure.

19. The method according to claim 18, characterized in that, Forming at least two rows of contact structures that at least partially penetrate the second stacked structure along the first direction and a connection structure that penetrates the barrier structure along a third direction and connects the contact structures to the corresponding conductive layers in the first stacked structure, including: The second stacked structure is at least partially penetrated along the first direction to form at least two rows of contact holes arranged along the second direction; The second dielectric layer of the second stacked structure is removed from the contact hole to expose the barrier layer, forming a first contact path; A second contact path is formed by removing the barrier layer from the first contact path along the third direction to expose the corresponding conductive layer; A conductive layer is formed in the contact hole, the first contact path, and the second contact path to form the contact structure and the connection structure.

20. The method according to claim 18 or 19, characterized in that, Also includes: Remove the conductive layer on the sidewall of the gate line gap; A gate line gap structure is formed in the gate line gap.

21. The method according to claim 19 or 20, characterized in that, A barrier structure extending along the first and second directions is formed between the first stacked structure and the second stacked structure, further comprising: Remove the sacrificial structure from the merged barrier holes; Remove the second dielectric layer from the sidewalls of the merged barrier holes; Self-merging barrier holes remove the filled barrier layer; The barrier structure is formed in the merged barrier holes.

22. The method according to any one of claims 16 to 21, characterized in that, The plurality of channel holes also includes a plurality of channel holes arranged along the second direction; The method further includes: Remove the sacrificial structures from the plurality of channel holes; A channel structure is formed in the plurality of channel holes, which at least partially penetrates the first stacked structure along the first direction.

23. A semiconductor device, characterized in that, Includes the semiconductor structure described in any one of claims 1 to 7 or 8 to 14.

24. A storage system, characterized in that, Includes the semiconductor device as described in claim 23 and a controller coupled to said semiconductor device.

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