SONOS memory manufacturing method

Abstract

The invention discloses a method for manufacturing an SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory, which comprises the following steps of: depositing a polycrystalline silicon layer on the surface of a gate dielectric layer, carrying out photoetching to form selection tube grid polycrystalline silicon and storage tube grid polycrystalline silicon which are spaced in pairs, only opening a region between the left and right adjacent selection tube grid polycrystalline silicon through photoetching, and carrying out ion implantation on the left and right adjacent selection tube grid polycrystalline silicon during ion implantation. The ion implantation region is limited between the left and right adjacent selection tube grid polycrystalline silicon, and no redundant selection tube threshold voltage ion implantation region exists between the selection tube grid polycrystalline silicon and the storage tube grid polycrystalline silicon, so that the threshold voltage change and electric leakage of the selection tube can be avoided, the electric leakage problem of the GIDL is effectively improved, and the service life of the GIDL is prolonged. And the device performance and reliability are improved.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and in particular to a method for manufacturing SONOS memory. Background Technology

[0002] As market demands for higher integration levels in Flash memory devices continue to increase, the contradiction between the reliability of data storage and the operating speed, power consumption, and size of traditional Flash devices is becoming increasingly prominent. SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) non-volatile memory, due to its small cell size, low operating voltage, and compatibility with CMOS processes, is widely used in various embedded electronic products. Continuous improvements to SONOS technology will drive the development of semiconductor memory towards miniaturization, high performance, large capacity, and low cost.

[0003] The cell structure of a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory includes a storage transistor and a select transistor. The gate dielectric layer of both devices experiences a greater longitudinal electric field during memory operation than that of CMOS devices, resulting in significant gate-induced leakage current (GIDL). While the channel of the SONOS storage transistor already has a high concentration of N-type impurities to form dissipation, the doping concentration of the lightly doped drain region (LDD) required for the storage cell is lower than that of the select transistor.

[0004] Common SONOS memory manufacturing methods include the following steps: 1. A gate dielectric layer is formed on a substrate 10, wherein the gate dielectric layer is composed of ONO (Oxide-Nitride-Oxide) dielectric layers 111 and gate oxide layers 112 arranged sequentially and alternately from right to left; as shown in the figure. Figure 1 As shown; 2. Photoresist (PR) is coated on the gate dielectric layer. The photoresist on the gate oxide layer 112 is removed by photolithography, leaving the photoresist on the ONO dielectric layer 111. Figure 2 As shown; 3. Perform ion implantation to form a selector SG threshold voltage ion implantation region 113 on the surface of the substrate 10 under the gate oxide layer 112, such as... Figure 3 As shown; IV. Removal of photoresist by dry and / or wet methods, such as Figure 4 As shown; 5. A polysilicon layer 114 is grown on the upper surface of the gate dielectric layer, such as... Figure 5 As shown; 6. Photoresist (PR) is coated on the upper surface of the polysilicon layer 114. Photolithography is used to remove the photoresist between the memory gate regions and the select gate regions, forming spaced photoresist strips for the memory gate regions and select gate regions. Two spaced photoresist strips for the left and right memory gate regions are formed above the same ONO (Oxide-Nitride-Oxide) dielectric layer 111, and two spaced photoresist strips for the left and right select gate regions are formed above the same gate oxide layer 112. Figure 6 As shown; VII. Etching to remove the polysilicon layer 114 exposed by photolithography in step six, as shown... Figure 7 As shown; 8. Dry and / or wet methods are used to remove the photoresist, forming two spaced-apart gate polysilicon SGs for the select transistors and gate polysilicon CGs for the memory transistors. Two spaced-apart gate polysilicon CGs for the memory transistors are formed above the same ONO (Oxide-Nitride-Oxide) dielectric layer 111, and two spaced-apart gate polysilicon SGs for the select transistors are formed above the same gate oxide layer 112. Figure 8 As shown.

[0005] In common SONOS memory manufacturing methods, select-transistor threshold voltage ion implantation is performed before depositing the polysilicon layer 114. This results in excess select-transistor threshold voltage ion implantation regions 113 on the surface of the substrate 10 below the gate dielectric layer between the selected-transistor gate polysilicon SG and the memory gate polysilicon CG. Figure 7 , Figure 8 As shown, the excess selector threshold voltage ion implantation region 113 will cause the selector gate-induce drain leakage current (GIDL), which will cause a change in the selector threshold voltage Vt and leakage current, thus reducing the device performance. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a SONOS memory manufacturing method that can avoid changes in the threshold voltage Vt of the select transistor and leakage current, and effectively improve the leakage current problem of GIDL (gate-induce drain leakage current) in the select transistor region.

[0007] To solve the above-mentioned technical problems, the present invention provides a SONOS memory manufacturing method, which includes the following steps: S1. A gate dielectric layer is formed on the substrate 10, the gate dielectric layer being composed of an ONO dielectric layer 111 and a gate oxide layer 112 arranged sequentially and alternately from left to right; S2. A polysilicon layer 114 is grown on the upper surface of the gate dielectric layer; S3. Photoresist is coated on the upper surface of the polysilicon layer 114, and then photolithography is used to remove the photoresist between each memory gate region and select gate region to expose the polysilicon layer 114, forming photoresist tapes for memory gate regions and select gate regions spaced apart. Two spaced left and right memory gate region photoresist tapes are formed above the same ONO dielectric layer 111, and two spaced left and right select gate region photoresist tapes are formed above the same gate oxide layer 112. S4. Etch away the polysilicon layer 114 exposed by photolithography; S5. Remove the photoresist to form two spaced-apart gate polysilicon for select transistors and two spaced-apart gate polysilicon for memory transistors. Two spaced-apart gate polysilicon CGs for memory transistors are formed above the same ONO dielectric layer 111, and two spaced-apart gate polysilicon SGs for select transistors are formed above the same gate oxide layer 112. S6. Photoresist is applied to cover the polysilicon layer 114 and the upper surface of the gate dielectric layer; then photolithography is used to remove the photoresist between the gate polysilicon layers SG of the two adjacent left and right select transistors, the photoresist on the right side of the left select transistor gate polysilicon layer SG, and the photoresist on the left side of the right select transistor gate polysilicon layer SG, exposing the gate oxide layer 112 between the two adjacent left and right select transistor gate polysilicon layers SG, while retaining the photoresist between the gate polysilicon layers CG of the memory transistors, between the gate polysilicon layers CG of the memory transistors and the gate polysilicon layers SG of the select transistors, and above the gate polysilicon layers CG of the memory transistors. S7. Ion implantation is performed at a tilted angle at the gate oxide layer 112 without photoresist coverage to form a selector threshold voltage ion implantation region 113. The selector threshold voltage ion implantation region 113 is located between the left and right adjacent selector gate polysilicon SG, the left part of the right selector gate polysilicon SG, and the surface layer of the substrate 10 under the gate oxide layer 112 under the right part of the left selector gate polysilicon SG. S8. Remove photoresist; S9. Proceed with subsequent processes to manufacture the SONOS memory.

[0008] Preferably, the ONO dielectric layer 111 is a silicon oxide-silicon nitride-silicon oxide stack; The gate oxide layer 112 is silicon oxide.

[0009] Preferably, in step S1, a P-well is formed on the upper part of the substrate 10, and a gate dielectric layer is formed on the P-well of the substrate 10.

[0010] Preferably, in step S1, the upper surface of the substrate 10 under the ONO dielectric layer 111 corresponding to the gate polysilicon of the memory transistor is doped with N-type ions.

[0011] Preferably, in step S7, P-type ion Halo implantation is performed at a tilted angle at the gate oxide layer 112 that is not covered by photoresist.

[0012] Preferably, the P-type ion is a boron ion.

[0013] Preferably, the depth of Halo implantation of P-type ions is 150 Å-200 Å.

[0014] Preferably, the energy for Halo implantation of P-type ions is 8 keV to 12 keV.

[0015] Preferably, the dose of P-type ion Halo implantation is 4E13 / cm2 to 7E13 / cm2.

[0016] Preferably, the set angle is a lateral included angle of 25° to 35°.

[0017] The SONOS memory manufacturing method of the present invention first deposits a polysilicon layer 114 on the surface of the gate dielectric layer, and forms two spaced-apart select transistor gate polysilicon SG and memory transistor gate polysilicon CG by photolithography. Then, the region between the left and right adjacent select transistor gate polysilicon SG is opened by photolithography. During ion implantation, the ion implantation region is limited to the left and right adjacent select transistor gate polysilicon SG. There is no extra select transistor threshold voltage ion implantation region between the select transistor gate polysilicon SG and the memory transistor gate polysilicon CG, which can avoid changes in the select transistor threshold voltage Vt and leakage current. This effectively improves the GIDL (gate-induce drain leakage) leakage current problem in the select transistor region and improves device performance and reliability. Attached Figure Description

[0018] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figures 1 to 8 This is a vertical cross-sectional diagram of each step in a common SONOS memory manufacturing process.

[0020] Figures 9 to 15 This is a vertical cross-sectional schematic diagram of each step in an embodiment of the SONOS memory manufacturing method of the present invention.

[0021] Explanation of reference numerals in the attached figures: 10 Substrate; 111 ONO dielectric layer; 112 Gate oxide layer; 114 Polysilicon layer; 113 Selector threshold voltage ion implantation region. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] The terms "first," "second," and similar words used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "front," and "back" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. Example

[0025] A method for manufacturing SONOS memory includes the following steps: S1. A gate dielectric layer is formed on the substrate 10, the gate dielectric layer being composed of ONO (Oxide-Nitride-Oxide) dielectric layers 111 and gate oxide layers 112 arranged sequentially and alternately from left to right, such as... Figure 1 As shown; S2. A polysilicon layer 114 is grown on the upper surface of the gate dielectric layer, such as... Figure 9 As shown; S3. Photoresist (PR) is coated on the upper surface of the polysilicon layer 114. Then, photolithography is used to remove the photoresist between the memory gate regions and the select gate regions, exposing the polysilicon layer 114, forming photoresist strips for the memory gate regions and select gate regions spaced apart. Two spaced photoresist strips for the left and right memory gate regions are formed above the same ONO dielectric layer 111, and two spaced photoresist strips for the left and right select gate regions are formed above the same gate oxide layer 112. Figure 10 As shown; S4. Etching to remove the polysilicon layer 114 exposed by photolithography in step S3, as shown. Figure 11 As shown; S5. Remove the photoresist using dry and / or wet methods to form two spaced-apart select transistor gate polysilicon SGs and memory transistor gate polysilicon CGs. Two spaced-apart left and right memory transistor gate polysilicon CGs are formed above the same ONO dielectric layer 111, and two spaced-apart select transistor gate polysilicon SGs are formed above the same gate oxide layer 112. Figure 12 As shown; S6. Apply photoresist to cover the polysilicon layer 114 and the upper surface of the gate dielectric layer; then, use photolithography to remove the photoresist between the gate polysilicon layers SG of the two adjacent select transistors, the photoresist on the right side of the left select transistor gate polysilicon layer SG, and the photoresist on the left side of the right select transistor gate polysilicon layer SG, exposing the gate oxide layer 112 between the two adjacent select transistor gate polysilicon layers SG, while retaining the photoresist between the gate polysilicon layers CG of the memory transistors, between the gate polysilicon layers CG of the memory transistors and the gate polysilicon layers SG of the select transistors, and above the gate polysilicon layers CG of the memory transistors. Figure 13 As shown; S7. Ion implantation at a tilted angle is performed on the gate oxide layer 112 without photoresist coverage to form a selector threshold voltage ion implantation region 113. The selector threshold voltage ion implantation region 113 is located between the left and right adjacent selector gate polysilicon SGs, on the left side of the right selector gate polysilicon SG, and on the surface of the substrate 10 under the gate oxide layer 112 below the right side of the left selector gate polysilicon SG. Figure 14 As shown; tilting the device at a set angle during injection can prevent excessive lateral diffusion; S8. Dry and / or wet removal of photoresist, such as... Figure 15 As shown.

[0026] S9. Proceed with subsequent processes to manufacture the SONOS memory.

[0027] The SONOS memory manufacturing method in Example 1 first deposits a polysilicon layer 114 on the surface of the gate dielectric layer, and then forms two spaced-apart gate polysilicon SGs for the select transistors and gate polysilicon CGs for the memory transistors by photolithography. Then, the region between the left and right adjacent gate polysilicon SGs is opened by photolithography. During ion implantation, the ion implantation region is limited to the left and right adjacent gate polysilicon SGs. There is no extra select transistor threshold voltage ion implantation region between the select transistor gate polysilicon SGs and the memory transistor gate polysilicon CGs, which can avoid changes in the select transistor threshold voltage Vt and leakage current. This effectively improves the GIDL (gate-induce drain leakage) leakage current problem in the select transistor region and improves device performance and reliability. Example

[0028] Based on the SONOS memory manufacturing method of Embodiment 1, the ONO dielectric layer 111 is a silicon oxide-silicon nitride-silicon oxide stack; The gate oxide layer 112 is silicon oxide. Example

[0029] According to the SONOS memory manufacturing method of Embodiment 1, in step S1, a P-well is formed on the upper part of the substrate 10, and a gate dielectric layer is formed on the P-well of the substrate 10.

[0030] Preferably, in step S1, the upper surface of the substrate 10 under the ONO dielectric layer 111 corresponding to the gate polysilicon of the memory transistor is doped with N-type ions.

[0031] Preferably, in step S7, a Halo implantation of P-type ions (e.g., boron ions) at a tilted angle is performed at the gate oxide layer 112 that is not covered by photoresist.

[0032] Preferably, the depth of Halo implantation of P-type ions (e.g., boron ions) is 150 Å–200 Å.

[0033] Preferably, the Halo implantation energy for P-type ions (e.g., boron ions) is 8 keV to 12 keV.

[0034] Preferably, the dose of P-type ions (e.g., boron ions) implanted in Halo is 4E13 / cm2 to 7E13 / cm2.

[0035] Preferably, the set angle is a lateral included angle of 25° to 35° (e.g., 30°).

[0036] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a SONOS memory, characterized in that, It includes the following steps: S1. A gate dielectric layer is formed on a substrate (10), the gate dielectric layer being composed of an ONO dielectric layer (111) and a gate oxide layer (112) arranged sequentially and alternately from left to right; S2. A polysilicon layer (114) is grown on the upper surface of the gate dielectric layer; S3. Photoresist is coated on the upper surface of the polysilicon layer (114), and then photolithography is used to remove the photoresist between each memory gate region and select gate region to expose the polysilicon layer (114), forming photoresist tapes for memory gate regions and select gate regions spaced apart. Two spaced left and right memory gate regions photoresist tapes are formed above the same ONO dielectric layer (111), and two spaced left and right select gate regions photoresist tapes are formed above the same gate oxide layer (112). S4. Etch away the polysilicon layer exposed by photolithography (114); S5. Remove the photoresist to form two spaced-apart gate polysilicon for select transistors and two spaced-apart gate polysilicon for memory transistors. Two spaced-apart gate polysilicon (CG) for memory transistors are formed above the same ONO dielectric layer (111), and two spaced-apart gate polysilicon (SG) for select transistors are formed above the same gate oxide layer (112). S6. Photoresist is applied to cover the polysilicon layer (114) and the upper surface of the gate dielectric layer; then photolithography is used to remove the photoresist between the gate polysilicon (SG) of two adjacent left and right select transistors, the photoresist on the right side of the left select transistor gate polysilicon (SG), and the photoresist on the left side of the right select transistor gate polysilicon (SG), exposing the gate oxide layer (112) between the two adjacent left and right select transistor gate polysilicon (SG), while retaining the photoresist between the gate polysilicon (CG) of the memory transistor, between the gate polysilicon (CG) of the memory transistor and the gate polysilicon (SG) of the select transistor, and above the gate polysilicon (CG) of the memory transistor; S7. Ion implantation is performed at a tilted angle at the gate oxide layer (112) without photoresist coverage to form a select tube threshold voltage ion implantation region (113). The select tube threshold voltage ion implantation region (113) is located on the substrate (10) surface layer under the gate oxide layer (112) under the left and right adjacent select tube gate polysilicon (SG), the left part of the right select tube gate polysilicon (SG), and the right part of the left select tube gate polysilicon (SG). S8. Remove photoresist; S9. Proceed with subsequent processes to manufacture the SONOS memory.

2. The SONOS memory manufacturing method according to claim 1, characterized in that, The ONO dielectric layer (111) is a silicon oxide-silicon nitride-silicon oxide stack; The gate oxide layer (112) is silicon oxide.

3. The SONOS memory manufacturing method according to claim 1, characterized in that, In step S1, a P-well is formed on the upper part of the substrate (10), and a gate dielectric layer is formed on the P-well of the substrate (10).

4. The SONOS memory manufacturing method according to claim 1, characterized in that, In step S1, N-type ion doping is performed on the upper surface of the substrate (10) under the ONO dielectric layer (111) corresponding to the gate polysilicon of the storage tube.

5. The SONOS memory manufacturing method according to any one of claims 1 to 4, characterized in that, In step S7, P-type ion Halo implantation is performed at a tilted angle at the gate oxide layer (112) that is not covered by photoresist.

6. The SONOS memory manufacturing method according to claim 5, characterized in that, The P-type ion is a boron ion.

7. The SONOS memory manufacturing method according to claim 6, characterized in that, The depth of Halo implantation of P-type ions was 150 Å–200 Å.

8. The SONOS memory manufacturing method according to claim 6, characterized in that, The energy for Halo implantation of P-type ions is 8 keV to 12 keV.

9. The SONOS memory manufacturing method according to claim 6, characterized in that, The dose of P-type ion Halo implantation is 4E13 / cm2 to 7E13 / cm2.

10. The SONOS memory manufacturing method according to claim 1, characterized in that, The set angle is a lateral angle of 25° to 35°.

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