Semiconductor structure and forming method thereof
By covering the first device on the bottom and sidewalls of the interconnect structure in the semiconductor structure, the contact area is increased, which solves the problem of insufficient performance of existing semiconductor devices and achieves performance improvement.
Patent Information
- Application Number
- CN202411164754.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-22
- Publication Date
- 2026-03-03
AI Technical Summary
Existing semiconductor devices are struggling to meet the size and power consumption requirements of static random access memory (SRAM) and dynamic random access memory (DRAM). Traditional memory devices are gradually transitioning to non-volatile memory, but their performance still needs improvement.
A first device and a first interconnect structure are formed within a first dielectric layer, such that the first device covers the bottom and sidewalls of the first interconnect structure, thereby increasing the contact area and reducing the on-resistance.
By increasing the contact area between the interconnect structure and the top electrode layer, the on-resistance is reduced, thereby improving the performance of the semiconductor structure.
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Figure CN121604440A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Traditional memory devices are mainly made of semiconductor materials based on electron charge. With the rapid development of computing technology, existing memory devices are unable to meet the size and power consumption requirements of memory such as static random access memory (SRAM) and dynamic random access memory (DRAM).
[0003] With the development of semiconductor technology, traditional memory devices are gradually transitioning to non-volatile memory. Among them, magnetic random access memory (MRAM) is a type of non-volatile magnetic random access memory. The term "non-volatile" means that the memory can still be intact after the power is turned off. It has high-speed read / write capabilities and is compatible with existing CMOS technology. Its application prospects are very promising, and it is expected to dominate the next generation of memory market.
[0004] However, the performance of currently developed semiconductor devices needs to be improved. Summary of the Invention
[0005] In view of this, embodiments of the present invention provide a semiconductor structure and a method for forming the same, which can improve the performance of the semiconductor structure.
[0006] This invention provides a semiconductor structure, including: a substrate; a first dielectric layer located on the substrate; a first interconnect structure located within the first dielectric layer; and a first device located within the first dielectric layer, wherein the first device covers the bottom and sidewalls of the first interconnect structure. The first device includes a stacked first bottom electrode layer, a first magnetic tunnel junction structure layer, and a first top electrode layer, wherein the first top electrode layer is closest to the first interconnect structure and is electrically connected to the first interconnect structure.
[0007] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first device layer on the substrate, wherein the step of forming the first device layer comprises: forming a first dielectric layer on the substrate; forming a first device and a first interconnect structure located within the first dielectric layer, wherein the first device covers the bottom and sidewalls of the first interconnect structure, the first device comprising a stacked first bottom electrode layer, a first magnetic tunnel junction structure layer and a first top electrode layer, wherein the first top electrode layer is closest to the first interconnect structure and is electrically connected to the first interconnect structure.
[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0009] In the semiconductor structure provided by the embodiments of the present invention, the first interconnect structure and the first device are both located within the first dielectric layer, and the first device covers the bottom and sidewalls of the first interconnect structure. The first interconnect structure is in contact with the sidewalls and bottom surface of the first top electrode layer, which can increase the contact area between the first interconnect structure and the first top electrode layer and reduce the on-resistance, thereby improving the performance of the semiconductor structure.
[0010] In the semiconductor structure formation method provided in the embodiments of the present invention, a first device and a first interconnect structure are formed in a first dielectric layer, and the first device covers the bottom and sidewalls of the first interconnect structure, thereby making the first interconnect structure in contact with the sidewalls and bottom surface of the first top electrode layer. This can increase the contact area between the first interconnect structure and the first top electrode layer, reduce the on-resistance, and thus improve the performance of the semiconductor structure. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of a corresponding embodiment of the semiconductor structure of the present invention;
[0012] Figure 2 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;
[0013] Figures 3 to 15 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention;
[0014] Figure 16 This is a schematic diagram of the structure of the second embodiment of the semiconductor structure formation method of the present invention;
[0015] Figure 17 This is a schematic diagram of the third embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0016] As described in the background section, the performance of currently developed semiconductor devices needs to be improved.
[0017] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure. By forming a first device and a first interconnect structure within a first dielectric layer, and ensuring that the first device covers the bottom and sidewalls of the first interconnect structure, the first interconnect structure is in contact with both the sidewalls and bottom surface of the first top electrode layer. This increases the contact area between the first interconnect structure and the first top electrode layer, reduces the on-resistance, and thus improves the performance of the semiconductor structure.
[0018] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described exemplarily below with reference to the accompanying drawings.
[0019] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 1 As shown, in this embodiment, the semiconductor structure includes: a substrate (not shown), a first dielectric layer 102 located on the substrate; a first interconnect structure 120 located within the first dielectric layer 102; and a first device 110 located within the first dielectric layer 102, wherein the first device 110 covers the bottom and sidewalls of the first interconnect structure 120. The first device 110 includes a stacked first bottom electrode layer 104, a first magnetic tunnel junction structure layer 106, and a first top electrode layer 108. The first top electrode layer 108 is closest to the first interconnect structure 120 and is electrically connected to the first interconnect structure 120.
[0020] By making the first device 110 contact the bottom and sidewalls of the first interconnect structure 120, the contact area between the first interconnect structure 120 and the first device 110 can be increased, the on-resistance can be reduced, and thus the performance of the semiconductor structure can be improved.
[0021] The substrate is used to provide a process platform for subsequent process manufacturing.
[0022] In this embodiment, the substrate serves as a process platform for forming magnetic random access memory (MRAM). Specifically, the MRAM device is a spin-transfer torque magnetoresistive random access memory (STT-MRAM).
[0023] In other embodiments, the substrate may also provide a process platform for forming other types of MOS devices, such as 3D NAND flash memory devices, NOR flash memory, static random access memory (SRAM), etc., which are not limited herein.
[0024] In this embodiment, the substrate includes a substrate made of silicon. In other embodiments, the substrate material may also include other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.
[0025] In this embodiment, a transistor is formed in the substrate. The transistor may include one or both of NMOS and PMOS transistors.
[0026] Specifically, the transistor includes a gate structure and source / drain doped regions located in the substrate on both sides of the gate structure.
[0027] In this embodiment, the substrate may further include an interlayer dielectric layer and contact hole plugs that penetrate the interlayer dielectric layer and contact the source / drain doped regions. The interlayer dielectric layer covers the surface of the source / drain doped regions and the sidewalls of the gate structure. Other types of semiconductor devices may also be formed in the substrate, and functional structures such as resistive structures and conductive structures may also be formed in the substrate.
[0028] In this embodiment, an intermetallic dielectric layer (IMD) is also formed in the substrate. The intermetallic dielectric layer is used to achieve electrical isolation between metal interconnects in the subsequent process.
[0029] In this embodiment, a metal layer 100 is formed on the substrate, and the metal layer 100 is used to realize the connection between the substrate and the subsequently formed semiconductor device.
[0030] In this embodiment, the semiconductor structure further includes a first conductive plug 112 located within the first dielectric layer 102 at the bottom of the first device 110. The first conductive plug 112 is located between the first bottom electrode layer 104 and the substrate, and is electrically connected to the first bottom electrode layer 104.
[0031] The first conductive plug 112 is used to realize the electrical connection between the first device 110 and the substrate. For example, the first conductive plug 112 is used to realize the electrical connection between the first device 110 and the metal layer 100.
[0032] In this embodiment, the material of the first conductive plug 112 may include one or more of Cu, W, Al, TiN, TaN, and Ti.
[0033] In one specific embodiment, the material of the first conductive plug 112 is Cu.
[0034] In this embodiment, the first dielectric layer 102 is used to achieve electrical isolation between the first conductive plugs 112 in the later process. The first dielectric layer 102 is also used to achieve isolation between subsequent first devices 110.
[0035] In this embodiment, the material of the first dielectric layer 102 includes low-k dielectric materials (low-k dielectric materials refer to dielectric materials with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9), ultra-low-k dielectric materials (ultra-low-k dielectric materials refer to dielectric materials with a relative permittivity less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc.
[0036] Specifically, the material of the first dielectric layer 102 is a low-k dielectric material, which helps to reduce the parasitic capacitance between the subsequent interconnect structures, and thus helps to reduce the subsequent RC delay.
[0037] In this embodiment, the first dielectric layer 102 is located above the metal layer 100.
[0038] It should be noted that, in some other embodiments, the semiconductor structure further includes: a second dielectric layer located between the first dielectric layer and the substrate; and a first conductive plug located within the second dielectric layer and electrically connected to the first bottom electrode layer. That is, the first conductive plug and the first device are located within different dielectric layers.
[0039] For a description of the material of the second dielectric layer, please refer to the relevant description of the first dielectric layer 102, which will not be repeated here.
[0040] The first device 110 can store and retrieve data.
[0041] In this embodiment, the first device 110 may include a stacked first bottom electrode (BE) layer 104, a first magnetic tunnel junction (MTJ) structure layer 106, and a first top electrode (TE) layer 108; wherein, among the first bottom electrode layer 104, the first magnetic tunnel junction structure layer 106, and the first top electrode layer 108, the first top electrode layer 108 is closest to the first interconnect structure 120 and is electrically connected to the first interconnect structure 120.
[0042] The first bottom electrode layer 104 is used to electrically connect the first conductive plug 112 and the first magnetic tunnel junction structure 106.
[0043] In this embodiment, the material of the first bottom electrode layer 104 includes one or more of tantalum nitride, tantalum, titanium, and titanium nitride.
[0044] In one specific embodiment, the first bottom electrode layer 104 is a single-layer structure, and the material of the first bottom electrode layer 204 is tantalum nitride.
[0045] The first magnetic tunnel structure layer 106 is used to store data by changing its own magnetization direction.
[0046] In one specific embodiment, the first magnetic tunnel junction structure layer 106 may include a stacked first magnetic layer (not shown), a barrier layer (not shown), and a second magnetic layer (not shown), with the second magnetic layer being closest to the first top electrode layer 108.
[0047] In this embodiment, the first magnetic layer can serve as a magnetic reference layer, and the magnetization direction of the magnetic reference layer is fixed, thereby enabling the magnetic reference layer to serve as a reference layer for defining the magnetization direction of the magnetic free layer.
[0048] In this embodiment, the material of the first magnetic layer includes a ferromagnetic metal material, such as CoFeB or CoFe.
[0049] In this embodiment, the barrier layer is the core device of the first magnetic tunnel junction structure layer 106, and its formation quality determines the performance of the first magnetic tunnel junction structure layer, such as increasing the tunnel magnetoresistive ratio (TMR ratio) and reducing leakage current. Correspondingly, the performance of the formed first device 110 is also improved.
[0050] In this embodiment, the material of the barrier layer includes MgO. In other embodiments, the material of the barrier layer may also include SrO, BaO, RaO, SiO2, Al2O3, HfO2, NiO, GdO, Ta2O5, MoO2, TiO2, or WO2, etc.
[0051] In this embodiment, the second magnetic layer can be used as a magnetically free layer, and the magnetization direction of the magnetically free layer has two stable orientations, which are parallel or opposite to the magnetization direction of the magnetically reference layer, respectively, so that the magnetic tunnel junction can be in a low-resistance state or a high-resistance state.
[0052] In this embodiment, the material of the second magnetic layer includes ferromagnetic metal materials, such as CoFeB or CoFe.
[0053] The first top electrode layer 108 is used to realize the electrical connection between the first magnetic tunnel junction structure layer 106 and external circuits, other interconnect structures or other components.
[0054] For example, the first top electrode layer 108 is used to realize the electrical connection between the first magnetic tunnel junction structure layer 106 and the first interconnect structure 120.
[0055] In this embodiment, the material of the first top electrode layer 108 includes one or more of tantalum nitride, tantalum, titanium, and titanium nitride.
[0056] In one specific embodiment, the first top electrode layer 108 is a single-layer structure, and the material of the first top electrode layer 208 is tantalum nitride.
[0057] The first interconnect structure 120 is used to realize the electrical connection between the first device 110 and external circuits, other interconnect structures or other components.
[0058] In this embodiment, the width of the first interconnect structure 120 along the direction parallel to the substrate surface cannot be too large or too small. If the width is too large, the first interconnect structure 120 will occupy a large area along the direction of the substrate surface, increasing device power consumption; if the width is too small, it will easily lead to poor electrical connection between the first top electrode layer 108 and other devices, affecting the performance of the first device 110. Based on this, in this embodiment, the width of the first interconnect structure 120 along the direction parallel to the substrate surface is 10nm to 100nm.
[0059] In this embodiment, the material of the first interconnect structure 120 is copper. In other embodiments, depending on the actual process, the material of the first interconnect structure 120 may also include conductive materials such as tungsten, aluminum, and cobalt.
[0060] See next Figure 1 The semiconductor structure also includes a second interconnect structure 122, which is located in the first dielectric layer between adjacent first devices 110 and electrically connected to the first bottom electrode layers 104 on both sides to realize electrical connection between different first devices 110.
[0061] By connecting adjacent first devices 110, the first devices 110 can be accessed in parallel, improving the speed of data reading and storage.
[0062] In this embodiment, the top surface height of the second interconnect structure 122 is flush with the top surface height of the first device 110, thereby providing a flat surface for forming other structures above the second interconnect structure 122 and the first device 110.
[0063] In this embodiment, the material of the second interconnect structure 122 is copper.
[0064] In other embodiments, depending on the actual process, the material of the second interconnect structure 122 may also include conductive materials such as tungsten, aluminum, and cobalt.
[0065] See next Figure 1 The semiconductor structure also includes a third dielectric layer 144, located on top of the first device 110 and the first interconnect structure 120.
[0066] The third dielectric layer 144 is used to achieve electrical isolation between the second conductive plugs 146 in the later stages of the manufacturing process. The third dielectric layer 144 is also used to achieve isolation between the second devices 140.
[0067] In this embodiment, the material of the third dielectric layer 144 is the same as the material of the first dielectric layer 102.
[0068] See next Figure 1 The semiconductor structure further includes: a second device 140 buried in the third dielectric layer 144, and the second device 140 includes: a second bottom electrode layer 134; a second magnetic tunnel junction structure layer 136 located on top of the second bottom electrode layer 134; and a second top electrode layer 138 located on top of the second magnetic tunnel junction structure layer 136.
[0069] The second bottom electrode layer 134, the second magnetic tunnel junction structure layer 136, and the second top electrode layer 138 are stacked sequentially along the longitudinal direction; wherein, among the second bottom electrode layer 134, the second magnetic tunnel junction structure layer 136, and the second top electrode layer 138, the second bottom electrode layer 134 is closest to the first device 110 and is electrically connected to the first device 110.
[0070] The descriptions of the second bottom electrode layer 134, the second magnetic tunnel junction structure layer 136, and the second top electrode layer 138 can be found in the foregoing descriptions of the first bottom electrode layer 104, the first magnetic tunnel junction structure layer 106, and the first top electrode layer 108, and will not be repeated here in this embodiment.
[0071] In this embodiment, by using a stacked first device 110 and a second device 140, the area of the magnetic storage structure can be efficiently increased within the same spatial area, thereby increasing the capacitance density of the memory by several times.
[0072] See next Figure 1 The semiconductor structure also includes a second conductive plug 146, which is located within a third dielectric layer 144 on top of the second top electrode layer 138 and is electrically connected to the second top electrode layer 138.
[0073] The second conductive plug 146 leads out the electrical properties of the second device 140 and is used to realize the electrical connection between the second device 140 and external circuits, other interconnection structures or other components.
[0074] In this embodiment, the material of the first conductive plug 112 may include one or more of Cu, W, Al, TiN, TaN, and Ti.
[0075] In one specific embodiment, the material of the first conductive plug 112 is Cu.
[0076] See next Figure 1 In this embodiment, when the third dielectric layer 144 is located on top of the first device 110 and the first interconnect structure 120, the second device 140 is stacked with the first device 110, thereby reducing the area occupied by the second device 140 and the first device 110.
[0077] In this case, the semiconductor structure further includes: a fourth dielectric layer 124 located between the third dielectric layer 144 and the first dielectric layer 102; and a third conductive plug 126 located within the fourth dielectric layer 124 and between the second device 140 and the first device 110, wherein the third conductive plug 126 is electrically connected to the first interconnect structure and the second bottom electrode layer 134 of 110.
[0078] The fourth dielectric layer 124 is used to achieve electrical isolation between the third conductive plugs 126. The fourth dielectric layer 124 is also used to achieve electrical isolation between the second devices 130.
[0079] In this embodiment, the fourth dielectric layer 124 is made of a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride, etc.
[0080] Specifically, the material of the fourth dielectric layer 124 is a low-k dielectric material, which helps to reduce the parasitic capacitance between the subsequent interconnect structures, and thus helps to reduce the subsequent RC delay.
[0081] For a description of the material of the fourth dielectric layer 124, please refer to the relevant description of the first dielectric layer 102.
[0082] The third conductive plug 126 is used to realize the electrical connection between the first device 110 and the second device layer. For example, the third conductive plug 126 is located on top of the first interconnect structure 120, and by making the second device 140 electrically connected to the first interconnect structure 120 through the third conductive plug 126, the electrical connection between the first device 110 and the second device layer can be realized.
[0083] In this embodiment, the material of the third conductive plug 126 may include one or more of Cu, W, Al, TiN, TaN, and Ti.
[0084] In one specific embodiment, the material of the third conductive plug 126 is Cu.
[0085] Correspondingly, the second device 140 is located on the third conductive plug 126, and the second bottom electrode layer 134 is electrically connected to the third conductive plug 126.
[0086] In some other embodiments, a third dielectric layer may be located between the first dielectric layer and the substrate. In this case, the second device is located below the first device.
[0087] In one specific embodiment, the second device is stacked with the first device, and the second conductive plug is located between the second top electrode layer and the first bottom electrode layer, and is electrically connected to the second top electrode layer and the first bottom electrode layer.
[0088] See next Figure 1 The semiconductor structure further includes a protective layer 142, which is located at least between the top and sidewalls of the second device 140 and the third dielectric layer 144. That is, the protective layer 142 is located at least between the top of the second device 140 and the third dielectric layer 144, and between the sidewalls of the second device 140 and the third dielectric layer 144.
[0089] The protective layer 142 can be used to protect the sidewalls and top of the second device 140.
[0090] In some other embodiments, the protective layer 142 may also cover the top of the fourth dielectric layer 124 on the side of the second device 140.
[0091] In this embodiment, the material of the protective layer 142 may include one or more of the following: silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, boron carbonitride, and silicon oxide.
[0092] In one specific embodiment, the material of the protective layer 142 includes silicon nitride.
[0093] In this embodiment, when the semiconductor structure includes a protective layer 142, the second conductive plug 146 can be located within the third dielectric layer 144 on top of the second top electrode layer 138 and penetrate the protective layer 142.
[0094] In some other embodiments, the first dielectric layer may be a stacked structure. For example, the first dielectric layer may include a two-layer structure stacked vertically, wherein the first conductive plug may be located within the bottom layer structure and the first device may be located within the top layer structure.
[0095] See Figure 2 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention, and... Figure 1 The similarities between the semiconductor structures shown can be found in the section on Figure 1 The description, and Figure 1 The difference is that the second device 340 is located between the substrate 300 and the first device 310.
[0096] Specifically, the first device 310 and the second device 340 are stacked; wherein, the first device 310 includes a stacked first bottom electrode layer 304, a first magnetic tunnel junction structure layer 306 and a first top electrode layer 308; the second device 340 includes a stacked second bottom electrode layer 334, a second magnetic tunnel junction structure layer 336 and a second top electrode layer 338.
[0097] In this case, the second conductive plug 346 is electrically connected to the second top electrode layer 338 and the first bottom electrode layer 304.
[0098] Furthermore, the second device layer is located above the second dielectric layer 348, and the second bottom electrode layer 334 is located above the first conductive plug 312 and is electrically connected to the first conductive plug 312.
[0099] Figures 3 to 15 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.
[0100] Reference Figures 3 to 7A substrate (not shown) is provided; a first device layer (not identified) is formed on the substrate.
[0101] The substrate is used to provide a process platform for subsequent process manufacturing.
[0102] In this embodiment, the substrate serves as a process platform for forming a magnetic random access memory (MRAM). Specifically, the MRAM device is a spin-transfer torque magnetoresistive random access memory (STT-MRAM).
[0103] In other embodiments, the substrate may also provide a process platform for forming other types of MOS devices, such as 3D NAND flash memory devices, NOR flash memory, static random access memory (SRAM), etc., which are not limited herein.
[0104] In this embodiment, the substrate includes a substrate made of silicon. In other embodiments, the substrate material may also include other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.
[0105] In this embodiment, a transistor is formed in the substrate. The transistor may include one or both of NMOS and PMOS transistors.
[0106] Specifically, the transistor includes a gate structure and source / drain doped regions located in the substrate on both sides of the gate structure.
[0107] In this embodiment, an interlayer dielectric layer and contact hole plugs that penetrate the interlayer dielectric layer and contact the source / drain doped regions are also formed in the substrate. The interlayer dielectric layer covers the surface of the source / drain doped regions and the sidewalls of the gate structure. Other types of semiconductor devices can also be formed in the substrate, and functional structures such as resistive structures and conductive structures can also be formed in the substrate.
[0108] In this embodiment, an intermetallic dielectric layer is also formed in the substrate, which is used to achieve electrical isolation between metal interconnects in the subsequent process.
[0109] like Figure 3 As shown, in this embodiment, a metal layer 200 is formed on the substrate, and the metal layer 200 is used to realize the connection between the substrate and the subsequently formed semiconductor device.
[0110] See Figures 4 to 7 A first device layer (unidentified) is formed on the substrate.
[0111] The first device layer includes a first device, which can store data.
[0112] The steps for forming the first device layer are described in detail below with reference to the accompanying drawings.
[0113] See Figure 4 A first dielectric layer 202 is formed on the substrate.
[0114] The first dielectric layer 202 is used to implement the first conductive plug 212 (see...) Figure 6 Electrical isolation between them. The first dielectric layer 202 is also used to implement the subsequent first device 210 (see Figure 6 Electrical isolation between them.
[0115] In this embodiment, the material of the first dielectric layer 202 includes low-k dielectric materials, ultra-low-k dielectric materials, silicon oxide, silicon nitride, or silicon oxynitride, etc.
[0116] Specifically, the material of the first dielectric layer 202 is a low-k dielectric material, which helps to reduce the parasitic capacitance between the subsequent interconnect structures, and thus helps to reduce the subsequent RC delay.
[0117] In this embodiment, a deposition process (e.g., chemical deposition process) can be used to form a first dielectric layer 202 above the metal layer 200.
[0118] See Figures 5 to 7 This forms a first device 210 and a first interconnect structure 220 located within the first dielectric layer 202.
[0119] In this embodiment, the first device 210 covers the bottom and sidewalls of the first interconnect structure 220. By making the first device 210 contact the bottom and sidewalls of the first interconnect structure 220, the contact area between the first interconnect structure 220 and the first device 210 can be increased, the on-resistance can be reduced, and thus the performance of the semiconductor structure can be improved.
[0120] In this embodiment, the steps of forming the first device 210 and the first interconnect structure 220 located within the first dielectric layer 202 include:
[0121] See Figure 5 A first trench T1 is formed in the first dielectric layer 202.
[0122] The first trench T1 is used to provide space for forming the first device 210 and the first interconnect structure 220.
[0123] In this embodiment, the bottom of the first trench T1 is located in the first dielectric layer 202, that is, the first trench T1 does not penetrate the first dielectric layer 202.
[0124] In this embodiment, dry etching or wet etching can be used to remove a portion of the thickness of the first dielectric layer 202 and form a first trench T1 in the first dielectric layer 202.
[0125] See Figure 6 A first device 210 is formed with conformal coverings at the bottom and sidewalls of the first trench T1.
[0126] In this embodiment, the first device 210 may include a stacked first bottom electrode (BE) layer 204, a first magnetic tunnel junction (MTJ) structure layer 206, and a first top electrode (TE) layer 208; wherein, among the first bottom electrode layer 204, the first magnetic tunnel junction structure layer 206, and the first top electrode layer 208, the first top electrode layer 208 is closest to and electrically connected to the subsequently formed first interconnect structure 220.
[0127] Accordingly, see [link / reference] Figure 7 The step of forming a first device 210 with conformal coverage at the bottom and sidewalls of the first trench T1 includes: forming a first bottom electrode layer 204 with conformal coverage at the sidewalls and bottom of the first trench T1; forming a first magnetic tunnel junction structure layer 206 with conformal coverage at the first bottom electrode layer 204; and forming a first top electrode layer 208 with conformal coverage at the first magnetic tunnel junction structure layer 206.
[0128] The first bottom electrode layer 204 is used to electrically connect the first conductive plug 212 and the first magnetic tunnel junction structure 206.
[0129] In this embodiment, the material of the first bottom electrode layer 204 is one or more of tantalum nitride, tantalum, titanium and titanium nitride.
[0130] In one specific embodiment, the first bottom electrode layer 204 is a single-layer structure, and the material of the first bottom electrode layer 204 is tantalum nitride.
[0131] The first magnetic tunnel structure layer 206 is used to store data by changing its own magnetization direction.
[0132] In one specific embodiment, the first magnetic tunnel junction structure layer 206 may include a stacked first magnetic layer (unidentified), a barrier layer (unidentified), and a second magnetic layer (unidentified), with the second magnetic layer being closest to the first top electrode layer 208.
[0133] In this embodiment, the first magnetic layer can serve as a magnetic reference layer, and the magnetization direction of the magnetic reference layer is fixed, thereby enabling the magnetic reference layer to serve as a reference layer for defining the magnetization direction of the magnetic free layer.
[0134] In this embodiment, the material of the first magnetic layer includes a ferromagnetic metal material, such as CoFeB or CoFe.
[0135] In this embodiment, the barrier layer is the core device of the first magnetic tunnel junction structure layer 206, and its formation quality determines the performance of the first magnetic tunnel junction structure layer. For example, by improving the formation quality of the barrier layer, the tunnel magnetoresistance ratio (TMR ratio) can be increased and the leakage current can be reduced. Correspondingly, the performance of the first device 210 is also improved.
[0136] In this embodiment, the material of the barrier layer includes MgO.
[0137] In other embodiments, the material of the barrier layer may also include SrO, BaO, RaO, SiO2, Al2O3, HfO2, NiO, GdO, Ta2O5, MoO2, TiO2, or WO2, etc.
[0138] In this embodiment, the second magnetic layer can be used as a magnetically free layer, and the magnetization direction of the magnetically free layer has two stable orientations, which are parallel or opposite to the magnetization direction of the magnetically reference layer, respectively, so that the magnetic tunnel junction can be in a low-resistance state or a high-resistance state.
[0139] In this embodiment, the material of the second magnetic layer includes ferromagnetic metal materials, such as CoFeB or CoFe.
[0140] The first top electrode layer 208 is used to realize the electrical connection between the first magnetic tunnel junction structure layer 206 and external circuits, other interconnect structures or other components. For example, the first top electrode layer 208 is used to realize the electrical connection between the first magnetic tunnel junction structure layer 206 and the first interconnect structure 220.
[0141] In this embodiment, the material of the first top electrode layer 208 is one or more of tantalum nitride, tantalum, titanium and titanium nitride.
[0142] In one specific embodiment, the first top electrode layer 208 is a single-layer structure, and the material of the first top electrode layer 208 is tantalum nitride.
[0143] In this embodiment, atomic layer deposition (ALD) is used to form a first bottom electrode layer 204, a first magnetic tunnel junction structure layer 206, and a first top electrode layer 208. ALD is a self-limiting reaction process, allowing the deposited film to reach a single-atom thickness. Using ALD facilitates precise control over the thicknesses of the first bottom electrode layer 204, the first magnetic tunnel junction structure layer 206, and the first top electrode layer 208. Furthermore, films prepared by ALD exhibit good bonding strength, consistent film thickness, good compositional uniformity, and good shape retention, which helps improve the thickness uniformity and film quality of the first bottom electrode layer 204, the first magnetic tunnel junction structure layer 206, and the first top electrode layer 208.
[0144] In other embodiments, depending on the actual process, physical vapor deposition or other suitable processes may be used to form the first bottom electrode layer 204, the first magnetic tunnel junction structure layer 206, and the first top electrode layer 208.
[0145] See Figure 7 A first interconnect structure 220 is formed in a first trench T1 in which the first device 210 is formed.
[0146] The first interconnect structure 220 is used to realize the electrical connection between the first device 210 and external circuits, other interconnect structures or other components.
[0147] In this embodiment, the step of forming the first interconnect structure 220 includes: filling the first trench T1 where the first device 210 is formed with metal material for forming the first top electrode layer 208, so as to serve as the first interconnect structure 220.
[0148] Specifically, the step of forming the first interconnect structure 220 further includes: planarizing the metal material and removing the metal material located on top of the first dielectric layer 202. During the planarization process, the first bottom electrode layer 204, the first magnetic tunnel junction structure layer 206, and the first top electrode layer 208 located on top of the first dielectric layer 202 are also removed, leaving only the first bottom electrode layer 204, the first magnetic tunnel junction structure layer 206, and the first top electrode layer 208 located within the first trench T1.
[0149] In this embodiment, after planarization, the top surfaces of the first top electrode layer 208 and the first interconnect structure 220 can be repaired by means of ion beam etching, so as to reduce the roughness of the top surfaces of the first top electrode layer 208 and the first interconnect structure 220.
[0150] In this embodiment, the width of the first interconnect structure 220 along the direction parallel to the substrate surface cannot be too large or too small. If the width of the first interconnect structure 220 is too large, it will occupy a large area along the substrate surface, increasing device power consumption. If the width of the first interconnect structure 220 is too small, it may lead to poor electrical connection between the first top electrode layer 208 and other devices, affecting the performance of the first device 210. Therefore, in this embodiment, the width of the first interconnect structure 220 along the direction parallel to the substrate surface is 10 nm to 100 nm.
[0151] In this embodiment, the material of the first interconnect structure 220 is copper.
[0152] In other embodiments, depending on the actual process, the material of the first interconnect structure 220 may also include conductive materials such as tungsten, aluminum, and cobalt.
[0153] In this embodiment, the step of forming the first device layer 210 further includes: forming a first conductive plug 212 located within the first dielectric layer 202 (e.g., Figure 7 (as shown); correspondingly, the first bottom electrode layer 204 is located above the first conductive plug 212 and is electrically connected to the first conductive plug 212.
[0154] The first conductive plug 212 is used to realize the electrical connection between the first device 210 and the substrate. For example, the first conductive plug 212 is used to electrically connect the first device 210 and the metal layer 200.
[0155] In this embodiment, see next. Figures 5 to 7 The steps of forming the first conductive plug 212, the first device 210, and the first interconnect structure 220 within the first dielectric layer 202 include: See [link to previous steps] Figure 5 A first trench T1 and a first through hole G1 are formed in the first dielectric layer 202; see also Figure 6 A first conductive plug 212 is formed within the first through hole G1; see also Figure 7 After the first conductive plug 212 is formed, the first device 210 and the first interconnect structure 220 are formed in the first trench T1.
[0156] By forming a first trench T1 and a first through hole G1 that are interconnected in the first dielectric layer 202, the process steps can be simplified.
[0157] In this embodiment, the first trench T1 is located above the first through hole G1 and along a direction parallel to the substrate surface, and the opening size of the first through hole G1 is smaller than the opening size of the first trench T1.
[0158] In one specific embodiment, the steps of forming a first trench T1 and a first through hole G1 that are interconnected in the first dielectric layer 202 include: forming a first trench T1 in a first dielectric layer 202 of a certain thickness; forming a shielding layer (not shown) in the first trench T1 that contacts the sidewall of the first trench T1, with the shielding layer exposing a portion of the first dielectric layer 202 below the first trench T1; using the shielding layer as a mask, removing the first dielectric layer 202 exposed by the shielding layer in the first trench T1, and forming a first through hole G1 in the first dielectric layer 202 at the bottom of the first trench T1; and removing the shielding layer after forming the first through hole G1.
[0159] In this embodiment, when forming the shielding layer, the shielding layer also covers the top surface of the first dielectric layer 202, thereby reducing damage to the top surface of the first dielectric layer 202 when the first through hole G1 is formed using the shielding layer as a mask.
[0160] In this embodiment, when removing the shielding layer, the shielding layer and the first dielectric layer 202 have an etching selectivity ratio, thereby reducing damage to the first dielectric layer 202.
[0161] In this embodiment, the shielding layer may be made of a dielectric material, wherein the dielectric material may include at least one of SiC, SiO2 and SiON.
[0162] It is understood that the first trench T1 and the first via G1 can be formed using a damascene process; however, the methods for forming the first trench T1 and the first via G1 are not limited to the steps described above. In other implementations, the first trench and the first via can also be formed in other ways, such as all-in-one etching (AIO etch).
[0163] The first conductive plug 212 is used to realize the electrical connection between the first bottom electrode layer 204 and the metal layer 200.
[0164] In this embodiment, the step of forming the first conductive plug 212 in the first through hole G1 includes: forming a first conductive material layer (not shown) that fills the first through hole G1 and the first trench T1; removing the first conductive material layer above the top of the first through hole G1, and using the first conductive material layer located in the first through hole G1 as the first conductive plug 212.
[0165] In this embodiment, the material of the first conductive plug 212 may include one or more of Cu, W, Al, TiN, TaN, and Ti.
[0166] In one specific embodiment, the material of the first conductive plug 212 is Cu.
[0167] The steps for forming the first device 210 and the first interconnect structure 220 can refer to the method described in the foregoing example, or other methods can be used to form the first device 210 and the first interconnect structure 220.
[0168] After forming the first interconnect structure 220, see Figure 8 A second interconnect structure 222 is formed in the first dielectric layer 202 between adjacent first devices 210. The second interconnect structure is electrically connected to the first devices on both sides. The top surface of the second interconnect structure is flush with the top surface of the first device.
[0169] The second interconnection structure 222 is used to realize the electrical connection between adjacent first devices 210. By connecting adjacent first devices 210, the first devices 210 can be accessed in parallel, improving the speed of data reading and storage.
[0170] In this embodiment, the step of forming a second interconnect structure 222 in the first dielectric layer 202 between adjacent first devices 210 includes: removing the first dielectric layer 202 between adjacent first devices 210 to form a second trench (not shown) exposing the sidewall of the first device 210; forming a second interconnect structure 222 in the second trench, and the top surface height of the second interconnect structure 222 is flush with the top surface height of the first device 210.
[0171] In this embodiment, the step of forming the second interconnect structure 222 in the second trench includes: filling the second trench with a metal material for forming the second interconnect structure 222, so as to serve as the second interconnect structure 222.
[0172] Specifically, the step of forming the second interconnect structure 222 further includes: planarizing the metal material and removing the metal material located on top of the first dielectric layer 202.
[0173] In this embodiment, the material of the second interconnect structure 222 is copper. In other embodiments, depending on the actual process, the material of the second interconnect structure 222 may also include conductive materials such as tungsten, aluminum, and cobalt.
[0174] In this embodiment, after forming the first device layer, a second device layer can be formed on the first device layer. The second device layer includes a second device that can store data. Furthermore, by integrating the first device layer and the second device layer, the storage function of the semiconductor device can be enriched while reducing the overall area of the semiconductor device.
[0175] In this embodiment, when a second device layer is formed on the first device layer after the first device layer is formed, the forming step may further include: forming a fourth dielectric layer on the first device layer, wherein a third conductive plug located on top of the first interconnect structure is formed in the fourth dielectric layer, and the third conductive plug is electrically connected to the top of the first interconnect structure.
[0176] In this embodiment, the steps of forming the fourth dielectric layer 224 and the third conductive plug 226 include:
[0177] See Figure 9 A fourth dielectric layer 224 is formed on the first device layer.
[0178] The fourth dielectric layer 224 is used to achieve electrical isolation between the third conductive plugs 226 in the later stages of the manufacturing process. The fourth dielectric layer 224 is also used to achieve electrical isolation between subsequent second devices 240.
[0179] In this embodiment, the fourth dielectric layer 224 is made of a low-k dielectric material, an ultra-low-k dielectric material, silicon oxide, silicon nitride, or silicon oxynitride, etc.
[0180] Specifically, the material of the fourth dielectric layer 224 is a low-k dielectric material, which helps to reduce the parasitic capacitance between the subsequent interconnect structures, and thus helps to reduce the subsequent RC delay.
[0181] In this embodiment, a deposition process (e.g., chemical deposition process) can be used to form a fourth dielectric layer 224 over the first device 210 and the first interconnect structure 220.
[0182] See next Figure 9 A third conductive plug 226 is formed within the fourth dielectric layer 224.
[0183] The third conductive plug 226 is used to achieve an electrical connection between the first device 210 and the second device layer. For example, as... Figure 9 As shown, the third conductive plug 226 is located on top of the first interconnect structure 220. By making the second device formed subsequently electrically connected to the first interconnect structure 220 through the third conductive plug 226, the electrical connection between the first device 210 and the second device can be realized.
[0184] In this embodiment, the step of forming a third conductive plug 226 in the fourth dielectric layer 224 includes: forming a through third via (not shown) in the fourth dielectric layer 224; forming a third conductive material layer (not shown) that fills the third via; removing the third conductive material layer above the top of the third via, and using the third conductive material layer located in the third via as the third conductive plug 226.
[0185] In this embodiment, the material of the third conductive plug 226 may include one or more of Cu, W, Al, TiN, TaN, and Ti.
[0186] In one specific embodiment, the material of the third conductive plug 226 is Cu.
[0187] After forming a fourth dielectric layer 224 having a third conductive plug 226, a second device layer electrically connected to the third conductive plug 226 is formed on the fourth dielectric layer 224.
[0188] In this embodiment, see Figures 10 to 15 The steps for forming the second device layer include:
[0189] See Figure 10 and Figure 11 This forms the second device 240.
[0190] In this embodiment, the second device 240 may include a stacked second bottom electrode layer 234, a second magnetic tunnel junction structure layer 236, and a second top electrode layer 238; wherein, among the second bottom electrode layer 234, the second magnetic tunnel junction structure layer 236, and the second top electrode layer 238, the second bottom electrode layer 234 is closest to the first device 210 and is electrically connected to the first device 210.
[0191] In this embodiment, the second device 240 is formed on the third conductive plug 226, and the second bottom electrode layer 234 is electrically connected to the third conductive plug 226.
[0192] Accordingly, the steps for forming the second device 240 include: see [link to relevant documentation] Figure 10 A bottom electrode material layer 228, a magnetic tunnel junction material layer 230, and a top electrode material layer 232 are sequentially formed on the fourth dielectric layer 224; see also Figure 11 The top electrode material layer 232, the magnetic tunnel junction material layer 230 and the bottom electrode material layer 228 are patterned sequentially to form a second bottom electrode layer 234 electrically connected to the third conductive plug 226, a second magnetic tunnel junction structure layer 236 located on the second bottom electrode layer 234, and a second top electrode layer 238 located on the second magnetic tunnel junction structure layer 236.
[0193] The descriptions of the second bottom electrode layer 234, the second magnetic tunnel junction structure layer 236, and the second top electrode layer 238 can be found in the foregoing descriptions of the first bottom electrode layer 204, the first magnetic tunnel junction structure layer 206, and the first top electrode layer 208, and will not be repeated here in this embodiment.
[0194] In this embodiment, the step of patterning the top electrode material layer 232, the magnetic tunnel junction material layer 230, and the bottom electrode material layer 228 in sequence includes: forming a mask structure (not shown) on the top electrode material layer 232, the mask structure having a patterned opening; etching the top electrode material layer 232, the magnetic tunnel junction material layer 230, and the bottom electrode material layer 228 in sequence along the patterned opening (e.g., dry etching process), and using the remaining portion of the top electrode material layer 232 as the second top electrode layer 238, the remaining portion of the magnetic tunnel junction material layer as the second magnetic tunnel junction structure layer 236, and the remaining portion of the bottom electrode material layer 228 as the second bottom electrode layer 234.
[0195] In this embodiment, after the second magnetic tunnel junction structure layer 236 is formed, an annealing process is performed.
[0196] Annealing is used to repair lattice defects in the second magnetic tunnel junction structure layer 236, thereby improving the lattice quality and crystallization uniformity of the second magnetic tunnel junction structure layer 236, and thus improving the film quality of the second magnetic tunnel junction structure layer 236.
[0197] See Figure 12 A third dielectric layer 244 is formed covering the second device 240.
[0198] The third dielectric layer 244 is used to achieve electrical isolation between the second conductive plugs. The fourth dielectric layer 224 is also used to achieve isolation between the second devices 240.
[0199] In this embodiment, a deposition process is used to form a third dielectric layer 244 covering the second device 240, wherein the deposition process can be a low-temperature atomic layer deposition process.
[0200] In this embodiment, the material of the third dielectric layer 244 includes one or more of SiN, SiO2, SiON, SiOC, SiCOH and SiCN.
[0201] In this embodiment, see continue to refer to Figure 12 The step of forming the second device layer further includes forming a protective layer 242 that covers at least the top and sidewalls of the second device 240 before forming the third dielectric layer 244. That is, the protective layer 242 is located at least between the top of the second device 240 and the third dielectric layer 244, and between the sidewalls of the second device 240 and the third dielectric layer 244.
[0202] The protective layer 242 can protect the sidewalls and top of the second device 240 during the subsequent formation of the second conductive plug.
[0203] In this embodiment, an atomic layer deposition process is used to form a protective layer 242 covering the top and sidewalls of the second device 240.
[0204] In some other embodiments, the protective layer 242 may also cover the top of the fourth dielectric layer 224 on the side of the second device 240.
[0205] In this embodiment, the material of the protective layer 242 may include one or more of the following: silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, boron carbonitride, and silicon oxide.
[0206] In one specific embodiment, the material of the protective layer 242 includes silicon nitride.
[0207] See Figures 13 to 15 This forms a second conductive plug 246 that penetrates the top of the third dielectric layer 244 of the second device 240.
[0208] The second conductive plug 246 is located on top of the second top electrode layer 238 and is electrically connected to the second top electrode layer 238.
[0209] In this embodiment, the second conductive plug 246 leads out the electrical properties of the second device 240, and the second conductive plug 246 is used to realize the electrical connection between the second device 240 and external circuits, other interconnection structures or other components.
[0210] In this embodiment, the second conductive plug 246 forming the third dielectric layer 244 penetrating the top of the second device 240 includes: See Figure 13 Using the top of the protective layer 242 as the stop position, an initial via G2 is formed in the third dielectric layer 244 on top of the second device 240 to expose the protective layer 242; see also Figure 14 Remove the protective layer 242 at the bottom of the initial via G2 to expose the top surface of the second top electrode layer 238, thereby forming a second via G3 penetrating the third dielectric layer 244 and the protective layer 242; see also Figure 15 A second conductive plug 246, which is electrically connected to the second top electrode layer 238, is formed in the second through hole G3.
[0211] It should be noted that during the process of removing the protective layer 242 on the top surface of the second top electrode layer 238, a portion of the thickness of the second top electrode layer 238 is also removed.
[0212] It should be noted that when the protective layer 242 is not formed, the relevant description of the second conductive plug 246 can be found in the description of the first conductive plug 212 in the previous example, and will not be repeated in this embodiment.
[0213] Figure 16This is a schematic diagram of the second embodiment of the semiconductor structure formation method of the present invention.
[0214] The similarities between this embodiment and the previous embodiment will not be repeated here. The differences between this embodiment and the first embodiment are as follows:
[0215] See Figure 16 In the step of providing the substrate 400, a second dielectric layer 448 is also formed on the substrate 400, and a first conductive plug 412 is formed in the second dielectric layer 448.
[0216] That is to say, in Figure 16 In the corresponding semiconductor structure formation method, the first conductive plug 412 and the first device 410 are formed in different dielectric layers to reduce the process difficulty of forming the first conductive plug 412 and the first device 410; wherein, the first device 410 includes a stacked first bottom electrode layer 404, a first magnetic tunnel junction structure layer 406 and a first top electrode layer 408.
[0217] Figure 17 This is a schematic diagram of the third embodiment of the semiconductor structure formation method of the present invention.
[0218] The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are as follows:
[0219] A second device layer is formed on the substrate before the first device layer is formed. That is, see [link to documentation]. Figure 17 The second device layer is located between the substrate and the first device layer. Specifically, the first device 510 and the second device 540 are stacked together.
[0220] In this case, see Figure 17 In the step of forming the first device layer on the substrate 500, the second conductive plug 546 is electrically connected to the second top electrode layer 528 and the first bottom electrode layer 504.
[0221] Furthermore, the second device layer is located above the second dielectric layer 548, and the second bottom electrode layer 534 is located above the first conductive plug 512 and is electrically connected to the first conductive plug 512.
[0222] It should be noted that the semiconductor structure described in this embodiment can be formed using any of the formation methods described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.
[0223] While this specification discloses the invention as described above, the invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of this invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: Base; A first dielectric layer is located on the substrate; A first interconnect structure is located within the first dielectric layer; A first device is located within the first dielectric layer and covers the bottom and sidewalls of the first interconnect structure. The first device includes a stacked first bottom electrode layer, a first magnetic tunnel junction structure layer, and a first top electrode layer. The first top electrode layer is closest to the first interconnect structure and is electrically connected to the first interconnect structure.
2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A second dielectric layer is located between the first dielectric layer and the substrate; The first conductive plug is located within the second dielectric layer and is electrically connected to the first bottom electrode layer; Alternatively, the semiconductor structure may further include: A first conductive plug is located within a first dielectric layer at the bottom of the first device. The first conductive plug is located between the first bottom electrode layer and the substrate, and is electrically connected to the first bottom electrode layer.
3. The semiconductor structure according to claim 1, characterized in that, The first magnetic tunnel junction structure layer includes a stacked first magnetic layer, a barrier layer, and a second magnetic layer, with the second magnetic layer being closest to the first top electrode layer.
4. The semiconductor structure according to claim 1, characterized in that, Along a direction parallel to the surface of the substrate, the width of the first interconnect structure is 10 nm to 100 nm.
5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The second interconnect structure is located within the first dielectric layer between adjacent first devices and is electrically connected to the first bottom electrode layers on both sides.
6. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A third dielectric layer is located between the first dielectric layer and the substrate, or on top of the first device and the first interconnect structure; The second device is embedded within the third dielectric layer. The second device includes: a second bottom electrode layer; a second magnetic tunnel junction structure layer located on top of the second bottom electrode layer; and a second top electrode layer located on top of the second magnetic tunnel junction structure layer. The second conductive plug is located within the third dielectric layer on top of the second top electrode layer and is electrically connected to the second top electrode layer.
7. The semiconductor structure according to claim 6, characterized in that, The third dielectric layer is located between the first dielectric layer and the substrate, and the second device is stacked with the first device; The second conductive plug is located between the second top electrode layer and the first bottom electrode layer, and is electrically connected to the second top electrode layer and the first bottom electrode layer; or, The third dielectric layer is located on top of the first device and the first interconnect structure, and the second device is stacked with the first device; The semiconductor structure further includes: a fourth dielectric layer located between the third dielectric layer and the first dielectric layer; The third conductive plug is located within the fourth dielectric layer and between the second device and the first device. The third conductive plug is electrically connected to the first interconnect structure and the second bottom electrode layer. The second device is located on the third conductive plug, and the second bottom electrode layer is electrically connected to the third conductive plug.
8. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure also includes: A protective layer is located at least between the top and sidewalls of the second device and the third dielectric layer; The second conductive plug is located within the third dielectric layer on top of the second top electrode layer and penetrates the protective layer.
9. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Forming a first device layer on the substrate, the step of forming the first device layer includes: forming a first dielectric layer on the substrate; A first device and a first interconnect structure are formed within the first dielectric layer. The first device covers the bottom and sidewalls of the first interconnect structure. The first device includes a stacked first bottom electrode layer, a first magnetic tunnel junction structure layer, and a first top electrode layer. The first top electrode layer is closest to the first interconnect structure and is electrically connected to the first interconnect structure.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, The steps of forming the first device and the first interconnect structure located within the first dielectric layer include: A first trench is formed in the first dielectric layer; A first device with conformal coverage is formed at the bottom and sidewalls of the first trench; A first interconnect structure is formed in a first trench in which the first device is formed.
11. The method for forming a semiconductor structure according to claim 10, characterized in that, The step of forming a conformal cover on the bottom and sidewalls of the first trench includes: A first bottom electrode layer is formed to conformally cover the sidewalls and bottom of the first trench; A first magnetic tunnel junction structure layer is formed to conformally cover the first bottom electrode layer; A first top electrode layer is formed to conformally cover the first magnetic tunnel junction structure layer.
12. The method for forming a semiconductor structure according to claim 11, characterized in that, The first bottom electrode layer, the first magnetic tunnel junction structure layer, and the first top electrode layer are formed using an atomic layer deposition process.
13. The method for forming a semiconductor structure according to claim 9, characterized in that, In the step of providing the substrate, a second dielectric layer is further formed on the substrate, and a first conductive plug is formed within the second dielectric layer; The first device layer is formed on the second dielectric layer, and the first bottom electrode layer is located above the first conductive plug and is electrically connected to the first conductive plug.
14. The method for forming a semiconductor structure according to claim 9, characterized in that, The step of forming the first device layer further includes: forming a first conductive plug located within the first dielectric layer; The first bottom electrode layer is located above the first conductive plug and is electrically connected to the first conductive plug.
15. The method for forming a semiconductor structure according to claim 14, characterized in that, The steps of forming the first conductive plug, the first device, and the first interconnect structure within the first dielectric layer include: A first trench and a first through hole are formed in the first dielectric layer, wherein the first trench is located above the first through hole and is in a direction parallel to the substrate surface, and the opening size of the first through hole is smaller than the opening size of the first trench. The first conductive plug is formed within the first through hole; After the first conductive plug is formed, an interconnect structure with the first device and the first interconnect structure is formed in the first trench.
16. The method for forming a semiconductor structure according to claim 15, characterized in that, The step of forming the first conductive plug within the first through hole includes: A first conductive material layer is formed to fill the first through-hole and the first trench; Remove the first conductive material layer above the top of the first through hole, and use the first conductive material layer located inside the first through hole as the first conductive plug.
17. The method for forming a semiconductor structure according to any one of claims 9 to 16, characterized in that, Also includes: A second interconnect structure is formed in a first dielectric layer between adjacent first devices. The second interconnect structure is electrically connected to the first devices on both sides. The top surface of the second interconnect structure is flush with the top surface of the first devices.
18. The method for forming a semiconductor structure according to any one of claims 9 to 16, characterized in that, Also includes: A second device layer may be formed on the substrate before the first device layer is formed, or a second device layer may be formed on the first device layer after the first device layer is formed. The step of forming the second device layer includes: forming a second device, the second device including a second bottom electrode layer, a second magnetic tunnel junction structure layer and a second top electrode layer stacked sequentially in the longitudinal direction; forming a third dielectric layer covering the second device; forming a second conductive plug penetrating the top of the third dielectric layer of the second device, the second conductive plug being located on top of the second top electrode layer and electrically connected to the second top electrode layer.
19. The method for forming a semiconductor structure according to claim 18, characterized in that, After the first device layer is formed, a second device layer is formed on the first device layer; Before forming the second device layer, the method further includes: forming a fourth dielectric layer on the first device layer, wherein a third conductive plug is formed in the fourth dielectric layer and located on top of the first interconnect structure, and the third conductive plug is electrically connected to the top of the first interconnect structure; In the step of forming the second device layer, the second device is formed on the third conductive plug, the second bottom electrode layer is electrically connected to the third conductive plug, and the third dielectric layer covers the second device; or, A second device layer is formed on the substrate prior to the formation of the first device layer; In the step of forming a first device layer on the substrate, the first device and the second device are stacked together, and the second conductive plug is electrically connected to the second top electrode layer and the first bottom electrode layer.
20. The method for forming a semiconductor structure according to claim 18, characterized in that, The step of forming the second device layer further includes: Before forming the third dielectric layer, a protective layer is formed that at least covers the top and sidewalls of the second device; The step of forming a second conductive plug penetrating the third dielectric layer at the top of the second device includes: forming an initial through-hole in the third dielectric layer at the top of the second device, with the top of the protective layer as the stop position; removing the protective layer at the bottom of the initial through-hole to expose the top surface of the second top electrode layer, thereby forming a second through-hole penetrating the third dielectric layer and the protective layer; and forming a second conductive plug electrically connected to the second top electrode layer in the second through-hole.