Package structure

Abstract

The invention provides a packaging structure. The package structure includes a first electronic component, a second electronic component and a data access structure. The data access structure is partially disposed in a gap between the first electronic component and the second electronic component. The data access structure includes a logic portion and a storage portion. One of the logic portion and the storage portion is in the gap, and the other of the logic portion and the storage portion is outside the gap.

Description

Technical Field

[0001] This disclosure generally relates to a packaging structure. Background Technology

[0002] Currently, high-bandwidth memory (HBM) devices are typically located adjacent to CPUs and arranged side-by-side, with communication between the CPU and the HBM device achieved via bridging dies. An HBM device may contain multiple memory dies (Dynamic Random Access Memory; DRAM) stacked with logic dies. The logic dies are configured to receive command signals from outside the HBM and generate control signals to control the memory dies, such as reading data from or writing data to selected memory cells on the memory dies. However, the logic dies located within the HBM and between CPUs typically have a relatively large size and may therefore unintentionally increase the transmission path between CPUs. Summary of the Invention

[0003] In one or more arrangements, a package structure includes a first electronic component, a second electronic component, and a data access structure. The data access structure is partially disposed in a gap between the first electronic component and the second electronic component. The data access structure includes a logic portion and a storage portion. One of the logic portion and the storage portion is located within the gap, and the other of the logic portion and the storage portion is located outside the gap.

[0004] In one or more arrangements, a package structure includes a first electronic component, a second electronic component, a memory stack, and a bridging component. The memory stack includes a plurality of memory dies stacked one on top of the other. The bridging component includes a first portion configured to provide electrical communication between the first and second electronic components, and a second portion configured to control access to the memory stack. The second portion of the bridging component and the memory stack together constitute the memory structure.

[0005] In one or more arrangements, a package structure includes a first electronic component, a second electronic component, and a third electronic component. The first electronic component and the second electronic component are separated from each other by a gap. The third electronic component includes a first portion and a second portion. The first portion is disposed within the gap, and the second portion extends outward from the gap. The second portion is larger than the first portion. Attached Figure Description

[0006] The aspects of this disclosure will be better understood from the following embodiments when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale, and the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This is a cross-section of a packaging structure according to some arrangements of this disclosure.

[0008] Figure 1A This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure.

[0009] Figure 1B This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure.

[0010] Figure 1C This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure.

[0011] Figure 2A This is a top view of an encapsulation structure arranged according to some of the present disclosure.

[0012] Figure 2B This is a top view of an encapsulation structure arranged according to some of the present disclosure.

[0013] Figure 2C This is a top view of an encapsulation structure arranged according to some of the present disclosure.

[0014] Figure 2D This is a top view of an encapsulation structure arranged according to some of the present disclosure.

[0015] Figure 2E This is a top view of an encapsulation structure arranged according to some of the present disclosure.

[0016] Figure 3A This is a cross-section of a packaging structure according to some arrangements of this disclosure.

[0017] Figure 3B This is a cross-section of a packaging structure according to some arrangements of this disclosure.

[0018] Figure 3C This is a cross-section of a packaging structure according to some arrangements of this disclosure.

[0019] Figure 3D This is a cross-section of a packaging structure according to some arrangements of this disclosure.

[0020] Figures 4A to 4H The illustration depicts various stages of an exemplary method for forming an encapsulation structure according to some arrangements of this disclosure.

[0021] Common element symbols are used throughout the drawings and embodiments to indicate the same or similar elements. This disclosure will become more apparent from the following detailed description accompanying the drawings. Detailed Implementation

[0022] Figure 1This is a cross-section of a package structure 1 according to some arrangements of the present disclosure. The package structure 1 may include a substrate structure 10, electronic components 20A, 20B and 60, a memory stack 30A (also referred to as the "memory portion of the data access structure"), an interconnector 40 (which may include a bridging portion configured for electrical connection and a logic portion configured for controlling the data access structure of the memory stack), connection elements 71 and 72, protective elements 30u, 73 and 74, and electrical contacts 80.

[0023] The substrate structure 10 supports electronic components 20A and 20B, as well as a memory stack 30A. In some arrangements, the substrate structure 10 includes redistribution layers (RDLs) 110 and 130 (also referred to as "fan-out structures"), an encapsulation 120 between RDLs 110 and 130, and conductive pillars 120p within the encapsulation 120. In some arrangements, the conductive pillars 120p are electrically connected to RDLs 110 and 130.

[0024] In some arrangements, RDL 110 includes a dielectric layer 110d, at least one conductive layer 110c, and vias 110v1 and 110v2. The spacing between vias 110v2 may be smaller than the spacing between vias 110v1. The width of vias 110v2 may be smaller than the width of vias 110v1. The conductive layer 110c and vias 110v1 and 110v2 may contain a conductive material, such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0025] In some arrangements, encapsulation 120 connects RDL 110 to RDL 130. In some arrangements, conductive posts 120p are encapsulated by encapsulation 120. Conductive posts 120p can electrically connect RDL 110 to RDL 130. Encapsulation 120 may comprise an epoxy resin with filler, an encapsulation material (e.g., epoxy encapsulation material or other encapsulation material), polyimide (PI), a phenolic compound or material, a material in which silicone is dispersed, or a combination thereof. Conductive posts 120p may comprise a conductive material, such as a metal or metal alloy. Examples include Au, Ag, Al, Cu, or alloys thereof.

[0026] In some arrangements, RDL 130 includes a dielectric layer 130d, at least one conductive layer 130c, and vias 130v1, 130v1', and 130v2. The spacing between vias 130v2 may be substantially equal to or less than the spacing between vias 130v1 and 130v1'. The width of via 130v2 may be substantially equal to or less than the width of vias 130v1 and 130v1'. The spacing between vias 110v1 may be substantially equal to or less than the spacing between vias 130v2. The width of via 110v1 may be substantially equal to or less than the width of via 130v2. The conductive layer 130c and vias 130v1, 130v1', and 130v2 may comprise a conductive material, such as a metal or metal alloy. Examples include Au, Ag, Al, Cu, or alloys thereof.

[0027] Electronic components 20A and 20B may be disposed above substrate structure 10. In some arrangements, electronic components 20A and 20B are spaced apart from each other by a gap G1 of width W1. In some arrangements, electronic components 20A and 20B are electrically connected to RDL 130 (e.g., conductive layer 130c and vias 130v1 and 130v2). In some arrangements, conductive pads 210A and 210B of electronic components 20A are electrically connected to conductive pads 130a of RDL 130 via connection element 72. In some arrangements, connection element 72 is encapsulated by protective element 74. Electronic components 20A and 20B may include processing components (or processing elements). In some arrangements, electronic components 20A and 20B may independently include an ASIC, a system-on-a-chip (SoC), an FPGA, a GPU, or the like, or combinations thereof. In some arrangements, electronic components 20A and 20B may independently contain a processing core or processing chip. Conductive pads 210A, 210B, and 130a may contain conductive materials such as metals or metal alloys. Examples include Au, Ag, Al, Cu, or alloys thereof. Connecting element 72 may include conductive bumps, which may be or may contain Ag, Al, Cu, another metal, solder alloys, or combinations thereof. Protective element 77 may include an underfill, which may contain an epoxy resin with filler, an encapsulation material (e.g., epoxy encapsulation material or other encapsulation materials), polyimide (PI), a phenolic compound or material, a material in which silicone is dispersed, or a combination thereof.

[0028] Package structure 1 may include a data access structure comprising a storage portion configured to store data and a logic portion configured to access the storage portion. The data access structure may be or include an HBM device, the storage portion may be or include memory elements, and the logic portion may be or include logic dies. The logic portion or logic die is configured to receive command signals from outside the data access structure (or HBM device) and generate control signals to access the storage portion (or memory elements). In some arrangements, one of electronic components 20A and 20B is configured to access the storage portion via the logic portion. In some arrangements, one of the logic portion and the storage portion has a first size, and the other of the logic portion and the storage portion has a second size larger than the first size, the second size being outside gap G1, and the first size being within gap G1. In some arrangements, the storage portion may be a memory stack 30A, and the logic portion may be located outside gap G1 between electronic components 20A and 20B. The logic portion of the logic die disposed outside the gap G1 prevents the width W1 of the gap G1 from being unintendedly enlarged by the relatively wide logic portion (or logic die) stacked with the memory portion (or memory element), and thus prevents the unintended enlargement of the transmission path between electronic components 20A and 20B. In some arrangements, the memory stack 30A is disposed adjacent to electronic components 20A and 20B. In some arrangements, the memory stack 30A is disposed in the gap G1 between electronic components 20A and 20B. The memory stack 30A may be disposed above the substrate structure 10. In some arrangements, the memory stack 30A is electrically connected to RDL 130 (e.g., conductive layer 130c and vias 130v1, 130v1' and 130v2). In some arrangements, the conductive pads of the memory stack 30A are electrically connected to the conductive pads 130a of RDL 130 via connection element 72. In some arrangements, memory stack 30A has a width W30, memory stack 30A is spaced apart from electronic component 20A by a distance D1A, and memory stack 30A is spaced apart from electronic component 20B by a distance D1B. In some arrangements, memory stack 30A does not include logic dies stacked with memory stack 30A in gap G1.

[0029] In some arrangements, the memory stack 30A includes a plurality of memory dies (e.g., memory dies 310, 320, 330, and 340) stacked on top of each other and connection elements 30c electrically connecting the memory dies. The memory dies may include DRAM. One or more of the memory dies may include vias 30V (e.g., TSVs) electrically connected to the connection elements 30c. In some arrangements, a protective element 30u at least partially encapsulates the memory stack 30A and is spaced from the circuit layer 40R of the interconnect 40. The vias 30V can penetrate opposite surfaces of the memory dies. In some arrangements, the conductive pad 340a of memory die 340 is electrically connected to the conductive pad 330b of memory die 330 via the connection elements 30c. In some arrangements, the conductive pad 330a of memory die 330 is electrically connected to the conductive pad 320b of memory die 320 via the connection elements 30c. In some arrangements, the conductive pad 320a of the memory die 320 is electrically connected to the conductive pad 310b of the memory die 310 via a connection element 30c. In some arrangements, the conductive pad 310a of the memory die 310 is electrically connected to the conductive pad 130a of the RDL 130 via a connection element 72.

[0030] Interconnect 40 may be disposed beneath memory stack 30A. Interconnect 40 may be referred to as a bridging component and is also configured to act as a logic die for an HBM device. In some arrangements, interconnect 40 is configured to provide electrical communication between electronic components 20A and 20B. In some arrangements, at least one of electronic components 20A and 20B is configured to partially access memory stack 30A via interconnect 40, which acts as a logic die in an HBM device. In some arrangements, interconnect 40 is embedded in substrate structure 10. In some arrangements, interconnect 40 is disposed between RDL 110 and RDL 130 and encapsulated by encapsulation 120. In some arrangements, interconnect 40 is electrically connected to RDL 110 and RDL 130.

[0031] In some arrangements, interconnect 40 includes a substrate 40s, a circuit layer 40R above the substrate 40s, conductive pads 40a on surface 401 (also referred to as the "top surface"), conductive pads 40b on surface 402 (also referred to as the "bottom surface") opposite surface 401, and vias 40V extending between surfaces 401 and 402 to electrically connect the conductive pads 40a and 40b. In some arrangements, the substrate 40s includes a semiconductor substrate layer, such as a Si layer. In some arrangements, circuit layer 40R includes bridging portions configured to provide electrical connections and logic portions configured to generate control signals to perform write and / or read operations on memory stack 30A (or the storage portion of a data access structure). In some arrangements, circuit layer 40R includes bridging circuitry or bridging portions configured to provide electrical communication between electronic components 20A and 20B (e.g., Figures 2A to 2D The circuit 410 shown in the diagram). In some arrangements, circuit layer 40R includes control logic circuitry or logic portions configured to control access to memory stack 30A (e.g., Figures 2A to 2D The circuit 420 shown in the diagram. In some arrangements, the control logic circuitry (or logic section) is configured to generate control signals to perform write and / or read operations.

[0032] In some arrangements, the wafer node of circuit layer 40R (or control logic) is less than or smaller than the wafer node of memory stack 30A (or memory die). The wafer node of circuit layer 40R (or control logic) may lead the wafer node of memory stack 30A (or memory die) by one or more generations. For example, circuit layer 40R (or control logic) may be a 7nm or larger node wafer, and the memory die may be a 14nm or larger node wafer, such as a 16nm or larger node wafer, a 20nm or larger node wafer, or a larger node wafer.

[0033] In some arrangements, interconnect 40 is configured to provide electrical communication between electronic components 20A and 20B along path P1. In some arrangements, path P1 includes a vertical portion that passes through RDL 130 and connects electronic components 20A and 20B to interconnect 40. In some arrangements, path P1 includes a horizontal portion that passes through circuit layer 40R without passing through a portion of RDL 130 below memory stack 30A. In some arrangements, path P1 vertically overlaps with memory stack 30A from a cross-sectional view. In some arrangements, electronic component 20A is configured to access memory stack 30A along path P2A. In some arrangements, electronic component 20B is configured to access memory stack 30A along path P2B. In some arrangements, paths P2A and P2B include vertical portions that directly connect circuit layer 40R to memory stack 30A without passing through logic dies. In some arrangements, paths P2A and P2B are at least partially and substantially parallel to path P1.

[0034] In some arrangements, the control logic circuitry (or logic portion) of interconnect 40 and memory stack 30A together constitute a memory structure (or data access structure). The memory structure (or data access structure) may be or include a high-bandwidth memory (HBM) device. The memory structure (or data access structure) may be referred to as an additional electronic component distinct from electronic components 20A and 20B. The memory stack 30A (or memory portion) and the control logic circuitry (or logic portion) of interconnect 40 may be referred to as two separate portions electrically connected to each other via conductive structures (e.g., RDL 130). In some arrangements, memory stack 30A (or a first portion of the additional electronic component) is configured to not be operably communicateable with electronic components 20A and / or 20B without operating in conjunction with the control logic circuitry (or a second portion of the additional electronic component) of interconnect 40. In some arrangements, the control logic circuitry (or a second portion of the additional electronic components) of interconnect 40 is configured to cooperate with memory stack 30A (or a first portion of the additional electronic components) to operatively communicate with electronic components 20A and / or electronic components 20B.

[0035] In some arrangements, path P2A passes through a portion of RDL 130 below electronic component 20A, a portion of circuit layer 40R where control signals are generated by control logic circuitry (or logic section) and transmitted by bridge circuitry (or bridge section), and a portion of RDL 130 below memory stack 30A. In some arrangements, path P2B passes through a portion of RDL 130 below electronic component 20B, a portion of circuit layer 40R where control signals are generated by control logic circuitry (or logic section) and transmitted by bridge circuitry (or bridge section), and a portion of RDL 130 below memory stack 30A.

[0036] In some arrangements, RDL 130 is above interconnect 40 and electrically connected to surface 401 (or top surface) of interconnect 40. In some arrangements, interconnect 40 is electrically connected to RDL 130 via conductive pad 40a. In some arrangements, memory stack 30A and circuit layer 40R are located on opposite sides of RDL 130. In some arrangements, RDL 130 is situated between memory stack 30A and interconnect 40, and RDL 130 electrically connects surface 401 (top surface) of interconnect 40 to memory stack 30A. In some arrangements, RDL 130 is situated between electronic components 20A and 20B and interconnect 40, and at least one of electronic components 20A and 20B is configured to transmit electrical signals to circuit layer 40R of interconnect 40 via an electrical path (e.g., path P1, path P2A, and / or path P2B) passing through RDL 130 once. In some arrangements, the control logic circuitry of circuit layer 40R (e.g., Figures 2A to 2D The circuit 420 shown is configured to access data in memory stack 30A via paths through RDL 130 (e.g., path P2A and / or path P2B). In some arrangements, encapsulation 120 encapsulates control logic circuitry (e.g., ...) in circuit layer 40R. Figures 2A to 2D The circuit 420 shown is spaced apart from the memory stack 30A. The control logic circuit (or logic section) may include a transceiver containing physical layer circuitry or a physical layer interface portion (often abbreviated as "PHY") connected to a physical medium via conductive pads 40a, RDL 130, and conductive pads 210A and 210B, through which data is transmitted between electronic components 20A and 20B and interconnect 40.

[0037] In some arrangements, RDL 110 is below interconnect 40 and electrically connected to surface 402 (or bottom surface) of interconnect 40. In some arrangements, conductive pad 40b of interconnect 40 is electrically connected to conductive pad 110a of RDL 110 via connection element 71. Conductive pad 110a may be or include an under-bump metallization (UBM) layer. Connection element 71 may include conductive bumps, which may be or may include Ag, Al, Cu, another metal, solder alloy, or a combination thereof. In some arrangements, interconnect 40 may further include a protective element 40u encapsulating conductive pads 40b and 110a and connection element 71. Protective element 40u may be or include an underfill, comprising an epoxy resin with filler, an encapsulation material (e.g., epoxy encapsulation material or other encapsulation material), polyimide (PI), a phenolic compound or material, a material in which silicone is dispersed, or a combination thereof.

[0038] Electronic component 60 may be embedded in substrate structure 10. In some arrangements, electronic component 60 is encapsulated by encapsulation 120. Electronic component 60 may include conductive pads 60a and 60b on opposite surfaces of electronic component 60. In some arrangements, electronic component 60 is electrically connected to RDL 110 via conductive pad 60a and to RDL 130 via conductive pad 60b. Conductive pads 60a and 60b may contain conductive materials, such as metals or metal alloys. Examples include Au, Ag, Al, Cu, or alloys thereof. Electronic component 60 may be or contain passive components, such as capacitors, inductors, or other suitable passive components. In some arrangements, electronic component 60 is or contains a deep trench capacitor (DTC).

[0039] Protective element 73 may encapsulate electronic components 20A and 20B, memory stack 30A, connection element 72, and protective elements 30u and 74. In some arrangements, protective element 73 encapsulates conductive pads 310a, 310b, 320a, 320b, 330a, 330b, and 340a, as well as connection element 30c. Protective element 73 may comprise an encapsulating body, an epoxy resin with filler, an encapsulation material (e.g., epoxy encapsulation material or other encapsulation material), polyimide (PI), a phenolic compound or material, a material in which silicone is dispersed, or a combination thereof.

[0040] Electrical contact 80 may be located below RDL 110. In some arrangements, electrical contact 80 is electrically connected to RDL 110. Electrical contact 80 may contain solder balls. Electrical contact 80 may be or contain a crash control chip connection (C4) bump, ball grid array (BGA), or platform grid array (LGA).

[0041] According to some arrangements of this disclosure, the control logic circuitry of circuit layer 40R is integrated into interconnect 40 instead of being formed by a single logic die, and is stacked with memory dies 310, 320, 330, and 340 in the gap G1 between electronic components 20A and 20B. Therefore, memory stack 30A does not include logic dies with a width greater than the width of the memory dies stacked with them. Thus, the distances D1A and D1B between memory stack 30A and electronic components 20A and 20B can be minimized, thereby preventing the width W1 of gap G1 from being unintentionally expanded by the relatively wide logic dies of the memory die stack. In this way, the distance between electronic components 20A and 20B (e.g., the width W1 of gap G1) can be reduced, thus shortening the transmission path between electronic components 20A and 20B, and also shortening the transmission path between memory stack 30A and electronic components 20A and 20B. Therefore, transmission losses can be reduced, power efficiency can be improved, signal attenuation can be reduced, and latency can be reduced.

[0042] In addition, the HBM device includes an integrated memory stack (e.g., memory stack 30A) and a logic die (e.g., Figure 3D The logic die 50 shown in the illustration may have a relatively large thickness; for example, the thickness of the HBM device may be greater than the thickness of the interconnect 40. Therefore, when the entire HBM device, including the memory stack and logic die, is housed or embedded in the encapsulation 120 to reduce the size of the gap G1 between electronic components 20A and 20B, the thickness of the entire package structure increases unintentionally. In contrast, according to some arrangements of this disclosure, only a portion of the memory structure (e.g., the HBM device) (e.g., the control logic circuitry of circuit layer 40R) is housed or embedded in the encapsulation 120, while another portion of the memory structure (memory stack 30A) remains housed in the gap G1. Therefore, the thickness of the entire package structure 1 does not increase, and the distance between electronic components 20A and 20B (e.g., the gap G1) can be shortened.

[0043] Furthermore, according to some arrangements of this disclosure, the bridging circuitry (or bridging portion) for enabling electrical communication between electronic components 20A and 20B is integrated into the circuit layer 40R of interconnect 40, instead of placing two separate bridging components for electrical communication with the two electronic components 20A and 20B. Therefore, the process is simplified by fabricating a single bridging structure (e.g., interconnect 40) instead of fabricating two bridging components in a package structure. Moreover, according to some arrangements of this disclosure, the path P1 for enabling electrical communication between electronic components 20A and 20B can pass through RDL 130 only twice and extend along the circuit layer 40R of interconnect 40, instead of passing through the respective two bridging components connected to electronic components 20A and 20B. Therefore, path P1 can pass through fewer heterogeneous interfaces (e.g., the interface between RDL 130 and interconnect 40), and path P1 can be relatively short, which further helps to reduce power consumption, signal attenuation, and delay.

[0044] Furthermore, according to some arrangements of this disclosure, the control logic circuitry (or logic portion) for accessing the memory stack 30A is further integrated into the circuit layer 40R of the interconnect 40, rather than stacking the logic die with the memory stack 30A to enable electrical communication between the electronic components 20A and 20B and the memory stack 30A. Therefore, the process is further simplified by fabricating an integrated structure (e.g., interconnect 40) instead of fabricating a logic die and two bridging components. Additionally, according to some arrangements of this disclosure, the paths (e.g., paths P2A and P2B) for enabling electrical communication between the electronic components 20A and 20B and the memory stack 30A pass through a portion of the circuit layer 40R for control signal generation and signal transmission, without further passing through the logic die. Therefore, paths P2A and P2B can be relatively short, which further benefits increased computing speed and reduced power consumption, signal attenuation, and latency.

[0045] Furthermore, according to some arrangements of this disclosure, the interconnect 40 integrates bridging functions (e.g., bridging circuits) and computing functions (e.g., control logic circuits) into a single unit to form a package structure 1 (also referred to as a "combodie"). Consequently, the distance between the wiring of the bridging circuit (or bridging portion) and the control logic circuit (or logic portion) is reduced, thus shortening the transmission distance between the bridging circuit (or bridging portion) and the control logic circuit (or logic portion). Therefore, the computing speed within the interconnect 40 of the package structure 1 (or combodie) is increased, and thus the performance of the package structure 1 is improved. Additionally, multiple package structures 1 containing interconnects 40 each having multiple functions can act as combodies integrated into various devices or packages, thereby improving the scalability and applicability of the package structure 1.

[0046] Furthermore, according to some arrangements of this disclosure, the interconnect 40 includes vias 40V connecting conductive pads 40a and 40b on opposing surfaces 401 and 402. Therefore, transmission speed can be further increased via vertical transmission, thereby increasing bandwidth, reducing latency, and decreasing power consumption and heat generation.

[0047] Furthermore, according to some arrangements of this disclosure, the wafer node of the logic control circuit (or logic die) is less than or smaller than the wafer node of the memory stack 30A, and the memory stack 30A and the control logic circuit are manufactured separately rather than being manufactured as a single memory module. Therefore, the precision required to manufacture the memory stack 30A is less than the precision required to manufacture the control logic circuit (or logic die), and performing processes requiring different levels of processing precision separately simplifies the entire process and reduces costs. Additionally, by manufacturing the control logic circuit and the memory stack 30A separately, the interconnect 40 with the control logic circuit and the memory stack 30A can be identified as known good dies (KGD) and / or known bad dies (KGD) before continuing the manufacturing process. Only KGD dies are used, and KGD dies can be reworked or replaced, thus increasing yield.

[0048] Figure 1A This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure. In some arrangements, Figure 1A for Figure 1 The cross-section of portion 1A of the package structure 1 is shown in the figure.

[0049] In some arrangements, the memory die 310 includes a substrate layer 310s, a device layer 310c, a via 30V, a conductive pad 310a, and a dielectric layer 310d. In some arrangements, the substrate layer 310s includes a semiconductor substrate layer, such as a Si layer. The via 30V penetrates the substrate layer 310s and connects to the device layer 310c. The conductive pad 310a is electrically connected to the device layer 310c. The device layer 310c may include a memory element, such as a capacitor or the like. The dielectric layer 310d may partially cover the device layer 310c and the conductive pad 310a. The conductive pads 310a and 310b and the via 30V may contain a conductive material, such as a metal or metal alloy. Examples include Au, Ag, Al, Cu, or alloys thereof. Figure 1 The memory dies 320, 330, and 340 illustrated may independently include a structure similar to that of memory die 310. The topmost memory die (e.g., memory die 340) may not contain vias 30V.

[0050] In some arrangements, the memory die 310 further includes a conductive layer 310u. The conductive layer 310u may be disposed on an exposed portion of the conductive pad 310a. The conductive layer 310u may be referred to as an under-bump metallization (UBM) layer. In some arrangements, the conductive pad 310a is connected to the conductive pad of the RDL 130 via the conductive layer 310u and connection elements 72 and 72'.

[0051] In some arrangements, the connecting element 72 includes an alloy layer 72a, a bonding layer 72c, and an intermetallic compound (IMC) layer 72b. In some arrangements, the bonding layer 72c includes a welding material. In some arrangements, the alloy layer 72a includes metallic elements of the welding material and metallic elements of the conductive layer 310u. In some arrangements, the IMC layer 72b includes one or more metallic elements of the welding material and metallic elements of the conductive layer 310u. For example, the alloy layer 72a may include a Ni-Sn alloy, the bonding layer 72c may include an Au-Sn alloy, and the IMC layer 72b may include an Au-Sn-Ni IMC. In some arrangements, the conductive layer 310u is not aligned with the conductive pad 130a.

[0052] In some arrangements, the connecting element 72' includes an alloy layer 72a', a bonding layer 72c', and an IMC layer 72b'. In some arrangements, the bonding layer 72c' includes welding material. In some arrangements, the alloy layer 72a' includes metallic elements of the welding material and metallic elements of the conductive layer 310u. In some arrangements, the IMC layer 72b' includes one or more metallic elements of the welding material and metallic elements of the conductive layer 310u. For example, the alloy layer 72a' may include a Ni-Sn alloy, the bonding layer 72c' may include an Au-Sn alloy, and the IMC layer 72b' may include an Au-Sn-Ni IMC. In some arrangements, the geometry of the connecting element 72 differs from the geometry of the connecting element 72'.

[0053] Figure 1B This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure. In some arrangements, Figure 1B for Figure 1 The cross-section of portion 1B of the package structure 1 is shown in the figure.

[0054] In some arrangements, electronic component 20A includes a conductive pad 210A, a dielectric layer 210d defining an opening exposing the conductive pad 210A, and a connecting element 210P. The connecting element 210P may be or include a conductive post. The conductive pad 210A may be electrically connected to the conductive pad 130a via the connecting element 72. The conductive pad 210A may not be aligned with the conductive pad 130a. In some arrangements, the thickness of the conductive pad 130a is less than the thickness of the connecting element 72, and the thickness of the connecting element 72 is less than the thickness of the connecting element 210P.

[0055] Figure 1C This is a cross-section of a portion of an encapsulation structure according to some arrangements of this disclosure. In some arrangements, Figure 1C for Figure 1 The cross-section of portion 1C of the package structure 1 is shown in the figure.

[0056] In some arrangements, electronic component 60 includes a conductive pad 60b, a dielectric layer 60d defining an opening exposing the conductive pad 60b, and a connection element 60P. The connection element 60P may be or include a conductive post. The conductive pad 60b may be electrically connected to the conductive pad 110a via the connection element 71. The conductive pad 60b may not be aligned with the conductive pad 110a. In some arrangements, the thickness of the conductive pad 110a is less than the thickness of the connection element 71, and the thickness of the connection element 71 is less than the thickness of the connection element 60P.

[0057] Figure 2A This is a top view of an encapsulation structure 1 according to some arrangements of the present disclosure. In some arrangements, Figure 2A for Figure 1 The diagram shows a top view of the encapsulation structure 1. In some arrangements, Figure 1 Display along Figure 2A The cross section of line 1-1' in the middle.

[0058] In some arrangements, package structure 1 includes multiple memory stacks (e.g., memory stacks 30A and 30B). In some arrangements, memory stacks 30A and 30B are above interconnect 40. Memory stack 30B may have a structure similar to that of memory stack 30A, which includes memory dies 310, 320, 330, and 340. In some arrangements, memory stacks 30A and 30B are spaced apart by a gap G2.

[0059] In some arrangements, interconnect 40 (or circuit layer 40R) includes circuit 410 and circuit 420, which is different from circuit 410. In some arrangements, from a top view, circuits 410 and 420 are partially covered by electronic components 20A and 20B. In some arrangements, from a top view, circuits 410 and 420 are partially covered by memory stacks 30A and 30B.

[0060] In some arrangements, circuit 410 may be referred to as a bridging circuit (or bridging portion). In some arrangements, circuit 410 is configured to provide electrical communication between electronic components 20A and 20B. In some arrangements, circuit 410 (or bridging circuit) is configured to transmit one or more electrical signals between electronic components 20A and 20B via path P1. In some arrangements, from a top view perspective, circuit 410 is at least partially located between memory stacks 30A and 30B. In some arrangements, circuit 410 is at least partially exposed through gap G2 between memory stacks 30A and 30B.

[0061] See Figure 1 and Figure 2A In some arrangements, from a cross-sectional view, the circuit 410 of circuit layer 40R vertically overlaps with memory stacks 30A and 30B. In some arrangements, RDL 130 is situated between electronic components 20A and 20B and interconnect 40, and at least one of electronic components 20A and 20B is configured to transmit one or more electrical signals to circuit 410 (or bridging circuit) of circuit layer 40R of interconnect 40 via an electrical path (e.g., path P1) through RDL 130.

[0062] In some arrangements, circuit 420 may be referred to as logic circuitry or control logic circuitry (or the logic portion of a data access structure). In some arrangements, circuit 420 is configured to control access to a memory stack. In some arrangements, circuit 420 is configured to control access to one or more of memory stacks 30A and 30B. Circuit 420 may be configured to generate control signals to perform write and / or read operations. In some arrangements, electronic component 20A is configured to access memory stacks 30A and 30B via circuit 420. In some arrangements, electronic component 20B is configured to access memory stacks 30A and 30B by sending command signals to circuit 420 (or the logic portion of the data access structure), said circuit 420 being configured to generate control signals in response to command signals for accessing memory stacks 30A and 30B (or the memory portion of the data access structure). In some arrangements, from a top view, circuitry 420 overlaps with portions of memory stacks 30A and 30B, portions of electronic components 20A, and portions of electronic components 20B. In some arrangements, from a top view, circuitry 420 is at least partially located between memory stacks 30A and 30B and electronic components 20A and 20B. In some arrangements, circuitry 420 is at least partially exposed by the gap G1 between electronic components 20A and 20B.

[0063] In some arrangements, circuit 420 includes portions 420A and 420B (also referred to as "circuit areas"). In some arrangements, electronic component 20A is configured to access memory stack 30A by sending a command signal to portion 420A, said portion 420A being configured to generate a control signal in response to a command for accessing memory stack 30A, and electronic component 20B is configured to access memory stack 30A by sending a command signal to portion 420B, said portion 420B being configured to generate a control signal in response to a command for accessing memory stack 30A. In some arrangements, from a top view perspective, portions 420A and 420B of circuit 420 are located on the same side of circuit 410. In some arrangements, the width W2 of circuit 420 is greater than the width W1 of the gap G1 between electronic components 20A and 20B. In some arrangements, the width W2 of circuit 420 (or control logic circuit) is greater than the distance between electronic components 20A and 20B (e.g., width W1).

[0064] In some arrangements, circuit 420 further includes portions 420A' and 420B' (also referred to as "circuit areas"). In some arrangements, electronic component 20A is configured to access memory stack 30B by sending a command signal to portion 420A', said portion 420A' being configured to generate a control signal in response to the command signal for accessing memory stack 30B, and electronic component 20B is configured to access memory stack 30B by sending a command signal to portion 420B', said portion 420B' being configured to generate a control signal in response to the command signal for accessing memory stack 30B. In some arrangements, from a top view perspective, portions 420A' and 420B' of circuit 420 are located on the same side of circuit 410.

[0065] In some arrangements, circuit 420 (or control logic circuitry) is configured to access data in one or more of memory stacks 30A and 30B via a path (e.g., at least one of paths P2A, P2B, P2A', and P2B'). In some arrangements, a portion 420A (or circuit area) of circuit 420 is configured to access data in memory stack 30A via path P2A. In some arrangements, a portion 420B (or circuit area) of circuit 420 is configured to access data in memory stack 30A via path P2B. In some arrangements, a portion 420A' (or circuit area) of circuit 420 is configured to access data in memory stack 30B via path P2A'. In some arrangements, a portion 420B' (or circuit area) of circuit 420 is configured to access data in memory stack 30B via path P2B'.

[0066] See Figure 1 and Figure 2AIn some arrangements, circuitry 420 (or control logic circuitry) of circuitry layer 40R is embedded within encapsulation 120. In some arrangements, electronic component 20A (or processing element) is above substrate structure 10 and configured to access one or more memory stacks 30A and 30B by sending command signals to circuitry 420 (or control logic circuitry), said circuitry 420 being configured to generate control signals in response to command signals for accessing one or more memory stacks 30A and 30B. In some arrangements, electronic component 20B (or processing element) is above substrate structure 10 and configured to access one or more memory stacks 30A and 30B by sending command signals to circuitry 420 (or control logic circuitry), said circuitry 420 being configured to generate control signals in response to command signals for accessing one or more memory stacks 30A and 30B. In some arrangements, the envelope 120 encapsulates the circuitry 420 (or control logic circuitry) and is spaced apart from the memory stacks 30A and 30B. In some arrangements, conductive pads 40a are embedded in the envelope 120 and electrically connect the circuitry 420 (or control logic circuitry) to one or more of the memory stacks 30A and 30B. In some arrangements, conductive pads 40a electrically connect the circuitry 420 (or control logic circuitry) to the RDL 130.

[0067] See Figure 1 and Figure 2A In some arrangements, RDL 130 is above circuitry 420 (or control logic circuitry) and electrically connected to one or more of memory stacks 30A and 30B. In some arrangements, electronic components 20A and 20B are located on opposite sides of circuitry 420 (or control logic circuitry) within RDL 130. In some arrangements, memory stacks 30A and 30B are located on opposite sides of circuitry 420 (or control logic circuitry) within RDL 130. In some arrangements, memory dies 310, 320, 33, and 340 are electrically connected to circuitry 420 (or control logic circuitry) via RDL 130.

[0068] See Figure 1 and Figure 2A In some arrangements, circuit 420 (or control logic circuitry) is configured to access data in one or more of memory stacks 30A and 30B via a path through RDL 130 (e.g., at least one of paths P2A, P2B, P2A', and P2B'). In some arrangements, RDL 130 is situated between electronic components 20A and 20B and interconnect 40, and at least one of electronic components 20A and 20B is configured to transmit electrical signals to circuit 420 (or control logic circuitry) of circuit layer 40R of interconnect 40 via an electrical path through RDL 130 (e.g., at least one of paths P2A, P2B, P2A', and P2B').

[0069] See Figure 1 and Figure 2A In some arrangements, electronic component 60 (or passive component) is positioned adjacent to circuit 420 (or control logic circuit) and encapsulated by encapsulation 120.

[0070] Figure 2B This is a top view of the encapsulation structure 1b according to some arrangements of this disclosure. In some arrangements, Figure 1 Display along Figure 2B The cross section of line 1-1' in the middle. Figure 2B The structure shown in the figure and Figure 2A The structures are similar, and the differences between them are described below.

[0071] In some arrangements, from a top view perspective, circuit 410 is exposed through the gap G2 between memory stacks 30A and 30B.

[0072] Figure 2C This is a top view of the encapsulation structure 1c according to some arrangements of this disclosure. In some arrangements, Figure 1 Display along Figure 2C The cross section of line 1-1' in the middle. Figure 2C The structure shown in the figure and Figure 2A The structures are similar, and the differences between them are described below.

[0073] In some arrangements, from a top view perspective, portions 420A and 420B of circuit 420 (or control logic circuit) are located on opposite sides of circuit 410.

[0074] Figure 2D This is a top view of an encapsulation structure 1d according to some arrangements of this disclosure. In some arrangements, Figure 1 Display along Figure 2D The cross section of line 1-1' in the middle. Figure 2D The structure shown in the figure and Figure 2B The structures are similar, and the differences between them are described below.

[0075] In some arrangements, from a top view perspective, circuit 410 is exposed through the gap G2 between memory stacks 30A and 30B.

[0076] Figure 2E This is a top view of the encapsulation structure 1e according to some arrangements of this disclosure. In some arrangements, Figure 1 Display along Figure 2E The cross section of line 1-1' in the middle. Figure 2E The structure shown in the figure and Figure 2A The structures are similar, and the differences between them are described below.

[0077] In some arrangements, the encapsulation structure 1e includes Figure 2A Multiple structures (e.g., package structure 1) are illustrated herein. Package structures 1 are arranged in an array above substrate 100A to form package structure 1e. According to some arrangements of this disclosure, multiple package structures 1 include interconnects 40, each having multiple functions, which can act as combined dies integrated into package structure 1e, thereby improving the scalability and applicability of package structure 1e.

[0078] Figure 3A This is a cross-section of a package structure 3A according to some arrangements of the present disclosure. Package structure 3A is similar to... Figure 1 The encapsulation structure 1 in the text is described below, and the differences between it and the encapsulation structure 1 are described below.

[0079] In some arrangements, the protective element 30u at least partially encapsulates the memory stack 30A and is spaced apart from the circuit layer 40R of the interconnect 40. In some arrangements, see... Figure 2A and Figure 3A The protective element 30u at least partially encapsulates the memory stack 30A and is spaced apart from the circuit 420 (or control logic circuit). The protective element 30u may include an encapsulation body, an epoxy resin with filler, an encapsulation material (e.g., epoxy resin encapsulation material or other encapsulation material), a polyimide (PI), a phenolic compound or material, a material in which silicone is dispersed, or a combination thereof.

[0080] In some arrangements, the top surface of the memory stack 30A is below the top surfaces of the electronic components 20A and 20B relative to the substrate structure 10. In some arrangements, a protective element 73 encapsulates the top surface of the memory stack 30A.

[0081] Figure 3B This is a cross-section of the packaging structure 3B according to some arrangements of the present disclosure. The packaging structure 3B is similar to... Figure 1 The encapsulation structure 1 in the text is described below, and the differences between it and the encapsulation structure 1 are described below.

[0082] In some arrangements, interconnect 40 is electrically connected to RDL 110 via conductive pad 110a. In some arrangements, electronic component 60 is electrically connected to RDL 110 via conductive pad 60a. Electronic component 60 and interconnect 40 are connected to RDL 110 via Cu-Cu bonding.

[0083] Figure 3C The image shows a cross-section of a package structure 3C according to some arrangements of this disclosure. The package structure 3C is similar to... Figure 1 The encapsulation structure 1 in the text is described below, and the differences between it and the encapsulation structure 1 are described below.

[0084] The package structure 3C may include a substrate structure 10, electronic components 20A, 20B and 60, a memory stack 30A, a bridging component 40B, a logic die 50, connecting elements 71 and 72, protective elements 73 and 74, and electrical contacts 80.

[0085] In some arrangements, bridging component 40B includes a substrate layer 40s, a conductive layer 40c (also referred to as a "bridging circuit") above the substrate layer 40s, conductive pads 40a on a surface 401 (also referred to as a "top surface"), conductive pads 40b on a surface 402 (also referred to as a "bottom surface") opposite to surface 401, and vias 40V extending between surfaces 401 and 402 to electrically connect the conductive pads 40a and 40b. Conductive layer 40c is configured to provide electrical communication between electronic components 20A and 20B. Conductive layer 40c is also configured to provide electrical communication between memory stack 30A and at least one of electronic components 20A and 20B.

[0086] In some arrangements, electronic component 20A is configured to electrically communicate with electronic component 20B via path P1C through bridging component 40B. In some arrangements, bridging component 40B is electrically connected to electronic components 20A and 20B via a portion of RDL 130. In some arrangements, path P1C passes through a portion of RDL 130 beneath electronic component 20A, the conductive layer 40c of bridging component 40B, and then through another portion of RDL 130 beneath electronic component 20B. Path P1C passes only through a few heterogeneous interfaces, such as the interface between RDL 130 and bridging component 40B. Therefore, path P1C is more efficient than... Figure 3D The path P1D shown in the diagram can be relatively short. Therefore, power consumption can be reduced, and signal delay and latency can be relatively low.

[0087] Logic die 50 may be stacked with memory stack 30A. In some arrangements, logic die 50 is configured to access memory stack 30A. In some arrangements, logic die 50 is configured to access at least one of memory dies 310, 320, 330, and 340. Logic die 50 may be configured to control access to memory stack 30A. In some arrangements, logic die 50 is configured to generate control signals to perform write and / or read operations. In some arrangements, electronic component 20A is configured to access memory stack 30A by sending command signals to logic die 50, the logic die being configured to generate control signals in response to the command signals for accessing memory stack 30A. In some arrangements, electronic component 20B is configured to access memory stack 30A by sending command signals to logic die 50, the logic die being configured to generate control signals in response to the command signals for accessing memory stack 30A. In some arrangements, the logic die 50 is positioned between the RDL 130 and the memory stack 30A. In some arrangements, the logic die 50 is positioned above the RDL 130 and electrically connected to the memory stack 30A via conductive pads 50b and connection elements 30c. In some arrangements, the logic die 50 is electrically connected to the RDL 130 via conductive pads 50a, connection elements 72, and conductive pads 130a. In some arrangements, the logic die 50 is spaced from the envelope 120. In some arrangements, the memory stack 30A has a width W30, and the logic die 50 has a width W50 that is substantially the same as the width W30 of the memory stack 30A. In some arrangements, the logic die 50 and the memory stack 30A are spaced apart from the electronic component 20A by a distance D1A. In some arrangements, the logic die 50 and the memory stack 30A are spaced apart from the electronic component 20B by a distance D1B. In some arrangements, the separation width W1 between electronic components 20A and 20B is less than Figure 3D The gap with width W1' shown in the figure.

[0088] In some arrangements, logic die 50 is configured to access data in memory stack 30A via a path through RDL 130 (e.g., at least one of paths P2C and P2C'). In some arrangements, path P2D traverses a portion of RDL 130 below electronics 20A, a portion of conductive layer 40c, a portion of RDL 130 below logic die 50, and a portion of logic die 50 in which control signals are generated and transmitted to memory stack 30A. In some arrangements, path P2C' traverses a portion of RDL 130 below electronics 20B, a portion of conductive layer 40c, a portion of RDL 130 below logic die 50, and a portion of logic die 50 in which control signals are generated and transmitted to memory stack 30A. When the width W50 of logic die 50 is substantially the same as the width W30 of memory stack 30A, paths P2C and P2C' will... Figure 3D The paths P2C and P2C' shown in the diagram can be relatively short, thus improving computation speed, reducing power consumption, and minimizing signal attenuation and delay.

[0089] Figure 3D This is a 3D cross-section of a package structure according to some arrangements of this disclosure. The 3D package structure is similar to... Figure 3C The packaging structure of 3C is described below, and the differences between them are described as follows.

[0090] In some arrangements, the package structure 3D includes two bridging components 40B. In some arrangements, the memory stack 30A has a width W30, and the logic die 50 has a width W50 greater than the width W30 of the memory stack 30A. In some arrangements, the memory stack 30A is spaced from the electronic component 20A by a distance greater than [missing information]. Figure 1 and Figure 3C The distance D1A shown in the figure is the distance D2A, and the memory stack 30A is spaced from the electronic component 20B by more than [a certain value]. Figure 1 and Figure 3C The distance D1B is shown as the distance D2B. In some arrangements, the separation width W1' of electronic components 20A and 20B is greater than... Figure 1 and Figure 3C The gap with width W1 is shown in the figure.

[0091] In some arrangements, electronic component 20A is configured to communicate electrically with electronic component 20B via path P1D. Path P1D traverses multiple heterogeneous interfaces, such as the interface between RDL 130 and bridging component 40B. Therefore, path P1D is more complex than... Figure 1 and Figures 2A to 2D The path P1 and shown in the figure Figure 3CThe path P1C shown in the figure can be relatively long, thus increasing power consumption, signal attenuation, and delay.

[0092] In some arrangements, logic die 50 is configured to access data in memory stack 30A via a path that traverses RDL 130 twice (e.g., at least one of paths P2D and P2D'). In some arrangements, path P2D traverses a portion of RDL 130 below electronics 20A, a portion of conductive layer 40c, a portion of RDL 130 below logic die 50, and a portion of logic die 50 where control signals are generated and transmitted to memory stack 30A. In some arrangements, path P2D' traverses a portion of RDL 130 below electronics 20B, a portion of conductive layer 40c, a portion of RDL 130 below logic die 50, and a portion of logic die 50 where control signals are generated and transmitted to memory stack 30A. Thus, paths P2D and P2D' are compared to... Figure 1 and Figures 2A to 2D The paths P2A and P2B shown in the diagram can be relatively long, which can reduce computation speed, increase power consumption, and result in relatively high signal attenuation and delay.

[0093] Figures 4A to 4H The various stages of an exemplary method for forming an encapsulation structure 1 according to some arrangements of this disclosure are illustrated.

[0094] See Figure 4A A carrier 1001 may be provided, and an RDL 110 may be formed on the carrier 1001. In some arrangements, the RDL 110 includes a dielectric layer 110d, at least one conductive layer 110c, and vias 110v1 and 110v2.

[0095] See Figure 4B Conductive pillars 120p and conductive pads 110a may be formed on RDL 110. Conductive pads 110a may be or include a UBM layer.

[0096] See Figure 4C Interconnector 40 and electronic component 60 can be connected to RDL 110. In some arrangements, interconnector 40 includes a substrate layer 40s, a circuit layer 40R, conductive pads 40a and 40b, and a via 40V. In some arrangements, interconnector 40 and electronic component 60 are connected or bonded to RDL 110 via conductive pads 40a and 60a, connection element 71, and conductive pad 110a. The bonding operation may be or may include soldering techniques.

[0097] See Figure 4DAn encapsulation 120 can be formed to encapsulate the interconnect 40, conductive pillars 120p, and electronic component 60. In some arrangements, encapsulation material or encapsulating material can be placed to cover the interconnect 40, conductive pillars 120p, and electronic component 60, and then a planarization operation (e.g., a polishing operation or a CMP operation) can be performed to remove portions of the interconnect 40, conductive pillars 120p, and electronic component 60 to form the encapsulation 120.

[0098] See Figure 4E RDL 130 may be formed on and electrically connected to interconnect 40, conductive pillar 120p and electronic component 60. In some arrangements, RDL 130 includes conductive pad 130a, dielectric layer 130d, at least one conductive layer 130c and vias 130v1 and 130v2.

[0099] See Figure 4F Electronic components 20A and 20B, as well as memory stack 30A, may be mounted on and electrically connected to RDL 130. Electronic components 20A and 20B are connected or bonded to RDL 130 via conductive pads 210A and 210B, connecting element 72, and conductive pad 130a. The bonding operation may be or may include soldering techniques.

[0100] See Figure 4G A protective element 73 can be formed to encapsulate electronic components 20A and 20B and memory stack 30A. In some arrangements, encapsulation material or encapsulating material can be placed to cover electronic components 20A and 20B and memory stack 30A, and then a planarization operation (e.g., a polishing operation or a CMP operation) can be performed to remove portions of electronic components 20A and 20B and memory stack 30A to form the protective element 73.

[0101] See Figure 4H The carrier 1001 can be removed, and electrical contacts can be formed on the bottom surface of RDL 110. Thus, a package structure 1 can be formed.

[0102] Unless otherwise specified, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” and “below” are relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not compromised by such arrangement.

[0103] As used herein, the terms “approximately,” “generally,” “roughly,” “about,” and “approximately” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, these terms may refer to a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if a first value is within a range of variation less than or equal to ±10% of a second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value may be considered “generally” the same as or equal to the second value. For example, "roughly" vertical can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0104] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface does not exceed 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0105] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may contain a plural or multiple indicators.

[0106] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are those that offer little or no resistance to the flow of electric current. A unit of measurement for conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m, for example, at least 10 5 S / m or at least 10 6 A material with conductivity of S / m. The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0107] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted as including not only the numerical values ​​explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0108] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and alternative equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments may exist that are not specifically described in this disclosure. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to suit particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are considered to be included within the scope of the appended claims. Although the disclosed methods have been described herein with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A packaging structure comprising: First electronic component and second electronic component; A data access structure is partially disposed in the gap between the first electronic component and the second electronic component, wherein the data access structure includes a logic portion and a storage portion, one of the logic portion and the storage portion is in the gap, and the other of the logic portion and the storage portion is outside the gap.

2. The packaging structure according to claim 1, wherein one of the logic portion and the storage portion has a first size, the other of the logic portion and the storage portion has a second size larger than the first size, the one having the second size is outside the gap, and the other having the first size is inside the gap.

3. The packaging structure according to claim 2, wherein the storage portion is in the gap and the logic portion is outside the gap.

4. The packaging structure of claim 3, further comprising an interconnect configured to provide electrical communication between the first electronic component and the second electronic component, wherein the logic portion is integrated into the interconnect.

5. The packaging structure of claim 4, wherein the interconnect further includes a bridging portion distinct from the logic portion, the bridging portion being configured to provide the electrical communication between the first electronic component and the second electronic component, and one of the first electronic component and the second electronic component being configured to access the storage portion via the logic portion.

6. The packaging structure of claim 5, wherein the logic portion includes a first component and a second component, the first electronic component being configured to access the storage portion by sending a first command signal to the first component, the first component being configured to generate a first control signal in response to the first command signal for accessing the storage portion, and the second electronic component being configured to access the storage portion by sending a second command signal to the second component, the second component being configured to generate a second control signal in response to the second command signal for accessing the storage portion.

7. The packaging structure of claim 6, wherein, from a top view perspective, the first component and the second component of the logic portion are located on opposite sides of the bridging portion.

8. The packaging structure according to claim 1, wherein the width of the logic portion is greater than the width of the gap between the first electronic component and the second electronic component.

9. The packaging structure of claim 5, wherein the storage portion includes a first memory stack and a second memory stack above the interconnect, and, from a top view perspective, the bridging portion is at least partially located between the first memory stack and the second memory stack.

10. The packaging structure of claim 4, wherein the interconnect is configured to provide the electrical communication between the first electronic component and the second electronic component along a first path, and at least one of the first electronic component and the second electronic component is configured to access the storage portion along a second path generally parallel to the first path.

11. The packaging structure of claim 10, wherein, from a cross-sectional view, the first path vertically overlaps with the storage portion.

12. A packaging structure comprising: First electronic component and second electronic component; A memory stack, which comprises multiple memory dies stacked one on top of the other; as well as A bridging component includes a first portion configured to provide electrical communication between the first electronic component and the second electronic component, and a second portion configured to control access to the memory stack, wherein the second portion of the bridging component and the memory stack together constitute a memory structure.

13. The packaging structure of claim 12, further comprising a redistribution layer RDL, wherein the memory stack comprises a stack of a plurality of DRAMs, and the memory stack is located on the opposite side of the second portion of the bridging component in the RDL.

14. The packaging structure of claim 13, wherein the second portion of the bridging component is configured to access data in the memory stack via a path traversing the RDL.

15. The packaging structure of claim 14, further comprising a passive component disposed adjacent to the second portion of the bridging component and encapsulated by the encapsulation body, wherein, from a top view perspective, the second portion of the bridging component overlaps with a portion of the memory stack, a portion of the first electronic component, and a portion of the second electronic component.

16. The packaging structure according to claim 12, further comprising: A first RDL is located between the memory stack and the bridging component, wherein the first RDL electrically connects the top surface of the bridging component to the memory stack. as well as A second RDL is located below the bridging assembly and electrically connected to a bottom surface opposite the top surface of the bridging assembly.

17. A packaging structure comprising: The first electronic component and the second electronic component are separated from each other by a gap; as well as A third electronic component includes a first portion disposed in the gap and a second portion extending outward from the gap, wherein the second portion is larger than the first portion.

18. The packaging structure of claim 17, wherein the first portion is separate from the second portion, and the first portion is electrically connected to the second portion via a conductive structure.

19. The packaging structure of claim 17, wherein the first portion of the third electronic component is configured to be unable to operatively communicate with the first electronic component or the second electronic component without cooperating with the second portion.

20. The packaging structure of claim 19, wherein the second portion of the third electronic component is configured to cooperate with the first portion to operatively communicate with the first electronic component or the second electronic component.

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