Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer, a first high-voltage well, a first doped region, a gate dielectric layer and a gate electrode. The substrate has a first conductivity type. The epitaxial layer is disposed on the substrate and has a second conductivity type different from the first conductivity type. The first high-voltage well is arranged in the epitaxial layer and has a second conductive type. The first doped region is disposed in the first high-voltage well and has a first conductivity type. The gate dielectric layer is disposed on the epitaxial layer. The gate electrode is disposed on the gate dielectric layer. Wherein the first doped region covers the first part of the first high-voltage well and exposes the second part of the first high-voltage well.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices including a first doped region. Background Technology

[0002] Current high-voltage integrated circuits (HVICs) may include a high-side circuit in the high-side region, a low-side circuit in the low-side region, and an isolation structure between them. Bootstrap diodes in bootstrap circuits are often integrated with HVICs to provide power to transistors in the high-voltage region.

[0003] However, integrating bootstrap diodes and HVICs can lead to problems due to complex fabrication processes and structures, such as insufficient switching speed, excessively long recovery time, excessive forward voltage, insufficient forward current, and insufficient breakdown voltage, resulting in insufficient reliability of the semiconductor device. Therefore, although existing semiconductor devices have gradually met their intended applications, they are not yet completely satisfactory in all aspects. Thus, some issues regarding semiconductor devices still need to be overcome. Summary of the Invention

[0004] This disclosure achieves the characteristics of both a Schottky diode (SBD) and a PIN diode by setting a current path analogous to a merged PIN Schottky (MPS) structure. This improves the electrical properties and reliability of the semiconductor device. Furthermore, the breakdown voltage characteristics of the semiconductor device can be adjusted by modifying the dimensions of the first high-voltage well and the first buried layer.

[0005] In some embodiments, this disclosure provides a semiconductor device. The semiconductor device includes a substrate, an epitaxial layer, a first high-voltage well, a first doped region, a gate dielectric layer, and a gate electrode. The substrate has a first conductivity type. The epitaxial layer is disposed on the substrate and has a second conductivity type different from the first conductivity type. The first high-voltage well is disposed in the epitaxial layer and has the second conductivity type. The first doped region is disposed in the first high-voltage well and has the first conductivity type. The gate dielectric layer is disposed on the epitaxial layer. The gate electrode is disposed on the gate dielectric layer. The first doped region covers a first portion of the first high-voltage well and exposes a second portion of the first high-voltage well.

[0006] The semiconductor device disclosed herein can be applied to various types of electronic devices and methods of forming thereof. To make the components and advantages of this disclosure more apparent and understandable, various embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0007] This disclosure will be more fully understood when read in conjunction with the drawings, as detailed in the following description. It is important to note that, in accordance with industry standard practice, the components are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced.

[0008] Figure 1 , Figure 2 , Figure 3 This is a cross-sectional schematic diagram of each stage of a method for forming a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 5 and Figure 6 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 7 , Figure 8 , Figure 9 These are top views of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 10 and Figure 11 These are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure.

[0013] Symbol Explanation

[0014] 1,2,3,4,5: Semiconductor devices

[0015] 100:Substrate

[0016] 102: First Embedded Layer

[0017] 104: Second Embedded Layer

[0018] 106: Epitaxial layer

[0019] 112: First High-Pressure Trap

[0020] 112a: Part One

[0021] 112b: Part Two

[0022] 114: Second High-Pressure Trap

[0023] 200: Isolation layer

[0024] 210: Gate dielectric layer

[0025] 220: Gate electrode

[0026] 310: First doped region

[0027] 312: Opening

[0028] 320: Second doped region

[0029] 330: Third doped region

[0030] 400: Interlayer dielectric layer

[0031] 410: First contact object

[0032] 420: Second contact object

[0033] 430: Third contact object

[0034] 510: First conductive layer

[0035] 520: Second conductive layer

[0036] 530: Third conductive layer

[0037] AA: Active Zone

[0038] D1: First Direction

[0039] D2: Second Direction

[0040] D3: Third direction

[0041] I-I',II-II': line segment

[0042] P1, P1': First current path

[0043] P2: Second current path

[0044] W102, W112, W310: Width Detailed Implementation

[0045] The semiconductor devices of various embodiments of this disclosure are described in detail below. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of this disclosure. The specific elements and arrangements described below are merely for simple and clear description of some embodiments of this disclosure. Of course, these are only examples and not limitations of this disclosure. Furthermore, similar and / or corresponding element symbols may be used in different embodiments to identify similar and / or corresponding elements for clear description of this disclosure. However, the use of these similar and / or corresponding element symbols is only for simple and clear description of some embodiments of this disclosure and does not represent any association between the different embodiments and / or structures discussed.

[0046] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in various embodiments to describe the relative relationship of one element to another in the diagram. It is understood that if the arrangement in the diagram is flipped upside down, an element depicted on the "lower" side will become an element on the "higher" side. The embodiments disclosed herein should be understood in conjunction with the drawings, which are also considered part of the disclosure.

[0047] Furthermore, when it is stated that a first material layer is on or over a second material layer, this may include situations where the first material layer and the second material layer are in direct contact, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly on the second material layer, it indicates that the first material layer and the second material layer are in direct contact.

[0048] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify elements, are not intended to imply any prior ordinal number for that (or these) element, nor to indicate the order of one element with another, or the order of manufacture. The use of these ordinal numbers is solely to clearly distinguish one named element from another element with the same name. The claims and specification may not use the same terminology; for example, the first element in the specification may be the second element in the claims.

[0049] In some embodiments disclosed herein, terms such as "connect," "interconnect," and "bond," unless specifically defined, may refer to two structures in direct contact, or to two structures not in direct contact, with another structure disposed between them. Furthermore, these terms may include situations where both structures are movable or both are fixed. Additionally, the terms "electrical connection" or "electrical coupling" include any direct or indirect electrical connection means.

[0050] In this text, the terms "approximately," "about," and "substantially" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "approximately," "about," or "substantially," the meaning of "approximately," "about," or "substantially" is implied. The phrases "the range is between the first value and the second value" or "the first value to the second value" indicate that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies that there may be an error between the first and second values ​​within approximately 10%, 5%, 3%, 2%, 1%, or 0.5%.

[0051] Throughout this disclosure, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as "comprise" and "having" are open-ended terms and should therefore be interpreted as "including but not limited to...". Thus, when the terms "comprise" and / or "having" are used in the description of this disclosure, they specify the presence of the corresponding component, area, step, operation, and / or element, but do not exclude the presence of one or more of the corresponding component, area, step, operation, and / or element.

[0052] It should be understood that, without departing from the spirit of this disclosure, components in multiple different embodiments can be replaced, reorganized, or combined to complete other embodiments. Components in each embodiment can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art. It is understood that such terms, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0054] In this disclosure, the directions are not limited to the three axes of a Cartesian coordinate system such as the X, Y, and Z axes, and can be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but are not limited thereto. For ease of explanation, in the following text, the X-axis direction is the first direction D1 (width direction), the Y-axis direction is the second direction D2 (length direction), and the Z-axis direction is the third direction D3 (height direction). In some embodiments, the top view described herein is a schematic diagram of viewing the XY plane, and the cross-sectional view described herein is a schematic diagram of viewing the XZ plane. The normal direction of the substrate described herein is the third direction D3.

[0055] Reference Figure 1 This is a cross-sectional schematic diagram of the various stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a substrate 100 having a first conductivity type is provided. In some embodiments, the substrate 100 may include a wafer, such as a silicon wafer. In some embodiments, the substrate 100 may include a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like, to provide an insulating layer on a silicon or glass substrate. In some embodiments, the substrate may include a multilayer substrate or a gradient substrate.

[0056] In some embodiments, substrate 100 may include elemental semiconductors, including silicon, germanium, the like, or combinations thereof; substrate 100 may include compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, the like, or combinations thereof; substrate 100 may include alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, the like, or combinations thereof, but this disclosure is not limited thereto.

[0057] In some embodiments, the first conductivity type and the second conductivity type may be adjusted according to electrical characteristics. In some embodiments, the doping concentration, doping depth, and size of the doped region may also be adjusted according to electrical characteristics. In some embodiments, the first conductivity type may be either P-type or N-type, and the second conductivity type may be either P-type or N-type. For ease of explanation, in the following text, the first conductivity type may be P-type and the second conductivity type may be N-type, but this disclosure is not limited thereto.

[0058] like Figure 1 As shown, in some embodiments, a first buried layer 102 and a second buried layer 104 may be formed in the substrate 100. The first buried layer 102 may have a second conductivity type different from the first conductivity type, i.e., N-type. The second buried layer 104 may have the first conductivity type, i.e., P-type. In some embodiments, the first buried layer 102 and the second buried layer 104 may be formed by processes such as ion implantation, diffusion, drive-in, similar processes, or combinations thereof, but this disclosure is not limited thereto. Furthermore, the implanted dopant may be further activated by a rapid thermal annealing (RTA) process. In some embodiments, depending on the required conductivity type, the dopant may be an N-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb), or a P-type dopant such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0059] like Figure 1As shown, in some embodiments, an epitaxial layer 106 may be formed on the substrate 100, and the epitaxial layer 106 may have a second conductivity type different from the first conductivity type, i.e., N-type. In some embodiments, the epitaxial layer 106 may be formed on the first buried layer 102 and the second buried layer 104. In some embodiments, after the epitaxial layer 106 is formed, the doping profile on the first buried layer 102 and the second buried layer 104 may be changed by performing the aforementioned diffusion process, thermal ingress process and / or rapid thermal annealing process.

[0060] like Figure 1 As shown, in some embodiments, a first high voltage well 112 may be formed in the epitaxial layer 106, and the first high voltage well 112 may have a second conductivity type, i.e., N-type. In some embodiments, a first buried layer 102 may be disposed between the substrate 100 and the first high voltage well 112. In some embodiments, in the first direction D1, the width W112 of the first high voltage well 112 may be smaller than the width W102 of the first buried layer 102, but this disclosure is not limited thereto. In some embodiments, the projection of the first high voltage well 112 onto the substrate 100 is located within the projection of the first buried layer 102 onto the substrate 100. In some embodiments, the first high voltage well 112 may penetrate the epitaxial layer 106. In some embodiments, the first high voltage well 112 may be formed by performing the aforementioned ion implantation, diffusion process, thermal ingress process, and / or rapid thermal annealing process. In some embodiments, the doping concentration of the first high voltage well 112 may be smaller than the doping concentration of the first buried layer 102. In some embodiments, the doping concentration of the first high voltage well 112 may be greater than the doping concentration of the epitaxial layer 106.

[0061] like Figure 1 As shown, in some embodiments, a second high-voltage well 114 may be formed in the epitaxial layer 106, and the second high-voltage well 114 may have a first conductivity type, i.e., P-type. In some embodiments, the second buried layer 104 may be disposed between the substrate 100 and the second high-voltage well 114. In some embodiments, in the first direction D1, the width of the second high-voltage well 114 may be substantially the same as the width of the second buried layer 104. In some embodiments, the projection of the second high-voltage well 114 onto the substrate 100 is aligned with the projection of the second buried layer 104 onto the substrate 100. In some embodiments, the second high-voltage well 114 may penetrate the epitaxial layer 106. In some embodiments, the second high-voltage well 114 may be formed by performing the aforementioned ion implantation, diffusion process, thermal ingress process, and / or rapid thermal annealing process. In some embodiments, the doping concentration of the second high-voltage well 114 may be less than the doping concentration of the second buried layer 104.

[0062] like Figure 1As shown, in some embodiments, an active region AA of a semiconductor device is defined on substrate 100, and an isolation layer 200 is formed according to the location of the active region AA. In some embodiments, the isolation layer 200 may be formed on epitaxial layer 106. In some embodiments, the isolation layer 200 may be disposed between epitaxial layer 106 and subsequently formed interlayer dielectric layer. In some embodiments, the isolation layer 200 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxides oxynitride such as silicon oxynitride, the like, or combinations thereof, but this disclosure is not limited thereto. For example, the isolation layer 200 may include field oxide. In some embodiments, the isolation layer 200 may be formed by local oxidation of silicon (LOCOS) formed by thermal oxidation.

[0063] like Figure 1 As shown, in some embodiments, a gate dielectric layer 210 is formed on the isolation layer 200 and the epitaxial layer 106, and a gate electrode 220 is formed on the gate dielectric layer 210. In some embodiments, the gate dielectric layer 210 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxide oxynitrides such as silicon oxynitride, the like, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the gate dielectric layer 210 may include a high dielectric constant dielectric material. For example, the gate dielectric layer 210 may include silicon oxide.

[0064] In some embodiments, the gate electrode 220 may comprise amorphous silicon, polysilicon, metal, metal nitride, conductive metal oxide, the like, or combinations thereof, but this disclosure is not limited thereto. The metal may comprise gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), the like, or combinations thereof, but this disclosure is not limited thereto. For example, the gate electrode 220 may comprise polysilicon. In some embodiments, the gate electrode 220 may be formed by sputtering, chemical vapor deposition (CVD), resistance heating evaporation, electron beam evaporation, similar processes, or combinations thereof, but this disclosure is not limited thereto.

[0065] Reference Figure 2This is a cross-sectional schematic diagram of the various stages of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, a first doped region 310 is formed in a first high-voltage well 112. The first doped region 310 may have a first conductivity type, i.e., P-type. In some embodiments, a second doped region 320 is formed in an epitaxial layer 106, and the second doped region 320 may have a second conductivity type, i.e., N-type. In some embodiments, a third doped region 330 is formed in a second high-voltage well 114, and the third doped region 330 may have a first conductivity type, i.e., P-type. In some embodiments, the first doped region 310, the second doped region 320, and the third doped region 330 may be formed by performing the aforementioned ion implantation, diffusion process, thermal ingress process, and / or rapid thermal annealing process. In some embodiments, the first doped region 310 and the third doped region 330 may be formed in the same or different process layers.

[0066] like Figure 2 As shown, in some embodiments, the first doped region 310 may cover a first portion 112a of the first high-voltage well 112 and expose a second portion 112b of the first high-voltage well 112. In some embodiments, the first portion 112a and the second portion 112b may have corresponding patterns. In some embodiments, the first portion 112a may surround the second portion 112b. In some embodiments, on a third-direction D3, at least a portion of the first portion 112a is disposed on a subsequently formed first contact ( Figure 3 Below the first contact 410. In some embodiments, on the third-direction D3, at least a portion of the second portion 112b is disposed below the subsequently formed first contact. Accordingly, this disclosure allows for adjustment of the shape and size of the first doped region 310 by adjusting the mask pattern, thereby facilitating the adjustment of the ratio of the current path analogous to that of a Schottky diode to that analogous to that of a PIN diode.

[0067] like Figure 2 As shown, in some embodiments, in the cross-sectional view, a pair of first doped regions 310 may be provided. However, the pair of first doped regions 310 are substantially continuous. In some embodiments, a portion of the first high-voltage well 112 may be inserted into the pair of first doped regions 310. In some embodiments, the first doped region 310 may directly contact the epitaxial layer 106 and the first high-voltage well 112, but this disclosure is not limited thereto. In some embodiments, the epitaxial layer 106 may be disposed between the isolation layer 200 and the first doped region 310. In some embodiments, the epitaxial layer 106 may be disposed between the first doped region 310 and the third doped region 330.

[0068] like Figure 2As shown, in some embodiments, the first doped region 310 may be disposed between the second doped region 320 and the third doped region 330. In some embodiments, the gate electrode 220 may be disposed between the first doped region 310 and the second doped region 320. Therefore, in some embodiments, the first doped region 310 may be analogous to the source doped region, and the second doped region 320 may be analogous to the drain doped region. In some embodiments, the first doped region 310 may or may not overlap with the gate electrode 220 in the normal direction (third direction D3) of the substrate 100.

[0069] Reference Figure 3 This is a cross-sectional schematic diagram of each stage of a method for forming a semiconductor device 1 according to an embodiment of the present disclosure. Figure 3 Showing along the subsequent Figure 5 The diagram shows a cross-sectional view captured by line segment I-I'. In some embodiments, an interlayer dielectric layer 400 may be formed on the gate electrode 220 in a blanket manner. In some embodiments, the interlayer dielectric layer 400 may include oxides such as silicon oxide, nitrides such as silicon nitride, oxynitrides such as silicon oxynitride, the like, or combinations thereof, but this disclosure is not limited thereto.

[0070] like Figure 3 As shown, in some embodiments, vias (not shown) may be formed in the interlayer dielectric layer 400 to expose the top surfaces of the first doped regions 310 to the third doped regions 330. In some embodiments, a first contact 410 may be formed in the via to be disposed on the first high-voltage well 112 and the first doped region 310. In some embodiments, the first contact 410 may be in direct contact with the first high-voltage well 112 and the first doped region 310. In some embodiments, the first contact 410 may cover a portion of the top surface of the first doped region 310 and expose a portion of the top surface of the first doped region 310. In some embodiments, on the third direction D3, the projection of the first contact 410 onto the substrate 100 may overlap with the projection of the first doped region 310 onto the substrate 100.

[0071] like Figure 3As shown, in some embodiments, a second contact 420 may be formed in the via so that the second contact 420 is disposed on the second doped region 320. In some embodiments, the second contact 420 may be in direct contact with the second doped region 320. In some embodiments, a third contact 430 may be formed in the via so that the third contact 430 is disposed on the third doped region 330. In some embodiments, the third contact 430 may be in direct contact with the third doped region 330. In some embodiments, the first contact 410, the second contact 420, and the third contact 430 may each penetrate the interlayer dielectric layer 400 and may include metals, metal nitrides, conductive metal oxides, the like, or combinations thereof, but this disclosure is not limited thereto.

[0072] like Figure 3 As shown, in some embodiments, a first conductive layer 510 may be formed on the interlayer dielectric layer 400, and the first conductive layer 510 is electrically connected to the first high-voltage well 112 and the first doped region 310 via a first contact 410. In some embodiments, since the opening 312 may be disposed in the first doped region 310, the first contact 410 may directly contact the first high-voltage well 112 and the first doped region 310 via the opening 312 of the first doped region 310. In some embodiments, on the third direction D3, the projection of the opening 312 surrounded by the first doped region 310 onto the substrate 100 may be located within the projection of the first contact 410 onto the substrate 100. In some embodiments, a second conductive layer 520 may be formed on the interlayer dielectric layer 400, and the second conductive layer 520 is electrically connected to the second doped region 320 via a second contact 420. In some embodiments, a third conductive layer 530 may be formed on the interlayer dielectric layer 400, and the third conductive layer 530 may be electrically connected to the third doped region 330 via a third contact 430. Thus, a semiconductor device 1 can be obtained.

[0073] like Figure 3 As shown, in some embodiments, the active region AA, in which the first doped region 310 and the first conductive layer 510 are disposed, can be the anode region of the semiconductor device, and therefore the first conductive layer 510 can serve as the anode electrode of the semiconductor device 1. In some embodiments, the active region AA, in which the second doped region 320 and the second conductive layer 520 are disposed, can be the cathode region of the semiconductor device, and therefore the second conductive layer 520 can serve as the cathode electrode of the semiconductor device 1.

[0074] like Figure 3As shown, in some embodiments, in the first current path P1, when a voltage is applied to the first conductive layer 510, current flows sequentially along the first contact 410, the first doped region 310, the epitaxial layer 106, the second doped region 320, and the second contact 420 to the second conductive layer 520. Since the first doped region 310 is analogous to a P-type semiconductor in a PIN diode, the epitaxial layer 106 is analogous to an intrinsic (I-type) semiconductor in a PIN diode, and the second doped region 320 is analogous to an N-type semiconductor in a PIN diode, the first current path P1 is analogous to the current path of a PIN diode structure to reduce the on-state leakage current of the semiconductor device 1. In some embodiments, the first doped region 310 near the second doped region 320 and the first doped region 310 near the third doped region 330 can both form the first current path P1.

[0075] like Figure 3 As shown, in some embodiments, in the first current path P1', when a voltage is applied to the first conductive layer 510, the current flows sequentially along the first contact 410, the first doped region 310, the first high-voltage well 112, the epitaxial layer 106, the second doped region 320, and the second contact 420 to the second conductive layer 520. Since the first doped region 310 is analogous to a P-type semiconductor in a PIN diode, the first high-voltage well 112 and the epitaxial layer 106 are analogous to an intrinsic (I-type) semiconductor in a PIN diode, and the second doped region 320 is analogous to an N-type semiconductor in a PIN diode, the first current path P1' is analogous to the current path of a PIN diode structure to reduce the on-state leakage current of the semiconductor device 1. The breakdown voltage of the first current path P1 can be greater than the breakdown voltage of the first current path P1'. Accordingly, the breakdown voltage of the semiconductor device 1 can be adjusted by adjusting the size of the contact interface between the first doped region 310 and the epitaxial layer 106, or the size of the contact interface between the first doped region 310 and the first high-voltage well 112.

[0076] like Figure 3 As shown, in some embodiments, in the second current path P2, when a voltage is applied to the first conductive layer 510, the current flows sequentially along the first contact 410, the first high-voltage well 112, the epitaxial layer 106, the second doped region 320, and the second contact 420 to the second conductive layer 520. Since the first contact 410, which is in direct contact with the first high-voltage well 112, can serve as the metal portion in a Schottky diode, and the first high-voltage well 112 can serve as the semiconductor portion in a Schottky diode, a Schottky barrier is generated at the interface between the first high-voltage well 112 and the first contact 410. Therefore, the second current path P2 can be analogous to the current path of a Schottky diode structure to improve the switching speed of the semiconductor device 1, reduce the recovery time, and / or reduce the on-state voltage.

[0077] In some embodiments, the first current paths P1, P1' may be connected in parallel with the second current path P2. Accordingly, the semiconductor device 1 disclosed herein may include a merged PIN Schottky (MPS) diode that connects a Schottky diode and a PIN diode in parallel.

[0078] Reference Figure 4 This is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present disclosure. Figure 4 Showing along the subsequent Figure 5 The diagram shows a cross-sectional view taken from line segment II-II'. In some embodiments, the first doped region 310 physically separates the first contact 410 from the first high-voltage well 112, thereby preventing the formation of a Schottky barrier at the interface between the first high-voltage well 112 and the first contact 410. Therefore, in Figure 4 In this embodiment, semiconductor device 1 may have first current paths P1 and P1', but not a second current path P2. In some embodiments, in the first direction D1, the width W112 of the first high-voltage well 112 may be smaller than the width W310 of the first doped region 310.

[0079] Reference Figure 5 This is a top view schematic diagram of a semiconductor device 1 according to an embodiment of the present disclosure. In some embodiments, in the top view, the first doped region 310 may surround the first contact 410. In some embodiments, in the top view, the extending direction of the gate electrode 220 is a second direction D2, and the openings 312 of the first doped region 310 may be spaced apart along the extending direction of the gate electrode 220, i.e., the second direction D2. In some embodiments, the openings 312 may have triangular, rectangular, circular, elliptical, polygonal, polygonal with arcuate edges, or other suitable shapes, but the present disclosure is not limited thereto. In some embodiments, the number of openings 312 may be a positive integer from 1 to 100, but the present disclosure is not limited thereto.

[0080] Reference Figure 6 This is a top view schematic diagram of a semiconductor device 1 according to an embodiment of the present disclosure. For ease of explanation, in Figure 6The diagram only shows the substrate 100, the first high-voltage well 112, the first doped regions 310 to the third doped regions 330, and the opening 312. In some embodiments, in the top view, the first doped region 310 may cover a first portion 112a of the first high-voltage well 112, forming a current path (first current path P1, P1') analogous to a PIN diode structure. In some embodiments, in the top view, the first doped region 310 may expose a second portion 112b of the first high-voltage well 112, forming a current path (second current path P2) analogous to a Schottky diode structure. The second portion 112b may correspond to the opening 312.

[0081] Therefore, the area of ​​the first portion 112a can correspond to the area of ​​the PIN diode, and the area of ​​the second portion 112b can correspond to the area of ​​the Schottky diode. In some embodiments, when the area of ​​the first portion 112a can be A1 and the area of ​​the second portion 112b can be A2, the ratio of the PIN diode to the Schottky diode (PIN diode / Schottky diode) can be A1 / A2. In some embodiments, A1 / A2 can be 0.1 to 10, but this disclosure is not limited thereto. For example, A1 / A2 can be 0.1, 0.125, 0.2, 0.25, 0.5, 0.75, 1, 1.33, 2, 4, 5, 8, 10, or any value or a range of values ​​between the aforementioned values, but this disclosure is not limited thereto. Figure 6 As shown, in some embodiments, A1 / A2 can be approximately 4.

[0082] In the following text, identical or similar component symbols and descriptions are omitted.

[0083] Reference Figure 7 This is a top view schematic diagram of a semiconductor device 2 according to an embodiment of the present disclosure. In some embodiments, in the top view, the opening 312 of the first doped region 310 may have different sizes to adjust the ratio of an analog Schottky diode structure to an analog PIN diode structure. Figure 7 As shown, in some embodiments, A3 / A4 may be approximately 2.

[0084] Reference Figure 8 This is a top view of a semiconductor device 3 according to an embodiment of the present disclosure. In some embodiments, in the top view, the extending direction of the gate electrode 220 is a second direction D2, and the openings 312 of the first doped region 310 may extend along the extending direction of the gate electrode 220 (second direction D2) and are spaced apart along a first direction D1 perpendicular to the extending direction of the gate electrode 220 (second direction D2).

[0085] Reference Figure 9This is a top view schematic diagram of a semiconductor device 4 according to an embodiment of the present disclosure. In some embodiments, an opening 312 may be disposed on the upper part of the first doped region 310, but not on the lower part of the first doped region 310. In some embodiments, in the top view, the upper edge of the opening 312 may be flush with the upper edge of the first doped region 310. In other embodiments (not shown), in the top view, the upper edge of the opening 312 may be spaced apart from the upper edge of the first doped region 310 by a distance to reduce leakage current.

[0086] Reference Figure 10 and Figure 11 These are cross-sectional schematic diagrams of a semiconductor device 5 according to an embodiment of this disclosure. Figure 10 Showing along the aforementioned Figure 5 The diagram shows a cross-sectional view captured by line segment I-I', and Figure 11 Showing along the aforementioned Figure 5 The diagram shows a cross-sectional view captured by line segment II-II'.

[0087] like Figure 10 As shown, in some embodiments, the first doped region 310 can directly contact the first high-voltage well 112, and the first doped region 310 is spaced apart from the epitaxial layer 106 by a distance. In some embodiments, the first high-voltage well 112 can be inserted between the first doped region 310 and the epitaxial layer 106. In some embodiments, the first high-voltage well 112 can surround the first doped region 310. In some embodiments, the projection of the first doped region 310 onto the substrate 100 is located within the projection of the first high-voltage well 112 onto the substrate 100.

[0088] like Figure 11 As shown, in some embodiments, in the first direction D1, the width W112 of the first high-voltage well 112 may be greater than the width W102 of the first buried layer 102. In some embodiments, in the first direction D1, the width W112 of the first high-voltage well 112 may be greater than the width W310 of the first doped region 310. Therefore, in Figure 10 In this process, semiconductor device 5 may have a first current path P1' and a second current path P2. Figure 11 In this embodiment, semiconductor device 5 may have a first current path P1' and no second current path P2. In some embodiments, the breakdown voltage of semiconductor device 5 may be less than the breakdown voltage of semiconductor devices 1 to 4.

[0089] In some embodiments, one or more of the semiconductor devices 1 to 5 disclosed herein can be applied to high voltage integrated circuits (HVICs), particularly to bootstrap circuits.

[0090] Accordingly, the first current paths P1 and P1' disclosed herein are analogous to the current paths of a PIN diode structure, thus reducing the on-state leakage current of the semiconductor device. Since the second current path P2 disclosed herein is analogous to the current path of a Schottky diode structure, it can improve the switching speed of the semiconductor device, reduce the recovery time, and / or reduce the on-state voltage.

[0091] Since the first current path P1, P1' and the second current path P2 disclosed herein can both be compared to the current paths of a combined PIN Schottky diode structure, they can possess the characteristics of both Schottky diodes and PIN diodes. Furthermore, the electrical properties of the semiconductor device can be adjusted by changing the ratio (e.g., area ratio) between the structure comparable to a Schottky diode and the structure comparable to a PIN diode.

[0092] Furthermore, this disclosure adjusts the breakdown voltage of the semiconductor device by modifying the contact interface with the first doped region. Accordingly, this disclosure can reduce on-state leakage current, increase switching speed, reduce recovery time, reduce on-state voltage, and / or increase breakdown voltage, thereby improving the electrical properties and reliability of the semiconductor device.

[0093] The scope of protection of this disclosure is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Those skilled in the art can understand from the content of this disclosure any existing or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps that can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. No embodiment or claim of this disclosure is required to achieve all the objects, advantages, and / or features described herein.

[0094] The above outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments disclosed herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments disclosed herein to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first conductivity type; An epitaxial layer is disposed on the substrate and has a second conductivity type different from the first conductivity type; A first high-voltage well is disposed in the epitaxial layer and has the second conductivity type; A first doped region is disposed in the first high-voltage well and has the first conductivity type; A gate dielectric layer is disposed on the epitaxial layer; and A gate electrode is disposed on the gate dielectric layer; The first doped region covers a first portion of the first high-voltage well and exposes a second portion of the first high-voltage well.

2. The semiconductor device as claimed in claim 1, characterized in that, Including: A first contact material is disposed on the first high-voltage well and the first doped region, and contacts the first high-voltage well and the first doped region.

3. The semiconductor device as claimed in claim 1, characterized in that, In a top view, the first doped region surrounds the first high-voltage well.

4. The semiconductor device as claimed in claim 1, characterized in that, The first doped region includes an opening that exposes the first high-voltage well.

5. The semiconductor device as claimed in claim 4, characterized in that, The opening is arranged along the extension direction of the gate electrode, or along a direction perpendicular to the extension direction of the gate electrode.

6. The semiconductor device as claimed in claim 1, characterized in that, The width of the first high-pressure well is greater than or less than the width of the first doped region.

7. The semiconductor device as claimed in claim 1, characterized in that, Including: A second doped region is disposed in the epitaxial layer and has the second conductivity type, and the gate electrode is disposed between the first doped region and the second doped region.

8. The semiconductor device as claimed in claim 7, characterized in that, Including: A first buried layer is disposed between the substrate and the first high-voltage trap, and has the second conductivity type.

9. The semiconductor device as claimed in claim 8, characterized in that, The width of the first high-pressure well is greater than or less than the width of the first buried layer.

10. The semiconductor device as claimed in claim 8, characterized in that, Including: A second high-voltage well is disposed in the epitaxial layer and has the first conductivity type; A third doped region is disposed in the second high-voltage well, has the first conductivity type, and is disposed between the second doped region and the third doped region; and A second buried layer is disposed between the substrate and the second high-voltage trap, and has the first conductivity type.

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