Groove type device and manufacturing method thereof
By designing a trench-type device structure with a width greater than its depth and three non-uniformly doped epitaxial layers, the problem of charge balance and integration of P-type and N-type pillars in wide-bandgap semiconductors was solved, achieving synergistic optimization of low on-resistance and high breakdown voltage.
Patent Information
- Application Number
- CN202511803747.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-01
- Publication Date
- 2026-03-03
AI Technical Summary
In wide bandgap semiconductor materials, how to precisely control the charge balance of P-type and N-type pillars and optimize their integration with trench gate structures to significantly reduce specific on-resistance while maintaining high breakdown voltage?
Design a trench-type device structure including a trench gate with a width greater than its depth, with first and second buried pillar regions forming a superjunction structure, and the epitaxial layer adopting a three-layer non-uniform doped structure. The area where the bottom of the trench gate intersects with the sidewall directly contacts the epitaxial layer to optimize the electric field distribution.
It significantly reduces the specific on-resistance of the device, improves the breakdown voltage and reliability, optimizes the electric field distribution, and achieves a reduction in conduction loss and an increase in breakdown voltage.
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Figure CN121604455A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of trench device manufacturing technology, and in particular to a trench device and its manufacturing method. Background Technology
[0002] Power trench devices are core components of modern power electronic systems, and their performance directly affects the efficiency and reliability of power conversion. To achieve high breakdown voltage, metal-oxide-semiconductor field-effect transistors (MOSFETs) typically require a thin, lightly doped epitaxial layer as the drift region. However, this increases the on-resistance of the device, limiting further performance improvements. The concept of super-junctions, by alternating P-type and N-type semiconductor pillars within the same drift region, achieves an ideal trade-off between on-resistance and breakdown voltage, breaking the "silicon limit" of traditional structures.
[0003] However, applying superjunction structures to trench power devices presents new challenges. Especially in wide-bandgap semiconductor materials (such as silicon carbide and gallium nitride), precisely controlling the charge balance of P-type and N-type pillars and optimizing their integration with the trench gate structure becomes crucial for improving device performance. Therefore, a new trench device structure and its fabrication method are needed to more effectively integrate the superjunction principle, significantly reducing specific on-resistance while maintaining high breakdown voltage. Summary of the Invention
[0004] To address the aforementioned problems, this disclosure proposes an optimized trench device and its manufacturing method to resolve the problems existing in the prior art.
[0005] According to one aspect of the embodiments of this disclosure, a trench-type device is provided, comprising:
[0006] Substrate;
[0007] An epitaxial layer, having a first conductivity type, is located on the substrate;
[0008] A trench gate extends from the surface of the epitaxial layer into the epitaxial layer, wherein the width of the trench gate is greater than its depth.
[0009] The body region, having a second conductivity type, is located in the epitaxial layer and adjacent to the sidewall of the trench gate;
[0010] A source region, having the first conductivity type, is located in the body region and adjacent to the sidewall of the trench gate; and
[0011] The first and second embedded pillar regions, having the second conductivity type, are located within the epitaxial layer.
[0012] Wherein, the first conductivity type is the opposite of the second conductivity type.
[0013] The first embedded post area is located below the trench grid and adjacent to the bottom of the trench grid, while the second embedded post area is located below the body area and adjacent to the bottom of the body area.
[0014] The first embedded column region, the second embedded column region, and the epitaxial layer sandwiched between them constitute a superjunction structure.
[0015] Optionally, in the corner region where the bottom of the trench gate intersects with the sidewall, the gate dielectric layer is in direct contact with the epitaxial layer and is not covered by the body region.
[0016] Optionally, the epitaxial layer includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked longitudinally in sequence, wherein the doping concentration of the first epitaxial layer and the third epitaxial layer is less than the doping concentration of the second epitaxial layer.
[0017] Optionally, the first embedded column area and the second embedded column area are located in the second epitaxial layer.
[0018] Optionally, the first embedded column area and the second embedded column area have the same thickness as the second epitaxial layer in the longitudinal direction.
[0019] Optionally, the trench gate and the body region are located in the third epitaxial layer, and the bottom of the trench gate is located near the adjacent surface of the second epitaxial layer and the third epitaxial layer.
[0020] Optionally, along the width direction of the trench gate, the body region includes adjacent shallow-doped regions and deep-doped regions, the shallow-doped regions being adjacent to the sidewalls of the trench gate, and the bottom of the shallow-doped regions being higher than the bottom of the trench gate.
[0021] The bottom of the deeply doped region is substantially flush with the bottom of the trench gate.
[0022] Optionally, the thicknesses of the first epitaxial layer and the third epitaxial layer are both less than the thickness of the second epitaxial layer.
[0023] Optionally, it also includes a plurality of lead-out regions disposed along the length direction of the trench gate, wherein adjacent lead-out regions are separated by the second epitaxial layer.
[0024] The doping type of the plurality of lead-out regions is the same as that of the body region, and the plurality of lead-out regions connect the first buried pillar region and the second buried pillar region.
[0025] According to another aspect of the embodiments of this disclosure, a method for manufacturing a trench-type device is provided.
[0026] include:
[0027] A first epitaxial layer is grown on the substrate;
[0028] A second sub-epitaxial layer is grown on the first epitaxial layer;
[0029] Dopant is implanted into the first and second regions of the second sub-epitaxial layer to form a first doped region and a second doped region spaced apart from each other.
[0030] The second sub-epieptaxial layer is repeatedly grown, and dopant is implanted into the first and second regions of the second sub-epieptaxial layer to form multiple layers of the second sub-epieptaxial layer, multiple layers of the first doped region, and multiple layers of the second doped region.
[0031] Among them, multiple second sub-epitaxial layers form a second epitaxial layer, multiple first doped regions form a first buried pillar region, and multiple second doped regions form a second buried pillar region;
[0032] A third epitaxial layer is grown on the second epitaxial layer;
[0033] A volume region and a trench gate are formed in the third epitaxial layer; and
[0034] A source region is formed in the body region.
[0035] Optionally, the doping concentrations of the first epitaxial layer and the third epitaxial layer are lower than the doping concentration of the second epitaxial layer.
[0036] Optionally, in the steps of repeatedly growing the second sub-epilithographic layer and implanting dopant into the first and second regions of the second sub-epilithographic layer:
[0037] After each dopant implantation, a partial push-up process is performed to allow the dopant to diffuse longitudinally within the second sub-epieptaxial layer grown in that cycle.
[0038] Through the aforementioned partial advancement process, the first doped region and the second doped region formed in each implantation are controlled to not completely penetrate the second sub-epitaxial layer in that implantation.
[0039] By repeating the above steps, the first doped region and the second doped region formed by multiple implantations are connected to each other in the longitudinal direction to form a continuous first buried pillar region and second buried pillar region.
[0040] One of the above technical solutions has the following beneficial effects:
[0041] By configuring the trench gate as a wide trench structure with a width greater than its depth, it is possible to establish separate first and second buried pillar regions below the trench gate and below the body region, respectively, within a limited space. These two buried pillar regions, together with the epitaxial layer sandwiched between them, constitute a superjunction structure. This structure brings significant technical benefits: First, it greatly increases the lateral density of P-pillars (i.e., buried pillar regions) in the superjunction structure. Compared to schemes that only place P-pillars below the trench or only below the body region, the double P-pillar design allows the N-type region (i.e., the epitaxial layer portion) between adjacent P-pillars to be narrower. According to superjunction theory, while maintaining charge balance to achieve a high breakdown voltage, narrower N-type pillars allow for a higher doping concentration, thereby significantly reducing the resistance of the drift region and ultimately effectively reducing the specific on-resistance (Rsp) of the device, thus optimizing conduction losses. Second, this layout optimizes the electric field distribution inside the device, contributing to improved breakdown voltage and reliability.
[0042] By ensuring that the gate dielectric layer at the corner where the bottom of the trench gate intersects with the sidewall is in direct contact with the epitaxial layer and is not covered by the body region, or in other words, exposing the corner of the trench gate to the epitaxial layer, the need for an electric field shielding region connected to the body region is avoided. This design allows the entire sidewall of the trench to be used to form a conductive channel. Compared to solutions that sacrifice the channel on one side of the trench gate due to partial shielding, this disclosure significantly increases the effective channel width while ensuring gate oxide reliability, thereby effectively reducing the on-resistance of the device.
[0043] By configuring the epitaxial layer into a three-layer structure—a first and third epitaxial layer with a relatively low doping concentration, and a second epitaxial layer with a relatively high doping concentration sandwiched in between—this non-uniformly doped epitaxial layer structure offers significant technical advantages. The highly doped second epitaxial layer, serving as the primary current conduction path, helps to further reduce the device's on-resistance. Meanwhile, the lightly doped first and third epitaxial layers located above and below it optimize the electric field distribution. Particularly in the first epitaxial layer near the substrate and the third epitaxial layer near the active region, the lower doping concentration mitigates the electric field peaks at the interface, preventing breakdown from occurring first in these regions, thus synergistically improving the overall breakdown voltage in conjunction with the superjunction structure.
[0044] Furthermore, the first and second buried pillar regions are confined within a highly doped second epitaxial layer. This confinement allows the superjunction structure (composed of a P-type buried pillar region and an N-type second epitaxial layer) to be precisely positioned in the critical region for device resistance and electric field management. The highly doped N-type second epitaxial layer and P-type buried pillar region achieve a more precise charge balance, thereby ensuring high breakdown voltage while achieving low on-resistance. Concentrating the superjunction structure within the second epitaxial layer also facilitates fabrication and control.
[0045] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this disclosure. Attached Figure Description
[0046] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.
[0047] Figure 1 A three-dimensional structural schematic diagram of the trench-type device in an embodiment of this disclosure is shown.
[0048] Figure 2 It shows Figure 1 A schematic diagram of the structure of the mid-section 10.
[0049] Figure 3 It shows Figure 1 A schematic diagram of the structure of the epitaxial layer.
[0050] Figure 4 It shows along Figure 1 A cross-sectional view of the section cut by line AA.
[0051] Figures 5 to 10 The diagram shows a schematic representation of a portion of the method for fabricating a trench-type device according to an embodiment of this disclosure. Detailed Implementation
[0052] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.
[0053] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.
[0054] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".
[0055] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.
[0056] Figure 1 A three-dimensional structural schematic diagram of the trench device according to an embodiment of the present disclosure is shown. Figure 2 It shows Figure 1 A structural schematic diagram of mid-section 10. Wherein, Figure 1 The structures above other epitaxial layers are omitted to more clearly express the positional relationships between the various structures.
[0057] like Figure 1 and Figure 2 As shown, the trench device of this embodiment includes: a substrate 101, an epitaxial layer 110, a first buried pillar region 121, a second buried pillar region 122, a body region 130, a trench gate 140, a source region 150, a body contact region 151, an interlayer dielectric layer 160, a first conductive layer 171, and a second conductive layer 172.
[0058] The trench-type device in this disclosure can be used as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT).
[0059] The epitaxial layer 110 is located on the substrate 101, and the first buried pillar region 121, the second buried pillar region 122, the body region 130 and the trench gate 140 are located in the epitaxial layer 110.
[0060] The substrate 101 is made of materials such as SiC, GaN, Ga2O3, Al2O3, or other wide bandgap semiconductor materials, and the epitaxial layer 110 is made of materials such as SiC, GaN, or other wide bandgap semiconductor materials.
[0061] The surface of the epitaxial layer 110 has a trench, and a trench gate 140 is located in the trench. The trench gate 140 includes a gate dielectric layer 141 and a gate conductor 142. The gate dielectric layer 141 covers the inner surface of the trench, and the gate conductor 142 is located in the trench. The gate dielectric layer 141 is located between the epitaxial layer 110 and the gate conductor 142, serving to separate the epitaxial layer 110 from the gate conductor 142.
[0062] The width direction of the trench gate 140 is defined as the X-axis, the depth direction as the Z-axis, and the length direction as the Y-axis, where the Z-axis corresponds to the longitudinal direction of the device. Optionally, the X-axis, Y-axis, and Z-axis directions are mutually perpendicular.
[0063] In this embodiment, the width of the trench gate 140 is greater than its depth. In some alternative embodiments, the width of the trench gate 140 is not less than 1 μm.
[0064] Body region 130 extends from the surface of epitaxial layer 110 into the epitaxial layer 110 and is adjacent to the two sidewalls of trench gate 140. Source region 150 and body contact region 151 are located in body region 130, and source region 150 is adjacent to the two sidewalls of trench gate 140.
[0065] The first buried column area 121 is located below the trench grid 140 and adjacent to the bottom of the trench grid 140. The corner where the bottom of the trench grid 140 is adjacent to the sidewall is exposed in the epitaxial layer 110. In other words, the grid dielectric layer 141 in the corner area where the bottom of the trench grid 140 intersects with the sidewall is in direct contact with the epitaxial layer 110 and is not covered by the body area 130.
[0066] The second embedded column area 122 is located below the body area 130 and adjacent to the bottom of the body area 130.
[0067] In this embodiment, the first embedded pillar region 121, the second embedded pillar region 122, and the epitaxial layer 110 sandwiched between them constitute a superjunction structure.
[0068] An interlayer dielectric layer 160 is located on the surface of the epitaxial layer 110 and covers the trench gate 140. The interlayer dielectric layer 160 is located on the first surface 101 of the semiconductor layer 100 and covers the trench gate 140. A first conductive layer 171 serves as the source, covering the exposed surfaces of the interlayer dielectric layer 160 and the epitaxial layer 110, thereby electrically connecting to the source region 150 and the body contact region 151. A second conductive layer 172 serves as the drain, covering the back side of the substrate 101.
[0069] The epitaxial layer 110 and the source region 150 are of the first conductivity type, while the body region 130, the first buried pillar region 121, the second buried pillar region 122, and the body contact region 151 are of the second conductivity type. The doping concentration of the body contact region 151 is greater than that of the body region 130. The first conductivity type is the opposite of the second conductivity type; the first conductivity type is either P-type or N-type, and the second conductivity type is either P-type or N-type.
[0070] For ease of description, this embodiment uses N-type as the first conductivity type and P-type as the second conductivity type to illustrate the specific implementation of this disclosure. Based on this, the first buried pillar region 121 and the second buried pillar region 122 can serve as the P-pillar regions of the superjunction structure, while the portion of the epitaxial layer 110 sandwiched between the P-pillar regions serves as the N-pillar region of the superjunction structure.
[0071] like Figure 3 As shown, in some specific embodiments, the epitaxial layer 110 includes a first epitaxial layer 111, a second epitaxial layer 112 and a third epitaxial layer 113 stacked longitudinally on the substrate 101.
[0072] The doping concentrations of the first epitaxial layer 111 and the third epitaxial layer 113 are lower than the doping concentration of the second epitaxial layer 112.
[0073] The thickness of the first epitaxial layer 111 and the third epitaxial layer 113 is less than the thickness of the second epitaxial layer 112.
[0074] The first embedded pillar region 121 and the second embedded pillar region 122 are located in the second epitaxial layer 112. The first embedded pillar region 121 and the second embedded pillar region 122 have the same thickness as the second epitaxial layer 112 in the longitudinal direction, or in other words, the first embedded pillar region 121 and the second embedded pillar region 122 extend longitudinally to the adjacent surfaces of the first epitaxial layer 111 and the second epitaxial layer 112, as well as the adjacent surfaces of the second epitaxial layer 112 and the third epitaxial layer 113.
[0075] The trench gate 140 and the body region 130 are located in the third epitaxial layer 113, and the bottom of the trench gate 140 is located near the adjacent surface of the second epitaxial layer 112 and the third epitaxial layer 113.
[0076] In some alternative embodiments, along the X-axis, the body region 130 includes a shallowly doped region 131 and a deeply doped region 132 adjacent to each other. The shallowly doped region 131 is adjacent to the sidewall of the trench gate 140, and the bottom of the shallowly doped region 131 is higher than the bottom of the trench gate 140. The bottom of the deeply doped region 132 is substantially flush with the bottom of the trench gate 140.
[0077] The second buried pillar region 122 is adjacent to the bottom of the deeply doped region 132, but not adjacent to the shallow doped region 131, thereby creating conditions for the corner of the trench gate 140 to be exposed in the third epitaxial layer 113.
[0078] like Figure 1 and Figure 4 As shown, in some specific embodiments, the trench-type device of this disclosure further includes a plurality of pick-up areas 180 arranged along the Y-axis direction, and adjacent pick-up areas 180 are separated by a second epitaxial layer 112 along the Y-axis direction.
[0079] The doping type of the lead-out region 180 is the same as that of the body region 130, and multiple lead-out regions 180 connect the first buried pillar region 121 and the second buried pillar region 122. Thus, the first buried pillar region 121 below the trench gate 140 is electrically connected to the source electrode in sequence through the lead-out region 180, the body region 130 and the source region 150, thereby achieving a stable shielding effect.
[0080] Figures 5 to 10 The diagram shows a partial structural schematic of a method for fabricating a trench-type device according to an embodiment of this disclosure. The method includes the following steps:
[0081] like Figure 5 As shown, multiple epitaxial growths are performed sequentially on substrate 101 to form longitudinally stacked epitaxial layers.
[0082] In this step, for example, a first epitaxial layer 111 is first grown on a substrate 101, and then a second epitaxial layer 112 is grown on the first epitaxial layer 111. The doping concentration and thickness of the second epitaxial layer 112 are adjusted by controlling the deposition process parameters so that the doping concentration of the second epitaxial layer 112 is higher than that of the first epitaxial layer 111, and the second epitaxial layer 112 is thicker than the first epitaxial layer 111.
[0083] Furthermore, a first embedded pillar region 121 and a second embedded pillar region 122 are formed in the second epitaxial layer 112, such as Figure 6 As shown.
[0084] In this step, for example, doping elements are introduced into the second epitaxial layer 112 by ion implantation, and the first buried pillar region 121 and the second buried pillar region 122 are extended longitudinally to the upper and lower surfaces of the second epitaxial layer 112 by high temperature propulsion.
[0085] like Figure 7 As shown, in some optional embodiments, the second epitaxial layer 112 can be deposited in multiple stages, with each deposition forming a sublayer 112a. After each deposition of the sublayer 112a, ion implantation and partial propulsion are performed, so that the buried pillar regions in each sublayer 112a are gradually superimposed to form a continuous structure with a length that runs through the second epitaxial layer 112.
[0086] Specifically, it may include the following steps:
[0087] A second sub-epithelial layer 112a is grown on the first epitaxial layer 111;
[0088] Dopant is implanted into the first region 11 and the second region 12 of the second sub-epitaxial layer 112a to form a first doped region 121a and a second doped region 122a that are spaced apart from each other.
[0089] The second sub-epipolar layer 112a is repeatedly grown and dopant is implanted into the first region 11 and the second region 12 of the second sub-epipolar layer 112a to form a multilayer second sub-epipolar layer 112a, a multilayer first doped region 121a and a multilayer second doped region 122a, wherein the multilayer second sub-epipolar layer 112a forms the second epitaxial layer 112, the multilayer first doped region 121a forms the first buried pillar region 121, and the multilayer second doped region 122a forms the second buried pillar region 122.
[0090] This method can form a vertically continuous distribution of pillar regions with precisely controllable doping gradients, thereby improving the uniformity of device breakdown voltage.
[0091] The multiple epitaxial layer growth method allows for the deposition of a thinner second sub-epitaxy layer 112a each time, and the repeated ion implantation process results in better epitaxial layer uniformity and higher epitaxial layer quality. Furthermore, it reduces the energy required for each ion implantation, improves the control precision of ion implantation, and forms a higher quality first buried pillar region 121 and second buried pillar region 122.
[0092] The steps of repeatedly growing the second sub-epilithographic layer 112a and implanting dopant into the first region 11 and the second region 12 of the second sub-epilithographic layer 112a may include:
[0093] After each ion implantation, a partial propulsion process is performed to allow the dopant to diffuse longitudinally within the second sub-epithetic layer 112a grown in that cycle.
[0094] By using a partial push-in process, the first doped region 121a and the second doped region 122a formed in each implantation are controlled to not completely penetrate the second sub-epitaxial layer 112a in that current implantation.
[0095] By repeating the above steps, the first doped region 121a and the second doped region 122a formed by multiple implantations are connected to each other in the longitudinal direction to form a continuous first buried pillar region 121 and second buried pillar region 122.
[0096] Since each injection is followed by a propulsion, but the propulsion is "partial", the first doped region 121a and the second doped region 122a can diffuse within the monolayer without penetrating the monolayer. This allows for precise control of the vertical doping distribution and avoids excessive diffusion that could lead to premature connection of adjacent buried pillar regions or loss of doping profile control.
[0097] Furthermore, a third epitaxial layer 113 is grown on the second epitaxial layer 112, such as... Figure 8 As shown.
[0098] In this step, the doping concentration of the third epitaxial layer 113 is controlled to be lower than that of the second epitaxial layer 112 by adjusting the growth conditions, and the thickness adapter device breakdown voltage requirement is met.
[0099] Optionally, the thickness of the third epitaxial layer 113 is less than the thickness of the second epitaxial layer 112.
[0100] In this embodiment, the contribution of the highly doped layer to the conduction performance is maximized. The second epitaxial layer 112 serves as the main drift region, and its large thickness provides sufficient conductive cross-sectional area, further reducing longitudinal resistance. It can effectively suppress the on-state voltage drop, especially in high-voltage applications.
[0101] Furthermore, a volume region 130 is formed in the third epitaxial layer 113, such as Figure 9 As shown.
[0102] In this step, doping elements are implanted into the third epitaxial layer 113 by mask control and advanced at high temperature to form a bulk region 130 including a shallow doped region 131 and a deep doped region 132.
[0103] The bottom of the deeply doped region 132 is in direct contact with the second buried pillar region 122, while the shallowly doped region 131 is located above the first buried pillar region 121 and is not connected to the first buried pillar region 121.
[0104] In some alternative embodiments, an exit region 180 is also formed in the epitaxial layer 110, which is formed by an ion implantation process, and adjacent exit regions 180 are separated by the second epitaxial layer 112 along the Y-axis direction. The doping type of the exit region 180 is the same as that of the body region 130, and it is connected to the first buried pillar region 121, the second buried pillar region 122, and the body region 130, respectively.
[0105] Further, trenches are etched on the surface of the third epitaxial layer 113, and a gate dielectric layer 141 and a gate conductor 142 are sequentially deposited within the trenches to form a trench gate 140, as shown below. Figure 10 As shown.
[0106] In this step, the trench depth is precisely controlled by anisotropic etching to ensure that the bottom of the trench is located near the interface between the third epitaxial layer 113 and the second epitaxial layer 112, thereby maintaining the device's breakdown voltage characteristics. A combination of high-temperature oxidation and chemical vapor deposition is used to deposit the gate dielectric layer 141, improving the interface state density control capability; subsequently, polysilicon is filled as the gate conductor 142.
[0107] Subsequently, the source region 150, the bulk contact region 151, the interlayer dielectric layer 160, and the conductive layer are injected sequentially, ultimately completing the process as follows: Figures 1 to 4 Fabrication of the trench-type device shown.
[0108] In this manufacturing method, a three-layer epitaxial structure (low-high-low) with non-uniform doping characteristics is formed by performing multiple epitaxial growths on substrate 101 in sequence, and a through-type P-type buried pillar region is constructed in the highly doped second epitaxial layer 112 to finally form a trench gate device. This method achieves synergistic optimization of the device's specific on-resistance (Rsp) and breakdown voltage (BV).
[0109] This manufacturing method overcomes the performance bottleneck of traditional uniform epitaxial layers. Specifically, traditional devices use epitaxial layers with a single doping concentration, making it difficult to simultaneously achieve low on-resistance and high breakdown voltage. This invention significantly reduces the drift region resistance at the same breakdown voltage by setting a second, highly doped epitaxial layer 112 in the middle as the main current channel.
[0110] This manufacturing method also enables the precise construction of superjunction structures. Specifically, the first buried pillar region 121 and the second buried pillar region 122 of the P-type are confined within a highly doped N-type layer, and through process control, they are extended longitudinally to near the upper and lower interfaces to ensure that the P-pillars and N-pillars are fully matched in the key regions, forming a superjunction structure with good charge balance and improving the current carrying capacity per unit area.
[0111] Furthermore, devices fabricated using this method can improve electric field distribution and enhance reliability. The first epitaxial layer 111 and the third epitaxial layer 113 are lightly doped, which mitigates electric field concentration on the substrate side and the surface side, respectively, avoiding local breakdown and improving the edge breakdown voltage and long-term operational stability of the device. Moreover, it is compatible with standard CMOS process flows, based on conventional epitaxy, implantation, and etching steps, requiring no special equipment and possessing good mass production feasibility and process robustness.
[0112] The present disclosure has been described in detail above with reference to specific embodiments, but the present disclosure is not limited to the details of the above embodiments. Without departing from the spirit and scope of the present disclosure, those skilled in the art can make various equivalent modifications, substitutions or variations to the technical solutions of the present disclosure, and such modifications, substitutions or variations should all be covered within the protection scope defined by the claims of the present disclosure.
Claims
1. A trench-type device, comprising: Substrate; An epitaxial layer, having a first conductivity type, is located on the substrate; A trench gate extends from the surface of the epitaxial layer into the epitaxial layer, wherein the width of the trench gate is greater than its depth. The body region, having a second conductivity type, is located in the epitaxial layer and adjacent to the sidewall of the trench gate; A source region, having the first conductivity type, is located in the body region and adjacent to the sidewall of the trench gate; and The first and second embedded pillar regions, having the second conductivity type, are located within the epitaxial layer. Wherein, the first conductivity type is the opposite of the second conductivity type. The first embedded post area is located below the trench grid and adjacent to the bottom of the trench grid, while the second embedded post area is located below the body area and adjacent to the bottom of the body area. The first embedded column region, the second embedded column region, and the epitaxial layer sandwiched between them constitute a superjunction structure.
2. The trench-type device according to claim 1, wherein, The corner region where the bottom of the trench gate intersects with the sidewall has its gate dielectric layer in direct contact with the epitaxial layer and is not covered by the body region.
3. The trench-type device according to claim 1, wherein, The epitaxial layer It includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer stacked vertically in sequence, wherein the doping concentration of the first epitaxial layer and the third epitaxial layer is less than the doping concentration of the second epitaxial layer.
4. The trench-type device according to claim 3, wherein, The first embedded column area and the second embedded column area are located in the second epitaxial layer.
5. The trench-type device according to claim 4, wherein, The first embedded column area and the second embedded column area have the same thickness as the second epitaxial layer in the longitudinal direction.
6. The trench-type device according to claim 3, wherein, The trench gate and the body region are located in the third epitaxial layer, and the bottom of the trench gate is located near the adjacent surface of the second epitaxial layer and the third epitaxial layer.
7. The trench-type device according to claim 6, wherein, Along the width direction of the trench gate, the body region includes adjacent shallow-doped regions and deep-doped regions. The shallow-doped regions are adjacent to the sidewalls of the trench gate, and the bottom of the shallow-doped regions is higher than the bottom of the trench gate. The bottom of the deeply doped region is substantially flush with the bottom of the trench gate.
8. The trench-type device according to any one of claims 3 to 7, wherein, The thicknesses of the first epitaxial layer and the third epitaxial layer are both less than the thickness of the second epitaxial layer.
9. The trench device according to claim 3 further includes a plurality of lead-out regions disposed along the length direction of the trench gate, wherein adjacent lead-out regions are separated by the second epitaxial layer. in, The doping type of the plurality of lead-out regions is the same as that of the body region, and the plurality of lead-out regions connect the first buried pillar region and the second buried pillar region.
10. A method for manufacturing a trench-type device, comprising: A first epitaxial layer is grown on the substrate; A second sub-epitaxial layer is grown on the first epitaxial layer; Dopant is implanted into the first and second regions of the second sub-epitaxial layer to form a first doped region and a second doped region spaced apart from each other. The second sub-epieptaxial layer is repeatedly grown, and dopant is implanted into the first and second regions of the second sub-epieptaxial layer to form multiple layers of the second sub-epieptaxial layer, multiple layers of the first doped region, and multiple layers of the second doped region. Among them, multiple second sub-epitaxial layers form a second epitaxial layer, multiple first doped regions form a first buried pillar region, and multiple second doped regions form a second buried pillar region; A third epitaxial layer is grown on the second epitaxial layer; A volume region and a trench gate are formed in the third epitaxial layer; and A source region is formed in the body region.
11. The manufacturing method according to claim 10, wherein, The doping concentrations of the first epitaxial layer and the third epitaxial layer are less than the doping concentration of the second epitaxial layer.
12. The manufacturing method according to claim 10, wherein, In the steps of repeatedly growing the second sub-epilithographic layer and implanting dopant into the first and second regions of the second sub-epilithographic layer: After each dopant implantation, a partial push-up process is performed to allow the dopant to diffuse longitudinally within the second sub-epieptaxial layer grown in that cycle. Through the aforementioned partial advancement process, the first doped region and the second doped region formed in each implantation are controlled to not completely penetrate the second sub-epitaxial layer in that implantation. By repeating the above steps, the first doped region and the second doped region formed by multiple implantations are connected to each other in the longitudinal direction to form a continuous first buried pillar region and second buried pillar region.