Semiconductor device with synchronous photogates

Abstract

A semiconductor device includes a high electron mobility transistor (HEMT) and a light emitting device. The HEMT has a nucleating layer, a buffer layer, a channel layer, a barrier layer, a source and a drain, a P-type doped III-V layer and a gate. The nucleating layer is on the substrate over which the buffer layer and the channel layer are stacked. A 2DEG region can be formed at an interface between the channel layer and the barrier layer. Source and drain electrodes are on the barrier layer. A P-type doped III-V layer may be formed. The gate electrode is located between the source electrode and the drain electrode and located above the P-type doped III-V layer. A light emitting device is over the HEMT that emits an optical signal synchronized with the gate drive signal to create a synchronized photogated switch.

Description

Technical Field

[0001] This invention generally relates to nitride-based semiconductor devices; more specifically, this invention relates to a semiconductor device having a synchronous photogate. Background Technology

[0002] Power devices are electronic devices used to control and convert electrical energy in power systems, playing a crucial role in power electronics, energy management, and electrical equipment. To reduce system power consumption, power devices need to provide low on-resistance and low turn-off leakage current (i.e., high breakdown voltage). However, the on-resistance (Ron) of power devices... ON There is a trade-off between the voltage and the breakdown voltage (BV), which is determined by the material properties of the device and evaluated using the Baliga figure of merit (BFOM). Wide bandgap semiconductor materials, such as gallium nitride (GaN) and silicon carbide (SiC), have higher BFOM values ​​than silicon due to their wider bandgap, making them more advantageous for achieving high-efficiency power electronic systems.

[0003] Commercial gallium nitride power devices, represented by P-GaN high electron mobility transistors (HEMTs), have been widely used in various consumer electronics products.

[0004] Compared to silicon-based power devices, P-GaN gate HEMT devices feature a high-concentration, high-mobility two-dimensional electron gas (2DEG channel), and their channel material has a higher critical breakdown electric field, enabling them to reduce Ro. ON At the same time, it significantly improves the breakdown voltage, providing considerable energy-saving potential for power systems. However, despite gallium nitride's unique material advantages, optimization and improvement of gallium nitride power devices remain limited.

[0005] For example, there is a trade-off between the threshold voltage and the conductivity of the 2DEG channel in P-GaN gate HEMT devices. Due to the polarization effect of the AlGaN / GaN heterojunction, the 2DEG concentration increases with the thickness of the AlGaN barrier. However, when the AlGaN barrier is thick, the 2DEG under the P-GaN gate cannot be depleted, the threshold voltage of the device becomes negative, and it lacks fail-safe capability. Therefore, for enhancement-mode P-GaN gate HEMT devices, there are certain limitations on the 2DEG concentration and on-resistance.

[0006] In silicon-based power devices, channel conductivity can be modulated through minority carrier injection, significantly reducing on-resistance. In P-GaN gate HEMTs, holes exist in the P-GaN layer, which can be injected into the 2DEG channel to achieve conductivity modulation, thereby reducing on-resistance. However, compared to silicon and silicon carbide, which have indirect bandgap semiconductors, gallium nitride (GaN) is a direct bandgap semiconductor with an extremely short minority carrier lifetime (approximately 10 ns), resulting in a less significant effect on channel conductivity modulation. Specifically, in a P-GaN gate HEMT structure, under forward gate bias, holes are injected into the 2DEG region and the buffer layer; in the 2DEG region, the injected holes recombine rapidly with electrons. However, in the buffer layer, the injected holes do not effectively modulate the on-state channel conductivity but increase off-state leakage.

[0007] Therefore, for P-GaN gate HEMT devices, there is an urgent need to develop a conductivity modulation technique that can simultaneously and effectively reduce the on-state resistance of the device while maintaining a low off-state current. Summary of the Invention

[0008] The present invention provides devices and methods that aim to overcome the shortcomings of the prior art and address unmet needs.

[0009] This invention discloses a semiconductor device with a synchronous photogate for enhanced conductivity modulation. The semiconductor device is synchronously controlled by electrical and optical signals through field effects and photogate effects. According to one embodiment, a gallium nitride (GaN) high electron mobility transistor (HEMT) and a light-emitting device as a photon source are provided. The gallium nitride HEMT includes a substrate layer, a buffer layer, a channel layer, a barrier layer, a p-type doped III-V layer, and / or an N-type doped III-V layer. The gate can be transparent or semi-transparent, thereby allowing the p-type gallium nitride layer to absorb optical signals. The light-emitting device can generate photons carrying energy exceeding the bandgap energy of the p-type gallium nitride layer, and the light-emitting device is co-packaged or monolithically integrated with the gallium nitride HEMT, located above the gallium nitride HEMT. The semiconductor device can rapidly generate and remove holes in the p-GaN gate to adjust the electron concentration in the underlying channel, thereby adjusting the channel conductivity and providing low on-resistance and high switching current ratio.

[0010] According to a first aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a high electron mobility transistor (HEMT) and a light-emitting device. The HEMT includes a nucleation layer, a buffer layer, a channel layer, a source and a drain, a p-type doped III-V layer, and a gate. The nucleation layer is disposed on a substrate. The buffer layer is disposed on the nucleation layer; the channel layer is disposed on the buffer layer; a barrier layer is disposed on the channel layer, and a two-dimensional electron gas (2DEG) region is generated at the interface between the channel layer and the barrier layer; the source and drain are disposed above the barrier layer; the p-type doped III-V layer is disposed on the barrier layer; the gate is located between the source and drain and is disposed on the p-type doped III-V layer, and an electrical drive signal is applied to the gate electrode. The light-emitting device is disposed above the p-GaN gate HEMT and is used to provide an optical signal propagating to the gate and the p-type doped III-V layer of the p-GaN gate HEMT. When the light-emitting device receives a light-emitting device drive signal synchronized with the gate drive signal, it synchronously emits an optical signal, thereby realizing a synchronous optoelectronic-gated switch (SOGS).

[0011] The above configuration realizes the basic structure of a synchronous photogate switch. Besides controlling the channel with an electrical control signal, the synchronous photogate switch also generates photogenerated carriers through the photogate effect to enhance channel conductivity. In the on state, in addition to the electrical signal from the gate driver, photons with energy higher than the bandgap are used as the optical driving signal to generate electron-hole pairs in the gate stack of the gallium nitride HEMT. Driven by the electric field, electrons flow to the gate, while holes accumulate in the P-type III-V layer, thereby inducing more electrons in the channel and improving its conductivity. In the off state, the device is turned off by applying an electrical signal, and the optical signal is simultaneously turned off. In this way, the accumulated holes can be quickly discharged from the gate stack, maintaining a low off-state current. Attached Figure Description

[0012] The embodiments of the present invention will now be described in more detail with reference to the accompanying drawings, wherein:

[0013] Figure 1A This is a vertical cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0014] Figure 1B This is a top view of a semiconductor device according to an embodiment of the present invention;

[0015] Figure 2A A schematic diagram illustrating a synchronous photoelectric gate-controlled switch device having a P-GaN gate HEMT and a light-emitting device according to an embodiment of the present invention;

[0016] Figure 2B and Figure 2CThe following are respectively shown according to embodiments of the present invention: during the on state and the off state, the following are demonstrated: Figure 2A The energy band diagram of the tangent in the gate region;

[0017] Figure 3 This is a vertical cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0018] Figure 4 This is a top view of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 5 This is a top view of a semiconductor device according to an embodiment of the present invention; and

[0020] Figure 6 This is a top view of a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0021] In the following description, semiconductor devices characterized by synchronous photogratings and related devices are used as preferred examples. Those skilled in the art will understand that modifications, including additions and / or substitutions, can be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, this disclosure is intended to enable those skilled in the art to practice the teachings herein without extensive experimentation.

[0022] Figure 1A This is a vertical cross-sectional view of the semiconductor device 100A according to an embodiment of the present invention; Figure 1B This is a top view of a semiconductor device 100A according to an embodiment of the present invention. The semiconductor device 100A includes a high electron mobility transistor (HEMT) 110 and a light-emitting device 180.

[0023] HEMT 110 includes a substrate 112, a nucleation layer 114, a buffer layer 116, a channel layer 118, a barrier layer 120, a source 122 and a drain 124, a P-type doped III-V layer 126, a gate 128 and a passivation layer 130.

[0024] Substrate 112 is a semiconductor or insulating substrate. For example, substrate 112 may be made of materials such as silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), gallium arsenide (GaAs), p-type doped silicon, n-type doped silicon, sapphire, diamond, or semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) or other suitable substrate materials. In some embodiments, substrate 112 may include group III, group IV, group V elements, or combinations thereof (e.g., III-V compounds), such as aluminum nitride and gallium nitride. In other embodiments, substrate 112 may include one or more features, such as doped regions, buried layers, epitaxial layers, or combinations thereof.

[0025] A nucleation layer 114 is disposed on a substrate 112, and a buffer layer 116 is disposed on the nucleation layer 114. The nucleation layer 114 is formed between the substrate 112 and the buffer layer 116. The nucleation layer 114 can provide a transition space to allow the mismatch / difference between the substrate 112 and the buffer layer 116, which comprises a III-nitride material, to be gradually accommodated. Exemplary materials for the nucleation layer 114 may include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or any alloy thereof.

[0026] A buffer layer 116 is formed to reduce lattice and thermal mismatch between the substrate 112 and the channel layer 118, thereby eliminating defects caused by mismatch / difference. The buffer layer 116 may include III-V compounds, including aluminum, gallium, indium, nitride, or combinations thereof. In some embodiments, the material of the buffer layer 116 may also include aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), or combinations thereof.

[0027] A channel layer 118 is located on a buffer layer 116, and a barrier layer 120 is located on a channel layer 118. Both the channel layer 118 and the barrier layer 120 are formed using a nitride-based material. The nitride-based material of the channel layer 118 may include nitrides or III-V compounds, such as aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or alloys thereof. For example, the nitride-based material of the channel layer 118 may also include In... x Al y Ga (1-x-y) N, where x+y≤1, Al y Ga (1-y) N, where y ≤ 1. The nitride-based material of the barrier layer 120 may include binary group III nitride compounds, ternary group III nitrides, quaternary group III nitrides, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), indium aluminum gallium nitride (InAlGaN), or combinations thereof, such as In x Al y Ga (1-x-y) N, where x+y≤1, Al y Ga (1-y) N, where y ≤ 1. The barrier layer 120 can be formed as a single layer or a stacked layer, and includes aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or alloys thereof, or has doped or undoped regions. For example, the barrier layer 120 can be an aluminum nitride body, a gallium nitride body, an indium nitride body, or an alloy body thereof, and may have doped or undoped regions. Similarly, the nitride-based material of the barrier layer 120 may also include In. x Al y Ga(1–x–y) N (where x+y≤1) or Al y Ga (1–y) N (where y≤1).

[0028] As a HEMT device, the materials of the channel layer 118 and the barrier layer 120 can be selected such that the band gap of the barrier layer 120 is larger than that of the channel layer 118. The difference in band gap and electron affinity between the barrier layer and the channel layer will lead to the formation of a heterojunction with a unique band alignment structure between the layers, forming a triangular potential well at its interface. Due to the unique polarization effect of III-V nitrides, electrons will accumulate in the potential well, forming a two-dimensional electron gas (2DEG) region adjacent to the interface / heterojunction between the channel layer 118 and the barrier layer 120.

[0029] Source 122 and drain 124 are formed over channel layer 118 and barrier layer 120. In some embodiments, source 122 and drain 124 may comprise metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds (e.g., silicides and nitrides), other conductive materials, or combinations thereof. For example, source 122 and drain 124 may comprise titanium (Ti), tantalum (Ta), titanium nitride (TiN), aluminum (Al), tungsten (W), gold (Au), aluminum-silicon alloy (AlSi), aluminum-copper alloy (AlCu), nickel (Ni), platinum (Pt), or combinations thereof. In some embodiments, each of source 122 and drain 124 may be a single layer or a multilayer with the same or different compositions. Source 122 and drain 124 may form an ohmic contact with barrier layer 120.

[0030] A p-type doped III-V layer 126 is disposed on top of the barrier layer 120, and a gate 128 is disposed on top of the p-type doped III-V layer 126. The p-type doped III-V layer 126 and the gate 128 are located between the source 122 and the drain 124.

[0031] In some embodiments, the P-GaN gate HEMT 110 operates in enhancement mode and remains normally off when the gate 128 is at approximately zero bias. A p-type doped III-V layer 126 forms at least one heterojunction with the barrier layer 120 to achieve the desired threshold voltage while depleting the 2DEG region beneath the gate 128. The depletion of the P-GaN gate alters the electron concentration in a specific region compared to the rest of the 2DEG region, effectively preventing current flow in that region. In other embodiments, the P-GaN gate HEMT 110 is a depletion-mode device that remains normally on when the gate bias is approximately zero. In this configuration, the 2DEG channel in the gate region maintains a high electron concentration, enabling continuous current flow even when the gate bias is approximately zero.

[0032] In one embodiment, the P-type doped III-V layer 126 is a P-type doped III-V semiconductor layer, such as a P-type gallium nitride layer formed from a single layer or stacked layers. In some embodiments, the P-type doping material is achieved by using P-type impurities (e.g., beryllium (Be), magnesium (Mg), zinc (Zn), cadmium (Cd), and magnesium (Mg)) with a wide range of doping concentrations. In enhancement mode, the P-type doped III-V layer 126 can cause the band structure to rise overall, depleting the 2DEG channel in the gate region, thereby achieving a turn-off state. In some embodiments, the P-type doped III-V layer 126 can be formed using other P-type materials, such as P-type doped III-V, P-type AlGaN, P-type InN, P-type AlInN, P-type InGaN, P-type AlInGaN, or combinations thereof.

[0033] In some embodiments, the gate 128 is formed using a conductive material such as a thin metal, which may include a thin metal alloy, a thin metal nitride, a metal oxide, or a combination thereof. In some embodiments, the gate 128 may be formed using heavily doped semiconductors, nickel (Ni), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), tungsten (W), chromium (Cr), titanium nitride (TiN), titanium-tungsten alloy (TiW), indium tin oxide (ITO), or a combination thereof. In some embodiments, the gate 128 is optically transparent or may be translucent, thereby allowing light or optical signals to pass through.

[0034] A passivation layer 130 is disposed above the barrier layer 120 and covers the sidewalls of the p-type doped III-V layer 126 and the gate 128. The passivation layer 130 includes at least one dielectric or insulating material, including silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon boron nitride (SiBN), silicon carbide boron nitride (SiCBN), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), gallium oxynitride (GaON), oxides, nitrides, or combinations thereof. In some embodiments, the passivation layer 130 is a multilayer structure, such as a composite dielectric layer of aluminum oxide / silicon nitride (Al2O3 / SiN), aluminum oxide / silicon dioxide (Al2O3 / SiO2), aluminum nitride / silicon nitride (AlN / SiNx), aluminum nitride / silicon dioxide (AlN / SiO2), or combinations thereof.

[0035] A light-emitting device 180 is disposed above a P-GaN gate HEMT 110 and configured to provide an optical signal 182 transmitted to the gate 128 of the P-GaN gate HEMT 110 and the P-type doped III-V layer 126. For example, the light-emitting device 180 may be vertically aligned with the gate 128 of the P-GaN gate HEMT 110 to transmit the optical signal 182. In some embodiments, the light-emitting device 180 is a photodiode configured to provide an optical signal 182 with photons at energy levels higher than the bandgap energy of the P-type doped III-V layer 126. For example, the photodiode used can provide an optical signal 182 with photons having energy levels in the ultraviolet (UV) region (e.g., greater than about 3.7 eV). This configuration is intended to facilitate increased 2DEG density when the device is turned on. In some embodiments, the light-emitting device 180 may comprise a plurality of sub-light-emitting devices connected in series or parallel.

[0036] The light-emitting device 180 can be combined with the P-GaN gate HEMT 110 to implement / establish a synchronous optoelectronic-gated switch (SOGS) mechanism for the P-GaN gate HEMT 110. For example, when the light-emitting device 180 receives a light-emitting device drive signal, the light-emitting device 180 is driven and emits a light signal 182, while the gate 128 can receive a gate drive signal, and the light-emitting device drive signal is synchronized with the gate drive signal. In some embodiments, the light-emitting device 180 can be co-packaged with the P-GaN gate HEMT 110 or monolithically integrated.

[0037] The P-GaN gate HEMT 110 is controlled by a gate drive signal applied to the gate 128 and an optical signal 182 generated from the light-emitting device 180. When the P-GaN gate HEMT 110 is driven by the gate drive signal applied to the gate 128, the conductivity of the 2DEG region is modulated through the capacitive coupling between the gate 128 and the channel layer 118, thereby gradually opening the channel and allowing current to flow from the source 122 to the drain 124. Simultaneously, the light-emitting device 180 generates photons above the bandgap as the optical signal 182. Photons with above-bandgap energy pass through the gate 128 and are then absorbed by the p-type doped III-V layer 126, thereby generating electron-hole pairs. The generated electrons flow to the gate 128, while the holes accumulate in the p-type doped III-V layer 126, thereby inducing more electrons in the 2DEG region and significantly increasing the channel conductivity.

[0038] Thus, by synchronously controlling the gate drive signal and the light-emitting device drive signal, more holes can be generated in the on state, and then the generated holes can be effectively removed in the off state, giving the P-GaN gate HEMT 110 the characteristics of low on-resistance and low off-current.

[0039] Figure 2A A schematic diagram of a synchronous photogate-controlled switch device having a P-GaN gate HEMT device and a light-emitting device according to an embodiment of the present invention is shown. The P-GaN gate HEMT 110 and the light-emitting device 180 have the structural configuration described above. The device 100A also includes a gate driver 190 for transmitting a gate drive signal and a light-emitting device drive signal to synchronously control the P-GaN gate HEMT 110 and the light-emitting device 180.

[0040] The light-emitting device 180 is a photodiode, with its anode connected to the gate driver 190 and its cathode connected to the source of the P-GaN gate HEMT 110. The gate of the P-GaN gate HEMT 110 is coupled to the gate driver 190. The anode of the light-emitting device 180 and the gate of the P-GaN gate HEMT 110 are also electrically coupled to the same node, and then coupled to the gate driver 190 through this same node. This is because the gate drive signal and the light-emitting device drive signal can be sent and transmitted simultaneously, thereby synchronously controlling the P-GaN gate HEMT 110 and the light-emitting device 180.

[0041] Figure 2B and Figure 2C The following are respectively shown according to embodiments of the present invention: during the on state and the off state, the following are demonstrated: Figure 2A The tangent at the gate stack in the band diagram. Figure 2B and Figure 2C In this context, p-GaN represents the p-type doped III-V layer 126; AlGaN represents the barrier layer 120; and GaN represents the channel layer 118.

[0042] To implement the SOGS mechanism, a gate drive signal is applied between the gate terminal G and the source terminal S of the P-GaN gate HEMT 110 to open the channel in the P-GaN gate HEMT 110, and a light-emitting device drive signal is applied between the anode and cathode of the light-emitting device 180 to generate photons above the bandgap energy level as optical signals.

[0043] like Figure 2B and Figure 2C As shown, electrons then accumulate in the channel of the P-GaN gate HEMT 110 under the influence of gate modulation, and the holes generated by photons further enhance the electron density. The P-GaN gate HEMT 110 can then be turned on to conduct current, and the drain-source voltage is switched to a low voltage (V).DS,ON Then, by switching the gate voltage to V... GS,OFF The light-emitting device 180 is turned off, the accumulated holes are quickly removed, and the 2DEG region / channel is depleted. Therefore, the channel of the P-GaN gate HEMT110 is in a non-conductive state, and the drain-source voltage is switched to a high voltage (V). DS,OFF This switching mechanism controls the power delivery function and performance of the load / sub-circuit.

[0044] Figure 3 This is a vertical cross-sectional view of a semiconductor device 100B according to an embodiment of the present invention. Semiconductor device 100B has a similar configuration to semiconductor device 100A, except that the P-GaN gate HEMT 110 of semiconductor device 100B further includes an n-type doped III-V layer 140 located between the source 122 and the drain 124. The n-type doped III-V layer 140 is disposed between the p-type doped III-V layer 126 and the gate 128, and contacts the p-type doped III-V layer 126 and the gate 128 to form a contact surface with the p-type doped III-V layer 126 and the gate 128.

[0045] In some embodiments, the N-type doped III-V layer 140 is an N-type doped III-V semiconductor layer, such as an N-type GaN layer formed from a single layer or stacked layers. In some embodiments, the N-type doping material is achieved by using N-type impurities (e.g., silicon (Si), germanium (Ge), sulfur (S), or selenium (Se)) having a wide range of doping concentrations. In some embodiments, the N-type doped III-V layer 140 may be formed using other N-type materials (e.g., N-type doped III-V, N-type AlGaN, N-type InN, N-type AlInN, N-type InGaN, N-type AlInGaN, or combinations thereof).

[0046] The N-type doped III-V layer 140 can form a depletion region near the P-type doped III-V layer 126. The electric field in the depletion region facilitates the separation of photogenerated electron-hole pairs, thereby enhancing the accumulation of photogenerated holes in the P-type doped III-V layer 126. This further enhances the 2DEG concentration in the on-state.

[0047] Figure 4 This is a top view of a semiconductor device 100C according to an embodiment of the present invention. Semiconductor device 100C has a similar configuration to semiconductor device 100A, except that the gate 128 included in the HEMT of semiconductor device 100C exposes at least a portion of the p-type doped III-V layer 126. Specifically, the gate 128 covers the underlying p-type doped III-V layer 126 and has a window region OP for exposing at least a portion of the p-type doped III-V layer 126 from the window region OP. Figure 4 In the provided content, the gate 128 has a stripe pattern forming a window region OP. The gate 128 allows more photons or optical signals from the light-emitting device to enter the p-type doped III-V layer 126 through these stripe patterns and the formed window region OP, thereby improving optical transmission efficiency.

[0048] Figure 5 This is a top view of a semiconductor device 100D according to an embodiment of the present invention. The semiconductor device 100D has a similar configuration to the semiconductor device 100A, except that the gate 128 included in the HEMT of the semiconductor device 100D exposes at least a portion of the p-type doped III-V layer 126 through a window region OP. The gate 128 has a rectangular pattern, thus forming the window region OP, thereby exposing the p-type doped III-V layer 126 to improve optical transmission efficiency.

[0049] Figure 6 This is a top view of a semiconductor device 100E according to an embodiment of the present invention. Semiconductor device 100D has a similar configuration to semiconductor device 100A, except that the gate 128 included in the HEMT of semiconductor device 100E exposes at least a portion of the p-type doped III-V layer 126 through a window region OP. The gate 128 has a circular pattern, thus forming the window region OP, thereby exposing the p-type doped III-V layer 126 to improve optical transmission efficiency.

[0050] As described above, in this invention, the synchronous photogate-controlled switch (SOGS) can be controlled by both electrical and optical signals to enhance conductivity. During the "on" state, in addition to the signal from the gate driver, photons with energy above the bandgap are used as the optical driving signal to generate electron-hole pairs in the gate structure of the P-GaN gate HEMT. With the aid of an electric field, electrons are swept toward the gate, while holes accumulate in the gate stack, simultaneously inducing more electrons in the channel, thereby enhancing channel conductivity. In the "off" state, the device is turned off by an electrical signal, and the optical signal is simultaneously removed. The accumulated holes can then be quickly discharged from the gate structure, maintaining a low off-state current.

[0051] Spatial references and similar terms such as “above,” “over,” and “below” are defined relative to the components or planes shown in the figures. These terms are for illustrative purposes only and do not limit the actual arrangement, provided that the described embodiments retain their intended advantages.

[0052] It should be noted that although various structures are depicted as approximate rectangles in the drawings, their actual shapes may differ in practice due to manufacturing conditions. These shapes may include curves, rounded edges, or variations in thickness. The use of straight lines and right angles in the drawings is merely for the convenience of depicting layers and features.

[0053] In this disclosure, unless the context clearly specifies otherwise, nouns not specifically named shall be interpreted to include both singular and plural forms. Furthermore, in describing embodiments, a component "on" or "above" another component can refer to a situation where two components are in direct contact or indirect contact is between them, with one or more intermediate components located between them.

[0054] The foregoing description of the invention is for illustrative purposes only. It is not intended to be exhaustive or to limit the invention to the specific forms disclosed. Many modifications and variations will be apparent to those skilled in the art.

[0055] The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for particular purposes.

Claims

1. A semiconductor device, characterized in that, include: High electron mobility transistors (HEMTs) include: Nucleation layer, disposed on the substrate; A buffer layer is disposed on the nucleation layer; A channel layer is disposed on the buffer layer; A barrier layer is disposed on the channel layer, and a two-dimensional electron gas (2DEG) region is generated at the interface between the channel layer and the barrier layer. The source and drain are disposed above the barrier layer; A p-type doped III-V layer is disposed on the barrier layer; and A gate, located between the source and the drain, and disposed on the p-type doped III-V layer, wherein a gate drive signal is applied to the gate; and A light-emitting device is disposed above the HEMT and is used to provide an optical signal propagating to the gate and the P-type doped III-V layer of the HEMT. The light-emitting device is driven to emit the optical signal when it receives a light-emitting device drive signal synchronized with the gate drive signal, thereby establishing a synchronous photogate control switch.

2. The semiconductor device according to claim 1 further includes a gate driver for transmitting the gate driver signal and the light emission driver signal to synchronously control the HEMT and the light-emitting device.

3. The semiconductor device according to claim 2, wherein the light-emitting device is a photodiode, the anode of which is connected to the gate driver, the cathode of which is connected to the source of the HEMT, and the gate of the HEMT is connected to the gate driver.

4. The semiconductor device according to claim 3, wherein the anode and the gate of the light-emitting device are connected to the same node, and then connected to the gate drive through the same node.

5. The semiconductor device of claim 1, wherein the light-emitting device is a photodiode configured to provide the optical signal having photons, and the energy level of the photons is higher than the bandgap energy of the p-type doped III-V layer.

6. The semiconductor device according to claim 5, wherein the optical signal provided by the photodiode has photons with energy levels in the ultraviolet (UV) spectral region.

7. The semiconductor device according to claim 1, wherein the gate is optically transparent or semi-transparent.

8. The semiconductor device according to claim 1, wherein the light-emitting device and the HEMT are co-packaged or monolithically integrated.

9. The semiconductor device of claim 8, wherein the light-emitting device is vertically aligned with the gate of the HEMT.

10. The semiconductor device of claim 1, wherein the gate cover of the HEMT is beneath the P-type doped III-V layer, and has a window region to expose at least a portion of the P-type doped III-V layer from the window region.

11. The semiconductor device of claim 10, wherein the window region has a striped pattern, a rectangular pattern, a circular pattern, or a combination thereof.

12. The semiconductor device according to claim 1, wherein the HEMT further comprises an N-type doped III-V layer disposed between the P-type doped III-V layer and the gate, and forming a contact surface with the P-type doped III-V layer and the gate.

13. The semiconductor device according to claim 1, wherein the light-emitting device comprises a plurality of sub-light-emitting devices connected in series or in parallel.

14. The semiconductor device of claim 1, wherein the HEMT further comprises a passivation layer covering the sidewalls of the p-type doped III-V layer and the gate.

15. The semiconductor device according to claim 1, wherein the barrier layer is a single-layer material or a stack of multiple materials.

16. The semiconductor device of claim 1, wherein the barrier layer comprises an alloy of aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or combinations thereof, and contains doped or undoped regions.

17. The semiconductor device according to claim 1, wherein the P-type doped III-V layer is a P-type gallium nitride layer formed by stacking one or more layers.

18. The device of claim 1, wherein the gate is made of a thin metal or semiconductor, including thin metal alloys, thin metal nitrides, metal oxides, heavily doped semiconductors, nickel (Ni), titanium (Ti), aluminum (Al), silver (Ag), gold (Au), tungsten (W), chromium (Cr), titanium nitride (TiN), titanium-tungsten alloy (TiW), indium tin oxide (ITO), or combinations thereof.

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