Semiconductor device

Abstract

A semiconductor device includes: a substrate including an active region extending in a first direction; gate structures extending in a second direction on the substrate and overlapping the active region, and spaced apart from each other in the first direction; a blocking gate structure overlapping the active region between the gate structures and extending in the second direction; a source / drain region disposed in a region where the active region is recessed on both sides of the barrier gate structure; the back contact structure is arranged below the at least one source / drain region; and back blocking structures disposed under the gate structure and the blocking gate structure, respectively. The blocking gate structure includes a first element different from the gate structure.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0109747, filed with the Korean Intellectual Property Office on August 16, 2024, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to semiconductor devices. Background Technology

[0004] As the demand for high performance, high speed, and / or versatility in semiconductor devices increases, the integration density of semiconductor devices is also increasing. In line with this trend towards higher integration in semiconductor devices, semiconductor devices with a Backside Power Delivery Network (BSPDN) structure in which power rails are placed on the back side of the wafer are being developed. Additionally, efforts are underway to develop semiconductor devices including FinFETs with three-dimensional channel structures to reduce the operational characteristic limitations caused by the shrinking size of planar metal-oxide-semiconductor FETs (MOSFETs). Summary of the Invention

[0005] An example implementation provides a semiconductor device that has reduced process costs and complexity, as well as improved reliability.

[0006] According to an example embodiment, a semiconductor device includes: a substrate including an active region extending in a first direction; gate structures extending on the substrate in a second direction and overlapping the active region, and spaced apart from each other in the first direction; barrier gate structures overlapping the active region between the gate structures and extending in the second direction; a plurality of channel layers surrounded by barrier gate structures and gate structures respectively on the active region, and spaced apart from each other in a third direction perpendicular to the upper surface of the substrate; source / drain regions in recessed portions of the active region, wherein the source / drain regions are on both sides of the barrier gate structures and connected to the plurality of channel layers; a first back contact structure below the first source / drain region, wherein the first back contact structure extends through the substrate and extends from the lower surface of the first source / drain region into the first source / drain region, wherein the first back contact structure is electrically connected to the first source / drain region; and a plurality of back barrier structures below the gate structures and barrier gate structures respectively, wherein the plurality of back barrier structures extend through the substrate and the active region and separate the active region. The barrier gate structures include a first element different from the gate structures.

[0007] According to an example embodiment, a semiconductor device includes: a substrate; a gate structure extending on the substrate in a first direction; a barrier gate structure adjacent to a first side of the gate structure and extending in the first direction; a source / drain region between the gate structure and the barrier gate structure, and in contact with both the gate structure and the barrier gate structure; a back contact structure extending into the substrate and partially extending from a lower surface of the source / drain region into the source / drain region, wherein the back contact structure is electrically connected to the source / drain region; and a back barrier structure including a first back barrier structure and a second back barrier structure, the first back barrier structure being below the barrier gate structure, extending through the substrate, and in contact with the barrier gate structure, and the second back barrier structure being below the gate structure, extending through the substrate, and in contact with the lower surface of the gate structure. A first transistor including the barrier gate structure is configured to exhibit a first threshold voltage, and a second transistor including the gate structure is configured to exhibit a second threshold voltage. The absolute value of the first threshold voltage is greater than the absolute value of the second threshold voltage.

[0008] According to an example embodiment, a semiconductor device includes: a substrate having a first region and a second region; a plurality of gate structures on the substrate; a plurality of source / drain regions, wherein each source / drain region is between adjacent gate structures in the plurality of gate structures; and a plurality of back barrier structures, each located below the plurality of gate structures, wherein the plurality of back barrier structures extend through the substrate and contact the plurality of gate structures. The plurality of gate structures include: first gate structures spaced apart from each other in a first direction and extending in a second direction intersecting the first direction in the first region; second gate structures spaced apart from each other in the first direction and extending in the second direction in the second region; a first barrier gate structure between the first gate structures in the first region; and a second barrier gate structure between the second gate structures in the second region. The first gate structure and the second barrier gate structure include a first element, and the second gate structure and the first barrier gate structure include a second element different from the first element. Attached Figure Description

[0009] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a plan view showing a semiconductor device according to an example embodiment; Figures 2A to 2B This is a cross-sectional view of a semiconductor device according to an example embodiment; Figures 3A to 3B This is a cross-sectional view of a semiconductor device according to an example embodiment; Figure 4 This is a cross-sectional view of a semiconductor device according to an example embodiment; Figure 5A This is a plan view showing a semiconductor device according to an example embodiment; Figure 5B This is a cross-sectional view of a semiconductor device according to an example embodiment; Figure 6A This is a plan view showing a semiconductor device according to an example embodiment; Figure 6B and Figure 6C This is a cross-sectional view of a semiconductor device according to an example embodiment; Figure 7A , Figure 8A , Figure 9 , Figure 10 , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15 A cross-sectional view of a method for manufacturing a semiconductor device according to an example embodiment is shown in the process sequence; and Figure 7B , Figure 8B , Figure 11B , Figure 12B , Figure 13B and Figure 14B This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an example embodiment, arranged in the process sequence. Detailed Implementation

[0010] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. Unless otherwise stated, terms such as “upper,” “upper part,” “upper surface,” “lower,” “lower part,” “lower surface,” and “side surface” can be understood with reference to the drawings.

[0011] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment. For ease of explanation, Figure 1 Only some components of the semiconductor device are shown in the image.

[0012] Figure 2A and Figure 2B This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 2A It shows Figure 1 The cross-section of the semiconductor device cut along the cutting line I-I', and Figure 2B It shows Figure 1 The cross-section of the semiconductor device cut along cutting lines II-II' and III-III'.

[0013] refer to Figures 1 to 2BThe semiconductor device 100 may include: a substrate 101 including an active region 105; a channel structure 140 including first to fourth channel layers 141, 142, 143, and 144 vertically disposed on the active region 105 and spaced apart from each other; gate structures 160 extending and overlapping the active region 105, each gate structure including a gate electrode 165; barrier gate structures 170 extending between the gate structures 160 and overlapping the active region 105, and including a barrier gate electrode 175; source / drain regions 150 disposed between the barrier gate structures 170 and the gate structures 160 and contacting the channel structure 140; back barrier structures 180 disposed below the gate structures 160 and the barrier gate structures 170, respectively; and a back contact structure 190 connected to the source / drain regions 150. The semiconductor device 100 may also include an interlayer insulating layer 115, a back insulating layer 194, and a back power structure. (Reference) Figure 3B The semiconductor device 100 may also include a component isolation layer 110.

[0014] In the semiconductor device 100, the active region 105 may have a fin structure, and the gate electrode 165 may be disposed between the active region 105 and the channel structure 140, between the first to fourth channel layers 141, 142, 143 and 144 of the channel structure 140, and on the channel structure 140. Therefore, the semiconductor device 100 may include a multi-bridge channel FET (MBCFET). TM A transistor with a fully all-around gate field-effect transistor structure.

[0015] Substrate 101 may have an upper surface extending in both the X and Y directions. Substrate 101 may include a semiconductor material (e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor). For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may be configured as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0016] The substrate 101 may include an active region 105 disposed therein. The active region 105 is defined within the substrate 101 by a device isolation layer 110 and may be configured to extend in a first direction (e.g., the X direction). However, depending on the description method, the active region 105 may also be described as being configured separately from the substrate 101. The active region 105 may partially protrude above the device isolation layer 110, such that the upper surface of the active region 105 may be located at a level higher than the upper surface of the device isolation layer 110. The active region 105 may be formed as part of the substrate 101, or may include an epitaxial layer grown from the substrate 101. However, on both sides of the barrier gate structure 170, the active region 105 may be partially recessed to form recessed regions, and source / drain regions 150 may be disposed in the recessed regions.

[0017] In the example implementation, the active region 105 may or may not include a well region containing impurities. For example, in the case of an n-type transistor (nFET), the well region may include p-type impurities (e.g., boron (B), gallium (Ga), or indium (In)). In the case of a p-type transistor (pFET), the well region may include n-type impurities (e.g., phosphorus (P), arsenic (As), or antimony (Sb)), and the well region may be located, for example, at a predetermined depth from the upper surface of the active region 105.

[0018] Let's refer to each other. Figure 3B The semiconductor device 100 may include a device isolation layer 110 that defines an active region 105 on a substrate 101. The device isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. The device isolation layer 110 may expose at least the upper surface of the active region 105, and may also expose a portion of the upper surface. The device isolation layer 110 may have a curved upper surface, such that it has a higher level as it approaches the active region 105. The device isolation layer 110 may be formed of an insulating material. The device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0019] Gate structure 160 may be configured to extend in one direction (e.g., in the Y direction) over active region 105. Channel regions of the transistor may be formed in channel structure 140 overlapping with gate electrode 165 of gate structure 160. Gate structures 160 may be configured to be spaced apart from each other in the X direction. Each gate structure 160 may include gate dielectric layer 162, gate spacer layer 164, gate electrode 165, and gate capping layer 167.

[0020] The gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165, and between the channel structure 140 and the gate electrode 165, and may be configured to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may be configured to surround all surfaces except the uppermost surface of the gate electrode 165. The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer layer 164, but is not limited thereto. The gate dielectric layer 162 may include oxides, nitrides, or high-k materials. High-k materials may refer to dielectric materials with a dielectric constant higher than that of silicon oxide (SiO2). High-k materials may be, for example, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O y ) and praseodymium oxide (HfAl) x O y Any of the following. According to the example embodiment, the gate dielectric layer 162 may be formed of a multilayer structure.

[0021] The gate electrode 165 may include a conductive material, such as a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)), and / or a metallic material (e.g., aluminum (Al), tungsten (W), or molybdenum (Mo)), or a semiconductor material (e.g., doped polycrystalline silicon). According to an example embodiment, the gate electrode 165 may be formed of a multilayer structure. The gate electrode 165 may be connected to a gate contact plug disposed thereon. The gate electrode 165 may include p-type or n-type metals depending on the conductivity type of the transistor. For example, in an n-type transistor, the gate electrode 165 may include a metal with a relatively small work function to facilitate transistor operation by reducing the transistor threshold voltage, which has a positive value, and these metals may be referred to as n-type metals. Conversely, in a p-type transistor, the gate electrode 165 may include a metal with a relatively large work function to facilitate transistor operation by reducing the absolute value of the transistor threshold voltage, which has a negative value, and these metals may be referred to as p-type metals.

[0022] A gate spacer layer 164 may be disposed on both sides of the gate electrode 165 on the channel structure 140. The gate spacer layer 164 may insulate the source / drain region 150 from the gate electrode 165. According to some exemplary embodiments, the shape of the upper portion of the gate spacer layer 164 may be varied, and the gate spacer layer 164 may be formed of a multilayer structure. The gate spacer layer 164 may include at least one of oxide, nitride, and oxynitride, and may be formed of, for example, a low-k film.

[0023] A gate capping layer 167 may be disposed on the gate electrode 165 and the gate spacer layer 164. In some embodiments, the lower surface of the gate capping layer 167 may have a downwardly convex shape. The gate capping layer 167 may include an insulating material and may include at least one of, for example, oxides, nitrides, and oxynitrides.

[0024] A barrier gate structure 170 may be disposed between gate structures 160. The barrier gate structure 170 may be configured to extend in one direction (e.g., the Y direction) over the active region 105. The barrier gate structure 170 may include a barrier gate dielectric layer 172, a barrier gate spacer layer 174, a barrier gate electrode 175, and a barrier gate capping layer 177, each having a configuration corresponding to the gate dielectric layer 162, the gate spacer layer 164, the gate electrode 165, and the gate capping layer 167 of the gate structure 160, respectively. The barrier gate structure 170 may have a structure substantially the same as or similar to that of the gate structure 160, but may have a configuration including materials different from those of the gate structure 160. Unless otherwise described, the barrier gate dielectric layer 172, barrier gate spacer layer 174, barrier gate electrode 175 and barrier gate capping layer 177 constituting the barrier gate structure 170 may have substantially the same or similar characteristics as the gate dielectric layer 162, gate spacer layer 164, gate electrode 165 and gate capping layer 167, respectively.

[0025] The absolute value of the minimum voltage that must be applied to the blocking gate electrode 175 to allow current to flow in the channel structure 140 surrounded by the blocking gate structure 170 may be greater than the absolute value of the minimum voltage that must be applied to the gate electrode 165 to allow current to flow in the channel structure 140 surrounded by the gate structure 160. For example, the absolute value of the threshold voltage of the transistor including the blocking gate structure 170 may be greater than the absolute value of the threshold voltage of the transistor including the gate structure 160. Hereinafter, for ease of explanation, the threshold voltage of the transistor including the blocking gate structure 170 will be described as a first threshold voltage Vt1, and the threshold voltage of the transistor including the gate structure 160 will be described as a second threshold voltage Vt2.

[0026] In some implementations... Figures 1 to 2BThe semiconductor device 100 may include an n-type transistor (nFET). In this case, the first threshold voltage Vt1 and the second threshold voltage Vt2 may have positive values, and the first threshold voltage Vt1 may be greater than the second threshold voltage Vt2. Therefore, even if an operating voltage greater than the second threshold voltage Vt2 is applied to the gate electrode 165 and the blocking gate electrode 175 to allow current to flow in the channel structure 140 surrounded by the gate structure 160, the operating voltage may be less than the first threshold voltage Vt1, and the current may not flow in the channel structure 140 surrounded by the blocking gate structure 170. Utilizing this principle, within the operating voltage range of the gate electrode 165, the source / drain regions 150 on both sides of the blocking gate structure 170 can be electrically isolated from each other.

[0027] In some nFET implementations, the blocking gate electrode 175 of the blocking gate structure 170 may include a material with a work function greater than that of the gate electrode 165 of the gate structure 160. For example, the work function of the blocking gate electrode 175 may be greater than that of the gate electrode 165. In some implementations, the gate electrode 165 may include an n-type metal, and the blocking gate electrode 175 may include a p-type metal. Therefore, the first threshold voltage Vt1 may be relatively offset in the positive direction and may have an amplitude greater than that of the second threshold voltage Vt2. In some implementations, the blocking gate electrode 175 and the gate electrode 165 may include different numbers of multilayer structures.

[0028] In some nFET implementations, the barrier gate dielectric layer 172 may include a different material than the gate dielectric layer 162. The barrier gate dielectric layer 172 may include a dipole-sensing material that shifts the first threshold voltage Vt1 in the positive direction. Therefore, the first threshold voltage Vt1 can be shifted in the positive direction and can have an amplitude greater than that of the second threshold voltage Vt2.

[0029] In some nFET implementations, the barrier gate structure 170 may include a first element different from the gate structure 160, and in these implementations, the first element may include a material that shifts the threshold voltage of the transistor in a positive direction. For example, the first element may include at least one of aluminum (Al), tantalum (Ta), tungsten (W), manganese (Mn), chromium (Cr), ruthenium (Ru), platinum (Pt), gallium (Ga), germanium (Ge), and gold (Au). The first element may be included in at least one of the barrier gate electrode 175 and the barrier gate dielectric layer 172. In some nFET implementations, both the barrier gate structure 170 and the gate structure 160 include the first element, but the concentration of the first element included in the barrier gate structure 170 may be greater than the concentration of the first element included in the gate structure 160. In some nFET implementations, the gate structure 160 may include a second element different from the first element, and this second element may include a material that shifts the threshold voltage of the transistor in a negative direction. For example, the second element may include at least one of lanthanum (La), gadolinium (Gd), ruthenium (Lu), yttrium (Y), and scandium (Sc). In some embodiments, the first threshold voltage Vt1 can be 2 to 4 times the second threshold voltage Vt2. In some embodiments, the difference between the first threshold voltage Vt1 and the second threshold voltage Vt2 can be 0.1V to 0.5V, or 0.15V to 0.25V.

[0030] In some implementations... Figures 1 to 2B The semiconductor device 100 may include a p-type transistor (pFET). In these cases, the first threshold voltage Vt1 and the second threshold voltage Vt2 may have negative values, and the first threshold voltage Vt1 may be less than the second threshold voltage Vt2. For example, the absolute value of the first threshold voltage Vt1 may be greater than the absolute value of the second threshold voltage Vt2. Therefore, even if an operating voltage with an absolute value greater than the absolute value of the second threshold voltage Vt2 is applied to the gate electrode 165 and the blocking gate electrode 175 to allow current to flow in the channel structure 140 surrounded by the gate structure 160, the absolute value of the corresponding operating voltage may be less than the absolute value of the first threshold voltage Vt1, and the current may not flow in the channel structure 140 surrounded by the blocking gate structure 170. Based on this principle, within the operating voltage range of the gate electrode 165, the source / drain regions 150 on both sides of the blocking gate structure 170 can be electrically isolated from each other.

[0031] In some pFET implementations, the blocking gate electrode 175 of the blocking gate structure 170 may include a material having a work function lower than that of the gate electrode 165 of the gate structure 160. For example, the work function of the blocking gate electrode 175 may be lower than that of the gate electrode 165. In some implementations, the gate electrode 165 may include a p-type metal, and the blocking gate electrode 175 may include an n-type metal. Therefore, the first threshold voltage Vt1 may be relatively offset in the negative direction, such that the absolute value of the first threshold voltage Vt1 may have a larger magnitude than the absolute value of the second threshold voltage Vt2. In some implementations, the blocking gate electrode 175 and the gate electrode 165 may include different numbers of multilayer structures. In some pFET implementations, the material used for the gate electrode 165 may be referred to as a p-type metal, and the material used for the blocking gate electrode 175 may be referred to as an n-type metal. In some implementations, the material of the blocking gate electrode 175 for the pFET may be the same as the material of the gate electrode 165 for the nFET.

[0032] In some pFET implementations, the barrier gate dielectric layer 172 may include a different material than the gate dielectric layer 162. The barrier gate dielectric layer 172 may include a dipole-sensing material that shifts the first threshold voltage Vt1 in the negative direction. Therefore, the first threshold voltage Vt1 is shifted in the negative direction such that the absolute value of the first threshold voltage Vt1 can have a larger magnitude than the absolute value of the second threshold voltage Vt2.

[0033] In some pFET implementations, to increase the absolute value of the first threshold voltage Vt1, the barrier gate structure 170 may include a first element different from the gate structure 160, and the first element may include a material that shifts the threshold voltage of the transistor in a negative direction. In example implementations, the first element may include at least one of lanthanum (La), gadolinium (Gd), ruthenium (Lu), yttrium (Y), and scandium (Sc). The first element may be included in at least one of the barrier gate electrode 175 and the barrier gate dielectric layer 172. In some pFET implementations, both the barrier gate structure 170 and the gate structure 160 include the first element, but the concentration of the first element included in the barrier gate structure 170 may be greater than the concentration of the first element included in the gate structure 160. In some implementations, the gate structure 160 may include a second element different from the first element, and in some pFET implementations, the second element may include a material that shifts the threshold voltage of the transistor in a positive direction. For example, the second element may include at least one of aluminum (Al), tantalum (Ta), tungsten (W), manganese (Mn), chromium (Cr), ruthenium (Ru), platinum (Pt), gallium (Ga), germanium (Ge), and gold (Au). In some embodiments, the first threshold voltage Vt1 may be two to four times the second threshold voltage Vt2. In some embodiments, the difference between the first threshold voltage Vt1 and the second threshold voltage Vt2 may be 0.1V to 0.5V, or 0.15V to 0.25V.

[0034] Semiconductor device 100 can electrically isolate adjacent transistors via a barrier gate structure 170. Since the absolute value of the first threshold voltage Vt1 is greater than the absolute values ​​of the threshold voltages and operating voltages of the surrounding transistors, adjacent transistors can be stably electrically isolated via the barrier gate structure 170 without the need for separate configurations. Because the barrier gate structure 170 can be formed using a process substantially the same or similar to that of the gate structure 160, process costs can be reduced. Furthermore, the complexity of subsequent processes can be reduced, thereby simplifying the process and improving the reliability of the semiconductor device.

[0035] A channel structure 140 may be disposed on the active region 105. The channel structure 140 may be surrounded by a gate structure 160 and a blocking gate structure 170. The channel structure 140 may include first channel layers to fourth channel layers 141, 142, 143, and 144, which are two or more channel layers spaced apart from each other in a direction perpendicular to the upper surface of the active region 105 (e.g., in the Z direction). The first channel layers to fourth channel layers 141, 142, 143, and 144 may be connected to the source / drain region 150 while being spaced apart from the upper surface of the active region 105. Unlike the channel structure 140 surrounded by the gate structure 160, the channel structure 140 surrounded by the blocking gate structure 170 may be a dummy channel structure 140 that does not form an electrical path. The first to fourth channel layers 141, 142, 143, and 144 may have the same or similar width in the Y direction as the active region 105 and the same or similar width in the X direction as the gate structure 160. In some embodiments, the width of the first to fourth channel layers 141, 142, 143, and 144 in the Y direction may decrease towards the lower channel layer. The number and shape of the channel layers 141, 142, 143, and 144 of each channel structure 140 may vary in example embodiments. In some embodiments, the semiconductor device 100 may have a FinFET structure that does not include the channel structure 140.

[0036] The first to fourth channel layers 141, 142, 143, and 144 may be formed of a semiconductor material (e.g., at least one of silicon (Si), silicon-germanium (SiGe), and germanium (Ge). The first to fourth channel layers 141, 142, 143, and 144 may be made of, for example, the same material as the substrate 101. According to an example embodiment, the first to fourth channel layers 141, 142, 143, and 144 may include impurity regions located in regions adjacent to the source / drain regions 150.

[0037] Source / drain regions 150 may be disposed on both sides of the blocking gate structure 170 to contact the channel structure 140. Source / drain regions 150 may be disposed between the blocking gate structure 170 and the gate structure 160. Source / drain regions 150 may be configured to cover the side surfaces of the respective first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140 in the X direction. At least some source / drain regions 150 may be connected to the back contact structure 190 via their lower surfaces or lower ends. Source / drain regions 150 connected to the back contact structure 190 may have a shape recessed by the back contact structure 190. In some embodiments, source / drain regions 150 may be configured as dummy source / drain regions not connected to the back contact structure 190. The upper surface of the source / drain region 150 may be located at the same level as the lower surface of the gate electrode 165 on the channel structure 140, or at a higher level than the lower surface of the gate electrode 165 on the channel structure 140, and this level may be varied in various embodiments.

[0038] The source / drain region 150 may include at least one of a semiconductor material (e.g., silicon (Si) and germanium (Ge)) and may also include a dopant as an impurity. The dopant may include an n-type dopant or a p-type dopant. For example, for an n-type transistor (nFET), the source / drain region 150 may include an n-type impurity (e.g., phosphorus (P), arsenic (As), or antimony (Sb)), and for a p-type transistor (pFET), the source / drain region 150 may include a p-type impurity (e.g., boron (B), gallium (Ga), or indium (In)). In some embodiments, the source / drain region 150 may include multiple epitaxial layers. The multiple epitaxial layers may include germanium (Ge) of different concentrations, or may include impurities of different concentrations. For example, the source / drain region 150 may include multiple epitaxial layers sequentially stacked from the bottom, and the concentration of germanium (Ge) and / or the concentration of impurities may sequentially increase from the bottom.

[0039] In some embodiments, the semiconductor device 100 may further include an internal spacer layer disposed between the side surface of the source / drain region 150 in the X direction and the gate dielectric layer 162 and / or the barrier gate dielectric layer 172. The internal spacer layer may include an insulating material.

[0040] A back barrier structure 180 may be disposed on the lowest surface of the gate structure 160 and the barrier gate structure 170. The back barrier structure 180 may penetrate the substrate 101 and the active region 105 to contact the gate structure 160 and the barrier gate structure 170 respectively, and may separate the active region 105. The back barrier structure 180 prevents leakage current that may occur in the active region 105 below the gate structure 160 and the barrier gate structure 170. The back barrier structure 180 may have a shape in which the width decreases with increasing horizontal direction, but is not limited thereto. For example, in some embodiments, the back barrier structure 180 may have a shape in which the width increases with increasing horizontal direction and then decreases again. In a second direction (e.g., the Y direction), the width of each back barrier structure 180 may be equal to or greater than the width of the active region 105. The active regions 105 extending in a first direction (e.g., the X direction) may be separated by the back barrier structure 180. The back barrier structure 180 may include an insulating material (e.g., at least one of oxides, nitrides, and oxynitrides).

[0041] The back contact structure 190 may be disposed below the source / drain region 150. The back contact structure 190 may penetrate the substrate 101 and the active region 105 to connect to the source / drain region 150 and may apply an electrical signal to the source / drain region 150. The back contact structure 190 may be partially recessed from below into the source / drain region 150 and extend into the source / drain region 150. The upper end of the back contact structure 190 may be located at a level higher than the upper end of the back barrier structure 180. The upper end of the back contact structure 190 may be located at a level higher than the lower surface of the lowermost channel layer 144.

[0042] At least a portion of the side surface of the back contact structure 190 may be tilted such that the width of the back contact structure 190 increases as the horizontal level decreases. The back contact structure 190 may include a metallic material (e.g., tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), ruthenium (Ru), aluminum (Al), etc.). The back contact structure 190 may include a metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)), or may include a metal (e.g., titanium (Ti), cobalt (Co), molybdenum (Mo), or platinum (Pt)). In an example embodiment, the back contact structure 190 may include a metal-semiconductor compound layer (e.g., a metal silicide layer) disposed at the interface with the source / drain region 150.

[0043] The back power structure 195 may be connected to the lower end or lower surface of the back contact structure 190. Together with the back contact structure 190, the back power structure 195 may form a BSPDN that applies power or ground voltage, and may also be referred to as a back power rail or buried power rail. In some embodiments, the back power structure 195 may be spaced apart from the back barrier structure 180. For example, the back power structure 195 may be a buried wiring extending in one direction (e.g., the Y direction) below the back contact structure 190, but the shape of the back power structure 195 is not limited thereto. For example, in some embodiments, the back power structure 195 may include via regions and / or line regions. In an example embodiment, the back power structure 195 may be a buried wiring line extending in the X direction. The width of the back power structure 195 may increase continuously downwards, but is not limited thereto. The back power structure 195 may include at least one of the following conductive materials: tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), and molybdenum (Mo)).

[0044] Interlayer insulating layer 115 may cover source / drain region 150, gate structure 160, and barrier gate structure 170. Back insulating layer 194 may cover the lower surface of substrate 101, the lower surface of back barrier structure 180, and the lower surface of back contact structure 190 beneath substrate 101. Interlayer insulating layer 115 and back insulating layer 194 may include at least one of oxide, nitride, and oxynitride, and may include, for example, a low-k material. According to an example embodiment, at least one of interlayer insulating layer 115 and back insulating layer 194 may include multiple insulating layers.

[0045] By Figures 2A to 2B The structure is flipped upside down so that the back power structure 195 is located on top to encapsulate the semiconductor device 100, but the encapsulation form of the semiconductor device 100 is not limited to this.

[0046] In the following description of exemplary implementations, references to the above will be omitted. Figures 1 to 2B Any description that overlaps with the description.

[0047] Figure 3A and Figure 3B This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 3A Showing with Figure 2A The corresponding area, and Figure 3B Showing with Figure 2B The corresponding area.

[0048] refer to Figure 3A and Figure 3BIn semiconductor device 100a, the back barrier structure 180 may include a first back barrier structure 181 located below the barrier gate structure 170, and a second back barrier structure 183 located below the corresponding gate structure 160. Figure 2A and Figure 2B Unlike the semiconductor device 100, the first back barrier structure 181 can be recessed from below into the barrier gate structure 170 and extend into the interior of the barrier gate structure 170. The upper end of the first back barrier structure 181 can be located at a level higher than the upper end of the second back barrier structure 183. The upper end of the first back barrier structure 181 can penetrate the lowermost channel layer 144. The level of the upper end of the first back barrier structure 181 is not limited thereto. For example, the first back barrier structure 181 can penetrate the third channel layer 143 and can be located at a level higher than the upper surface of the third channel layer 143. In some embodiments, the first back barrier structure 181 can also penetrate the first channel layer to the fourth channel layers 141, 142, 143 and 144. In a second direction (e.g., the Y direction), the width of the first back barrier structure 181 and the width of the second back barrier structure 183 can be different. Figure 3B In the diagram, the width of the second back-side blocking structure 183 is shown as larger, but it is not limited thereto. In some embodiments, the width of the first back-side blocking structure 181 may be equal to or greater than the width of the second back-side blocking structure 183.

[0049] Figure 4 This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 4 It shows the relationship with Figure 2A The corresponding area.

[0050] refer to Figure 4 ,and Figure 2A and Figure 2BUnlike semiconductor device 100, some source / drain regions 150 of semiconductor device 100b may not be connected to the back contact structure 190, but may be connected to the front contact structure 130. The front contact structure 130 may be configured to partially recess into the source / drain regions 150 from above by penetrating the interlayer insulating layer 115. Except for the location where the front contact structure 130 is positioned, the front contact structure 130 may have substantially the same or similar characteristics as the back contact structure 190. The front contact structure 130 may include metallic materials (e.g., tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), ruthenium (Ru), aluminum (Al), etc.). The front contact structure 130 may include metal nitrides (e.g., titanium nitride (TiN) film, tantalum nitride (TaN) film, or tungsten nitride (WN) film), or may include metals (e.g., titanium (Ti), cobalt (Co), molybdenum (Mo), or platinum (Pt)). In an example implementation, the front contact structure 130 may include a metal-semiconductor compound layer (e.g., a metal silicide layer) disposed at the interface with the source / drain region 150.

[0051] Figure 5A This is a plan view of a semiconductor device according to an example embodiment. Figure 5A It shows the relationship with Figure 1 The corresponding area. For ease of explanation, Figure 5A Only some components of the semiconductor device are shown in the image.

[0052] Figure 5B It shows Figure 5A The cross section of a semiconductor device taken along the cutting line IV-IV'.

[0053] refer to Figure 5A and Figure 5B The semiconductor device 100c may include an active region 105 disposed adjacently, and a gate structure 160 and a barrier gate structure 170 may extend to overlap with the active region 105. Figure 2A and Figure 2B Unlike the semiconductor device 100, the back barrier structure 180 may extend further in a second direction (e.g., the Y direction) to cut multiple active regions 105. In some embodiments, the first back barrier structure 181 below the gate structure 170 may cut multiple active regions 105, while the second back barrier structure 183 below the gate structure 160 may cut only one active region 105. Figure 3A and Figure 3BSimilar to the example embodiment of the semiconductor device 100a, the first back barrier structure 181 can be configured to be partially recessed from the bottom of the barrier gate structure 170, and the upper end of the first back barrier structure 181 can be located at a level higher than the upper end of the second back barrier structure 183. The form of the back barrier structure 180 can be modified in various ways depending on the intended design.

[0054] Figure 6A This is a plan view of a semiconductor device according to an example embodiment. Figure 6A It shows the relationship with Figure 1 The corresponding area. For ease of explanation, Figure 6A Only some components of the semiconductor device are shown in the image.

[0055] Figure 6B It shows Figure 6A The cross-section of the semiconductor device taken along the cutting line V-V', and Figure 6C It shows Figure 6A The cross section of a semiconductor device taken along the cutting line VI-VI'.

[0056] refer to Figures 6A to 6C The semiconductor device 100d may include a first region R1 and a second region R2. The first region R1 and the second region R2 may be adjacent to each other or spaced apart. The first region R1 and the second region R2 may be regions with different conductivity types. The first region R1 may be configured with a transistor of a first conductivity type, and the second region R2 may be configured with a transistor of a second conductivity type different from the first conductivity type. For example, the first region R1 may be an nFET region, and the second region R2 may be a pFET region. Conversely, the first region R1 may be a pFET region, and the second region R2 may be an nFET region. Hereinafter, an example embodiment in which the first region R1 is an nFET region and the second region R2 is a pFET region will be described.

[0057] In the first region R1, which is the nFET region, a first gate structure 160a and a first barrier gate structure 170a may be provided, and in the second region R2, which is the pFET region, a second gate structure 160b and a second barrier gate structure 170b may be provided. The first gate electrode 165a and the second barrier gate electrode 175b may include n-type metal with a relatively small work function, and the second gate electrode 165b and the first barrier gate electrode 175a may include p-type metal with a relatively large work function.

[0058] The first barrier gate structure 170a may include a first element that shifts the threshold voltage of the transistor in a positive direction, and the second barrier gate structure 170b may include a second element that shifts the threshold voltage of the transistor in a negative direction. The second gate structure 160b may include the first element, and the first gate structure 160a may include the second element. The first barrier gate structure 170a and the second gate structure 160b may be substantially the same structure and may be formed by substantially the same process. Since the first gate structure 160a includes the second element and the first barrier gate structure 170a includes the first element in the first region R1, which is the nFET region, the threshold voltage of the transistor including the first barrier gate structure 170a is shifted in a positive direction, and the threshold voltage of the transistor including the first gate structure 160a is shifted in a negative direction, such that the difference between these threshold voltages can increase. Therefore, within the operating voltage range in which current is generated in the channel structure 140 surrounded by the first gate structure 160a, current can be blocked in the channel structure 140 surrounded by the first blocking gate structure 170a. This principle can also be applied to the second gate structure 160b and the second blocking gate structure 170b in the second region R2, which is a pFET region.

[0059] Therefore, by forming a first barrier gate structure 170a and a second gate structure 160b with identical configurations, and forming a second barrier gate structure 170b and a first gate structure 160a with identical configurations, the semiconductor device 100d can include a structure that electrically isolates peripheral components in each region without requiring separate additional processes. This reduces process costs and complexity, and provides a semiconductor device with improved reliability.

[0060] Figures 7A to 15 The diagram illustrates a method for manufacturing a semiconductor device according to an example embodiment, arranged in the order of the manufacturing process.

[0061] Figure 7A , Figure 8A , Figure 9 , Figure 10 , Figure 11A , Figure 12A , Figure 13A , Figure 14A and Figure 15 It shows the relationship with Figure 2A The corresponding cross-section.

[0062] Figure 7B , Figure 8B , Figure 11B , Figure 12B , Figure 13B and Figure 14B It shows the relationship with Figure 2B The corresponding cross-section.

[0063] refer to Figure 7A and Figure 7B A sacrificial layer 120 and first to fourth channel layers 141, 142, 143 and 144 are alternately stacked on a substrate 101, and the sacrificial layer 120, the first to fourth channel layers 141, 142, 143 and 144 and the substrate 101 are partially removed to form an active structure including an active region 105.

[0064] Substrate 101 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Substrate 101 may include a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0065] The sacrificial layer 120 may be a layer that is replaced by the gate dielectric layer 162 and the gate electrode 165, and the barrier gate dielectric layer 172 and the barrier gate electrode 175 by subsequent processes, such as... Figure 2A and Figure 2B As shown. The sacrificial layer 120 may be formed of a material having etch selectivity relative to the first to fourth channel layers 141, 142, 143, and 144, respectively. The first to fourth channel layers 141, 142, 143, and 144 may include materials different from those of the sacrificial layer 120. The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 may include semiconductor materials including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), and the first to fourth channel layers 141, 142, 143, and 144 may include silicon (Si).

[0066] The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143 and 144 can be formed by performing an epitaxial growth process from the substrate 101. The number of channel layers 141, 142, 143 and 144, which are stacked alternately with the sacrificial layer 120, can vary in some embodiments.

[0067] The active structure may include an active region 105, a sacrificial layer 120, and first to fourth channel layers 141, 142, 143, and 144. The active structure may be formed as a line extending in one direction (e.g., the X direction). The side surfaces of the active structure along the Y direction may be coplanar with each other and may be located on a straight line.

[0068] In the regions where portions of the active region 105, the sacrificial layer 120, and the first to fourth channel layers 141, 142, 143, and 144 are removed, insulating material can be filled, and then a portion of the insulating material can be removed to allow the active region 105 to protrude, forming the element isolation layer 110. The upper surface of the element isolation layer 110 can be formed below the upper surface of the active region 105.

[0069] refer to Figure 8A and Figure 8B A sacrificial gate structure 200, a gate spacer layer 164, and a barrier gate spacer layer 174 can be formed on the active structure.

[0070] Each sacrificial gate structure 200 may be a sacrificial structure formed in the region on the channel structure 140 where the gate dielectric layer 162 and the gate electrode 165, as well as the blocking gate dielectric layer 172 and the blocking gate electrode 175, are disposed by subsequent processes. Figure 2A and Figure 2B As shown. The sacrificial gate structure 200 may have a line shape that extends in one direction and overlaps with the active structure. The sacrificial gate structure 200 may extend, for example, in the Y direction.

[0071] Each sacrificial gate structure 200 may include a first sacrificial gate layer 202 and a second sacrificial gate layer 205 sequentially stacked, and a mask patterning layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be patterned using the mask patterning layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be, but are not limited to, an insulating layer and a conductive layer, respectively, and the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be formed as a single layer. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask patterning layer 206 may include silicon oxide and / or silicon nitride.

[0072] Gate spacer layer 164 may be formed on the two sidewalls of the sacrificial gate structure 200 in the region where the gate structure 160 is to be formed, and barrier gate spacer layer 174 may be formed on the two sidewalls of the sacrificial gate structure 200 in the region where the barrier gate structure 170 is to be formed. Gate spacer layer 164 and barrier gate spacer layer 174 may be formed of a low-κ material and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0073] refer to Figure 9 The sacrificial layer 120 exposed by the sacrificial gate structure 200, as well as the first to fourth channel layers 141, 142, 143 and 144, can be partially removed to form a recessed region (RC).

[0074] By using the sacrificial gate structure 200, gate spacer layer 164, and barrier gate spacer layer 174 as a mask, the exposed sacrificial layer 120 and a portion of the first to fourth channel layers 141, 142, 143, and 144 can be removed, and the active region 105 can be partially removed to form a recessed region (RC). As a result, the first to fourth channel layers 141, 142, 143, and 144 can form a channel structure 140 with a finite length along the X direction.

[0075] refer to Figure 10 Source / drain regions 150 can be formed in the recessed region (RC).

[0076] The source / drain region 150 can be formed, for example, by selective epitaxial growth from the side surfaces of the channel structure 140, the active region 105, and the sacrificial layer 120. In some embodiments, the source / drain region 150 may include impurities by in-situ doping. Each source / drain region 150 may include multiple epitaxial layers. The multiple epitaxial layers may have different concentrations of non-silicon elements.

[0077] refer to Figure 11A and Figure 11B An interlayer insulating layer 115 can be formed, and the sacrificial layer 120 and the sacrificial gate structure 200 can be removed.

[0078] The interlayer insulating layer 115 can be formed by forming an insulating film covering the sacrificial gate structure 200 and the source / drain region 150 and performing a planarization process.

[0079] The sacrificial layer 120 and the sacrificial gate structure 200 can be selectively removed relative to the gate spacer layer 164, the barrier gate spacer layer 174, the interlayer insulating layer 115, the source / drain region 150, and the channel structure 140. First, the sacrificial gate structure 200 can be removed to form an upper gap region (UR), and then the sacrificial layer 120 exposed through the upper gap region (UR) can be removed to form a lower gap region (LR). For example, when the sacrificial layer 120 comprises silicon germanium (SiGe) and the channel structure 140 comprises silicon (Si), the sacrificial layer 120 can be selectively removed by performing a wet etching process.

[0080] refer to Figure 12A and Figure 12B It can form a gate structure 160 and a barrier gate structure 170.

[0081] A gate dielectric layer 162 and a gate electrode 165, as well as a barrier gate dielectric layer 172 and a barrier gate electrode 175, can be formed to fill the upper gap region (UR) and the lower gap region (LR). The gate dielectric layer 162 and the barrier gate dielectric layer 172 can be formed to conformally cover the inner surfaces of the upper gap region (UR) and the lower gap region (LR). The gate dielectric layer 162 and the barrier gate dielectric layer 172 can be formed simultaneously, but an annealing process can be performed to selectively implant a first element into the barrier gate dielectric layer 172. In some embodiments, an annealing process can be performed to implant a first element into the barrier gate dielectric layer 172 and implant a second element different from the first element into the gate dielectric layer 162. After forming the gate electrode 165 and the barrier gate electrode 175 to completely fill the upper gap region (UR) and the lower gap region (LR), the gate dielectric layer 162 and the gate spacer layer 164, as well as the barrier gate dielectric layer 172 and the barrier gate spacer layer 174, can be removed together from the upper portion of the upper gap region (UR) to a predetermined depth, and a gate capping layer 167 and a barrier gate capping layer 177 can be formed in the removed region. In some embodiments, unlike the gate electrode 165, the barrier gate electrode 175 can be formed to include a first element. In some embodiments, the barrier gate electrode 175 can be formed to include a first element, and the gate electrode 165 can be formed to include a second element different from the first element. Thereafter, an interlayer insulating layer 115 can be further formed on the gate structure 160 and the barrier gate structure 170.

[0082] refer to Figure 13A and Figure 13B This allows for the removal of a portion of the substrate 101.

[0083] In order to Figure 12A and Figure 12B Processes are performed on the lower surface of the substrate 101, a separate carrier substrate can be formed on the interlayer insulating layer 115, and the entire structure can be flipped to perform the following processes.

[0084] The substrate 101 can be thinned by removing a portion of the substrate, for example, through grinding, milling, and / or polishing processes. In some embodiments, the active region 105 and the device isolation layer 110 may be partially removed.

[0085] In this step, only the substrate 101 is partially removed, and the active region 105 and the device isolation layer 110 are not removed, or even if the active region 105 and the device isolation layer 110 are partially removed, other components (e.g., the barrier gate structure 170) are not removed, which reduces the process complexity and process cost.

[0086] refer to Figure 14A and Figure 14BThis can form a back-side barrier structure 180 that penetrates the substrate 101 and the active region 105.

[0087] A back barrier structure 180 can be formed by partially removing the substrate 101 and the active region 105 to form a hole to expose the gate structure 160 and the barrier gate structure 170, and then depositing an insulating material to fill the hole. In some embodiments, when the barrier gate structure 170 is partially recessed to form a hole, a back barrier structure 180 can be formed as shown below. Figure 3A The first back-side blocking structure 181.

[0088] refer to Figure 15 This can form a back contact structure 190 that penetrates the substrate 101 and the active region 105.

[0089] The back contact structure 190 can be formed by forming a contact hole that penetrates the substrate 101 and the active region 105 and extends into the interior of the source / drain region 150, and then filling the interior of the contact hole with a conductive material. When the back contact structure 190 includes a metal-semiconductor compound layer, the metal-semiconductor compound layer can be formed first along the surface of the source / drain region 150 exposed through the contact hole, and then a conductive layer can be formed to fill the contact hole.

[0090] Next, let's refer to... Figure 2A and Figure 2B A back insulating layer 194 can be formed on the lower surface of the substrate 101, and the back insulating layer 194 can be partially removed to form a back electrical structure 195 connected to the back contact structure 190. As a result, it is possible to manufacture... Figure 2A and Figure 2B Semiconductor devices.

[0091] As described above, according to some example embodiments, by utilizing the gate structure of a transistor that constitutes a threshold voltage higher than the operating voltage of the surrounding transistors together with a back-side barrier structure as an electrical blocking element, a semiconductor device with reduced process cost and process difficulty and improved reliability can be provided.

[0092] While this disclosure contains numerous specific implementation details, these details should not be construed as limiting the scope of any claims. Specific features described in the context of individual embodiments of this disclosure may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, one or more features in a combination may be removed from the combination in some cases, and the combination may be for sub-combinations or variations thereof.

[0093] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes an active region extending in a first direction; A gate structure extends on the substrate in a second direction and overlaps with the active region, and is spaced apart from each other in the first direction; A blocking gate structure, overlapping the active region between the gate structures, and extending in the second direction; Multiple channel layers are respectively surrounded by the barrier gate structure and the gate structure on the active region, and are spaced apart from each other in a third direction perpendicular to the upper surface of the substrate; Source / drain regions are located in recessed portions of the active region, wherein the source / drain regions are located on both sides of the barrier gate structure and are connected to the plurality of channel layers; A first back contact structure is located below the first source / drain region within the source / drain region, wherein the first back contact structure extends through the substrate and extends from the lower surface of the first source / drain region into the first source / drain region, wherein the first back contact structure is electrically connected to the first source / drain region; and Multiple back-side barrier structures are respectively located below the gate structure and the barrier gate structure, wherein the multiple back-side barrier structures extend through the substrate and the active region, and separate the active region. The barrier gate structure includes a first element that is different from the gate structure.

2. The semiconductor device according to claim 1, wherein, The source / drain regions comprise silicon and n-type dopant, and The first element includes a material configured to offset the threshold voltage of the transistor in a positive direction.

3. The semiconductor device according to claim 2, wherein, The first element includes at least one of aluminum, tantalum, tungsten, manganese, chromium, ruthenium, platinum, gallium, germanium and gold.

4. The semiconductor device according to claim 3, wherein, The barrier gate structure includes: A barrier gate dielectric layer is disposed on each of the plurality of channel layers; Barrier gate electrode, on the barrier gate dielectric layer; and A barrier gate capping layer extends on the barrier gate electrode in the second direction. Wherein, at least one of the barrier gate dielectric layer and the barrier gate electrode includes the first element.

5. The semiconductor device according to claim 1, wherein, The source / drain regions include silicon-germanium and p-type dopants, and The first element includes a material configured to offset the threshold voltage of the transistor in a negative direction.

6. The semiconductor device according to claim 5, wherein, The first element includes at least one of lanthanum, gadolinium, ruthenium, yttrium, and scandium.

7. The semiconductor device according to claim 6, wherein, The barrier gate structure includes: A barrier gate dielectric layer is present on each of the plurality of channel layers; Barrier gate electrode, on the barrier gate dielectric layer; and A barrier gate capping layer extends on the barrier gate electrode in the second direction. Wherein, at least one of the barrier gate dielectric layer and the barrier gate electrode includes the first element.

8. The semiconductor device according to claim 1, wherein, The plurality of back-side barrier structures include a first back-side barrier structure below the barrier gate structure, and second back-side barrier structures respectively disposed below the gate structure. The first back-side barrier structure extends from below into the barrier gate structure.

9. The semiconductor device according to claim 1, wherein, The plurality of back-side barrier structures include a first back-side barrier structure below the barrier gate structure, and second back-side barrier structures respectively disposed below the gate structure. The upper end of the first back barrier structure is located at a higher level relative to the substrate than the upper end of the second back barrier structure.

10. The semiconductor device according to claim 1, wherein, The upper end of the first back contact structure is located at a higher level relative to the substrate than the upper end of each of the plurality of back barrier structures.

11. The semiconductor device of claim 10, further comprising: A back insulating layer covers the corresponding lower surfaces of the substrate, the plurality of back barrier structures, and the first back contact structure; as well as A back-side electrical structure extends into the back-side insulation layer and is connected to the first back-side contact structure.

12. The semiconductor device according to claim 11, wherein, The back-side electrical structure is spaced apart from the plurality of back-side blocking structures.

13. The semiconductor device according to claim 1, wherein, In the second direction, the width of each of the plurality of back-side blocking structures is equal to or greater than the width of the active region.

14. A semiconductor device, comprising: Substrate; A gate structure extending on the substrate in a first direction; A barrier gate structure is provided on the substrate adjacent to a first side of the gate structure and extends in the first direction; The source / drain region is located between the gate structure and the barrier gate structure, and is in contact with both the gate structure and the barrier gate structure. A back contact structure extends into the substrate and partially extends from the lower surface of the source / drain region into the source / drain region, wherein the back contact structure is electrically connected to the source / drain region; and The back-side blocking structure includes: A first back-side barrier structure extends through the substrate below the barrier gate structure and contacts the barrier gate structure. A second back-side barrier structure extends through the substrate below the gate structure and contacts the lower surface of the gate structure. The first transistor including the blocking gate structure is configured to exhibit a first threshold voltage, the second transistor including the gate structure is configured to exhibit a second threshold voltage, and the absolute value of the first threshold voltage is greater than the absolute value of the second threshold voltage.

15. The semiconductor device according to claim 14, wherein, The absolute value of the first threshold voltage is 2 to 4 times the absolute value of the second threshold voltage.

16. The semiconductor device according to claim 14, wherein, The first threshold voltage and the second threshold voltage have positive values, and The difference between the first threshold voltage and the second threshold voltage is 0.15V or greater.

17. The semiconductor device according to claim 14, wherein, The first threshold voltage and the second threshold voltage have negative values, and The difference between the first threshold voltage and the second threshold voltage is 0.15V or greater.

18. A semiconductor device, comprising: The substrate has a first region and a second region; Multiple gate structures are present on the substrate; Multiple source / drain regions, wherein each source / drain region is located between adjacent gate structures in the plurality of gate structures; and Multiple back-side barrier structures are respectively located below the multiple gate structures, wherein the multiple back-side barrier structures extend through the substrate and respectively contact the multiple gate structures. The plurality of gate structures include: First gate structures are spaced apart from each other in a first direction and extend in a second direction intersecting the first direction in the first region. The second gate structures are spaced apart from each other in the first direction and extend in the second direction in the second region. A first barrier gate structure, located in the first region between the first gate structures, and The second barrier gate structure is located in the second region between the second gate structures. Wherein, the first gate structure and the second barrier gate structure include a first element, and The second gate structure and the first barrier gate structure include a second element that is different from the first element.

19. The semiconductor device according to claim 18, wherein, The first gate structure forms an N-type transistor, and the second gate structure forms a P-type transistor. The first element is at least one selected from aluminum, tantalum, tungsten, manganese, chromium, ruthenium, platinum, gallium, germanium, and gold. The second element is at least one of lanthanum, gadolinium, ruthenium, yttrium, and scandium.

20. The semiconductor device of claim 18, further comprising: A first back contact structure is located below a first source / drain region among the plurality of source / drain regions, wherein the first back contact structure extends through the substrate and partially extends from the lower surface of the first source / drain region into the first source / drain region.

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