Semiconductor device

Abstract

A semiconductor device may include: an insulating pattern on a first lower interlayer insulating layer; nanosheets vertically stacked on the insulating pattern; a gate electrode on the insulating pattern and surrounding the nanosheet; a source / drain region on one side of the gate electrode on the insulating pattern; and a source / drain contact electrically connected to the source / drain region. The source / drain region, the first lower interlayer insulating layer, and the insulating pattern may define a contact trench, and the source / drain contact may fill the contact trench. The source / drain contact may include a barrier layer, a first fill layer between portions of the barrier layer in the contact trench, and a second fill layer in the contact trench below the first fill layer. The first filled layer may be formed of multiple grains and may have a first average grain size. The second fill layer may be formed of a single die.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0113516, filed on August 23, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Various example embodiments relate to semiconductor devices. Specifically, this disclosure relates to devices including MBCFETs. TM Semiconductor devices (multi-bridge channel field-effect transistors). Background Technology

[0003] As one of the scaling techniques to increase the density of integrated circuit devices, multi-gate transistors have been proposed in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate and a gate is formed on the surface of the silicon body.

[0004] Because these multi-gate transistors utilize three-dimensional channels, they can be scaled up more easily. Additionally, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short-channel effect (SCE), where the potential in the channel region is affected by the drain voltage, can be suppressed more effectively. Summary of the Invention

[0005] This disclosure provides a semiconductor device with reduced defects and / or resistance in the source / drain contacts disposed below the source / drain regions.

[0006] The aspects of this disclosure are not limited to those mentioned above, and other aspects will be clearly understood by those skilled in the art from the following description.

[0007] According to embodiments of this disclosure, a semiconductor device may include: a first lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the first lower interlayer insulating layer; a plurality of nanosheets stacked vertically on the insulating pattern and spaced apart from each other; a gate electrode extending in a second horizontal direction on the insulating pattern, surrounding the plurality of nanosheets, the second horizontal direction being different from the first horizontal direction; a source / drain region on one side of the gate electrode and on the insulating pattern; and source / drain contacts. The source / drain region, the first lower interlayer insulating layer, and the insulating pattern may define a contact trench penetrating the first lower interlayer insulating layer and the insulating pattern in a vertical direction, the contact trench extending into the interior of the source / drain region. The source / drain contacts may fill the interior of the contact trench. The source / drain contacts may be electrically connected to the source / drain region. The source / drain contact may include a barrier layer, a first filler layer, and a second filler layer. The barrier layer extends along a portion of the upper sidewall and upper surface of a contact trench. The first filler layer fills the space between portions of the barrier layer within the contact trench. The second filler layer fills the interior of the contact trench below the bottom surface of the first filler layer. The sidewalls of the barrier layer in a first horizontal direction contact an insulating pattern. The first filler layer may be polycrystalline and may have a first average grain size in the first horizontal direction. The sidewalls of the second filler layer in the first horizontal direction may contact each of the first interlayer insulation layer and the insulating pattern. The second filler layer may be monocrystalline.

[0008] According to embodiments of the present disclosure, a semiconductor device may include: a first lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the first lower interlayer insulating layer; a gate electrode extending in a second horizontal direction on the insulating pattern, different from the first horizontal direction; a source / drain region on one side of the gate electrode and on the insulating pattern, the source / drain region, the first lower interlayer insulating layer, and the insulating pattern defining a contact trench penetrating the first lower interlayer insulating layer and the insulating pattern in a vertical direction, the contact trench extending into the interior of the source / drain region; a source / drain contact filling the interior of the contact trench, the source / drain contact being electrically connected to the source / drain region; a second lower interlayer insulating layer on a bottom surface of the first lower interlayer insulating layer; and a bottom via in a via trench defined in the second lower interlayer insulating layer, the bottom via contacting the bottom surface of the source / drain contact, the bottom via being polycrystalline. The source / drain contact may include a barrier layer, a first fill layer, and a second fill layer. The barrier layer extends along a portion of the upper sidewall and upper surface of a contact trench. The first fill layer fills the space between portions of the barrier layer within the contact trench. The second fill layer fills the interior of the contact trench below the bottom surface of the first fill layer. The sidewalls of the barrier layer in a first horizontal direction may contact an insulating pattern. The first fill layer may be polycrystalline and may have a first average grain size in the first horizontal direction. The bottom surface of the second fill layer may contact a bottom via. The sidewalls of the second fill layer in the first horizontal direction may contact each of a first interlayer insulating layer and an insulating pattern. The second fill layer may be monocrystalline. The second average grain size of the bottom via in the first horizontal direction may be at least 1.5 times larger than the first average grain size.

[0009] According to embodiments of the present disclosure, a semiconductor device may include: a first lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the first lower interlayer insulating layer; a plurality of nanosheets stacked vertically on the insulating pattern and spaced apart from each other; a gate electrode extending in a second horizontal direction on the insulating pattern, the second horizontal direction being different from the first horizontal direction, the gate electrode surrounding the plurality of nanosheets; a source / drain region on one side of the gate electrode and on the insulating pattern, wherein the source / drain region, the first lower interlayer insulating layer, and the insulating pattern define a contact trench penetrating the first lower interlayer insulating layer and the insulating pattern in a vertical direction, the contact trench extending into the interior of the source / drain region; a source / drain contact filling the interior of the contact trench, the source / drain contact being electrically connected to the source / drain region; a second lower interlayer insulating layer disposed on a bottom surface of the first lower interlayer insulating layer; and a bottom via in a via trench defined in the second lower interlayer insulating layer, the bottom via contacting the bottom surface of the source / drain contact, the bottom via being polycrystalline. The source / drain contact may include a barrier layer, a first fill layer, and a second fill layer. The barrier layer extends along a portion of the upper sidewall and upper surface of a contact trench. The first fill layer fills the space between portions of the barrier layer within the contact trench. The second fill layer fills the interior of the contact trench below the bottom surface of the first fill layer. The sidewalls of the barrier layer in a first horizontal direction may contact an insulating pattern. The first fill layer may contact the lowest surface of the barrier layer. The first fill layer may be polycrystalline and may have a first average grain size in the first horizontal direction. The bottom surface of the second fill layer may contact a bottom via. The lowest surface of the second fill layer may be lower than the bottom surface of a first interlayer insulation layer. The sidewalls of the second fill layer in the first horizontal direction contact each of the first interlayer insulation layer and the insulating pattern. The second fill layer may be monocrystalline. The second average grain size of the bottom via in the first horizontal direction may be at least 1.5 times larger than the first average grain size. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0011] Figure 1 This is a layout diagram used to explain some example embodiments of a semiconductor device according to this disclosure.

[0012] Figure 2 It is along Figure 1 A sectional view taken by line A-A'.

[0013] Figure 3 yes Figure 2 Enlarged views of each of regions R1 and R2.

[0014] Figure 4 It is along Figure 1 The sectional view taken by line B-B'.

[0015] Figure 5 It is along Figure 1 A sectional view taken by line C-C'.

[0016] Figures 6 to 33 This is an intermediate stage diagram used to explain a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure.

[0017] Figure 34 This is a cross-sectional view used to explain some example embodiments of a semiconductor device according to this disclosure.

[0018] Figure 35 This is a cross-sectional view used to explain some other example embodiments of a semiconductor device according to this disclosure.

[0019] Figure 36 This is a cross-sectional view used to explain some other example embodiments of a semiconductor device according to this disclosure.

[0020] Figure 37 and Figure 38 This is a cross-sectional view used to explain some other example embodiments of a semiconductor device according to this disclosure.

[0021] Figure 39 and Figure 40 This is a cross-sectional view used to explain some other example embodiments of a semiconductor device according to this disclosure.

[0022] Figure 41 and Figure 42 This is a cross-sectional view used to explain a semiconductor device according to some other example embodiments of this disclosure. Detailed Implementation

[0023] In the following diagrams of a semiconductor device according to some exemplary embodiments, the semiconductor device is described by way of example as including a transistor (MBCFET) comprising a nanosheet. TM (Multi-bridge channel field-effect transistor), but this disclosure is not limited thereto. In some other example embodiments, the semiconductor device may include a fin transistor (FinFET), a tunneling transistor (tunneling FET), or a three-dimensional (3D) transistor having a fin-patterned channel region. Additionally, the semiconductor device according to some other example embodiments may include a bipolar junction transistor or a laterally diffused metal-oxide-semiconductor (LDMOS) transistor.

[0024] In the following text, reference will be made to Figures 1 to 5 A semiconductor device according to some example embodiments of the present disclosure is described.

[0025] Figure 1This is a layout diagram used to explain some example embodiments of a semiconductor device according to this disclosure. Figure 2 It is along Figure 1 A sectional view taken by line A-A'. Figure 3 yes Figure 2 Enlarged views of each of regions R1 and R2. Figure 4 It is along Figure 1 The sectional view taken by line B-B'. Figure 5 It is along Figure 1 A sectional view taken by line C-C'.

[0026] Reference Figures 1 to 5 A semiconductor device according to some example embodiments of this disclosure includes a first lower interlayer insulating layer 110, a second lower interlayer insulating layer 100, an insulating pattern 111, a field insulating layer 115, a first plurality of nanosheets NW1, a second plurality of nanosheets NW2, a first gate electrode G1, a second gate electrode G2, a first gate spacer 121, a second gate spacer 122, a first gate insulating layer 131, a second gate insulating layer 132, a first cap pattern 141, a second cap pattern 142, a source / drain region SD, a first etch stop layer 150, a first upper interlayer insulating layer 155, a source / drain contact 160, a silicide layer SL, a bottom via 170, a first gate contact CB1, a second gate contact CB2, a second etch stop layer 180, a second upper interlayer insulating layer 185, a first upper via V1, and a second upper via V2. The source / drain region SD may also be referred to as a source / drain structure SD.

[0027] The first lower interlayer insulating layer 110 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material. The low-k dielectric material may include, for example, tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysiloxane (DADBS), trimethylsilane phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (toluene silazane), FSG (fluorinated silicate glass), polyimide nanofoams (such as polypropylene oxide), CDO (carbon-doped silicon oxide), OSG (organosilicon glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof, but this disclosure is not limited thereto.

[0028] In the following text, each of the first horizontal direction DR1 and the second horizontal direction DR2 can be defined as a direction parallel to the upper surface of the first lower interlayer insulation layer 110. The second horizontal direction DR2 can be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 can be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. In other words, the vertical direction DR3 can be defined as a direction perpendicular to the upper surface of the first lower interlayer insulation layer 110.

[0029] The second lower interlayer insulating layer 100 may be disposed on the bottom surface of the first lower interlayer insulating layer 110. For example, the second lower interlayer insulating layer 100 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material. In some example embodiments, the second lower interlayer insulating layer 100 may include a material different from the first lower interlayer insulating layer 110. However, this disclosure is not limited thereto. In some other example embodiments, the second lower interlayer insulating layer 100 may include the same material as the first lower interlayer insulating layer 110.

[0030] An insulating pattern 111 may extend on the upper surface of the first lower interlayer insulating layer 110 in a first horizontal direction DR1. The insulating pattern 111 may protrude from the upper surface of the first lower interlayer insulating layer 110 in a vertical direction DR3. The insulating pattern 111 may include an insulating material. For example, the insulating pattern 111 may include the same material as the first lower interlayer insulating layer 110. A field insulating layer 115 may be disposed on the upper surface of the first lower interlayer insulating layer 110. The field insulating layer 115 may surround the sidewalls of the insulating pattern 111. For example, the upper surface of the field insulating layer 115 may be formed below the upper surface of the insulating pattern 111. For example, the field insulating layer 115 may include an oxide layer, a nitride layer, an oxide oxynitride layer, or a combination thereof.

[0031] Each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 may be disposed on the upper surface of the insulating pattern 111. The second plurality of nanosheets NW2 may be spaced apart from the first plurality of nanosheets NW1 in a first horizontal direction DR1. For example, each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 may include a plurality of nanosheets stacked and spaced apart from each other in a vertical direction DR3. Figure 2 and Figure 4 In the illustration, each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 is shown as comprising three nanosheets stacked and spaced apart from each other in a vertical direction DR3, but this disclosure is not limited thereto. In some other exemplary embodiments, each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 may comprise four or more nanosheets stacked and spaced apart from each other in a vertical direction DR3. For example, each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 may comprise silicon (Si).

[0032] Each of the first gate electrode G1 and the second gate electrode G2 may extend in a second horizontal direction DR2 on the insulating pattern 111 and the field insulating layer 115. The second gate electrode G2 may be spaced apart from the first gate electrode G1 in a first horizontal direction DR1. The first gate electrode G1 may surround a first plurality of nanosheets NW1. The second gate electrode G2 may surround a second plurality of nanosheets NW2.

[0033] Each of the first gate electrode G1 and the second gate electrode G2 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride. The materials include (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Each of the first gate electrode G1 and the second gate electrode G2 may include conductive metal oxides, conductive metal nitrides, etc., and may also include oxide forms of the aforementioned materials.

[0034] The first gate spacer 121 may extend along the two sidewalls of the first gate electrode G1 in a second horizontal direction DR2 on the upper surface of the uppermost nanosheet of the plurality of first nanosheets NW1 and on the field insulating layer 115. The second gate spacer 122 may extend along the two sidewalls of the second gate electrode G2 in a second horizontal direction DR2 on the upper surface of the uppermost nanosheet of the plurality of second nanosheets NW2 and on the field insulating layer 115. Each of the first gate spacer 121 and the second gate spacer 122 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. However, this disclosure is not limited thereto.

[0035] For example, the source / drain region SD may be disposed between the first gate electrode G1 and the second gate electrode G2 on the upper surface of the insulating pattern 111. For example, the source / drain region SD may be in contact with the upper surface of the insulating pattern 111. For example, the source / drain region SD may be in contact with the sidewalls of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 on the first horizontal direction DR1, respectively. For example, the upper surface of the source / drain region SD may be formed above the upper surface of the uppermost nanosheet of each of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2. In some embodiments, the source / drain region SD may be disposed on one side of each of the first gate electrode G1 and the second gate electrode G2.

[0036] A first gate insulating layer 131 may be disposed between the first gate electrode G1 and the insulating pattern 111. A first gate insulating layer 131 may be disposed between the first gate electrode G1 and the field insulating layer 115. A first gate insulating layer 131 may be disposed between the first gate electrode G1 and the first gate spacer 121. A first gate insulating layer 131 may be disposed between the first gate electrode G1 and the first plurality of nanosheets NW1. A first gate insulating layer 131 may be disposed between the first gate electrode G1 and the source / drain region SD. A second gate insulating layer 132 may be disposed between the second gate electrode G2 and the insulating pattern 111. A second gate insulating layer 132 may be disposed between the second gate electrode G2 and the field insulating layer 115. A second gate insulating layer 132 may be disposed between the second gate electrode G2 and the second gate spacer 122. A second gate insulating layer 132 may be disposed between the second gate electrode G2 and the second plurality of nanosheets NW2. A second gate insulating layer 132 may be disposed between the second gate electrode G2 and the source / drain region SD.

[0037] Each of the first gate insulating layer 131 and the second gate insulating layer 132 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k dielectric material having a dielectric constant greater than that of silicon oxide. The high-k dielectric material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0038] The semiconductor device according to some example embodiments may include an NC (negative capacitance) FET utilizing a negative capacitor. For example, each of the first gate insulating layer 131 and the second gate insulating layer 132 may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0039] Ferroelectric material layers can have negative capacitance, while paraelectric material layers can have positive capacitance. For example, when two or more capacitors are connected in series and each of their capacitances has a positive value, the total capacitance decreases compared to the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance can have a positive value and be greater than the absolute value of each individual capacitor.

[0040] When a ferroelectric material layer with negative capacitance and a paraelectric material layer with positive capacitance are connected in series, the total capacitance of the two connected ferroelectric and paraelectric material layers can be increased. By utilizing the increase in total capacitance, a transistor including a ferroelectric material layer can have a subthreshold swing (SS) of less than 60 mV / decimal at room temperature.

[0041] The ferroelectric material layer may possess ferroelectric properties. The ferroelectric material layer may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. As another example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. In yet another example, hafnium zirconium oxide may be a compound of hafnium (Hf) and zirconium (Zr) with oxygen (O).

[0042] The ferroelectric material layer may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopants included in the ferroelectric material layer may vary depending on which ferroelectric material is contained within it.

[0043] When the ferroelectric material layer includes hafnium oxide, the dopants included in the ferroelectric material layer may include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0044] When the dopant is aluminum (Al), the ferroelectric material layer can contain 3 at% (atomic %) to 8 at% aluminum. Here, the dopant ratio can be the ratio of aluminum to the sum of hafnium and aluminum.

[0045] When the dopant is silicon (Si), the ferroelectric material layer may include 2 at% to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2 at% to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include 1 at% to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include 50 at% to 80 at% zirconium.

[0046] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one of silicon oxide and high-k metal oxides. The metal oxide included in the paraelectric material layer may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0047] The ferroelectric material layer and the paraelectric material layer may contain the same material. Although the ferroelectric material layer has ferroelectric properties, the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer contain hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0048] The ferroelectric material layer can have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer can be, for example, from 0.5 nm to 10 nm, but is not limited to this. Since each ferroelectric material can have a different critical thickness for exhibiting ferroelectric properties, the thickness of the ferroelectric material layer can vary depending on the specific ferroelectric material.

[0049] For example, each of the first gate insulating layer 131 and the second gate insulating layer 132 may include a single ferroelectric material layer. In another example, each of the first gate insulating layer 131 and the second gate insulating layer 132 may include a plurality of ferroelectric material layers spaced apart from each other. Each of the first gate insulating layer 131 and the second gate insulating layer 132 may have a stacked layer structure in which a plurality of ferroelectric material layers are alternately stacked with a plurality of paraelectric material layers.

[0050] A first etch stop layer 150 may be disposed on the sidewall of each of the first gate spacer 121 and the second gate spacer 122 in the first horizontal direction DR1. The first etch stop layer 150 may be disposed on the upper surface of the source / drain region SD. Although not shown, the first etch stop layer 150 may be disposed on the upper surface of the field insulating layer 115. Additionally, the first etch stop layer 150 may be disposed on the sidewall of the source / drain region SD in the second horizontal direction DR2. For example, the first etch stop layer 150 may be conformally formed. For example, the first etch stop layer 150 may include at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0051] A first cover pattern 141 may extend on each of the first gate spacer 121, the first gate insulating layer 131, and the first gate electrode G1 in a second horizontal direction DR2. A second cover pattern 142 may extend on each of the second gate spacer 122, the second gate insulating layer 132, and the second gate electrode G2 in the second horizontal direction DR2. For example, the bottom surface of each of the first cover pattern 141 and the second cover pattern 142 may contact the first etch stop layer 150. However, this disclosure is not limited thereto. In some other example embodiments, the sidewalls of each of the first cover pattern 141 and the second cover pattern 142 may contact the first etch stop layer 150. For example, each of the first cover pattern 141 and the second cover pattern 142 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof. However, this disclosure is not limited thereto.

[0052] A first upper interlayer insulating layer 155 may be disposed on the first etch stop layer 150. The first upper interlayer insulating layer 155 may be disposed on the sidewalls of each of the first cap pattern 141 and the second cap pattern 142. The first upper interlayer insulating layer 155 may cover the source / drain region SD on the field insulating layer 115. For example, the upper surface of the first upper interlayer insulating layer 155 may be formed on the same plane as the upper surfaces of each of the first cap pattern 141 and the second cap pattern 142. The first upper interlayer insulating layer 155 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material.

[0053] A contact trench 160T may be formed beneath the source / drain region SD. The contact trench 160T may penetrate the first lower interlayer insulating layer 110 and the insulating pattern 111 in the vertical direction DR3 and extend into the interior of the source / drain region SD. For example, the two sidewalls of the contact trench 160T in the first horizontal direction DR1 may be defined by the first lower interlayer insulating layer 110 and the insulating pattern 111. Additionally, the two sidewalls of the contact trench 160T in the first horizontal direction DR1 may be defined by the first lower interlayer insulating layer 110 and the field insulating layer 115. For example, the width of the contact trench 160T in the first horizontal direction DR1 and the width of the contact trench 160T in the second horizontal direction DR2 may each increase closer to the bottom surface of the first lower interlayer insulating layer 110. In some embodiments, the source / drain region SD, the first lower interlayer insulating layer 110, and the insulating pattern 111 may define a contact trench 160T penetrating the first lower interlayer insulating layer 110 and the insulating pattern 111 in the vertical direction DR3.

[0054] Source / drain contacts 160 may be disposed within contact trench 160T. For example, source / drain contacts 160 may completely fill the interior of contact trench 160T. That is, source / drain contacts 160 may penetrate the first lower interlayer insulation layer 110 and insulation pattern 111 in the vertical direction DR3 and extend into the interior of source / drain region SD. Source / drain contacts 160 may be electrically connected to source / drain region SD. For example, the two sidewalls of source / drain contacts 160 in the first horizontal direction DR1 may contact each of the first lower interlayer insulation layer 110 and insulation pattern 111. For example, the two sidewalls of source / drain contacts 160 in the second horizontal direction DR2 may contact each of the first lower interlayer insulation layer 110 and field insulation layer 115. For example, the widths of the first horizontal direction DR1 and the second horizontal direction DR2 of the source / drain contact 160 can each increase closer to the bottom surface of the first lower interlayer insulating layer 110. A silicide layer SL can be disposed along the interface between the source / drain region SD and the source / drain contact 160. For example, the silicide layer SL may comprise a metal silicide material. For example, the source / drain contact 160 may comprise a barrier layer 161, a first filler layer 162, and a second filler layer 163.

[0055] The barrier layer 161 may be disposed along a portion of the upper sidewall and upper surface of the contact trench 160T. For example, the barrier layer 161 may be conformally formed. For example, the upper surface of the barrier layer 161 may contact the silicide layer SL. That is, the silicide layer SL may be disposed along the interface between the source / drain region SD and the barrier layer 161. For example, the outer sidewall of the barrier layer 161 in the first horizontal direction DR1 may contact the insulating pattern 111. For example, the outer sidewall of the barrier layer 161 in the second horizontal direction DR2 may contact the field insulating layer 115. For example, the barrier layer 161 may include at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), aluminum (Al), molybdenum (Mo), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh).

[0056] The first filler layer 162 may be disposed within the contact trench 160T between the barrier layers 161. That is, at least a portion of the sidewalls of the first filler layer 162 may be surrounded by the barrier layers 161. For example, at least a portion of the first filler layer 162 may be disposed within the source / drain region SD (that is, the uppermost surface of the first filler layer 162 may be formed above the bottom surface of the source / drain region SD). For example, the first filler layer 162 may contact the lowermost surface of the barrier layer 161. For example, on the lowermost surface of the barrier layer 161, the sidewalls of the first filler layer 162 in the first horizontal direction DR1 may contact the insulating pattern 111. Additionally, on the lowermost surface of the barrier layer 161, the sidewalls of the first filler layer 162 in the second horizontal direction DR2 may contact the field insulating layer 115.

[0057] For example, the bottom surface 162a of the first filler layer 162 may be formed above the upper surface of the first lower interlayer insulating layer 110. However, this disclosure is not limited thereto. In some other example embodiments, the bottom surface 162a of the first filler layer 162 may be formed between the bottom surface of the first lower interlayer insulating layer 110 and the upper surface of the first lower interlayer insulating layer 110. For example, as Figure 3 As shown, the first filling layer 162 may be formed of polycrystalline materials. That is, the first filling layer 162 may include a plurality of first grains GR1. For example, the first filling layer 162 may have a first average grain size in the first horizontal direction DR1 (that is, the plurality of first grains GR1 included in the first filling layer 162 may have a first average grain size in the first horizontal direction DR1). The first average grain size may be the average of the sizes of the plurality of first grains GR1 included in the first filling layer 162 in the first horizontal direction DR1.

[0058] The second filler layer 163 may fill the interior of the contact groove 160T on the bottom surface of the first filler layer 162. For example, the upper surface of the second filler layer 163 may contact the bottom surface of the first filler layer 162. For example, the two sidewalls of the second filler layer 163 in the first horizontal direction DR1 may contact each of the first lower interlayer insulation layer 110 and the insulation pattern 111. Additionally, the two sidewalls of the second filler layer 163 in the second horizontal direction DR2 may contact each of the first lower interlayer insulation layer 110 and the field insulation layer 115. For example, the sidewalls of the second filler layer 163 in the first horizontal direction DR1 that contact the insulation pattern 111, the sidewalls of the first filler layer 162 in the first horizontal direction DR1 that contact the insulation pattern 111, and the outer sidewalls of the barrier layer 161 in the first horizontal direction DR1 that contact the insulation pattern 111 may each be aligned.

[0059] For example, the lowermost surface of the barrier layer 161 may be stacked on the upper surface of the second filler layer 163 in the vertical direction DR3. For example, the lowermost surface of the barrier layer 161 may be spaced apart from the upper surface of the second filler layer 163 in the vertical direction DR3. For example, the upper surface of the second filler layer 163 may be formed above the upper surface of the first lower interlayer insulating layer 110. However, this disclosure is not limited thereto. In some other example embodiments, the upper surface of the second filler layer 163 may be formed between the bottom surface of the first lower interlayer insulating layer 110 and the upper surface of the first lower interlayer insulating layer 110. For example, the bottom surface of the second filler layer 163 may be formed to protrude toward the bottom via 170. For example, the bottom surface of the second filler layer 163 may be formed below the bottom surface of the first lower interlayer insulating layer 110. That is, the lowermost surface 163a of the second filler layer 163 may be formed below the bottom surface of the first lower interlayer insulating layer 110. For example, the second filler layer 163 may be formed from a single grain.

[0060] A via trench 170T may be formed beneath the source / drain contact 160. The via trench 170T may be formed within the second lower interlayer insulating layer 100. The via trench 170T may penetrate the second lower interlayer insulating layer 100 in the vertical direction DR3 and extend into the bottom surface of the first lower interlayer insulating layer 110. For example, the width of the via trench 170T in the first horizontal direction DR1 and the width of the via trench 170T in the second horizontal direction DR2 may each increase as it approaches the bottom surface of the second lower interlayer insulating layer 100. For example, the width of the via trench 170T in the first horizontal direction DR1 may be greater than the width of the contact trench 160T in the first horizontal direction DR1. Furthermore, the width of the via trench 170T in the second horizontal direction DR2 may be greater than the width of the contact trench 160T in the second horizontal direction DR2.

[0061] A bottom via 170 may be disposed within a via trench 170T. For example, at least a portion of the second filler layer 163 may be disposed within the via trench 170T. The bottom via 170 may contact the bottom surface of the source / drain contact 160. In other words, the bottom via 170 may contact the bottom surface of the second filler layer 163. The bottom via 170 may fill the interior of the via trench 170T on the bottom surface of the second filler layer 163. For example, the width of the bottom via 170 in the first horizontal direction DR1 may be greater than the width of the source / drain contact 160 in the first horizontal direction DR1. Furthermore, the width of the bottom via 170 in the second horizontal direction DR2 may be greater than the width of the source / drain contact 160 in the second horizontal direction DR2. For example, at least a portion of the upper surface of the bottom via 170 may contact the bottom surface of the first lower interlayer insulating layer 110.

[0062] For example, such as Figure 3As shown, the bottom via 170 may be formed of polycrystalline materials. That is, the bottom via 170 may include a plurality of second grains GR2. For example, the bottom via 170 may have a second average grain size in the first horizontal direction DR1. In other words, the plurality of second grains GR2 included in the bottom via 170 may have a second average grain size in the first horizontal direction DR1. The second average grain size may be the average of the sizes of the plurality of second grains GR2 included in the bottom via 170 in the first horizontal direction DR1. For example, the second average grain size of the plurality of second grains GR2 included in the bottom via 170 may be larger than the first average grain size of the plurality of first grains GR1 included in the first filler layer 162. For example, the second average grain size of the plurality of second grains GR2 included in the bottom via 170 may be at least 1.5 times larger than the first average grain size of the plurality of first grains GR1 included in the first filler layer 162.

[0063] For example, each of the first filler layer 162, the second filler layer 163, and the bottom via 170 may include any one of molybdenum (Mo), tungsten (W), ruthenium (Ru), iridium (Ir), cobalt (Co), and copper (Cu). In some example embodiments, the first filler layer 162, the second filler layer 163, and the bottom via 170 may include the same material as each other. In some other example embodiments, any one of the first filler layer 162, the second filler layer 163, and the bottom via 170 may include different materials. In still some other example embodiments, the first filler layer 162, the second filler layer 163, and the bottom via 170 may each include different materials.

[0064] A first gate contact CB1 can penetrate the first cover pattern 141 in the vertical direction DR3 to connect to the first gate electrode G1. A second gate contact CB2 can penetrate the second cover pattern 142 in the vertical direction DR3 to connect to the second gate electrode G2. Each of the first gate contact CB1 and the second gate contact CB2 may include a conductive material. A second etch stop layer 180 may be disposed on the upper surface of the first upper interlayer insulating layer 155 and on the upper surfaces of the first gate contact CB1 and the second gate contact CB2, respectively. Figure 2 , Figure 4 and Figure 5 In this embodiment, the second etch stop layer 180 is shown as being formed of a single layer, but this disclosure is not limited thereto. In some other example embodiments, the second etch stop layer 180 may be formed as multiple layers. The second etch stop layer 180 may include at least one of, for example, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectric materials.

[0065] A second upper interlayer insulating layer 185 may be disposed on the second etch stop layer 180. The second upper interlayer insulating layer 185 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material. A first upper via V1 may penetrate the second upper interlayer insulating layer 185 and the second etch stop layer 180 in the vertical direction DR3 to connect to the first gate contact CB1. A second upper via V2 may penetrate the second upper interlayer insulating layer 185 and the second etch stop layer 180 in the vertical direction DR3 to connect to the second gate contact CB2. Each of the first upper via V1 and the second upper via V2 may include a conductive material.

[0066] A semiconductor device according to some exemplary embodiments of the present disclosure may have a source / drain contact 160, which includes a first fill layer 162 formed of a polycrystalline material and a second fill layer 163 formed of a single-crystal material. Furthermore, a bottom via 170 connected to the source / drain contact 160 may be formed of a polycrystalline material. Therefore, the semiconductor device according to some exemplary embodiments of the present disclosure may reduce defects formed in each of the first fill layer 162, the second fill layer 163, and the bottom via 170. Additionally, the semiconductor device according to some exemplary embodiments of the present disclosure may reduce the resistance between the first fill layer 162, the second fill layer 163, and the bottom via 170.

[0067] In the following text, reference will be made to Figures 2 to 33 A method for manufacturing a semiconductor device according to some example embodiments of the present disclosure is described.

[0068] Figures 6 to 33 This is an intermediate stage diagram used to explain a method of manufacturing a semiconductor device according to some example embodiments of the present disclosure.

[0069] Reference Figure 6 and Figure 7 The substrate 10 may be a silicon substrate or SOI (silicon-on-insulator). Optionally, the substrate 10 may include silicon germanium, SGOI (silicon-germanium-on-insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, this disclosure is not limited thereto.

[0070] Subsequently, a stacked structure 20 may be formed on the substrate 10. The stacked structure 20 may include a first semiconductor layer 21 and a second semiconductor layer 22 alternately stacked on the substrate 10. For example, the first semiconductor layer 21 may be formed at the bottom of the stacked structure 20, and the second semiconductor layer 22 may be formed at the top of the stacked structure 20. However, this disclosure is not limited thereto. In some other example embodiments, the first semiconductor layer 21 may also be formed at the top of the stacked structure 20. The first semiconductor layer 21 may include, for example, silicon germanium (SiGe). The second semiconductor layer 22 may include, for example, silicon (Si).

[0071] Subsequently, a portion of the stacked structure 20 may be etched. Simultaneously with etching the stacked structure 20, a portion of the substrate 10 may also be etched. Through this etching process, an active pattern 11 may be defined beneath the stacked structure 20 on the upper surface of the substrate 10. The active pattern 11 may protrude from the upper surface of the substrate 10 in the vertical direction DR3. The active pattern 11 may extend in the first horizontal direction DR1. For example, the active pattern 11 may comprise silicon (Si).

[0072] Next, a field insulating layer 115 may be formed on the upper surface of the substrate 10. The field insulating layer 115 may surround the sidewalls of the active pattern 11. For example, the upper surface of the field insulating layer 115 may be formed below the upper surface of the active pattern 11. Subsequently, a pad oxide layer 30 may be formed to cover the upper surface of the field insulating layer 115, the exposed sidewalls of the active pattern 11, and the sidewalls and upper surface of the stacked structure 20. For example, the pad oxide layer 30 may be formed conformally. The pad oxide layer 30 may include, for example, silicon oxide (SiO2).

[0073] Reference Figure 8 and Figure 9 The first dummy gate DG1, the second dummy gate DG2, the first dummy cover pattern DC1, and the second dummy cover pattern DC2, extending along the second horizontal direction DR2, can be formed on the pad oxide layer 30 on the stacked structure 20 and the field insulating layer 115. For example, the second dummy gate DG2 can be spaced apart from the first dummy gate DG1 along the first horizontal direction DR1. The first dummy cover pattern DC1 can be disposed on the first dummy gate DG1. The second dummy cover pattern DC2 can be disposed on the second dummy gate DG2. While forming the first dummy gate DG1, the second dummy gate DG2, the first dummy cover pattern DC1, and the second dummy cover pattern DC2, the remaining portion of the pad oxide layer 30, except for the portion stacked with each of the first dummy gate DG1 and the second dummy gate DG2 along the vertical direction DR3, can be removed from the substrate 10.

[0074] Subsequently, a spacer material layer SM can be formed to cover the sidewalls of each of the first dummy gate DG1 and the second dummy gate DG2, the sidewalls and top surface of each of the first dummy cover pattern DC1 and the second dummy cover pattern DC2, the exposed sidewalls and top surface of the stacked structure 20, and the top surface of the field insulating layer 115. For example, the spacer material layer SM can be formed conformally. The spacer material layer SM may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0075] Reference Figure 10The first dummy gate DG1, the second dummy gate DG2, the first dummy cover pattern DC1, and the second dummy cover pattern DC2 can be used as masks to etch the stacked structure 20 (see Figure 8 To form a source / drain trench ST. The source / drain trench ST may be formed between the first dummy gate DG1 and the second dummy gate DG2 on the active pattern 11. For example, the source / drain trench ST may extend into the interior of the active pattern 11. For example, while the source / drain trench ST is being formed, a spacer material layer SM (see [reference]) formed on the upper surface of each of the first dummy cap pattern DC1 and the second dummy cap pattern DC2 may be etched. Figure 8 (and a portion of each of the first dummy cover pattern DC1 and the second dummy cover pattern DC2.)

[0076] A spacer material layer SM is retained on the sidewall of each of the first dummy cover pattern DC1, the second dummy cover pattern DC2, the first dummy gate DG1, and the second dummy gate DG2 (see...). Figure 8 The gate spacer 121 and the gate spacer 122 can be defined. For example, after the source / drain trench ST is formed, a second semiconductor layer 22 remains below the first dummy gate DG1 (see...). Figure 8 ) can be defined as the first plurality of nanosheets NW1. After the source / drain trench ST is formed, a second semiconductor layer 22 (see) remains below the second dummy gate DG2. Figure 8 ) can be defined as the second multiple nanosheets NW2.

[0077] Reference Figure 11 and Figure 12 It can be done in the source / drain trench ST (see Figure 10 The source / drain region SD is formed inside the active pattern 11. For example, the bottom surface of the source / drain region SD may contact the active pattern 11. Subsequently, the exposed upper surface of the field insulating layer 115, the sidewalls of each of the exposed first gate spacer 121 and second gate spacer 122, and the exposed first dummy cover pattern DC1 and second dummy cover pattern DC2 (see...) Figure 10 A first etch stop layer 150 is formed on the upper surface of each of the first dummy gates DG1 and the surface of the exposed source / drain regions SD. Subsequently, a first upper interlayer insulating layer 155 may be formed on the first etch stop layer 150. A planarization process may then be performed to expose the upper surfaces of each of the first dummy gates DG1 and the second dummy gates DG2. The source / drain regions SD may comprise a semiconductor material (e.g., silicon, silicon-germanium) and may be doped with impurities to conduct electricity.

[0078] Reference Figure 13 and Figure 14 The first dummy gate DG1 and the second dummy gate DG2 can be etched separately (see...). Figure 11 ), Pad oxide layer 30 (see) Figure 11 ) and the first semiconductor layer 21 (see Figure 11 The first dummy gate DG1 (see...) Figure 11 ), Pad oxide layer 30 (see) Figure 11 ) and the first semiconductor layer 21 (see Figure 11 The etched portion can be defined as the first gate trench GT1. Additionally, the second dummy gate DG2 (see...) Figure 11 ), Pad oxide layer 30 (see) Figure 11 ) and the first semiconductor layer 21 (see Figure 11 The etched portion can be defined as the second gate trench GT2.

[0079] Reference Figure 15 and Figure 16 Each can be in the first gate trench GT1 (see Figure 13 The first gate insulating layer 131, the first gate electrode G1, and the first cap pattern 141 are sequentially formed inside the gate. Furthermore, each of these can be formed in the second gate trench GT2 (see...). Figure 13 A second gate insulating layer 132, a second gate electrode G2, and a second cap pattern 142 are sequentially formed inside the structure. For example, the first gate electrode G1 may surround a first plurality of nanosheets NW1. The second gate electrode G2 may surround a second plurality of nanosheets NW2.

[0080] Reference Figures 17 to 19 A first gate contact CB1 can be formed in the vertical direction DR3, penetrating the first cover pattern 141 and connected to the first gate electrode G1. Additionally, a second gate contact CB2 can be formed in the vertical direction DR3, penetrating the second cover pattern 142 and connected to the second gate electrode G2. Subsequently, a second etch stop layer 180 and a second upper interlayer insulating layer 185 can be sequentially formed on the upper surface of each of the first upper interlayer insulating layer 155, the first gate contact CB1, and the second gate contact CB2. Subsequently, a first upper via V1 can be formed in the vertical direction DR3, penetrating the second etch stop layer 180 and the second upper interlayer insulating layer 185 and connected to the first gate contact CB1. Additionally, a second upper via V2 can be formed in the vertical direction DR3, penetrating the second etch stop layer 180 and the second upper interlayer insulating layer 185 and connected to the second gate contact CB2.

[0081] Reference Figures 20 to 22 Each substrate can be etched 10 (see...) Figures 17 to 19 ) and active pattern 11 (see Figures 17 to 19 ).

[0082] Reference Figures 23 to 25 It can be used in active pattern 11 (see Figures 17 to 19An insulating pattern 111 is formed on the etched portion. The insulating pattern 111 may extend in the first horizontal direction DR1. Additionally, a first lower interlayer insulating layer 110 may be formed on the bottom surface of each of the insulating pattern 111 and the field insulating layer 115. For example, the insulating pattern 111 and the first lower interlayer insulating layer 110 may be formed by the same manufacturing process. Subsequently, a second lower interlayer insulating layer 100 may be formed on the bottom surface of the first lower interlayer insulating layer 110.

[0083] Reference Figure 26 and Figure 27 A via trench 170T can be formed inside the second lower interlayer insulating layer 100. A contact trench 160T can be formed on the via trench 170T. The contact trench 160T can penetrate the first lower interlayer insulating layer 110 and the insulating pattern 111 in the vertical direction DR3 to extend into the interior of the source / drain region SD. For example, the via trench 170T and the contact trench 160T can be formed by the same manufacturing process.

[0084] Reference Figure 28 and Figure 29 A silicide layer SL can be formed on the surface of the source / drain region SD exposed by the contact trench 160T. Subsequently, a barrier material layer 161M can be formed on the surface of the contact trench 160T, the surface of the via trench 170T, and the bottom surface of the second lower interlayer insulating layer 100. For example, the barrier material layer 161M can be formed conformally. Next, a sacrificial layer 40 can be formed inside the contact trench 160T. For example, the bottom surface of the sacrificial layer 40 can be formed above the upper surface of the first lower interlayer insulating layer 110. For example, the sacrificial layer 40 may include a spin-on hard mask (SOH).

[0085] Reference Figure 30 and Figure 31 Etchable barrier material layer 161M (see) Figure 28 and Figure 29 The portion of the sacrificial layer 40 exposed on its bottom surface. In the barrier material layer 161M (see...) Figure 28 and Figure 29 After the portion described above is etched, the remaining barrier material layer 161M (see...) Figure 28 and Figure 29 This can be defined as barrier layer 161. Subsequently, sacrificial layer 40 can be etched (see...). Figure 28 and 29 ).

[0086] Reference Figure 32 and Figure 33A first filler layer 162 may be formed between portions of the barrier layer 161 within the contact trench 160T. For example, the first filler layer 162 may be formed by growing out of the barrier layer 161. For example, the first filler layer 162 may be formed of polycrystalline material. For example, the first filler layer 162 may be formed on the lowest surface of the barrier layer 161. That is, the bottom surface 162a of the first filler layer 162 may be formed below the lowest surface of the barrier layer 161.

[0087] Subsequently, a second filler layer 163 can be formed to fill the interior of the contact trench 160T on the bottom surface 162a of the first filler layer 162. For example, the second filler layer 163 can be formed by growing from the first filler layer 162. For example, the second filler layer 163 can be formed from a single grain. For example, at least a portion of the second filler layer 163 can be formed inside the via trench 170T. In other words, the lowermost surface 163a of the second filler layer 163 can be formed below the bottom surface of the first lower interlayer insulating layer 110. Through such a manufacturing process, a source / drain contact 160 including a barrier layer 161, a first filler layer 162, and a second filler layer 163 can be formed inside the contact trench 160T.

[0088] Reference Figures 2 to 5 A bottom via 170 can be formed inside the via trench 170T. For example, the bottom via 170 can be formed by growing it from the second filler layer 163. For example, the bottom via 170 can be formed from polycrystalline materials. Through such a manufacturing process, a product can be manufactured... Figures 2 to 5 The semiconductor device shown in the figure.

[0089] In the following text, reference will be made to Figure 34 This description describes a semiconductor device according to several other exemplary embodiments of the present disclosure. The description will emphasize... Figures 1 to 5 The differences in semiconductor devices are shown in the figure.

[0090] Figure 34 This is a cross-sectional view used to explain some other example embodiments of a semiconductor device according to this disclosure.

[0091] Reference Figure 34 In some other example embodiments of the semiconductor device according to this disclosure, the source / drain contact 260 may include a seam pattern 264.

[0092] For example, the stitch pattern 264 may be disposed inside the first filler layer 162. The stitch pattern 264 may be spaced apart from the barrier layer 161. The stitch pattern 264 may contact the upper surface of the second filler layer 163.

[0093] In the following text, reference will be made to Figure 35 The description describes a semiconductor device according to some other exemplary embodiments of the present disclosure. The description will emphasize... Figures 1 to 5 The differences in semiconductor devices are shown in the figure.

[0094] Figure 35 This is a cross-sectional view used to explain a semiconductor device according to several other exemplary embodiments of this disclosure.

[0095] Reference Figure 35 In some other example embodiments of the semiconductor device according to this disclosure, the lowermost surface of the barrier layer 161 may contact the upper surface of the second filler layer 163.

[0096] For example, the source / drain contact 360 may include a barrier layer 161, a first filler layer 362, and a second filler layer 163. For example, the first filler layer 362 is not disposed between the lowermost surface of the barrier layer 161 and the upper surface of the second filler layer 163. The first filler layer 362 may be spaced apart from the insulating pattern 111. In some example embodiments, the bottom surface 362a of the first filler layer 362 may be formed on the same plane as the lowermost surface of the barrier layer 161. In some other example embodiments, the bottom surface 362a of the first filler layer 362 may be formed below the lowermost surface of the barrier layer 161.

[0097] In the following text, reference will be made to Figure 36 The description describes a semiconductor device according to some other exemplary embodiments of the present disclosure. The description will emphasize... Figures 1 to 5 The differences in semiconductor devices are shown in the figure.

[0098] Figure 36 This is a cross-sectional view used to explain a semiconductor device according to several other exemplary embodiments of this disclosure.

[0099] Reference Figure 36 In a semiconductor device according to some other example embodiments of the present disclosure, the bottom surface 462a of the first fill layer 462 may be formed to protrude toward the second fill layer 163. For example, the source / drain contact 460 may include a barrier layer 161, the first fill layer 462, and the second fill layer 163.

[0100] In the following text, reference will be made to Figure 37 and Figure 38 This description describes a semiconductor device according to several other exemplary embodiments of the present disclosure. The description will focus on... Figures 1 to 5 The differences in semiconductor devices are shown in the figure.

[0101] Figure 37 and Figure 38 This is a cross-sectional view used to explain a semiconductor device according to some other example embodiments of this disclosure.

[0102] Reference Figure 37 and Figure 38In some other example embodiments of the semiconductor device according to this disclosure, at least a portion of the bottom via 570 may be disposed inside the contact trench 160T.

[0103] For example, inside the contact trench 160T, the sidewall of the bottom via 570 in the first horizontal direction DR1 may contact the first lower interlayer insulation layer 110. Additionally, inside the contact trench 160T, the sidewall of the bottom via 570 in the second horizontal direction DR2 may contact the first lower interlayer insulation layer 110. For example, the source / drain contact 560 may include a barrier layer 161, a first filler layer 162, and a second filler layer 563. For example, the lowermost surface 563a of the second filler layer 563 may be formed below the bottom surface of the first lower interlayer insulation layer 110.

[0104] In the following text, reference will be made to Figure 39 and Figure 40 This description describes a semiconductor device according to some other example embodiments of the present disclosure. The description will focus on... Figures 1 to 5 The differences in semiconductor devices are shown in the figure.

[0105] Figure 39 and Figure 40 This is a cross-sectional view used to explain some other example embodiments of a semiconductor device according to this disclosure.

[0106] Reference Figure 39 and Figure 40 In a semiconductor device according to some other example embodiments of the present disclosure, the lowermost surface 663a of the second filling layer 663 may be formed above the bottom surface of the first lower interlayer insulating layer 110.

[0107] For example, inside the contact trench 160T, the sidewall of the bottom via 670 in the first horizontal direction DR1 may contact the first lower interlayer insulation layer 110. Additionally, inside the contact trench 160T, the sidewall of the bottom via 670 in the second horizontal direction DR2 may contact the first lower interlayer insulation layer 110. For example, the source / drain contact 660 may include a barrier layer 161, a first filler layer 162, and a second filler layer 663.

[0108] In the following text, reference will be made to Figure 41 and Figure 42 This description describes a semiconductor device according to some other example embodiments of the present disclosure. The description will focus on... Figures 1 to 5 The differences in semiconductor devices are shown in the figure.

[0109] Figure 41 and Figure 42 This is a cross-sectional view used to explain a semiconductor device according to another example embodiment of the present disclosure.

[0110] Reference Figure 41 and Figure 42 In a semiconductor device according to some other example embodiments of the present disclosure, at least a portion of the second fill layer 763 may contact the bottom surface of the first interlayer insulating layer 110.

[0111] For example, the source / drain contact 760 may include a barrier layer 161, a first filler layer 162, and a second filler layer 763. For example, in the portion adjacent to the two sidewalls of the contact trench 160T in the first horizontal direction DR1, at least a portion of the second filler layer 763 may contact the bottom surface of the first lower interlayer insulating layer 110. Additionally, in the portion adjacent to the two sidewalls of the contact trench 160T in the second horizontal direction DR2, at least a portion of the second filler layer 763 may contact the bottom surface of the first lower interlayer insulating layer 110. The bottom surface of the second filler layer 763 may contact the bottom via 770. The lowermost surface 763a of the second filler layer 763 may be formed below the bottom surface of the first lower interlayer insulating layer 110.

[0112] While some exemplary embodiments according to this disclosure have been described above with reference to the accompanying drawings, it will be understood that this disclosure is not limited to the above embodiments and can be made in various different forms. Those skilled in the art will recognize that the inventive concept can be implemented in other specific forms without altering the technical concept or essential features of this disclosure. Therefore, it should be understood that the above embodiments are non-limiting examples in all respects and not limiting.

Claims

1. A semiconductor device, comprising: First interlayer insulation layer; An insulating pattern extends in a first horizontal direction on the upper surface of the first lower interlayer insulating layer; Multiple nanosheets are stacked vertically on an insulating pattern and spaced apart from each other. A gate electrode extends in a second horizontal direction on an insulating pattern, the gate electrode surrounding the plurality of nanosheets, the second horizontal direction being different from the first horizontal direction; The source / drain region, on one side of the gate electrode and on the insulating pattern, the source / drain region, the first lower interlayer insulating layer and the insulating pattern define a contact trench that penetrates the first lower interlayer insulating layer and the insulating pattern in a vertical direction, the contact trench extending into the interior of the source / drain region; as well as The source / drain contacts fill the interior of the contact trenches and are electrically connected to the source / drain regions. The source / drain contact includes a barrier layer, a first filler layer, and a second filler layer. The barrier layer extends along a portion of the upper sidewall and the upper surface of the contact trench. The first filler layer fills the space between portions of the barrier layer inside the contact trench. The second filler layer fills the interior of the contact trench below the bottom surface of the first filler layer. The sidewalls of the barrier layer in the first horizontal direction are in contact with the insulating pattern. The first filler layer is formed of polycrystalline grains and has a first average grain size in the first horizontal direction. The sidewalls of the second filler layer in the first horizontal direction contact each of the first lower interlayer insulation layer and the insulation pattern, and The second filling layer is formed by single crystal grains.

2. The semiconductor device according to claim 1, wherein, The outer sidewall of the barrier layer in the first horizontal direction that contacts the insulating pattern is aligned with the sidewall of the second filler layer in the first horizontal direction that contacts the insulating pattern.

3. The semiconductor device according to claim 1, further comprising: The second lower interlayer insulation layer is on the bottom surface of the first lower interlayer insulation layer; as well as The bottom via, located in a via trench defined within a second lower interlayer insulating layer, contacts the bottom surface of the second filler layer. The bottom via is formed of polycrystalline materials and has a second average grain size in a first horizontal direction. The second average grain size is at least 1.5 times larger than the first average grain size.

4. The semiconductor device according to claim 3, wherein, The first filler layer, the second filler layer, and the bottom via all consist of the same material.

5. The semiconductor device according to claim 3, wherein, A portion of the bottom via is inside the contact trench, and the sidewall of the bottom via inside the contact trench in the first horizontal direction contacts the first lower interlayer insulation layer.

6. The semiconductor device according to claim 1, wherein, The bottom surface of the barrier layer overlaps the top surface of the second filler layer in the vertical direction.

7. The semiconductor device according to claim 1, wherein, The uppermost surface of the first filler layer is higher than the bottom surface of the source / drain region.

8. The semiconductor device according to claim 1, wherein, The lowest surface of the barrier layer contacts the first filler layer, and The sidewall of the first filler layer on the lowest surface of the barrier layer in the first horizontal direction contacts the insulating pattern.

9. The semiconductor device according to claim 1, wherein, The lowest surface of the second filler layer is lower than the bottom surface of the first interlayer insulation layer.

10. The semiconductor device according to claim 1, wherein, The source / drain contacts also include a slit pattern within the first filler layer. The stitch pattern is separated from the barrier layer, and The stitch pattern contacts the upper surface of the second filler layer.

11. The semiconductor device according to claim 1, wherein, The bottom surface of the first filler layer protrudes towards the second filler layer.

12. The semiconductor device according to claim 1, further comprising: The silicide layer runs along the interface between the source / drain region and the barrier layer.

13. A semiconductor device, comprising, First interlayer insulation layer; An insulating pattern extends in a first horizontal direction on the upper surface of the first lower interlayer insulating layer; The gate electrode extends on an insulating pattern in a second horizontal direction, different from the first horizontal direction. The source / drain region, on one side of the gate electrode and on the insulating pattern, the source / drain region, the first lower interlayer insulating layer and the insulating pattern define a contact trench that penetrates the first lower interlayer insulating layer and the insulating pattern in a vertical direction, the contact trench extending into the interior of the source / drain region; Source / drain contacts fill the interior of the contact trench and are electrically connected to the source / drain regions; The second lower interlayer insulation layer is on the bottom surface of the first lower interlayer insulation layer; as well as The bottom via, located in a via trench defined within the second lower interlayer insulating layer, contacts the bottom surface of the source / drain contact. The bottom via is formed from polycrystalline materials. The source / drain contact includes a barrier layer, a first filler layer, and a second filler layer. The barrier layer extends along a portion of the upper sidewall and the upper surface of the contact trench. The first filler layer fills the space between portions of the barrier layer inside the contact trench. The second filler layer fills the interior of the contact trench below the bottom surface of the first filler layer. The sidewalls of the barrier layer in the first horizontal direction are in contact with the insulating pattern. The first filler layer is formed of polycrystalline grains and has a first average grain size in the first horizontal direction. The bottom surface of the second filler layer contacts the bottom via. The sidewalls of the second filler layer in the first horizontal direction contact each of the first lower interlayer insulation layer and the insulation pattern. The second filling layer is formed by single grains, and The second average grain size of the bottom via in the first horizontal direction is at least 1.5 times larger than the first average grain size.

14. The semiconductor device according to claim 13, wherein, The bottom surface of the second filler layer protrudes towards the bottom through-hole.

15. The semiconductor device according to claim 13, wherein, At least a portion of the upper surface of the bottom via is in contact with the bottom surface of the first lower interlayer insulation layer.

16. The semiconductor device according to claim 13, wherein, At least one of the first filler layer, the second filler layer, and the bottom via comprises different materials.

17. The semiconductor device according to claim 13, wherein, The bottom surface of the barrier layer is in contact with the top surface of the second filler layer.

18. The semiconductor device according to claim 13, wherein, The lowest surface of the second filler layer is formed to be higher than the bottom surface of the first interlayer insulation layer.

19. The semiconductor device according to claim 13, wherein, At least a portion of the second filler layer is in contact with the bottom surface of the first interlayer insulation layer.

20. A semiconductor device, comprising: First interlayer insulation layer; An insulating pattern extends in a first horizontal direction on the upper surface of the first lower interlayer insulating layer; Multiple nanosheets are stacked vertically on an insulating pattern and spaced apart from each other. A gate electrode extends on an insulating pattern in a second horizontal direction, which is different from the first horizontal direction, and the gate electrode surrounds the plurality of nanosheets; The source / drain region, on one side of the gate electrode and on the insulating pattern, the source / drain region, the first lower interlayer insulating layer and the insulating pattern define a contact trench that penetrates the first lower interlayer insulating layer and the insulating pattern in a vertical direction, the contact trench extending into the interior of the source / drain region; Source / drain contacts fill the interior of the contact trench and are electrically connected to the source / drain regions; The second lower interlayer insulation layer is disposed on the bottom surface of the first lower interlayer insulation layer; as well as The bottom via, located in a via trench defined within the second lower interlayer insulating layer, contacts the bottom surface of the source / drain contact. The bottom via is formed from polycrystalline materials. The source / drain contact includes a barrier layer, a first filler layer, and a second filler layer. The barrier layer extends along a portion of the upper sidewall and the upper surface of the contact trench. The first filler layer fills the space between portions of the barrier layer inside the contact trench. The second filler layer fills the interior of the contact trench below the bottom surface of the first filler layer. The sidewalls of the barrier layer in the first horizontal direction are in contact with the insulating pattern. The first filler layer is in contact with the lowest surface of the barrier layer. The first filler layer is formed of polycrystalline grains and has a first average grain size in the first horizontal direction. The bottom surface of the second filler layer contacts the bottom via. The bottom surface of the second filler layer is lower than the bottom surface of the first interlayer insulating layer. The sidewalls of the second filler layer in the first horizontal direction contact each of the first lower interlayer insulation layer and the insulation pattern, and The second filling layer is formed by single grains, and The second average grain size of the bottom via in the first horizontal direction is at least 1.5 times larger than the first average grain size.

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