High voltage semiconductor device with offset drain

Abstract

The invention relates to a high voltage semiconductor device with an offset drain. The semiconductor device, such as, for example, a gate-all-around field effect transistor (GAAFET) device, is suitable for operability under higher operating voltage conditions (e.g., 1.2 volts to 3.3 volts). The semiconductor device includes: a first channel formed in a first plane of the semiconductor device; a second channel formed in a second plane, different from the first plane, of the semiconductor device; the drain electrode is formed around the first channel; the grid electrode is formed around the second channel; and the source electrode is formed around the second channel.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor manufacturing technology. More specifically, this disclosure relates to a wider range of semiconductor device structures that can be used to provide operating voltages for implementations of gate-all-around field-effect transistor (GAAFET) devices and other similar devices. Background Technology

[0002] For example, the semiconductor device structures described herein can be used in various implementations of laterally diffused metal-oxide-semiconductor (LDMOS) for a wide range of high-power applications, such as power amplifiers, radio frequency (RF) amplifiers, and power transistors for radio and wireless communication systems. As demand for high-power applications grows, research and development efforts continue to advance semiconductor technology to meet foundry manufacturing capabilities and capacity, and to enhance the functionality of various electronic devices and circuits. Summary of the Invention

[0003] One embodiment of this disclosure provides a semiconductor device comprising: a first channel formed in a first plane of the semiconductor device; a second channel formed in a second plane of the semiconductor device different from the first plane; a drain formed around the first channel; a gate formed around the second channel; and a source formed around the second channel.

[0004] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes: a first channel formed in a first plane of the semiconductor device; a second channel formed in a second plane of the semiconductor device different from the first plane; a drain formed around the first channel; a first gate formed around the second channel; a first source formed around the second channel and adjacent to the first gate; a second gate formed around the second channel; and a second source formed around the second channel and adjacent to the second gate.

[0005] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate including a first well and a second well, the first well being doped with a first dopant and the second well being doped with a second dopant different from the first dopant; a first channel formed in a first plane of the semiconductor device; a second channel formed in a second plane of the semiconductor device different from the first plane; a drain formed around the first channel and disposed above the first well; a gate formed around the second channel; and a source formed around the second channel and disposed above the second well. Attached Figure Description

[0006] Figure 1 A top view illustrating components of a semiconductor device according to some aspects of this disclosure.

[0007] Figure 2 Showing some aspects of this disclosure Figure 1 The first cross section is taken from the first plane of the semiconductor device.

[0008] Figure 3 Showing some aspects of this disclosure Figure 1 The second cross section is taken from the second plane of the semiconductor device.

[0009] Figure 4 Showing some aspects of this disclosure Figure 1 The third cross section is taken from the third plane of the semiconductor device. Detailed Implementation

[0010] In the following description, numerous details are set forth for illustrative purposes to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that other aspects can be practiced without some of these details. This document describes various instances, and while various features are attributed to instances, it should be understood that features described for one instance may be combined with those for other instances. However, for the same reason, a single feature or multiple features of any described instance should not be considered essential to every instance, as such features may be omitted in other instances.

[0011] When an element is referred to herein as “connected” or “coupled” to another element, it should be understood that the element may be directly connected to the other element or have an intermediary element present between the elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, it should be understood that there is no intermediary element in the “direct” connection between the elements. However, the presence of a direct connection does not preclude the existence of other connections in which intermediary elements may be present.

[0012] When an element is referred to herein as being "placed" in a certain way relative to another element (e.g., placed on it, placed between it, placed below it, placed adjacent to it, or placed in some other relative manner), it should be understood that the element may be placed directly relative to the other element (e.g., placed directly on the other element) or has an intervening element present between the elements. Conversely, when an element is referred to as being "placed directly" relative to another element, it should be understood that in the "direct" instance, there is no intervening element. However, the existence of direct placement does not preclude other instances in which an intervening element may be present.

[0013] Similarly, when a component is referred to herein as a “layer,” it should be understood that a layer may be a single layer or contain multiple layers. For example, a conductive layer may include multiple different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include multiple dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it should be understood that the coupling or connecting layer may contain intermediary elements present between the coupling or connecting layers. Conversely, when a layer is referred to as being “directly” connected or coupled to another layer, it should be understood that there are no intermediary elements between the layers. However, the presence of a directly coupled or connecting layer does not preclude the existence of other connections where intermediary elements may be present.

[0014] Furthermore, the terms left, right, front, back, top, bottom, forward, backward, clockwise, and counterclockwise are used for interpretive purposes only and are not limited to any fixed direction or orientation. Rather, they are used only to indicate the relative position and / or orientation between the various parts of an object and / or component.

[0015] Furthermore, unless otherwise indicated, all figures used herein to express quantity, size, etc., should be understood to be modified by the term “about” in all instances. In this application, unless otherwise specifically stated, the use of the singular includes the plural, and the use of the terms “and” and “or” means “and / or”, unless otherwise indicated. Furthermore, the use of the terms “comprising” and “having”, as well as other forms (e.g., “includes,” “included,” “has,” “have,” and “had”), should be considered non-exclusive. Additionally, terms such as “element” or “component” cover both elements and components comprising one unit and elements and components comprising more than one unit, unless otherwise specifically stated.

[0016] While some features and aspects have been described with reference to examples, those skilled in the art will recognize that many modifications are possible. For example, the methods and processes described herein can be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. Furthermore, although the various methods and processes described herein may be described with reference to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any particular structural and / or functional architecture, but can instead be implemented in any suitable hardware configuration. Similarly, while some functions belong to one or more system components, unless the context otherwise indicates, according to several embodiments, this functionality may be distributed across a variety of other system components.

[0017] Furthermore, although the procedures of the methods and processes described herein are presented in a specific order for ease of description, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context otherwise indicates. Moreover, procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described with respect to a particular architecture and / or system may be organized in an alternative architecture and / or incorporated into other described systems. Therefore, although various instances having or lacking certain features are described for ease of description and to illustrate aspects of those embodiments, various components and / or features described herein with respect to particular instances may be replaced, added, and / or subtracted from other described embodiments unless the context otherwise indicates. Therefore, although several examples have been described above, it should be understood that this disclosure is intended to cover all modifications and equivalents within the scope of the following claims.

[0018] refer to Figure 1 The illustration shows a top view of components of an example semiconductor device 100 according to some aspects of this disclosure. The semiconductor device 100 can be implemented as various types of semiconductor devices, such as various different types and combinations of transistor structures. For example, the semiconductor device 100 may include a non-planar (three-dimensional) GAAFET device, such as a gate-all-around LDMOS device. Figure 1 As shown, semiconductor device 100 includes channels 112, 114, 116, and 118; wells 122, 123, and 125; gate 132; dummy gate 133; gate 134; source 142, 144, 146, and 148; drain 150 and 250; trench 162 and 164; dummy gate 174, dummy gate 175, and dummy gate 274. Channels 112, 114, 116, and 118 can be implemented in various suitable ways. For example, channels 112, 114, 116, and 118 can each be implemented using one or more nanosheets to form one or more GAAFET devices.

[0019] Nanosheets can be formed using silicon and / or other suitable conductive materials, and are typically rectangular structures, for example, ranging from 10 to 50 nanometers wide and 3 to 7 nanometers thick. Channels 112, 114, 116, and 118 can also be implemented using one or more conductive channel structures other than nanosheets. For example, channels 112, 114, 116, and 118 can be implemented using conductive fins (e.g., silicon fins for forming one or more FinFET devices), one or more conductive nanowires (e.g., cylindrical silicon structures), or other suitable channel types suitable for various semiconductor manufacturing processes. However, specifically, using nanosheets to implement channels 112, 114, 116, and 118 offers advantages, particularly for smaller node sizes (e.g., 3-nanometer processes, 2-nanometer processes, and below).

[0020] Semiconductor device 100 is typically located on substrate 210 (e.g., Figures 2 to 4 The substrate 210 is formed on the semiconductor device 100 (as shown in the diagram). The substrate 210 can be formed using silicon (e.g., crystalline silicon) and / or other suitable materials or combinations thereof. The substrate 210 can be implemented using various manufacturing techniques, such as silicon-on-insulator (SOI) structures, bulk semiconductor structures, alloy semiconductors, compound semiconductors, germanium, and / or various other suitable materials and combinations thereof. The substrate 210 typically provides a base for forming components of the semiconductor device 100 thereon. The semiconductor device 100 can be implemented using various types of circuits, including various types of integrated circuit (IC) chips.

[0021] Wells 122, 123, and 125 may be at least partially formed within the substrate 210. Wells 122, 123, and 125 may also be at least partially separated from the substrate 210, for example, formed at least partially within various types of oxide layers and / or other insulating / dielectric layers within the semiconductor device 100. Well 122 may be relatively lightly doped using a first dopant, while wells 123 and 125 may be relatively lightly doped using a second dopant different from the first dopant. For an NLDMOS embodiment of the semiconductor device 100, the first dopant may be an n-type dopant (and therefore well 122 may be an n-type well), and the second dopant may be a p-type dopant (and therefore well 124 may be a p-type well). Conversely, for a PLDMOS embodiment of the semiconductor device 100, the first dopant may be a p-type dopant (and therefore well 122 may be a p-type well), and the second dopant may be an n-type dopant (and therefore well 124 may be an n-type well). Various suitable n-type dopants can be used to form wells 122, 123, and / or well 125, such as those containing arsenic, phosphorus, and / or other similar n-type dopants. Various suitable p-type dopants can also be used to form wells 122, 123, and / or well 125, such as those containing boron and / or other similar p-type dopants.

[0022] Gate 132 may be formed around channel 114 and channel 116. In a GAAFET embodiment, gate 132 may be formed around channel 114 and channel 116 such that gate 132 surrounds channel 114 and channel 116 on all sides. Depending on the desired application, gate 132 may be formed using a polysilicon material (e.g., for providing a high-k gate) and / or another suitable material or combination of materials (e.g., a metal gate). The voltage applied to gate 132 can typically control the operation and conductivity of semiconductor device 100 by controlling the operation and conductivity of channels 114 and 116. Various types of spacers may be formed at least partially around gate 132 to electrically isolate gate 132 and prevent charge leakage. For example, spacers may comprise materials having a high dielectric constant, such as silicon nitride, silicon oxide, and / or other suitable materials and combinations thereof. Furthermore, for example, materials (e.g., silicon nitride, aluminum oxide, silicon dioxide, and / or other suitable materials and combinations thereof) may be used to form one or more gate oxide layers between the gate 132 and the channel 114 and between the gate 132 and the channel 116. The gate 132 may be formed around the channel 114 and the channel 116 in various ways. For example, the gate 132 may completely surround the channel 114 and the channel 116, or the gate 132 may partially surround the channel 114 and the channel 116 (e.g., gaps may exist between the channel 114 and the gate 132 and / or between the channel 116 and the gate 132).

[0023] Similarly, gate 134 may be formed around channel 114 and around channel 116. In a GAAFET embodiment, gate 134 may be formed around channel 114 and around channel 116 such that gate 134 surrounds channel 114 and around channel 116 on all sides. Depending on the desired application, gate 134 may be formed using a polysilicon material (e.g., for providing a high-k gate) and / or another suitable material or combination of materials (e.g., a metal gate). The voltage applied to gate 134 can typically control the operation and conductivity of semiconductor device 100 by controlling the operation and conductivity of channels 114 and 116. Various types of spacers may be formed at least partially around gate 134 to electrically isolate gate 134 and prevent charge leakage. For example, spacers may comprise materials with a high dielectric constant, such as silicon nitride, silicon oxide, and / or other suitable materials and combinations thereof. Furthermore, for example, materials (e.g., silicon nitride, aluminum oxide, silicon dioxide, and / or other suitable materials and combinations thereof) may be used to form one or more gate oxide layers between the gate 134 and the channel 114 and between the gate 134 and the channel 116. The gate 134 may be formed around the channel 114 and the channel 116 in various ways. For example, the gate 134 may completely surround the channel 114 and the channel 116, or the gate 134 may partially surround the channel 114 and the channel 116 (e.g., gaps may exist between the channel 114 and the gate 134 and / or between the channel 116 and the gate 134).

[0024] Sources 142, 144, 146, and 148 may be at least partially implemented as epitaxial layers formed around channels 114 and 116, respectively. For example, source 142 may be at least partially implemented using a relatively heavily doped epitaxial layer formed around channel 114 and adjacent to gate 132, source 144 may be at least partially implemented using a relatively heavily doped epitaxial layer formed around channel 114 and adjacent to gate 134, source 146 may be at least partially implemented using a relatively heavily doped epitaxial layer formed around channel 116 and adjacent to gate 132, and source 148 may be at least partially implemented using a relatively heavily doped epitaxial layer formed around channel 116 and adjacent to gate 134. Although sources 142, 144, 146 and 148 may typically be formed adjacent to gates 132 and 134, respectively, such proximity may not be direct, as various spacer layers (e.g., silicon nitride, silicon oxide, etc.) may be disposed between sources 142, 144, 146, 148, gates 132 and 134, respectively.

[0025] Sources 142, 144, 146, and 148 can be formed around channels 114 and 116 in various ways. For example, sources 142, 144, 146, and 148 can completely surround channels 114 and 116, or sources 142, 144, 146, and 148 can partially surround channels 114 and 116 (e.g., gaps may exist therebetween). Furthermore, the semiconductor device 100 may include various types of spacer layers (e.g., silicon nitride, silicon oxide, etc.) disposed between sources 142, 144, 146, 148, and channels 114 and 116. The epitaxial materials that can be used to form source 142, source 144, source 146 and source 148 may include a variety of suitable materials, such as, for example, silicon, gallium arsenide and / or other suitable epitaxial materials and combinations thereof.

[0026] The epitaxial materials used to form sources 142, 144, 146, and 148 may be highly doped using a suitable n-type dopant (e.g., for an NLDMOS embodiment of semiconductor device 100) or a suitable p-type dopant (e.g., for a PLDMOS embodiment of semiconductor device 100). Wells 122, 123, and 125 may be doped according to a first doping concentration, and the epitaxial materials used to form sources 142, 144, 146, and 148 may be doped according to a second doping concentration, which may be greater than the first doping concentration. For example, sources 142, 144, 146, and 148 may be formed according to a convex source / drain (RSD) structure having advantageous electrical properties for preventing electrostatic discharge.

[0027] Drains 150 and 250 may be implemented at least partially using epitaxial layers formed around channels 112 and 118, respectively. For example, drain 150 may be implemented at least partially using a relatively heavily doped epitaxial layer formed around channel 112, and drain 250 may be implemented at least partially using a relatively heavily doped epitaxial layer formed around channel 118. Drains 150 and 250 may be formed around channels 112 and 118 in various ways. For example, drains 150 and 250 may completely surround channels 112 and 118, respectively, or drains 150 and 250 may partially surround channels 112 and 118, respectively (e.g., gaps may exist therebetween). Furthermore, the semiconductor device 100 may include various types of spacer layers (e.g., silicon nitride, silicon oxide, etc.) disposed between drains 150 and 250, and between channels 112 and 118.

[0028] The epitaxial materials used to form drains 150 and 250 may comprise a variety of suitable materials, such as, for example, silicon, gallium arsenide, and / or other suitable epitaxial materials and combinations thereof. The epitaxial materials used to form drains 150 and 250 may be heavily doped using suitable n-type dopant (e.g., for an NLDMOS embodiment of semiconductor device 100) or suitable p-type dopant (e.g., for a PLDMOS embodiment of semiconductor device 100). Wells 122, 123, and 125 may be doped according to a first doping concentration, and the epitaxial materials used to form drains 150 and 250 may be doped according to a third doping concentration, which may then be greater than the first doping concentration. For example, drains 150 and 250 may again be formed according to a convex source / drain (RSD) structure having advantageous electrical properties for preventing electrostatic discharge.

[0029] In such Figure 1 The top view of the semiconductor device 100 shown in the image reveals three separate planes: plane 200, plane 300, and plane 400. From... Figure 1 From the perspective shown, planes 200 and 300 are horizontal planes, and plane 400 is a vertical plane. As shown, channel 112 is formed in plane 200 (e.g., the first plane), while channel 114 is formed in plane 300 (e.g., the second plane). Therefore, since drain 150 can be formed around channel 112 (but not around channel 114), and source 142, gate 132, gate 134, and source 144 can be formed around channel 114 (but not around channel 112), drain 150 can be formed in a plane separate from source 142, gate 132, gate 134, and source 144, such that drain 150 is offset from source 142, gate 132, gate 134, and source 144. This particular structure of semiconductor device 100 may be particularly advantageous for high-voltage applications. In some alternative structures where the source, gate, and drain are all formed in a common plane, operating voltages exceeding approximately 0.75 volts can lead to performance degradation and, in some cases, component damage or failure (e.g., the gate may fail at higher operating voltages). However, using a separate plane for the drain 150 in semiconductor device 100 allows for operating voltages in the range of 1.2 volts to 3.3 volts.

[0030] like Figure 1As described, during operation of an embodiment of semiconductor device 100, current can flow from drain 150 to source 142 (as controlled by gate 132) and from drain 150 to source 144 (as controlled by gate 134). Similarly, current can flow from drain 250 to source 146 (as controlled by gate 132) and from drain 250 to source 148 (as controlled by gate 134). By forming drain 150 in plane 200 instead of plane 300, the area of ​​drain 150 can be significantly increased, and therefore (i) the resistance of drain 150 can be reduced, and (ii) the on-resistance (R) of semiconductor device 100 can be improved. on (iii) can improve the drive current of semiconductor device 100. Therefore, when a higher operating voltage (e.g., 1.2 V to 3.3 V) is applied to drain 150, semiconductor device 100 can operate without degradation (e.g., when current flows from drain 150 to gate 132 and gate 134, degradation of gate 132 and gate 134 may not occur). Furthermore, semiconductor device 100 can be implemented using GAAFET technology with a very small node size (3 nm and below) to maintain a compact footprint while providing operability at high voltages. Additionally, the structure of semiconductor device 100 can be implemented without significant changes to the manufacturing process, as it does not require any additional processing steps or mask layers.

[0031] Figure 1Some example dimensions associated with semiconductor device 100 are also shown. The length L1, as shown, typically represents the length of gate 132 as measured along plane 300 (e.g., from the end of gate 132 closest to source 142 to the end of gate 132 closest to trench 162). In some examples, length L1 may be between 65 nanometers and 310 nanometers. Next, the distance D1, as shown, typically represents the distance between dummy gate 175 and gate 134 formed around channel 112 (e.g., the distance between the end of dummy gate 175 closest to gate 134 and the end of gate 134 closest to dummy gate 175). In some examples, distance D1 may be between 15 nanometers and 105 nanometers. Finally, the width W1, as shown, typically represents the width of drain 150 as measured in a direction perpendicular to plane 200 (e.g., from the end of drain 150 furthest from gate 134 to the end of drain 150 closest to gate 134). In some instances, the width W1 can be between 20 nanometers and 55 nanometers. These specific dimensions can provide advantages in facilitating proper operation of the semiconductor device 100 under higher operating voltage conditions. For example, these specific dimensions can provide advantages by allowing higher voltages (e.g., 1.2 volts to 3.3 volts) to be applied to the drain 150 without damaging any components of the semiconductor device 100 or causing various types of performance degradation of the semiconductor device 100.

[0032] refer to Figure 2 According to some aspects of this disclosure, a cross-section of the semiconductor device 100 taken along plane 200 is shown. Therefore, Figure 2 The cross-section shown in the image illustrates the drain electrode 150 in more detail. From Figure 2 The cross-section shown in the figure reveals the substrate 210, as well as the channel 112, dummy gate 174, dummy gate 175, and well 122. Figure 2 The cross-section also shows various additional components of the semiconductor device 100, including epitaxial layers 151, 152, 154, 155, and 156; dummy gates 171, 172, 173, 176, and 177; interconnects 181, 182, 183, 184, 185, and 186; and isolation structures 221 and 222. Figure 2 As shown in the example cross-section, channel 112 is implemented using three separate nanosheets.

[0033] One or more of epitaxial layers 151, 152, 153, 154, 155, and / or 156 may cooperatively form the gate 150. Epitaxial layers 151, 152, 153, 154, 155, and 156 may be formed from various suitable materials, for example, silicon, gallium arsenide, and / or other suitable epitaxial materials and combinations thereof. Epitaxial layers 151, 152, 153, 154, 155, and 156 may be heavily doped using n-type or p-type dopant. Well 122 may be doped according to a first doping concentration, and epitaxial layers 151, 152, 153, 154, 155, and 156 may be doped according to a third doping concentration, which may then be greater than the first doping concentration. Since drain 150 may be formed around channel 112 formed in plane 200, rather than around channel 114 formed in plane 300, drain 150 may be implemented using one or more of epitaxial layers 151, 152, 153, 154, 155, and / or 156, and therefore the area of ​​drain 150 may be increased relative to some alternative structures. In particular, drain 150 may be disposed above well 122, rather than above well 123 or well 125.

[0034] Dummy gates 171, 172, 173, 174, 175, 176, and 177 may be formed around channel 112 such that, in a GAAFET embodiment, dummy gates 171, 172, 173, 174, 175, 176, and 177 surround channel 112 on all sides. Dummy gates 171, 172, 173, 174, 175, 176, and 177 may be formed using polysilicon and / or another suitable material. Various types of spacers may be formed at least partially around dummy gates 171, 172, 173, 174, 175, 176, and 177. Furthermore, one or more gate oxide layers may be formed between dummy gates 171, 172, 173, 174, 175, 176, and 177 and the channel 112.

[0035] Dummy gates 171, 172, 173, 174, 175, 176, and 177 can be formed around the channel 112 in various ways. For example, dummy gates 171, 172, 173, 174, 175, 176, and 177 can completely surround the channel 112, or dummy gates 171, 172, 173, 174, 175, 176, and 177 can partially surround the channel 112 (for example, gaps can exist between the channel 112 and the dummy gates 171, 172, 173, 174, 175, 176, and 177). Dummy gates 171, 172, 173, 174, 175, 176, and 177 are "dummy gates" in the sense that they do not operate as active gates within the semiconductor device 100 (unlike gates 132 and 134). Figure 2 As shown, the semiconductor device 100 may not include interconnects connected to dummy gates 171, dummy gate 172, dummy gate 173, dummy gate 174, dummy gate 175, dummy gate 176 and dummy gate 177.

[0036] Interconnectors 181, 182, 183, 184, 185, and 186 may be implemented using any suitable structural embodiment for forming electrical connections between components of semiconductor device 100 and / or components of circuitry (e.g., ICs) containing semiconductor device 100. For example, interconnectors 181, 182, 183, 184, 185, and 186 may be implemented as conductive copper vias and other possible types of interconnect structures. Interconnector 181 may be used to form electrical connections between epitaxial layer 151 and one or more additional components of semiconductor device 100 and / or components of circuitry containing semiconductor device 100. Interconnector 182 may be used to form electrical connections between epitaxial layer 152 and one or more additional components of semiconductor device 100 and / or components of circuitry containing semiconductor device 100.

[0037] Interconnect 183 can be used to form an electrical connection between epitaxial layer 153 and one or more additional components of semiconductor device 100 and / or components containing circuitry of semiconductor device 100. Interconnect 184 can be used to form an electrical connection between epitaxial layer 154 and one or more additional components of semiconductor device 100 and / or components containing circuitry of semiconductor device 100. Interconnect 185 can be used to form an electrical connection between epitaxial layer 155 and one or more additional components of semiconductor device 100 and / or components containing circuitry of semiconductor device 100. Finally, interconnect 186 can be used to form an electrical connection between epitaxial layer 156 and one or more additional components of semiconductor device 100 and / or components containing circuitry of semiconductor device 100. The structure of drain 250 may be similar to or the same as that shown in the figure. Figure 2 The structure of drain 150 shown in the figure.

[0038] For example, isolation structures 221 and 222 can be implemented as shallow trench isolation (STI) structures. Therefore, isolation structures 221 and 222 can be formed as a result of etching trenches in the semiconductor device 100. For example, after etching a first trench, isolation structure 221 can be formed by depositing dielectric material at least partially within the first trench. After etching a second trench, isolation structure 222 can be formed by depositing dielectric material at least partially within the second trench. The dielectric material used to form isolation structures 221 and 222 can be, for example, silicon oxide, silicon nitride, and / or other suitable materials and combinations thereof. Isolation structures 221 and 222 generally prevent current leakage between different components of the semiconductor device 100.

[0039] refer to Figure 3 The following diagram illustrates a cross-section of a semiconductor device 100 taken along plane 300, according to some aspects of this disclosure. Figure 3 The cross-section shown in the figure shows source 142, gate 132, dummy gate 133, gate 134, source 144, trench 162, trench 164, substrate 210, well 122, well 123 and well 125. Figure 3 The cross-section also shows various additional components of the semiconductor device 100, including dummy gate 131, dummy gate 135, isolation structure 223, isolation structure 224, isolation structure 225, interconnect 191, interconnect 192, interconnect 193, and interconnect 194. In particular, such as Figure 3 As shown, source 142 is positioned above well 123, but not above well 122; source 144 is positioned above well 125, but not above well 122; gate 132 is positioned above both well 122 and well 123; and gate 134 is positioned above both well 122 and well 125. Figure 3As shown in the example cross-section, channel 114 is implemented using three separate nanosheets.

[0040] Dummy gates 131 and 135 may be formed around channel 114 such that, in a GAAFET embodiment, dummy gates 131 and 135 may surround channel 114 on all sides. Various types of spacers may be formed at least partially around dummy gates 131 and 135. Furthermore, one or more gate oxide layers may be formed between dummy gates 131 and 135 and channel 114. Dummy gates 131 and 135 may be formed around channel 114 in various ways. For example, dummy gates 131 and 135 may completely surround channel 114, or dummy gates 131 and 135 may partially surround channel 114 (e.g., gaps may exist between channel 114 and dummy gates 131 and 135).

[0041] Dummy gate 133 may be similar to dummy gate 131 and dummy gate 135, except that dummy gate 133 may be formed between trench 162 and trench 164, rather than around channel 114. However, in some embodiments, dummy gate 133 may also be formed around channel 114 in a manner similar to dummy gate 131 and dummy gate 135 (e.g., trench 162 and trench 164 may be etched after dummy gate 133 is formed around channel 114). As shown, trench 162 may be disposed between gate 132 and dummy gate 133, and trench 164 may be disposed between dummy gate 133 and gate 134. Dummy gate 131, dummy gate 133, and dummy gate 135 are "dummy gates" in the sense that they do not operate as active gates within semiconductor device 100 (unlike gate 132 and gate 134). Figure 3 As shown, the semiconductor device 100 may not include interconnects connected to dummy gates 131, dummy gates 133, and dummy gates 135. Dummy gates 131, dummy gates 133, and dummy gates 135 may be formed using polysilicon and / or another suitable material.

[0042] Interconnectors 191, 192, 193, and 194 may be any suitable structural implementation for forming electrical connections between components of semiconductor device 100 and / or components of circuitry (e.g., ICs) containing semiconductor device 100. For example, interconnectors 191, 192, 193, and 194 may be conductive copper vias and other possible types of interconnect structures. Interconnector 191 may be used to form an electrical connection between source 142 and one or more additional components of semiconductor device 100 and / or components of circuitry containing semiconductor device 100. Interconnector 192 may be used to form an electrical connection between gate 132 and one or more additional components of semiconductor device 100 and / or components of circuitry containing semiconductor device 100. Interconnector 193 may be used to form an electrical connection between gate 134 and one or more additional components of semiconductor device 100 and / or components of circuitry containing semiconductor device 100. Ultimately, interconnect 194 can be used to form an electrical connection between source 144 and one or more additional components of semiconductor device 100 and / or components containing circuitry of semiconductor device 100.

[0043] For example, isolation structures 223, 224, and 225 can be implemented as STI structures. Therefore, isolation structures 223, 224, and 225 can be formed as a result of etching trenches in the semiconductor device 100. For example, after etching a third trench, isolation structure 223 can be formed by depositing dielectric material at least partially within the third trench. After etching a fourth trench, isolation structure 224 can be formed by depositing dielectric material at least partially within the fourth trench. After etching a fifth trench, isolation structure 225 can be formed by depositing dielectric material at least partially within the fifth trench. The dielectric material used to form isolation structures 223, 224, and 225 can be, for example, silicon oxide, silicon nitride, and / or other suitable materials and combinations thereof. Isolation structures 223, 224, and 225 generally prevent current leakage between different components of the semiconductor device 100.

[0044] refer to Figure 4 The following diagram illustrates a cross-section of a semiconductor device 100 taken along plane 400, according to some aspects of this disclosure. Figure 4 The cross-section shown in the figure shows channels 112, 114, 118, dummy gate 174, dummy gate 133, dummy gate 274, well 122 and substrate 210. Figure 4The cross-section also shows various additional components of the semiconductor device 100, including isolation structures 226, 227, 228, and 229. Isolation structure 227 is typically disposed in the well 122 and between the drain 150 and gates 132 and 134, and isolation structure 228 is typically disposed in the well 122 and between the drain 250 and gates 132 and 134. For example... Figure 4 As shown in the example cross-section, channels 112, 114 and 118 are each implemented using three separate nanosheets.

[0045] Furthermore, as shown, during operation of an embodiment of the semiconductor device 100, current flows from the dummy gate 174 below the isolation structure 227 (e.g., via... Figure 1 The drain 150 shown in the diagram flows to the dummy gate 133 (and if controlled by gate 132, flows to the source 142, and if controlled by gate 134, flows to the source 144, as shown in the diagram). Figure 1 (As shown in the diagram). Furthermore, as shown, during operation of the semiconductor device 100, current flows from the dummy gate 274 below the isolation structure 228 (e.g., via...). Figure 1 The drain 250 shown in the diagram flows to the dummy gate 133 (and if controlled by gate 132, flows to the source 146, and if controlled by gate 134, flows to the source 148, as shown in the diagram). Figure 1 (As shown in the diagram). Compared to some alternative structures with shorter current flow paths, this extended path, where current flows from drain 150 and drain 250 to source 142, source 144, source 146, and source 148 respectively, helps to provide extended operability of the semiconductor device 100 under higher operating voltage conditions.

[0046] For example, isolation structures 226, 227, 228, and 229 can be further implemented as STI structures. Therefore, isolation structures 226, 227, 228, and 229 can be formed as a result of etching trenches in the semiconductor device 100. For example, after etching the sixth trench, isolation structure 226 can be formed by depositing dielectric material at least partially within the sixth trench. After etching the seventh trench, isolation structure 227 can be formed by depositing dielectric material at least partially within the seventh trench. After etching the eighth trench, isolation structure 228 can be formed by depositing dielectric material at least partially within the eighth trench. After etching the ninth trench, isolation structure 229 can be formed by depositing dielectric material at least partially within the ninth trench. Furthermore, the dielectric material used to form isolation structures 226, 227, 228, and 229 can be, for example, silicon oxide, silicon nitride, and / or other suitable materials and combinations thereof. Isolation structures 226, 227, 228 and 229 typically prevent current leakage between different components of the semiconductor device 100.

Claims

1. A semiconductor device comprising: A first channel is formed in a first plane of the semiconductor device; A second channel is formed in a second plane of the semiconductor device that is different from the first plane; The drain electrode is formed around the first channel; A gate, which is formed around the second channel; and The source pole is formed around the second channel.

2. The semiconductor device of claim 1, comprising a dummy gate formed around the first channel, wherein the distance between the dummy gate formed around the first channel and the gate formed around the second channel is between 15 and 105 nanometers.

3. The semiconductor device of claim 1, wherein the drain is disposed above an n-type well and the source is disposed above a p-type well.

4. The semiconductor device of claim 3, wherein the gate is disposed above the n-type well and the p-type well.

5. The semiconductor device according to claim 1, comprising: A second gate is formed around the second channel; and The second source electrode is formed around the second channel; During operation of the semiconductor device, current flows from the drain to the source and from the drain to the second source.

6. The semiconductor device of claim 5, further comprising a dummy gate disposed between the gate and the second gate.

7. The semiconductor device of claim 6, comprising: A first trench is disposed between the gate and the dummy gate; and The second trench is disposed between the second gate and the dummy gate.

8. The semiconductor device of claim 1, wherein the length of the gate, measured along the second plane, is between 65 nanometers and 310 nanometers.

9. The semiconductor device of claim 1, wherein the width of the drain, measured in a direction perpendicular to the first plane, is between 20 nanometers and 55 nanometers.

10. A semiconductor device comprising: A first channel is formed in a first plane of the semiconductor device; A second channel is formed in a second plane of the semiconductor device that is different from the first plane; The drain electrode is formed around the first channel; A first gate is formed around the second channel; A first source electrode is formed around the second channel and adjacent to the first gate electrode; A second gate electrode is formed around the second channel; and A second source is formed around the second channel and adjacent to the second gate.

11. The semiconductor device according to claim 10, wherein, During operation of the semiconductor device, current flows from the drain to the first source and from the drain to the second source.

12. The semiconductor device of claim 10, comprising: A dummy gate is disposed between the first gate and the second gate; A first trench is disposed between the first gate and the dummy gate; and The second trench is disposed between the second gate and the dummy gate.

13. The semiconductor device according to claim 10, wherein: The drain is positioned above the n-type well; The first source electrode is positioned above the p-type well; and The first gate is positioned above the n-type well and the p-type well.

14. The semiconductor device of claim 10, wherein the drain comprises: A first epitaxial layer is disposed between a first dummy gate and a second dummy gate; and The second epitaxial layer is disposed between the second dummy gate and the third dummy gate.

15. The semiconductor device of claim 14, wherein the distance between the second dummy gate and the second gate is between 15 and 105 nanometers.

16. A semiconductor device comprising: The substrate includes a first well and a second well, wherein the first well is doped with a first dopant and the second well is doped with a second dopant different from the first dopant; A first channel is formed in a first plane of the semiconductor device; A second channel is formed in a second plane of the semiconductor device that is different from the first plane; A drain electrode is formed around the first channel and positioned above the first well; A gate is formed around the second channel; and The source electrode is formed around the second channel and positioned above the second well.

17. The semiconductor device of claim 16, comprising a dummy gate formed around the first channel, wherein the distance between the dummy gate formed around the first channel and the gate formed around the second channel is between 15 and 105 nanometers.

18. The semiconductor device of claim 16, wherein: The first dopant includes a p-type dopant; and The second dopant includes an n-type dopant.

19. The semiconductor device according to claim 16, wherein: The length of the gate, measured along the second plane, is between 65 nanometers and 310 nanometers; and The width of the drain electrode, measured in a direction perpendicular to the first plane, is between 20 nanometers and 55 nanometers.

20. The semiconductor device of claim 16, wherein the drain comprises: A first epitaxial layer is disposed between a first dummy gate and a second dummy gate; and The second epitaxial layer is disposed between the second dummy gate and the third dummy gate.

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