Preparation method of semiconductor device and semiconductor device

Abstract

The embodiment of the invention relates to a preparation method of a semiconductor device and the semiconductor device, and the method comprises the steps: providing a semiconductor structure which comprises a substrate and a to-be-etched layer on the substrate; forming a hard mask layer on the layer to be etched; patterning processing is carried out to form an opening which exposes a part of the surface of the layer to be etched; a first deposition step is executed, and a first material layer is formed and comprises a first part covering the upper surface of the hard mask layer, a second part covering the inner side wall of the opening and a third part covering the surface, exposed through the opening, of the to-be-etched layer; executing a first etching step so that the first part and the third part are removed and the second part is still reserved; a second etching step is executed, so that the opening extends in the direction of the substrate in the layer to be etched, the second part is removed, and the second etching step is stopped before the second part is completely removed; and repeating the first deposition step, the first etching step and the second etching step in sequence until the extension depth of the opening in the to-be-etched layer reaches the expected depth.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] As semiconductor technology nodes advance, the feature size of integrated circuits continues to shrink. This leads to an increase in the aspect ratio of the etched openings during device fabrication. How to etch openings with high aspect ratios and good morphology has become one of the key challenges in semiconductor manufacturing.

[0003] In traditional dry etching processes, etching is affected by several factors. First, as the aperture depth increases, it becomes more difficult for the reactants to reach the bottom of the aperture (known as the "deep silicon effect"), reducing the etching rate and causing the aperture sidewalls to tilt. Second, etching byproducts accumulate within the aperture (known as the "micro-loading effect"), hindering etching and leading to morphological defects such as sidewall depressions, bottom rounding, or distortion. Third, the structure being etched can also be affected. For example, when the structure undergoes changes in composition or doping concentration along its thickness, the reactants are influenced by the doped regions, making lateral etching more likely and resulting in uneven sidewall morphology.

[0004] Therefore, how to better control the morphology of the opening sidewall has become an urgent problem to be solved in this field. Summary of the Invention

[0005] In view of this, the present application provides a method for fabricating a semiconductor device to solve at least one problem existing in the background art.

[0006] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising: A semiconductor structure is provided, the semiconductor structure including a substrate and a layer to be etched on the substrate; A hard mask layer is formed on the layer to be etched; The hard mask layer is patterned to form openings that expose a portion of the surface of the layer to be etched; A first deposition step is performed to form a first material layer, the first material layer comprising a first portion covering the upper surface of the hard mask layer, a second portion covering the inner sidewall of the opening, and a third portion covering the surface of the layer to be etched exposed through the opening; A first etching step is performed to remove the first portion and the third portion, while the second portion remains. A second etching step is performed to extend the opening toward the substrate within the layer to be etched, and the second portion is gradually removed. The second etching step is stopped before the second portion is completely removed. Repeat the first deposition step, the first etching step, and the second etching step in sequence until the opening extends to the desired depth within the etched layer.

[0007] In conjunction with the first aspect of this application, in an optional embodiment, the first deposition step, the first etching step, and the second etching step are performed within the same device, and deposition or etching is achieved by controlling the operating modes of the source radio frequency and bias radio frequency of the device.

[0008] In conjunction with the first aspect of this application, in an alternative embodiment, during the first deposition step, the source radio frequency of the device is controlled to operate in continuous wave mode, while the bias radio frequency remains off.

[0009] In conjunction with the first aspect of this application, in an alternative embodiment, during the first etching step, the source radio frequency of the device is controlled to operate in pulse mode, and the bias radio frequency operates in continuous wave mode.

[0010] In conjunction with the first aspect of this application, in an optional embodiment, in the second etching step, the source radio frequency and the bias radio frequency of the device are controlled to operate in pulse mode, the on-time window of the bias radio frequency is located within the off-time window of the source radio frequency, and the on-time window of the source radio frequency is located within the off-time window of the bias radio frequency.

[0011] In conjunction with the first aspect of this application, in an optional embodiment, the first deposition step to the second etching step satisfies at least one of the following: (1) In the first deposition step, the reaction sources introduced into the reaction chamber of the device include: CH4 and N2; (2) The first material layer formed in the first deposition step comprises a layer of carbon, hydrogen, and nitrogen compounds; (3) The thickness of the first material layer ranges from 2 nm to 5 nm; (4) In the first deposition step, the process conditions include: pressure in the range of 10mTorr to 20mTorr, source RF power in the range of 500W to 600W, and duration in the range of 5s to 10s; (5) In the first etching step and the second etching step, the reaction sources introduced into the reaction chamber of the device include: CF4, SF6, O2 and N2; (6) In the first etching step, the process conditions include: pressure in the range of 3mTorr to 5mTorr, source RF power in the range of 500W to 600W, and bias RF voltage in the range of 100V to 200V; (7) In the second etching step, the process conditions include: pressure in the range of 3mTorr to 5mTorr, source RF power in the range of 500W to 600W, and bias RF voltage in the range of 100V to 200V; (8) The process conditions for the first etching step and the second etching step include: pressure in the range of 3mTorr to 5mTorr, source RF power in the range of 500W to 600W, bias RF voltage in the range of 100V to 200V; and the total duration of the first etching step and the second etching step in the range of 5s to 10s. (9) The process conditions in the first etching step are the same as those in the second etching step.

[0012] In conjunction with the first aspect of this application, in an alternative embodiment, the material of the hard mask layer comprises nitrogen-rich silicon oxynitride.

[0013] In conjunction with the first aspect of this application, in an optional embodiment, the hard mask layer is patterned, including: An advanced patterned thin film layer, a dielectric anti-reflective coating, a bottom anti-reflective coating, and a photoresist layer are sequentially formed on the hard mask layer; The photoresist layer is patterned. Perform the first mask etching step to transfer the pattern on the photoresist layer to the bottom anti-reflective coating and the dielectric anti-reflective coating; A second mask etching step is performed to transfer the patterns on the bottom anti-reflective coating and the dielectric anti-reflective coating to the advanced patterned thin film layer; The third mask etching step is performed to transfer the pattern on the advanced patterned thin film layer to the hard mask layer.

[0014] In conjunction with the first aspect of this application, in an optional embodiment, the semiconductor structure further includes an intermediate material layer located between the substrate and the layer to be etched; after sequentially repeating the first deposition step, the first etching step, and the second etching step, the method further includes: Perform a second deposition step to form a second material layer that conformally covers the intermediate material layer, the layer to be etched, and the hard mask layer; A third etching step is performed to etch the second material layer and the layer to be etched until the second material layer is removed. The etching rate of the third etching step on the layer to be etched is greater than the etching rate of the second etching step on the layer to be etched.

[0015] In conjunction with the first aspect of this application, in an alternative embodiment, the thickness of the second material layer is less than the thickness of the first material layer.

[0016] In conjunction with the first aspect of this application, in an optional embodiment, the second deposition step, the third etching step, and the first deposition step, the first etching step, and the second etching step are all performed in the same apparatus.

[0017] In conjunction with the first aspect of this application, in an alternative embodiment, the second deposition step to the third etching step satisfies at least one of the following: (1) In the second deposition step, the reaction sources introduced into the reaction chamber of the device include: CH4 and N2; (2) The second material layer formed in the second deposition step comprises a layer of carbon, hydrogen, and nitrogen compounds; (3) The pressure, source RF power, and bias RF voltage of the second deposition step are equal to the pressure, source RF power, and bias RF voltage of the first deposition step, respectively; (4) The duration of the second deposition step is less than the duration of the first deposition step; (5) In the second deposition step, the process conditions include: pressure in the range of 10mTorr to 20mTorr, source RF power in the range of 500W to 600W, and duration in the range of 5s to 8s; (6) In the third etching step, the reaction source introduced into the reaction chamber of the device includes: HBr, O2 and He; (7) The pressure of the third etching step is greater than the pressure of the second etching step; (8) The source RF power of the third etching step is less than the source RF power of the second etching step, and the bias RF voltage of the third etching step is greater than the bias RF voltage of the second etching step. (9) The duration of the third etching step is greater than the duration of the second etching step; (10) In the third etching step, the process conditions include: pressure in the range of 40mTorr to 50mTorr, source RF power in the range of 300W to 400W, bias RF voltage in the range of 150V to 250V, and duration in the range of 10s to 20s.

[0018] Secondly, embodiments of this application provide a semiconductor device prepared using the semiconductor device preparation method described in the first aspect.

[0019] The semiconductor device fabrication method and semiconductor device provided in this application, through the synergistic effect of deposition and etching, use the first material layer deposited on the inner sidewall of the opening as a protective layer against lateral etching, enhance anisotropic etching, and ensure the verticality and uniformity of the sidewall morphology. By decomposing one etching cycle into multiple shallow etching cycles, the "deep silicon effect" and "micro-load effect" are fundamentally alleviated, allowing reactants to reach effectively and byproducts to be discharged in a timely manner in each cycle, maintaining a stable and high etching rate throughout the entire etching depth range. In each cycle, the first material layer is deposited before shallow etching to avoid the formation of an excessively thick first material layer in one etching, which would lead to a reduction in the opening size. This comprehensively improves the problems of sidewall tilt and bottom defects. Therefore, this application can better control the morphology of the opening sidewall through a cyclic "deposition + shallow etching" etching process.

[0020] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 A schematic flowchart illustrating the fabrication method of the semiconductor device provided in the embodiments of this application; Figure 2 This is a schematic cross-sectional view of the gate structure formed by etching in related technologies. Figures 3 to 13 A schematic cross-sectional view of the semiconductor device during the fabrication process provided in the embodiments of this application; Figure 14 This is a cross-sectional schematic diagram of the gate structure formed by etching in an embodiment of this application. Detailed Implementation

[0022] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0023] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0024] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0025] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0026] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0029] This application provides a method for fabricating a semiconductor device. Please refer to the embodiments provided. Figure 1 The preparation method includes: Step S1: Provide a semiconductor structure, which includes a substrate and a layer to be etched on the substrate; Step S2: Form a hard mask layer on the layer to be etched; Step S3: Pattern the hard mask layer to form openings that expose a portion of the surface of the layer to be etched; Step S4: Perform the first deposition step to form a first material layer, the first material layer including a first portion covering the upper surface of the hard mask layer, a second portion covering the inner sidewall of the opening, and a third portion covering the surface of the layer to be etched exposed through the opening; Step S5: Perform the first etching step to remove the first and third parts, while the second part remains; Step S6: Perform a second etching step to extend the opening into the substrate within the layer to be etched, and gradually remove the second portion. The second etching step stops before the second portion is completely removed. Step S7: Repeat the first deposition step, the first etching step, and the second etching step in sequence until the opening extends to the expected depth within the etched layer.

[0030] Understandably, through the synergistic effect of deposition and etching, the first material layer deposited on the inner sidewall of the opening serves as a protective layer against lateral etching, thereby controlling anisotropic etching and ensuring the verticality and uniformity of the sidewall morphology. By decomposing a single etching process into multiple shallow etching cycles, the "deep silicon effect" and "micro-loading effect" are fundamentally alleviated, ensuring that reactants effectively reach the site and byproducts are promptly removed in each cycle, maintaining a stable and high etching rate throughout the entire etching depth range. Furthermore, in each cycle, the first material layer is deposited before shallow etching, avoiding the need for an excessively thick first material layer in a single etching process, which would lead to a reduction in the opening size. This comprehensively improves the problems of sidewall tilt and bottom defects. Therefore, this application, through a cyclic "deposition + shallow etching" etching process, can better control the morphology of the opening sidewall.

[0031] First, please refer to Figure 1 Step S1 is performed to provide a semiconductor structure, which includes a substrate 100 and an etchable layer 300 located on the substrate 100.

[0032] The substrate 100 may be a silicon substrate, or it may include Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other compound semiconductors, or it may include a multilayer structure composed of these semiconductors, etc. Alternatively, the substrate 100 may be silicon on insulator (SOI), silicon on insulator stacked (SSOI), silicon on insulator stacked (S-SiGeOI), silicon on insulator germanium (SiGeOI), and germanium on insulator (GeOI), etc. Those skilled in the art can choose according to their needs, and this application does not limit it.

[0033] In this embodiment, substrate 100 is specifically, for example, a silicon substrate.

[0034] The layer to be etched 300 can be any material layer in the semiconductor structure that needs to be formed into a specific structure through a patterning process; this application does not limit this.

[0035] In this embodiment, the material of the layer 300 to be etched is, for example, polysilicon. It is understood that polysilicon has wide applications in semiconductor devices, such as serving as the gate of a transistor. Due to the functional requirements of the device, polysilicon is often implanted with different types and concentrations of impurities during semiconductor device fabrication, thereby forming doped regions with different conductivity types and doping concentrations along its thickness direction. Because of differences in their chemical bonding states and lattice defect densities, the doped regions exhibit different chemical reactivity towards the reactants, leading to uneven etching rates even under uniform etching process conditions. This results in irregular steps, depressions, or uneven roughness on the final formed opening sidewalls.

[0036] Please refer to Figure 2In related technologies, the semiconductor device is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and the layer to be etched, 300, is a polysilicon layer. The remaining polysilicon layer after etching serves as the gate structure of the MOSFET. Because a doped region is formed on the top of the polysilicon layer, the etching rate at the top is faster, resulting in a larger top opening size and thus a shrinkage of the top size of the gate structure. For example... Figure 2 As shown in Figure (a), when the top of the polycrystalline silicon layer has an N-type doped region, the top dimension of the gate structure is 42.6 nm, and the bottom dimension is 50.8 nm. It can be seen that the size difference between the N-type doped region and the undoped region is 8.2 nm. With a height of 76.5 nm, the angle between the sidewall and the bottom is 87.2°, clearly indicating that the sidewall is tilted. Figure 2 As shown in Figure (b), when the top of the polysilicon layer has a P-type doped region, the top dimension of the gate structure is 46.0 nm, and the bottom dimension is 49.8 nm. The size difference between the P-type doped and undoped regions is 3.8 nm. With a height of 76.2 nm, the angle between the sidewall and the bottom is 86.6°, indicating a tilted sidewall. Comparing Figures (a) and (b), it can be found that the size difference between the N-type doped and undoped regions is greater than that between the P-type doped and undoped regions. The polysilicon loss at the N-type doped region is greater than that at the P-type doped region. This demonstrates that different doping types do indeed lead to different etching rates, resulting in different sidewall morphologies.

[0037] Next, step S2 is performed to form a hard mask layer 400 on the layer to be etched 300. Understandably, the semiconductor device fabrication method provided in this application involves repeatedly performing a first deposition step, a first etching step, and a second etching step. The entire process involves multiple, alternating deposition and etching environments. If only photoresist or other adhesive masks are used, they will be rapidly consumed and deformed in the process environment, leading to uncontrollable changes in the mask's critical dimensions. Ultimately, these mask morphological defects will be transferred to the underlying layer to be etched 300, causing problems such as increased opening top size and deteriorated sidewall contours.

[0038] In some embodiments, the hard mask layer 400 is made of silicon oxynitride. Understandably, silicon oxynitride has a higher hardness than photoresist and other adhesive materials, resulting in lower wear during etching and effectively preventing enlargement of critical aperture dimensions or topographic distortion due to mask wear. Further, the hard mask layer 400 is made of nitrogen-rich silicon oxynitride. Its nitrogen-rich nature gives it extremely high chemical inertness and physical stability in the face of subsequent etching cycles, further reducing the thickness loss of the hard mask layer 400. Moreover, after the etching of the layer 300 to be etched is completed, it can be removed using a wet etching process, making removal easier.

[0039] In this embodiment, the material of the hard mask layer 400 is specifically nitrogen-rich silicon oxynitride.

[0040] Next, please refer to Figure 7 In step S3, the hard mask layer 400 is patterned to form an opening 301 that exposes a portion of the surface of the layer to be etched 300.

[0041] In some embodiments, please refer to Figures 3 to 7 Patterning the hard mask layer 400 may include: An advanced patterned thin film layer 500, a dielectric anti-reflective coating 610, a bottom anti-reflective coating 620, and a photoresist layer 700 are sequentially formed on the hard mask layer 400. The photoresist layer 700 is patterned. Perform the first mask etching step to transfer the pattern on the photoresist 700 to the bottom anti-reflective coating 620 and dielectric anti-reflective coating 610; Perform a second mask etching step to transfer the patterns on the bottom anti-reflective coating 620 and dielectric anti-reflective coating 610 onto the advanced patterned thin film layer 500; The third mask etching step is performed to transfer the pattern on the advanced patterned thin film layer 500 to the hard mask layer 400.

[0042] In this field, photoresist is typically used to achieve patterning through photolithography-etching processes. However, it is understandable that as semiconductor technology nodes enter the sub-40nm range, and even the sub-55nm range, the thickness and morphology of the photoresist limit the requirements for pattern transfer, making a single photoresist layer insufficient. Specifically, during photolithography exposure, light reflects and interferes at the interfaces of different materials, causing distortion of the pattern in the photoresist layer 700. The bottom anti-reflective coating 620 (BARC) effectively absorbs interfering light, while the dielectric anti-reflective coating 610 (DARC) further optimizes optical properties, jointly ensuring that the photoresist forms a pattern with steep contours and precise dimensions after exposure. The mechanical strength and etching resistance of the photoresist layer 700 and the anti-reflective coating are relatively weak. If they are directly used as a mask to etch the hard mask layer 400, they will be rapidly consumed and deformed during the etching process, failing to completely protect the initial pattern until the etching is complete. Therefore, an advanced patterning film (APF) layer 500 is introduced. It is etched using two anti-reflective coatings as a composite mask, and then its etching resistance serves as a mask to withstand the physicochemical environment during the etching of the hard mask layer 400. The three-layer stacked structure consisting of APF, DARC, and BARC ensures sufficient mask thickness and hardness during the patterning of the hard mask layer 400, resulting in accurate size and morphology of the transferred pattern.

[0043] Understandably, the hard mask layer 400 has a higher hardness than the advanced patterning thin film layer 500. Since the advanced patterning thin film layer 500 suffers greater wear in the etching environment of the layer to be etched 300, using the hard mask layer 400 as the mask for etching the layer to be etched 300, rather than using the advanced patterning thin film layer 500, is more conducive to ensuring the accuracy of the opening size and morphology.

[0044] In a specific example, the photoresist layer 700 has a thickness of 1050 angstroms, the bottom anti-reflective coating 620 has a thickness of 300 angstroms, the dielectric anti-reflective coating 610 has a thickness of 300 angstroms, and the advanced patterning thin film layer 500 has a thickness of 1000 angstroms; the hard mask layer 400 has a thickness ranging from 600 angstroms to 1000 angstroms. Understandably, in the first mask etching step, the material layer serving as the mask is consumed simultaneously, and the same applies in the second and third mask etching steps. This setting of the thicknesses of these material layers not only ensures that the material layer serving as the mask is always present during the etching process of the current material layer (the material layer being etched), thus ensuring the accuracy of pattern transfer, but also facilitates the realization that the material layer serving as the mask is essentially consumed after the current material layer is etched, thereby avoiding the need for additional processes to remove the material layer serving as the mask. In this embodiment, the thickness of the hard mask layer 400 is 800 angstroms.

[0045] It should be noted that in the semiconductor field, etching processes include wet etching and dry etching. Dry etching includes ion milling, vapor phase etching, and plasma etching. In this embodiment, the etching process used in each etching step is plasma-enhanced chemical vapor deposition (hereinafter referred to as "plasma etching"). In plasma etching, plasma specifically refers to free radicals, ions, and electrons generated by ionized gas. Free radicals act as reactants to achieve chemical etching, while ions, accelerated by an electric field, bombard the metal and act as materials for physical sputtering, thus enhancing etching.

[0046] In some examples, the first mask etching step, the second mask etching step, and the third mask etching step are performed within the same apparatus. This apparatus is, for example, a plasma etching apparatus.

[0047] In the first mask etching step, the reaction sources introduced into the reaction chamber of the equipment may include CF4 and CHF3. Understandably, both CF4 and CHF3 can decompose to generate fluorine radicals, which serve as the primary etching agent. Furthermore, CHF3 also generates difluoromethyl radicals, which can form a passivation layer on the opening sidewall, effectively blocking the lateral etching of the sidewall by fluorine radicals, thereby ensuring the anisotropy of the etching and obtaining a vertical sidewall morphology. The gas flow rate of CF4 ranges from 30 SCCM to 60 SCCM, and the gas flow rate of CHF3 also ranges from 30 SCCM to 60 SCCM.

[0048] In the first mask etching step, the process conditions may include: pressure in the range of 3mTorr to 5mTorr, source RF power in the range of 500W to 600W, bias RF voltage in the range of 100V to 200V, and duration in the range of 40s to 50s.

[0049] Pressure, specifically referring to the gas pressure within the reaction chamber of the device, is a key factor affecting plasma characteristics and particle motion behavior. Maintaining the pressure at a relatively low level of 3-5 mTorr results in a longer mean free path for electrons, making it easier for them to extract energy from the electric field and efficiently ionize gas molecules, thus maintaining a plasma with moderate density and high stability. Simultaneously, the mean free paths of free radicals and ions also increase accordingly, making their movement within the chamber more directional and their diffusion capabilities better.

[0050] Source RF and bias RF are two independently controlled RF energy inputs in plasma etching processes. Source RF, typically applied through coupling devices on the sidewalls or top of the reaction chamber, is primarily used to ionize the introduced reactive gas, generating and maintaining a high-density plasma. The magnitude of the source RF power directly determines the overall concentration of free radicals and ions in the plasma. Setting the source RF power in the range of 500W to 600W ensures sufficient free radicals are efficiently generated, providing ample reactants for etching and passivation, thereby achieving a stable etching rate.

[0051] The bias radio frequency (RF) is typically applied to the electrode carrying the structure to be etched. Its main function is to create a DC self-bias voltage between the plasma and the structure, thereby vertically accelerating positively charged ions to bombard the surface of the structure. The magnitude of the bias RF voltage directly controls the ion energy. Setting the bias RF voltage within the range of 100V to 200V provides sufficient kinetic energy for the ions to bombard the structure, achieving physical sputtering. Simultaneously, it can also sputter away byproducts generated during chemical etching.

[0052] In the second mask etching step, the reaction sources introduced into the reaction chamber of the equipment can include HBr, Cl2, and O2. Understandably, the bromine radicals generated by the decomposition of HBr can react with the carbon elements constituting the advanced patterned thin film (usually materials such as amorphous carbon) to achieve etching; the chlorine radicals generated by the decomposition of Cl2 participate in etching, increasing the overall etching rate; the oxygen atoms generated by the decomposition of O2 can react with carbon to generate gaseous CO and CO2, contributing to etching, and can also form a passivation layer with carbon, bromine, and chlorine atoms, effectively blocking lateral etching. The gas flow rate of HBr ranges from 60 SCCM to 100 SCCM, the gas flow rate of Cl2 ranges from 20 SCCM to 50 SCCM, and the gas flow rate of O2 ranges from 60 SCCM to 100 SCCM. Therefore, a high etching rate can be maintained while ensuring steep sidewalls.

[0053] In the second mask etching step, the process conditions may include: pressure in the range of 3 mTorr to 5 mTorr, source RF power in the range of 400 W to 500 W, bias RF voltage in the range of 250 V to 350 V, and duration in the range of 40 s to 50 s. Understandably, in actual fabrication, those skilled in the art can adjust the process conditions according to the material and thickness of the structure to be etched.

[0054] In the third mask etching step, the reaction sources introduced into the reaction chamber of the equipment may include CF4, CHF3, and He. Understandably, both CF4 and CHF3 can decompose to generate fluorine radicals, which serve as the primary etching agents. Furthermore, CHF3 also generates difluoromethyl radicals, which can form a passivation layer on the sidewalls, effectively blocking the lateral etching of the sidewalls by fluorine radicals, thereby ensuring the anisotropy of the etching and obtaining a vertical sidewall morphology. He helps stabilize the plasma, improve process uniformity, and promote polymer removal. The gas flow rate of CF4 ranges from 60 SCCM to 100 SCCM, the gas flow rate of CHF3 ranges from 20 SCCM to 40 SCCM, and the gas flow rate of He ranges from 100 SCCM to 200 SCCM.

[0055] In the first mask etching step, the process conditions may include: pressure in the range of 3mTorr to 5mTorr, source RF power in the range of 500W to 600W, bias RF voltage in the range of 100V to 200V, and duration in the range of 50s to 60s.

[0056] In some embodiments, please refer to Figure 6 After performing the third mask etching process, an advanced patterned thin film layer 500 of a certain thickness remains on the hard mask layer 400; the fabrication method may also include removing the advanced patterned thin film layer 500. Since the hard mask layer 400 is the mask subsequently used to etch the layer 300 to be etched, in order to ensure that the hard mask layer 400 is penetrated, the thickness of the advanced patterned thin film layer 500 can be set to be greater than the thickness consumed in the third mask etching step. In a specific example, in the step of removing the advanced patterned thin film layer 500, the reaction source introduced into the reaction chamber of the device may include O2. O2 can react with carbon atoms in the advanced patterned thin film layer 500 to achieve etching. Furthermore, some polymers are also generated in the third mask etching step, and O2 can also react with the polymers to form highly volatile products, thereby achieving polymer removal.

[0057] After the hard mask is patterned, the etching process for the layer 300 to be etched begins.

[0058] Please refer to Figures 8 to 10First, step S4 is executed to perform a first deposition step, forming a first material layer 800. The first material layer 800 includes a first portion 810 covering the upper surface of the hard mask layer 400, a second portion 820 covering the inner sidewall of the opening 301, and a third portion 830 covering the surface of the layer 300 to be etched exposed through the opening 301. Then, step S5 is executed to perform a first etching step, so that the first portion 810 and the third portion 830 are removed, while the second portion 820 remains. Next, step S6 is executed to perform a second etching step, so that the opening 301 extends into the substrate 100 within the layer 300 to be etched, and the second portion 820 is gradually removed. The second etching step stops before the second portion 820 is completely removed. Thus, a combination of deposition and etching is completed. Through the synergistic effect of deposition and etching, the first material layer 800 deposited on the inner sidewall of the opening 301 serves as a protective layer against lateral etching. Etching is stopped before the first material layer 800 is completely removed, thereby achieving precise control over anisotropic etching and ensuring the verticality and uniformity of the sidewall morphology.

[0059] In some embodiments, the first deposition step, the first etching step, and the second etching step are performed within the same device, and deposition or etching is achieved by controlling the operating modes of the device's source radio frequency and bias radio frequency. Understandably, deposition processes are typically performed in deposition equipment, and etching processes are performed in etching equipment, requiring the semiconductor structure to be transferred between different devices. This embodiment designs the first deposition step, the first etching step, and the second etching step to be performed within the same device, with all steps completed continuously within the reaction chamber of the same device. This eliminates the cumbersome and time-consuming steps of transferring, queuing, and vacuuming between different devices, shortening processing time, reducing equipment footprint, avoiding the contamination risk from exposed semiconductor structures, and improving process reliability.

[0060] In this case, the operating modes of the source RF and bias RF of the device are controlled to flexibly adjust deposition or etching. The deposition process in the first deposition step is, for example, plasma deposition, and the etching processes in the first and second etching steps are, for example, plasma etching. In plasma deposition, the source RF is turned on, responsible for ionizing the reaction source and generating free radicals and ions, with the free radicals acting as reactants to form the material layer. The bias RF is turned off, and there is no DC electric field to accelerate the ions. The ions lose their ability to bombard the surface directionally, and the free radicals can then diffuse and migrate to uniformly cover all exposed surfaces, forming a material layer. In plasma etching, the source RF is turned on, separating free radicals and ions, with the free radicals reacting chemically with the material to achieve etching. The bias RF is then turned on, creating a DC electric field to accelerate the ions and bombard the surface, enhancing etching.

[0061] In one example, during the first deposition step, the source radio frequency (RF) of the control device operates in continuous wave mode, while the bias RF remains off. Setting the source RF to continuous wave mode provides a continuous, stable, and uninterrupted energy supply to the plasma, generating and maintaining a high-density and spatially uniform plasma, thereby ensuring a constant reactant supply rate. The continuous energy input ensures that the adsorption of reactants on all surfaces is consistent with the surface chemical reaction rate, which is beneficial for depositing high-quality films with uniform thickness.

[0062] Optionally, the thickness of the first material layer 800 ranges from 2 nm to 5 nm. Understandably, if the thickness of the first material layer 800 is too large, it will encroach on the size of the opening 301, resulting in inaccurate pattern transfer; if the first material layer 800 is too thin, it will be difficult to retain a sufficiently thick second portion 820 in the subsequent first etching step. Therefore, controlling the thickness of the first material layer 800 within this range can better achieve the desired effect.

[0063] In some embodiments, the first material layer 800 formed in the first deposition step comprises a layer of carbon, hydrogen, and nitrogen compounds.

[0064] In the first deposition step, the reaction sources introduced into the reaction chamber of the device may include CH4 and N2. CH4 is ionized to generate free radicals and ions such as methyl radicals, methylene radicals, and hydrocarbon radicals. N2 is activated in the high-energy environment of the plasma to generate nitrogen atoms. These products react and adsorb onto the upper surface of the hard mask layer 400, the inner wall of the opening 301, and the surface of the layer to be etched 300 exposed through the opening 301, forming hydrocarbon compounds. The gas flow rate of CH4 ranges from 100 SCCM to 200 SCCM, and the gas flow rate of N2 ranges from 100 SCCM to 200 SCCM.

[0065] In the first deposition step, the process conditions may include: a pressure in the range of 10 mTorr to 20 mTorr, a source RF power in the range of 500 W to 600 W, and a duration in the range of 5 s to 10 s. The 10 mTorr to 20 mTorr pressure range constitutes a low to medium vacuum environment, with a moderate mean free path for electrons. This ensures efficient excitation and maintenance of the plasma by the source RF, while also giving the free radicals strong directionality and good diffusion ability, resulting in good coverage and uniformity of the first material layer 800. A source RF power in the range of 500 W to 600 W can effectively electrolyze the reaction source, generating a sufficient amount of free radicals.

[0066] In one example, during the first etching step, the source radio frequency (RF) of the control device operates in pulse mode, and the bias RF operates in continuous wave mode. Understandably, when the source RF is turned on, the plasma is excited, generating free radicals and ions. Under the influence of the bias RF, the ions move vertically, preferentially bombarding the first portion 810 and the third portion 830 of the first material layer 800. After ion scattering, the second portion 820 is also bombarded. However, in pulse mode, the on-time of the source RF is divided into multiple on-time windows, separated by off-time windows. A shorter on-time window results in less ion scattering and less bombardment of the second portion 820. This significantly enhances the chemical reaction between the first portion 810 and the third portion 830 and the free radicals through ion-enhanced etching. Thus, through pulse modulation, the first portion 810 and the third portion 830 of the first material layer 800 are subjected to ion-enhanced etching, achieving efficient and rapid removal while maximizing the retention of the second portion 820 covering the inner wall of the opening 301. Meanwhile, setting the bias radio frequency to continuous wave mode ensures a continuous and stable ion bombardment energy throughout the etching process.

[0067] Furthermore, the source radio frequency of the control device operates in a periodic pulse mode.

[0068] In the first etching step, the reaction source introduced into the reaction chamber of the device may include CF4, SF6, O2, and N2. CF4 and SF6 serve as the main etching gases, providing a high concentration of fluorine radicals to etch the first material layer 800. O2 not only consumes byproducts but also participates in the formation of a passivation layer, helping to protect the sidewalls. N2 is used to enhance sidewall passivation and strengthen anisotropic etching.

[0069] In the first etching step, the process conditions may include: a pressure in the range of 3 mTorr to 5 mTorr, a source RF power in the range of 500 W to 600 W, and a bias RF voltage in the range of 100 V to 200 V. The lower operating pressure of 3 mTorr to 5 mTorr aims to reduce the mean free path of the ions, which decreases the probability of collisional scattering of ions accelerated by the bias RF before reaching the surface, thus ensuring highly directional ion bombardment, which is beneficial for selectively removing the first portion 810 and the third portion 830 of the first material layer 800. Applying a source RF power of 500 W to 600 W ensures efficient ionization of the reactive gas. The applied bias RF voltage of 100 V to 200 V creates a suitable DC self-bias on the surface of the first material layer 800, sufficient to accelerate the ions to achieve effective bombardment energy.

[0070] In some examples, during the second etching step, both the source RF and bias RF of the control device operate in pulse mode. The on-time window of the bias RF falls within the off-time window of the source RF, and vice versa. When the bias RF is off and the source RF is on, the reactive gas is ionized, generating free radicals and ions. However, the ions cannot be accelerated, and the physical sputtering effect is almost zero. At this stage, the process exhibits an isotropic etching trend. Free radicals etch all exposed surfaces, allowing for gentle chemical cleaning of any polymer residues that may remain after anisotropic etching, effectively mitigating the micro-load effect. When the source RF is off and the bias RF is on, no new free radicals and ions are generated, and chemical etching is suppressed. However, the ions remaining in the chamber are accelerated and bombard the surface vertically, exhibiting highly anisotropic etching. This is the main stage driving the increase in the depth of opening 301, ensuring the steepness of the sidewalls of opening 301. These two stages alternate in a cycle, forming a closed loop of "physical tunneling - chemical cleaning," which not only achieves vertical etching but also avoids polymer buildup at the bottom, resulting in a better morphology for the opening 301.

[0071] Furthermore, both the source RF and bias RF of the control device operate in a periodic pulse mode.

[0072] In one specific example, the pulses of the source radio frequency and the pulses of the bias radio frequency are synchronous pulses, and the two have a 180° phase offset.

[0073] In the second etching step, the reaction source introduced into the reaction chamber of the device may include CF4, SF6, O2, and N2. CF4 and SF6 serve as the main etching gases, enabling simultaneous etching of the first material layer 800 and the layer 300 to be etched.

[0074] In the second etching step, the process conditions may include: a pressure in the range of 3 mTorr to 5 mTorr, a source RF power in the range of 500W to 600W, and a bias RF voltage in the range of 100V to 200V. It should be noted that the specific process conditions for the second etching step are described above and will not be repeated here.

[0075] Specifically, the process conditions for both the first and second etching steps include: pressure in the range of 3mTorr to 5mTorr, source RF power in the range of 500W to 600W, and bias RF voltage in the range of 100V to 200V; the total duration of the first and second etching steps is in the range of 5s to 10s.

[0076] In some embodiments, the process conditions in the first etching step are the same as those in the second etching step. The reaction source introduced in the first etching step is the same as that introduced in the second etching step. The first and second etching steps can be considered as two stages in the same etching process, in which the introduced reaction source and process conditions remain unchanged. In some examples, while the introduced reaction source and process conditions remain unchanged, the operating modes of the source RF and bias RF in the first and second etching steps are controlled.

[0077] It should be noted that during the second etching process, the hard mask layer 400 will also suffer damage, specifically manifested as sharp corner loss at the tip of the opening 301. Figure 10 The illustration schematically shows the situation where no loss has occurred, and those skilled in the art can understand the morphology of the corner loss here.

[0078] Next, step S7 is executed, repeating the first deposition step, the first etching step, and the second etching step in sequence until the opening 301 reaches the expected depth within the etchable layer 300. By decomposing one etching cycle into multiple shallow etching cycles, the "deep silicon effect" and "micro-loading effect" are fundamentally alleviated. This ensures that reactants can effectively reach the target area and byproducts are promptly removed in each cycle, maintaining a stable and high etching rate throughout the entire etching depth range. Furthermore, a first material layer 800 is deposited before each shallow etching, avoiding the need for an excessively thick first material layer 800 in a single etching cycle, which would reduce the size of the opening 301. This comprehensively improves the problems of sidewall tilt and bottom defects.

[0079] It should be noted that, in actual preparation, those skilled in the art can control the number of cycles based on the expected depth of the opening 301, and this application does not limit this. In this embodiment, the number of cycles ranges from 5 to 8.

[0080] like Figure 10 As shown, after the first cycle is completed, the opening 301 extends into the layer 300 to be etched. At this time, the inner sidewall of the opening 301 is composed of the sidewall of the hard mask layer 400 and the sidewall of the layer 300 to be etched. Figures 8 to 10 The first deposition step, the first etching step, and the second etching step in the first cycle are shown only schematically.

[0081] Please refer to Figure 11The semiconductor structure also includes an intermediate material layer 200 located between the substrate 100 and the layer to be etched 300; after sequentially repeating the first deposition step, the first etching step, and the second etching step, the method further includes: performing the second deposition step to form a second material layer 900 conformally covering the intermediate material layer 200, the layer to be etched 300, and the hard mask layer 400; performing the third etching step to etch the second material layer 900 and the layer to be etched 300 until the second material layer 900 is removed, wherein the etching rate of the layer to be etched in the third etching step is greater than the etching rate of the layer to be etched in the second etching step. After the first and second etching steps, there may still be polymer residues in the opening 301, or some of the etchable layer 300 remaining at the bottom. By setting a third etching step, these can be effectively removed. Moreover, the etching rate of the etchable layer 300 in the third etching step is greater than that in the second etching step, which can achieve more thorough and faster etching. Before etching, a second material layer 900 is formed through a second deposition step as a protective layer to resist lateral etching and ensure that the sidewalls of the opening 301 are steep.

[0082] In a specific example, the etching rate of the third etching step on the layer 300 to be etched is greater than the etching rate of the third etching step on the intermediate material layer 200. This avoids damage to the intermediate material layer 200.

[0083] In this embodiment, the material of the intermediate material layer 200 is, for example, an oxide material.

[0084] In some embodiments, the second deposition step, the third etching step, and the first deposition step, the first etching step, and the second etching step are all performed within the same device. These steps can all be achieved by controlling the operating modes of the device's source radio frequency and bias radio frequency to perform deposition or etching. In this case, the deposition process in the second deposition step is specifically, for example, a plasma deposition process, and the etching process in the third etching step is specifically, for example, a plasma etching process.

[0085] In one example, during the second deposition step, the source RF of the control device operates in continuous wave mode, while the bias RF remains off. For details, please refer to the description of the first deposition step; further elaboration is omitted here.

[0086] In some embodiments, the second material layer 900 is made of the same material as the first material layer 800. In one example, the second material layer 900 formed in the second deposition step comprises a layer of hydrocarbon compounds. In the second deposition step, the reaction source introduced into the reaction chamber of the apparatus may include CH4 and N2. The reaction source introduced in the second deposition step is the same as the reaction source introduced in the first deposition step; furthermore, the gas flow rate of the reaction source introduced in the second deposition step is the same as the gas flow rate of the reaction source introduced in the first deposition step. For details, please refer to the description of the first deposition step, which will not be elaborated upon here.

[0087] In some embodiments, the thickness of the second material layer 900 is less than the thickness of the first material layer 800. This shortens the time of the third etching step, reduces the etching risk to the intermediate material layer 200, and minimizes the impact on the size of the opening 301.

[0088] In one specific example, the duration of the second deposition step is shorter than the duration of the first deposition step. Therefore, by controlling the duration, the thickness of the second material layer 900 can be made less than the thickness of the first material layer 800.

[0089] In some embodiments, the pressure, source RF power, and bias RF voltage of the second deposition step are equal to those of the first deposition step. In one example, the process conditions in the second deposition step include: a pressure in the range of 10 mTorr to 20 mTorr, a source RF power in the range of 500 W to 600 W, and a duration in the range of 5 s to 8 s.

[0090] In one example, during the third etching step, both the source RF and bias RF of the control device operate in continuous wave mode. This creates a continuous, stable, and high-intensity plasma etching environment, thereby increasing the etching rate.

[0091] In the third etching step, the reaction sources introduced into the reaction chamber of the equipment may include HBr, O2, and He. HBr, as the main etching gas, generates bromine radicals that provide a moderate and controllable etching rate to the layer to be etched 300 (e.g., polysilicon), while maintaining a high etching selectivity for the intermediate material layer 200 (e.g., oxide layer), thus avoiding damage to the intermediate material layer 200. O2 not only works synergistically with HBr to form a passivation layer on the sidewall of the opening 301, suppressing lateral etching and protecting the vertical morphology formed by the previous cycle process, but also effectively decomposes and removes byproduct residues. He, as an inert dilution gas and a highly efficient thermally conductive medium, can stabilize the temperature of the semiconductor structure, prevent localized overheating, and simultaneously assist in the effective removal of byproducts.

[0092] In some examples, the pressure of the third etching step is greater than that of the second etching step. Under higher pressure, the mean free path of the particles is shortened, reducing ion scattering and ensuring anisotropic etching.

[0093] In some examples, the source RF power of the third etching step is lower than that of the second etching step, while the bias RF voltage of the third etching step is higher than that of the second etching step. Reducing the source RF power lowers the free radical concentration, directly weakening the lateral chemical etching and thus better protecting the formed vertical sidewall morphology. Increasing the bias RF voltage increases the ion energy bombarding the surface, more effectively physically sputtering away any byproducts or material of the layer 300 to be etched at the bottom of the opening 301, maintaining a sufficiently high vertical etching rate, and ensuring process efficiency.

[0094] In some examples, the duration of the third etching step is longer than that of the second etching step. This allows sufficient processing time to ensure that even in areas with slow etching, any remaining etchable layer 300 can be completely removed.

[0095] Therefore, in a specific example, in the third etching step, the process conditions may include: pressure in the range of 40mTorr to 50mTorr, source RF power in the range of 300W to 400W, bias RF voltage in the range of 150V to 250V, and duration in the range of 10s to 20s.

[0096] Finally, please refer to Figure 12 and Figure 13 The preparation method may also include: removing the hard mask layer 400. Specifically, the hard mask layer 400 can be removed by a wet etching process, which can also simultaneously remove residual polymer from the previous etching process.

[0097] Please refer to Figure 14 The gate structure of a MOSFET is fabricated using the method provided in this application. The layer to be etched 300 is specifically a polysilicon layer, and the remaining layer 300 after etching serves as the gate structure. Figure 14 As shown in Figure (a), when the top of the polycrystalline silicon layer has an N-type doped region, the top dimension of the gate structure is 44.8 nm, and the bottom dimension is 48.9 nm. Figure 2 Comparing Figure (a), the size difference between the N-type doped and undoped regions decreased from 8.2 nm to 4.1 nm, indicating improvements in both top size shrinkage and sidewall tilt. Figure 14 As shown in Figure (b), when the top of the polysilicon layer has a P-type doped region, the top dimension of the gate structure is 45.6 nm, the bottom dimension is 50.5 nm, and the size difference between the P-type doped and undoped regions is 4.9 nm. Figure 2Compared with the related technologies shown, the size difference between the N-type doped and undoped regions and the P-type doped and undoped regions is reduced from 4.4 nm to 0.8 nm. It can be seen that the preparation method provided in this application can effectively eliminate the influence of different doping on the etching rate.

[0098] Correspondingly, this application also provides a semiconductor device, which is prepared using the semiconductor device preparation method provided in the above embodiments. The sidewall morphology of the opening 301 within the etchable layer 300 in the semiconductor device is improved.

[0099] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor structure is provided, the semiconductor structure including a substrate and a layer to be etched on the substrate; A hard mask layer is formed on the layer to be etched; The hard mask layer is patterned to form openings that expose a portion of the surface of the layer to be etched; A first deposition step is performed to form a first material layer, the first material layer comprising a first portion covering the upper surface of the hard mask layer, a second portion covering the inner sidewall of the opening, and a third portion covering the surface of the layer to be etched exposed through the opening; A first etching step is performed to remove the first portion and the third portion, while the second portion remains. A second etching step is performed to extend the opening toward the substrate within the layer to be etched, and the second portion is gradually removed. The second etching step stops before the second portion is completely removed. Repeat the first deposition step, the first etching step, and the second etching step in sequence until the opening extends to the desired depth within the etched layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The first deposition step, the first etching step, and the second etching step are performed in the same device, and deposition or etching is achieved by controlling the operating modes of the source radio frequency and the bias radio frequency of the device.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, In the first deposition step, the source radio frequency of the device is controlled to operate in continuous wave mode, while the bias radio frequency remains off.

4. The method for fabricating a semiconductor device according to claim 2, characterized in that, In the first etching step, the source radio frequency of the device is controlled to operate in pulse mode, and the bias radio frequency operates in continuous wave mode.

5. The method for fabricating a semiconductor device according to claim 2, characterized in that, In the second etching step, the source radio frequency and bias radio frequency of the control device are both operated in pulse mode. The turn-on time window of the bias radio frequency is located within the turn-off time window of the source radio frequency, and the turn-on time window of the source radio frequency is located within the turn-off time window of the bias radio frequency.

6. The method for fabricating a semiconductor device according to any one of claims 2 to 5, characterized in that, The first deposition step to the second etching step satisfies at least one of the following: (1) In the first deposition step, the reaction sources introduced into the reaction chamber of the device include: CH4 and N2; (2) The first material layer formed in the first deposition step comprises a layer of carbon, hydrogen, and nitrogen compounds; (3) The thickness of the first material layer ranges from 2 nm to 5 nm; (4) In the first deposition step, the process conditions include: pressure in the range of 10mTorr to 20mTorr, source RF power in the range of 500W to 600W, and duration in the range of 5s to 10s; (5) In the first etching step and the second etching step, the reaction sources introduced into the reaction chamber of the device include: CF4, SF6, O2 and N2; (6) In the first etching step, the process conditions include: pressure in the range of 3mTorr to 5mTorr, source RF power in the range of 500W to 600W, and bias RF voltage in the range of 100V to 200V; (7) In the second etching step, the process conditions include: pressure in the range of 3mTorr to 5mTorr, source RF power in the range of 500W to 600W, and bias RF voltage in the range of 100V to 200V; (8) The process conditions for the first etching step and the second etching step include: pressure in the range of 3mTorr to 5mTorr, source RF power in the range of 500W to 600W, bias RF voltage in the range of 100V to 200V; and the total duration of the first etching step and the second etching step in the range of 5s to 10s. (9) The process conditions in the first etching step are the same as those in the second etching step.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the hard mask layer includes nitrogen-rich silicon oxynitride.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, Patterning the hard mask layer includes: An advanced patterned thin film layer, a dielectric anti-reflective coating, a bottom anti-reflective coating, and a photoresist layer are sequentially formed on the hard mask layer; The photoresist layer is patterned. Perform the first mask etching step to transfer the pattern on the photoresist layer to the bottom anti-reflective coating and the dielectric anti-reflective coating; A second mask etching step is performed to transfer the patterns on the bottom anti-reflective coating and the dielectric anti-reflective coating to the advanced patterned thin film layer; The third mask etching step is performed to transfer the pattern on the advanced patterned thin film layer to the hard mask layer.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The semiconductor structure further includes an intermediate material layer located between the substrate and the layer to be etched; after sequentially repeating the first deposition step, the first etching step, and the second etching step, the method further includes: Perform a second deposition step to form a second material layer that conformally covers the intermediate material layer, the layer to be etched, and the hard mask layer; A third etching step is performed to etch the second material layer and the layer to be etched until the second material layer is removed. The etching rate of the third etching step on the layer to be etched is greater than the etching rate of the second etching step on the layer to be etched.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The thickness of the second material layer is less than the thickness of the first material layer.

11. The method for fabricating a semiconductor device according to claim 9, characterized in that, The second deposition step, the third etching step, the first deposition step, the first etching step, and the second etching step are all performed in the same equipment.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The second deposition step to the third etching step satisfy at least one of the following: (1) In the second deposition step, the reaction sources introduced into the reaction chamber of the device include: CH4 and N2; (2) The second material layer formed in the second deposition step comprises a layer of carbon, hydrogen, and nitrogen compounds; (3) The pressure, source RF power, and bias RF voltage of the second deposition step are equal to the pressure, source RF power, and bias RF voltage of the first deposition step, respectively; (4) The duration of the second deposition step is less than the duration of the first deposition step; (5) In the second deposition step, the process conditions include: pressure in the range of 10mTorr to 20mTorr, source RF power in the range of 500W to 600W, and duration in the range of 5s to 8s; (6) In the third etching step, the reaction source introduced into the reaction chamber of the device includes: HBr, O2 and He; (7) The pressure of the third etching step is greater than the pressure of the second etching step; (8) The source RF power of the third etching step is less than the source RF power of the second etching step, and the bias RF voltage of the third etching step is greater than the bias RF voltage of the second etching step. (9) The duration of the third etching step is greater than the duration of the second etching step; (10) In the third etching step, the process conditions include: pressure in the range of 40mTorr to 50mTorr, source RF power in the range of 300W to 400W, bias RF voltage in the range of 150V to 250V, and duration in the range of 10s to 20s.

13. A semiconductor device, characterized in that, It is prepared by the method of preparing a semiconductor device as described in any one of claims 1 to 12.

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