Manufacturing method of semiconductor structure
By forming a second sidewall on the gate electrode sidewall and utilizing the consumption of the sacrificial portion, the side-hole problem of the gate oxide layer during the etching process is solved, which improves the reliability of the gate oxide layer and the stability of device performance, increases the yield, and provides high flexibility in process control.
Patent Information
- Application Number
- CN202511848053.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-09
- Publication Date
- 2026-03-03
AI Technical Summary
In existing semiconductor manufacturing technologies, the gate oxide layer is easily etched laterally or recessed during the etching process, resulting in changes in the effective gate length, damage to the gate oxide layer, increased leakage current, and unstable device performance, leading to a decrease in yield.
A second sidewall is formed on the sidewall of the gate electrode, and the first sidewall is prevented from being side-cut during wet cleaning by the consumption of the sacrificial part, thereby protecting the gate oxide layer. The width of the sacrificial part is controlled by a multi-layer sidewall structure and etching process to improve process flexibility.
It effectively avoids side-penetration of the gate oxide layer, improves the reliability of the gate oxide layer, stabilizes device performance, increases yield, and offers high flexibility in process control.
Smart Images
Figure CN121604492A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure. Background Technology
[0002] Gate oxide is an extremely thin and high-quality insulating oxide film grown above the channel region and below the gate on a silicon substrate. The growth of gate oxide is one of the most delicate steps in chip manufacturing, requiring extremely high cleanliness, uniformity and thickness control.
[0003] In semiconductor manufacturing, unintended and excessive lateral etching or recessing of the gate structure, i.e., side-holeing of the gate sidewalls, can easily cause the following problems: 1) changes in the effective gate length, which in turn causes changes in the electrical characteristics of the device; 2) damage to the gate oxide layer, reducing the reliability of the gate oxide layer and increasing gate leakage current; 3) device performance drift and yield reduction, ultimately leading to device performance instability and reduced yield. Summary of the Invention
[0004] This application provides a method for fabricating a semiconductor structure that can prevent the sidewalls of the gate electrode from being side-hollowed out, thereby avoiding side-hollow defects in the gate oxide layer below the gate electrode, and the process has high control flexibility.
[0005] To achieve the above objectives, this application provides a method for fabricating a semiconductor structure. The method includes: providing a semiconductor substrate, on which a gate oxide layer and a gate electrode are formed; forming a first sidewall material layer on the semiconductor substrate, the first sidewall material layer conformally covering the semiconductor substrate, the gate electrode, and the gate oxide layer; forming a second sidewall on the first sidewall material layer, the second sidewall being located on the sidewall of the gate electrode and attached to the first sidewall material layer; etching the first sidewall material layer to remove the first sidewall material layer on the top surface of the gate electrode and a portion of the first sidewall material layer on the side of the second sidewall away from the gate electrode, retaining the first sidewall material layer as a first sidewall and a sacrificial portion, wherein the first sidewall material layer covered by the second sidewall serves as the first sidewall, and the first sidewall material layer exposed on the side of the second sidewall away from the gate electrode serves as the sacrificial portion; and performing a wet cleaning process, wherein the sacrificial portion is consumed during the wet cleaning process.
[0006] Optionally, the method of etching the first sidewall material layer includes: forming a patterned mask layer on the semiconductor substrate, the patterned mask layer covering the second sidewall and the sacrificial portion formation region, the sacrificial portion formation region being located on the side of the second sidewall away from the gate electrode and adjacent to the second sidewall, the patterned mask layer exposing the first sidewall material layer on the top surface of the gate electrode and exposing the first sidewall material layer on the side of the sacrificial portion formation region away from the second sidewall; and etching the first sidewall material layer under the masking of the patterned mask layer to form the sacrificial portion and the first sidewall.
[0007] Optionally, the first sidewall material layer can be etched using a dry etching process.
[0008] Optionally, the method of forming a second sidewall on the first sidewall material layer includes: forming a second sidewall material layer on the first sidewall material layer, the second sidewall material layer covering the first sidewall material layer; etching the second sidewall material layer and stopping on the first sidewall material layer to remove the second sidewall material layer on the top surface of the gate electrode and to remove a portion of the second sidewall material layer on the semiconductor substrate, retaining the second sidewall material layer on the sidewall of the gate electrode as the second sidewall.
[0009] Optionally, after forming a second sidewall material layer on the first sidewall material layer and before etching the first sidewall material layer, a third sidewall material layer is formed on the second sidewall material layer, the third sidewall material layer covering the second sidewall material layer; the third sidewall material layer and the second sidewall material layer are etched and stopped on the first sidewall material layer, the third sidewall material layer and the second sidewall material layer on the top surface of the gate electrode are removed, and a portion of the third sidewall material layer and a portion of the second sidewall material layer on the semiconductor substrate are removed, the third sidewall material layer on the sidewall of the gate electrode is retained as the third sidewall, and the second sidewall material layer covered by the third sidewall is retained as the second sidewall.
[0010] Optionally, the first sidewall material layer is an oxide layer, the second sidewall material layer is a nitride layer, and the third sidewall is an oxide layer.
[0011] Optionally, the sacrificial portion extends laterally from the edge of the second sidewall with a width greater than or equal to 100 nm and less than or equal to 150 nm.
[0012] Optionally, the material of the gate oxide layer includes silicon oxide, hafnium oxide, titanium oxide, lanthanum oxide, tantalum oxide, strontium titanium oxide, hafnium silicon oxide, or zirconium oxide.
[0013] Optionally, the width of the sacrificial portion extending laterally from the edge of the second sidewall is determined according to the amount of etching during the wet cleaning process.
[0014] Optionally, during the wet cleaning process, the sacrificial portion is partially or completely etched away and the first sidewall below the second sidewall is not side-excavated.
[0015] In the semiconductor structure fabrication method provided in this application, a gate oxide layer and a gate electrode located on the gate oxide layer are formed on the provided semiconductor substrate. A first sidewall material layer is formed on the semiconductor substrate, and the first sidewall material layer conformally covers the semiconductor substrate, the gate electrode, and the gate oxide layer. A second sidewall is formed on the first sidewall material layer, and the second sidewall is located on the sidewall of the gate electrode and adheres to the first sidewall material layer. The first sidewall material layer is etched to remove the first sidewall material layer on the top surface of the gate electrode and a portion of the first sidewall material layer on the side of the second sidewall away from the gate electrode. The remaining first sidewall material layer serves as the first sidewall and the sacrificial portion. The first sidewall material layer covered by the second sidewall serves as the first sidewall, and the first sidewall material layer exposed on the side of the second sidewall away from the gate electrode serves as the sacrificial portion. A wet cleaning process is performed, during which the sacrificial portion is consumed. In this way, the consumption of the sacrificial part during the wet cleaning process can prevent the first sidewall from being side-picked, thereby preventing the gate oxide layer below the gate electrode from being side-picked. This can improve the reliability of the gate oxide layer, avoid changes in the effective length of the gate electrode and gate leakage caused by side-picking of the gate oxide layer, and avoid changes in the electrical characteristics of the device. This is beneficial to improving the performance stability and yield of semiconductor devices, and the process control is highly flexible. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a structure in the related technology in which a protective layer is formed on the outside of the sidewall.
[0017] Figure 2 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application.
[0018] Figures 3 to 8 This is a schematic diagram of the process structure of a method for fabricating a semiconductor structure according to an embodiment of this application.
[0019] Explanation of reference numerals in the attached figures: 11-sidewall; 12-protective layer; 101-semiconductor substrate; 102-gate oxide layer; 103-gate electrode; 104-first sidewall material layer; 104a-sacrificial region; 105-second sidewall; 106-third sidewall; 107-patterned mask layer; 108a-sacrificial region; 108b-first sidewall. Detailed Implementation
[0020] In related technologies, to avoid the gate oxide layer being side-excavated during wet cleaning after etching the sidewall material layer, the following methods are used: (1) such as Figure 1 As shown, a protective layer 12 is formed on the outer side of the sidewall 11; (2) the process parameters such as the cleaning solution, cleaning temperature and cleaning time of the wet cleaning process are optimized to reduce the lateral etching of the gate oxide layer by the wet cleaning process; (3) the material of the sidewall of the gate sidewall is optimized to improve the etching resistance of the sidewall in the wet cleaning process, thereby protecting the gate oxide layer. However, the above method has low control flexibility to avoid the gate oxide layer being side-cut, that is, the process control flexibility is low and the adjustment range of the process is large.
[0021] In the semiconductor structure fabrication method provided in this application, a second sidewall is formed on a first sidewall material layer. The second sidewall is located on the sidewall of the gate electrode and is attached to the first sidewall material layer. Then, the first sidewall material layer is etched to form a first sidewall and a sacrificial portion. The first sidewall material layer covered by the second sidewall serves as the first sidewall, and the first sidewall material layer exposed on the side of the second sidewall away from the gate electrode serves as the sacrificial portion. The consumption of the sacrificial portion can be used to prevent the first sidewall from being side-hollowed out, thereby preventing the gate oxide layer under the gate electrode from being side-hollowed out. The width of the sacrificial portion extending laterally from the edge of the second sidewall can be determined according to the etching amount of wet cleaning, resulting in high process control flexibility.
[0022] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present application.
[0023] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly stated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly stated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly stated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly stated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly stated.
[0024] Figure 2This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 2 As shown, the method for fabricating the semiconductor structure provided in this embodiment includes:
[0025] Step S1: Provide a semiconductor substrate, on which a gate oxide layer and a gate electrode located on the gate oxide layer are formed;
[0026] Step S2: A first sidewall material layer is formed on the semiconductor substrate, wherein the first sidewall material layer conformally covers the semiconductor substrate, the gate electrode, and the gate oxide layer;
[0027] Step S3: A second sidewall is formed on the first sidewall material layer. The second sidewall is located on the sidewall of the gate electrode and is attached to the first sidewall material layer.
[0028] Step S4: Etch the first sidewall material layer to remove the first sidewall material layer on the top surface of the gate electrode and remove a portion of the first sidewall material layer on the side of the second sidewall away from the gate electrode. The remaining first sidewall material layer serves as the first sidewall and the sacrificial portion, wherein the first sidewall material layer covered by the second sidewall serves as the first sidewall, and the first sidewall material layer exposed on the side of the second sidewall away from the gate electrode serves as the sacrificial portion; and
[0029] Step S5: Perform wet cleaning, during which the sacrificial part is consumed.
[0030] Figures 3 to 8 This is a schematic diagram illustrating the process structure of a semiconductor structure fabrication method according to an embodiment of this application. The following is combined with... Figure 2 , Figures 3 to 8 The method for fabricating the semiconductor structure provided in this embodiment will be described.
[0031] refer to Figure 3 As shown, a gate oxide layer 102 and a gate electrode 103 located on the gate oxide layer 102 are formed on the semiconductor substrate 101 provided in step S1.
[0032] For example, the semiconductor substrate 101 can be a silicon substrate, germanium substrate, silicon-germanium substrate, silicon-carbon substrate, indium arsenide (InAs) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate, or other III / V compound semiconductor substrates. It can also be a silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI) substrate, etc. The semiconductor substrate 101 can also be implanted with certain doping particles to change the electrical parameters according to design requirements.
[0033] In this embodiment, the gate oxide layer 102 is a silicon oxide layer. In other embodiments, the gate oxide layer 102 may include a high-k dielectric layer. The material of the high-k dielectric layer may include, but is not limited to, hafnium oxide (HfO2), titanium oxide (TiO), lanthanum oxide (LaO), tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium silicon oxide (HfSiO), or zirconium oxide (ZrO2). The gate oxide layer 102 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal oxidation, or any combination thereof.
[0034] In this embodiment, the gate electrode 103 may be made of polysilicon, but is not limited thereto. In other embodiments, the gate electrode 103 may be made of metal.
[0035] refer to Figure 3 As shown, in this embodiment, the edge of the gate oxide layer 102 can be flush with the edge of the gate electrode 103, but is not limited to this.
[0036] refer to Figure 3 As shown, in step S2, a first sidewall material layer 104 is formed on the semiconductor substrate 101, and the first sidewall material layer 104 conformally covers the semiconductor substrate 101, the gate electrode 103 and the gate oxide layer 102.
[0037] Specifically, the first sidewall material layer 104 covers the top surface of the gate electrode 103, the sidewalls of the gate electrode 103 and the gate oxide layer 102, and the surface of the semiconductor substrate 101 on the side of the gate electrode 103.
[0038] For example, the first sidewall material layer 104 can be a silicon oxide layer. The first sidewall material layer 104 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0039] refer to Figure 4 As shown, in step S3, a second sidewall 105 is formed on the first sidewall material layer 104. The second sidewall 105 is located on the sidewall of the gate electrode 103 and is attached to the first sidewall material layer 104.
[0040] An exemplary method for forming a second sidewall 105 on a first sidewall material layer 104 may include: forming a second sidewall material layer on the first sidewall material layer 104, the second sidewall material layer covering the first sidewall material layer; etching the second sidewall material layer using an anisotropic dry etching process and stopping at the first sidewall material layer 104, removing the second sidewall material layer on the top surface of the gate electrode 103 and removing a portion of the second sidewall material layer on the semiconductor substrate 101, retaining the second sidewall material layer on the sidewall of the gate electrode 103 as the second sidewall 105.
[0041] For example, the second sidewall material layer 105 may be a silicon nitride layer, but is not limited thereto. The second sidewall material layer 105 may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc.
[0042] In this embodiment, reference Figure 4 As shown, a second sidewall 105 and a third sidewall 106 located on the second sidewall 105 can be formed on the first sidewall material layer 104. Specifically, after forming the second sidewall material layer, a third sidewall material layer can be formed on the second sidewall material layer, and the third sidewall material layer covers the second sidewall material layer. The third sidewall material layer and the second sidewall material layer are etched using an anisotropic dry etching process and the etching stops on the first sidewall material layer 104. The third sidewall material layer and the second sidewall material layer on the top surface of the gate electrode 103 are removed, as well as part of the third sidewall material layer and part of the second sidewall material layer on the semiconductor substrate 101. The third sidewall material layer on the sidewall of the gate electrode 103 is retained as the third sidewall 106, and the second sidewall material layer covered by the third sidewall 106 is retained as the second sidewall 105.
[0043] For example, the second sidewall 105 can be L-shaped, and the third sidewall 106 can be located in the L-shaped groove of the second sidewall 105, but the shape of the second sidewall 105 is not limited to this.
[0044] For example, the material of the third sidewall 106 can be silicon oxide, but it is not limited to this. The third sidewall material layer can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc.
[0045] refer to Figure 5 and Figure 6As shown, in step S4, the first sidewall material layer 104 is etched to remove the first sidewall material layer 104 on the top surface of the gate electrode 103 and a portion of the first sidewall material layer 104 on the side of the second sidewall 105 away from the gate electrode 103. The remaining first sidewall material layer 104 serves as the first sidewall 108b and the sacrificial portion 108a. The first sidewall material layer 104 covered by the second sidewall 105 serves as the first sidewall 108b, and the first sidewall material layer 104 exposed on the side of the second sidewall 105 away from the gate electrode 103 serves as the sacrificial portion 108a. That is, the sacrificial portion 108a is located outside the first sidewall 108b and the second sidewall 105.
[0046] Specifically, step S4 may include: such as Figure 5 As shown, a patterned mask layer 107 is formed on a semiconductor substrate 101. The patterned mask layer 107 covers the third sidewall 106, the second sidewall 105, and the sacrificial region 104a. The sacrificial region 104a is located on the side of the second sidewall 105 away from the gate electrode 103 and is adjacent to the second sidewall 105. The patterned mask layer 107 exposes the first sidewall material layer 104 on the top surface of the gate electrode 103 and exposes the first sidewall material layer 104 on the side of the sacrificial region 104a away from the second sidewall 105. (Reference) Figure 6 As shown, under the cover of the patterned mask layer 107, the first sidewall material layer 104 is etched and stops on the surface of the semiconductor substrate 101 and the top surface of the gate electrode 103 to form the sacrificial portion 108a and the first sidewall 108b.
[0047] For example, an anisotropic dry etching process is used to etch the first sidewall material layer 104 to form the first sidewall 108b and the sacrificial portion 108a, but it is not limited thereto.
[0048] For example, the patterned mask layer 107 may be a patterned photoresist layer, but is not limited thereto. A method for forming the patterned mask layer 107 may include: coating a photoresist layer on a semiconductor substrate 101 to form a photoresist layer, and exposing and developing the photoresist layer to form the patterned photoresist layer. The thickness of the patterned mask layer 107 needs to meet the requirement of protecting the third sidewall 106, the second sidewall 105, and the first sidewall material layer 104 to be retained during the etching of the first sidewall material layer 104.
[0049] It should be noted that the width of the sacrificial portion 108a can be determined based on the etching amount of the subsequent wet cleaning process (i.e., Figure 6The dimensions in the horizontal direction are adjusted, and the width of the sacrificial part 108a can be adjusted by adjusting the coverage area of the patterned mask layer 107. The process control is highly flexible and precise, and the degree of change to the existing process is small.
[0050] For example, refer to Figure 7 As shown, the width D of the sacrificial portion 108a can be greater than or equal to 100 nm and less than or equal to 150 nm, but is not limited thereto.
[0051] refer to Figure 7 As shown, the patterned mask layer 107 is removed. For example, the patterned mask layer 107 can be removed using an ashing process or similar method.
[0052] refer to Figure 8 As shown, in step S5, wet cleaning is performed, and the sacrificial part 108a is consumed during the wet cleaning process.
[0053] It should be noted that during the wet cleaning process, the sacrificial part 108a is consumed preferentially relative to the first sidewall 108b below the second sidewall 105. Thus, the first sidewall 108b can be protected by consuming the sacrificial part 108a, which in turn can protect the gate oxide layer 102 below the gate electrode 103 and prevent the gate oxide layer 102 below the gate electrode 103 from being side-cut.
[0054] In some embodiments, during wet cleaning, the sacrificial portion 108a may be partially or completely etched away and the first sidewall 108b below the second sidewall 105 may not be side-hollowed out. This can improve the problem of side-hollowing out of the sidewall structure (including the third sidewall 106, the second sidewall 105 and the first sidewall 108b) on the side of the gate electrode 103, and help avoid changes in the electrical performance of the semiconductor device due to side-hollowing out of the sidewall structure.
[0055] For example, the semiconductor structure can be fabricated on a BCD (Bipolar-CMOS-DMOS) platform, meaning that the fabrication method of the provided semiconductor structure is compatible with the BCD platform.
[0056] In the semiconductor structure fabrication method provided in this application, a gate oxide layer 102 and a gate electrode 103 located on the gate oxide layer 102 are formed on the provided semiconductor substrate 101. A first sidewall material layer 104 is formed on the semiconductor substrate 101, and the first sidewall material layer 104 conformally covers the semiconductor substrate 101, the gate electrode 103, and the gate oxide layer 102. A second sidewall 105 is formed on the first sidewall material layer 104, and the second sidewall 105 is located on the sidewall of the gate electrode 103 and adheres to the first sidewall material layer 104. The first sidewall material layer 104 is then etched. 04. Remove the first sidewall material layer 104 on the top surface of the gate electrode 103 and remove a portion of the first sidewall material layer 104 on the side of the second sidewall 105 away from the gate electrode 103. The remaining first sidewall material layer 104 serves as the first sidewall 108b and the sacrificial portion 108a. The first sidewall material layer 104 covered by the second sidewall 105 serves as the first sidewall 108b, and the first sidewall material layer 104 exposed on the side of the second sidewall 105 away from the gate electrode 103 serves as the sacrificial portion 108a. Perform wet cleaning, during which the sacrificial portion 108a is consumed. In this way, the consumption of the sacrificial portion 108a during the wet cleaning process can prevent the first sidewall 108b from being side-picked, thereby preventing the gate oxide layer 102 below the gate electrode 103 from being side-picked. This can improve the reliability of the gate oxide layer 102, avoid changes in the effective length of the gate electrode 103 and gate leakage caused by the side-picking of the gate oxide layer 102, and avoid changes in the electrical characteristics of the device. This is beneficial to improving the performance stability and yield of semiconductor devices, and the process control is more flexible and precise, with less change compared to existing processes.
[0057] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of the claims of this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, on which a gate oxide layer and a gate electrode located on the gate oxide layer are formed; A first sidewall material layer is formed on the semiconductor substrate, the first sidewall material layer conformally covering the semiconductor substrate, the gate electrode and the gate oxide layer; A second sidewall is formed on the first sidewall material layer, the second sidewall being located on the sidewall of the gate electrode and attached to the first sidewall material layer; The first sidewall material layer is etched to remove the first sidewall material layer on the top surface of the gate electrode and a portion of the first sidewall material layer on the side of the second sidewall away from the gate electrode. The remaining first sidewall material layer serves as the first sidewall and the sacrificial portion. The first sidewall material layer covered by the second sidewall serves as the first sidewall, and the first sidewall material layer exposed on the side of the second sidewall away from the gate electrode serves as the sacrificial portion. as well as The sacrificial part is consumed during the wet cleaning process.
2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The method for etching the first sidewall material layer includes: A patterned mask layer is formed on the semiconductor substrate, the patterned mask layer covering the second sidewall and the sacrificial region, the sacrificial region being located on the side of the second sidewall away from the gate electrode and adjacent to the second sidewall, the patterned mask layer exposing the first sidewall material layer on the top surface of the gate electrode and exposing the first sidewall material layer on the side of the sacrificial region away from the second sidewall; and Under the cover of the patterned mask layer, the first sidewall material layer is etched to form the sacrificial portion and the first sidewall.
3. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The first sidewall material layer was etched using a dry etching process.
4. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The method of forming a second sidewall on the first sidewall material layer includes: A second sidewall material layer is formed on the first sidewall material layer, the second sidewall material layer covering the first sidewall material layer; and The second sidewall material layer is etched and stopped on the first sidewall material layer. The second sidewall material layer on the top surface of the gate electrode and a portion of the second sidewall material layer on the semiconductor substrate are removed, while the second sidewall material layer on the sidewall of the gate electrode is retained as the second sidewall.
5. The method for fabricating a semiconductor structure as described in claim 4, characterized in that, After forming the second sidewall material layer on the first sidewall material layer and before etching the first sidewall material layer. A third sidewall material layer is formed on the second sidewall material layer, the third sidewall material layer covering the second sidewall material layer; The third sidewall material layer and the second sidewall material layer are etched and the etching stops on the first sidewall material layer. The third sidewall material layer and the second sidewall material layer on the top surface of the gate electrode are removed, and a portion of the third sidewall material layer and a portion of the second sidewall material layer on the semiconductor substrate are removed. The third sidewall material layer on the sidewall of the gate electrode is retained as the third sidewall, and the second sidewall material layer covered by the third sidewall is retained as the second sidewall.
6. The method for fabricating a semiconductor structure as described in claim 5, characterized in that, The first sidewall material layer is an oxide layer, the second sidewall material layer is a nitride layer, and the third sidewall is an oxide layer.
7. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The sacrificial portion extends laterally from the edge of the second sidewall with a width greater than or equal to 100 nm and less than or equal to 150 nm.
8. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The material of the gate oxide layer includes silicon oxide, hafnium oxide, titanium oxide, lanthanum oxide, tantalum oxide, strontium titanium oxide, hafnium silicon oxide, or zirconium oxide.
9. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The width of the sacrificial portion extending laterally from the edge of the second sidewall is determined according to the amount of etching during the wet cleaning process.
10. The method for fabricating a semiconductor structure as described in any one of claims 1 to 9, characterized in that, During the wet cleaning process, the sacrificial portion is partially or completely etched away and the first sidewall below the second sidewall is not side-excavated.