Parallel SiC MOSFET device and preparation method thereof

Abstract

The invention discloses a parallel SiC MOSFET device and a preparation method thereof, and the preparation method comprises the steps: dividing a device epitaxial layer into a cellular region and an auxiliary current sharing region, and enabling the auxiliary current sharing region to be located at the edge of one side of the cellular region; performing groove etching treatment on the device epitaxial layer through a first preset process so as to etch a plurality of main grooves in the cellular region; groove etching treatment is carried out on the device epitaxial layer again through a second preset process, so that a plurality of shallow grooves are etched in the auxiliary current sharing region, and the groove depth of the shallow grooves is smaller than that of the main grooves; performing light doping processing on the bottom of each shallow trench to enable the plurality of shallow trenches to form a dynamic current sharing structure; and sequentially preparing a grid electrode, a source electrode and a drain electrode on the epitaxial layer of the device through a third preset process to obtain the parallel SiC MOSFET device. According to the technical scheme, when the prepared parallel SiC MOSFET device is used in parallel, the dynamic current sharing effect can be achieved through adjustment of the internal structure of the device, and a complex external circuit does not need to be designed.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a parallel SiC MOSFET device and its fabrication method. Background Technology

[0002] In related technologies, when multiple SiC MOSFET devices (i.e., silicon carbide metal-oxide-semiconductor field-effect transistors) are connected in parallel, in order to ensure that the current is evenly distributed among the SiC MOSFET devices during high-speed switching, specially designed circuit layouts, topologies, and auxiliary component configurations are employed to suppress dynamic current unevenness caused by parameter differences and parasitic parameter asymmetries among the individual SiC MOSFET devices. However, in practical applications, it has been found that this approach requires the design of complex external circuits, which not only increases the design difficulty, size, and cost of the system, but also introduces additional parasitic parameters (i.e., inconsistencies in the external components themselves), weakening the current sharing effect and even causing new mismatch problems, making it difficult to guarantee the reliability of the overall solution. Summary of the Invention

[0003] The purpose of this application is to provide a parallel SiC MOSFET device and its fabrication method, aiming to improve the existing problem that when multiple SiC MOSFET devices are used in parallel, it is necessary to design additional complex external circuits for dynamic current sharing. This not only increases the design difficulty, size and cost of the system, but also makes it difficult to guarantee the reliability of the overall solution.

[0004] To achieve this objective, embodiments of this application provide a method for fabricating a parallel SiC MOSFET device, the method comprising: The epitaxial layer of the device is divided into a cell region and an auxiliary current sharing region, wherein the auxiliary current sharing region is located at one edge of the cell region; A trench etching process is performed on the epitaxial layer of the device using a first preset process to etch a number of main trenches in the cell region. The device epitaxial layer is subjected to trench etching again through a second preset process to etch several shallow trenches in the auxiliary current equalization region. The depth of the shallow trenches is less than the depth of the main trench. The bottom of each of the shallow trenches is lightly doped to form a dynamic flow-equalizing structure in the shallow trenches. The gate, source, and drain are sequentially fabricated on the epitaxial layer of the device using a third preset process to obtain the parallel SiC MOSFET device.

[0005] Optionally, in some embodiments of this application, the trench etching process performed on the epitaxial layer of the device using a first preset process to etch a plurality of main trenches in the cell region includes: A hard mask layer is deposited on the surface of the epitaxial layer of the device using a chemical vapor deposition process. A first photoresist layer is spin-coated on the side of the hard mask layer away from the epitaxial layer of the device. By combining photolithography and dry etching processes, the first photomask information containing the main trench region information is sequentially transferred to the first photoresist layer, the hard mask layer, and the device epitaxial layer to etch a plurality of the main trenches in the cell region.

[0006] Optionally, in some embodiments of this application, the step of sequentially transferring the first photomask information containing the main trench region information to the first photoresist layer, the hard mask layer, and the device epitaxial layer through a combination of photolithography and dry etching processes to etch a plurality of the main trenches in the cell region includes: transferring the first photomask information to the first photoresist layer through photolithography; transferring the first photomask information on the first photoresist layer to the hard mask layer through dry etching, and then removing the remaining portion of the first photoresist layer; transferring the first photomask information on the hard mask layer to the device epitaxial layer through dry etching, and then removing the hard mask layer after etching a plurality of the main trenches in the cell region; and / or, The thickness of the hard mask layer is 2μm to 10μm; and / or, The depth of the main trench is 0.8μm to 2μm.

[0007] Optionally, in some embodiments of this application, the step of performing trench etching on the device epitaxial layer again through a second preset process to etch several shallow trenches in the auxiliary current equalization region includes: A second photoresist layer is spin-coated onto the surface of the epitaxial layer of the device; By combining photolithography and dry etching processes, the second photomask information containing information about the shallow trench region is sequentially transferred to the second photoresist layer and the device epitaxial layer, so as to etch a plurality of the shallow trenches in the auxiliary current equalization region.

[0008] Optionally, in some embodiments of this application, the step of sequentially transferring the second photomask information containing shallow trench region information to the second photoresist layer and the device epitaxial layer through a combination of photolithography and dry etching processes to etch a plurality of the shallow trenches in the auxiliary current equalization region includes: transferring the second photomask information to the second photoresist layer through photolithography; transferring the second photomask information on the second photoresist layer to the device epitaxial layer through dry etching processes to etch a plurality of the shallow trenches in the auxiliary current equalization region; and / or, The depth of the shallow trench is 0.6 μm to 1 μm.

[0009] Optionally, in some embodiments of this application, the step of lightly doping the bottom of each of the shallow trenches to form a dynamic current-equalizing structure in the plurality of shallow trenches includes: The bottom of each of the shallow trenches is lightly doped using an ion implantation process to create a dynamic flow-equalizing structure in the shallow trenches.

[0010] Optionally, in some embodiments of this application, the step of sequentially fabricating the gate, source, and drain on the device epitaxial layer through a third preset process to obtain the parallel SiC MOSFET device includes: By combining thermal oxidation and chemical vapor deposition processes, gate oxide layer growth and gate metal filling processes are performed sequentially on several main trenches and several shallow trenches, so that the gate is fabricated in several main trenches while the shallow trenches are filled. By combining photolithography and ion implantation, a preset doping process is performed on a preset position of the cell region to define the bulk implantation region and the source region at the preset position. An insulating layer and several source contact holes are formed on the surface of the epitaxial layer of the device by combining chemical vapor deposition, photolithography and dry etching processes. After depositing a metal layer on the surface of the insulating layer and in several source contact holes using a physical vapor deposition process, passivation, device thinning, and back-side metallization are performed to complete the fabrication of the source and drain, thus obtaining the parallel SiC MOSFET device.

[0011] Optionally, in some embodiments of this application, the step of simultaneously completing the fabrication of the gate at the plurality of main trenches and the filling process of the plurality of shallow trenches includes: growing a gate oxide layer on the sidewalls of the plurality of main trenches and the sidewalls of the plurality of shallow trenches by a thermal oxidation process; filling the interior of the plurality of main trenches and the interior of the plurality of shallow trenches by a chemical vapor deposition process, so as to simultaneously complete the fabrication of the gate at the plurality of main trenches and the filling process of the plurality of shallow trenches; and / or, The step of defining the body implantation region and the source region at the preset positions includes: performing a first doping treatment on a first preset position of the cell region using a combination of photolithography and ion implantation processes to obtain the body implantation region; performing a second doping treatment on a second preset position of the cell region using a combination of photolithography and ion implantation processes to obtain the source region; and / or, The method of forming an insulating layer and a plurality of source contact holes on the surface of the epitaxial layer of the device includes: depositing the insulating layer on the surface of the epitaxial layer of the device by chemical vapor deposition; spin-coating a third photoresist layer on the surface of the insulating layer; and sequentially transferring third photomask information containing contact hole area information to the third photoresist layer and the insulating layer by a combination of photolithography and dry etching processes, so as to etch a plurality of the source contact holes on the insulating layer.

[0012] Optionally, in some embodiments of this application, the thickness of the insulating layer is 40 nm to 1000 nm; and / or, The thickness of the metal layer is 4μm to 10μm.

[0013] Furthermore, to achieve this objective, embodiments of this application also provide a parallel SiC MOSFET device, which is prepared by any of the above-described preparation methods.

[0014] The parallel SiC MOSFET device and its fabrication method provided in this application, through the above-described method steps, produce a parallel SiC MOSFET device that, compared to traditional structures, features a dynamic current-sharing structure formed by a shallow trench combined with light doping at the device edge. This structure design can act as a capacitor buffer between the gate and source when an external voltage is suddenly applied (i.e., in transient conditions, the rate of change of voltage over time, dv / dt, is a relatively high value). This mitigates the impact of excessively large rate of change of voltage over time, dv / dt, during voltage surges, thus providing additional charge regulation capability for the parallel SiC MOSFET device. This alleviates the direct impact of voltage surges on the cell structure of the parallel SiC MOSFET device, preventing premature threshold voltage reaching and channel premature turn-on. Consequently, when multiple parallel SiC MOSFET devices are used in parallel, the turn-on time of each parallel SiC MOSFET device is more uniform. As can be seen, the parallel SiC MOSFET devices prepared by this technical solution can achieve dynamic current sharing by adjusting the internal structure of the device when used in parallel, without the need to design complex external circuits. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0017] Figure 1 This is a flowchart illustrating the fabrication method of a parallel SiC MOSFET device according to an embodiment of this application.

[0018] Figure 2 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 1 .

[0019] Figure 3 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 2 .

[0020] Figure 4 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 3 .

[0021] Figure 5 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 4 .

[0022] Figure 6 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 5 .

[0023] Figure 7 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 6 .

[0024] Figure 8 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 7 .

[0025] Figure 9 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 8 .

[0026] Figure 10 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 9 .

[0027] Figure 11 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 10 .

[0028] Figure 12 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 10 one.

[0029] Figure 13 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 10 two.

[0030] Figure 14 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 10 three.

[0031] Figure 15 This is a schematic diagram illustrating the fabrication process of the parallel SiC MOSFET device in an embodiment of this application. Figure 10 five.

[0032] Figure 16 for Figure 1 The flowchart shows the specific steps of S120 in the fabrication method of the parallel SiC MOSFET device.

[0033] Figure 17 for Figure 1 The flowchart shows the specific steps of S130 in the fabrication method of the parallel SiC MOSFET device.

[0034] Figure 18 for Figure 1 The flowchart shows the specific steps of step S150 in the fabrication method of the parallel SiC MOSFET device.

[0035] Figure label: 10. Device epitaxial layer; 11. Cell region; 111. Main trench; 12. Auxiliary current equalization region; 121. Shallow trench; 122. Semiconductor thin layer; 20. Hard mask layer; 21. Second notch; 31. First photoresist layer; 311. First notch; 32. Second photoresist layer; 321. Third notch; 33. Third photoresist layer; 331. Fourth notch; 34. Fourth photoresist layer; 341. Fifth notch; 35. Fifth photoresist layer; 351. Sixth notch; 41. Gate oxide layer; 42. Gate metal; 51. Body injection region; 52. Source region; 60. Insulating layer; 61. Source contact hole; 70. Metal layer. Detailed Implementation

[0036] To make the inventive objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0038] The technical solution of this application will be further described below with reference to the accompanying drawings and specific embodiments.

[0039] Please see Figures 1 to 15 As shown, in one embodiment, this application provides a method for fabricating a parallel SiC MOSFET device, which specifically includes: Step S110: Divide the device epitaxial layer into a cell region and an auxiliary current equalization region, with the auxiliary current equalization region located at one edge of the cell region.

[0040] It should be noted that the method for fabricating parallel SiC MOSFET devices in this application is mainly used in the production and manufacturing of parallel SiC MOSFET devices. That is, the parallel SiC MOSFET devices prepared by this method are mainly used in scenarios where multiple SiC MOSFET devices are used in parallel.

[0041] The parallel SiC MOSFET device fabricated by this method is essentially still a SiC MOSFET device. Therefore, its specific fabrication process is roughly the same as that of a typical SiC MOSFET device. It also requires a SiC substrate for epitaxial growth via chemical vapor deposition (CVD) to obtain the epitaxial layer 10. Unlike typical SiC MOSFET devices, which treat the entire epitaxial layer 10 as a cell region 11, this method divides the epitaxial layer 10 into a cell region 11 and an auxiliary current-sharing region 12 after obtaining the epitaxial layer 10. The auxiliary current-sharing region 12 is located at one edge of the cell region 11, i.e., it is defined as one edge of the entire epitaxial layer 10, for setting the dynamic current-sharing structure in subsequent steps. It can be understood that the region division in this method is a virtual division based on the subsequent functional partitioning of the device, rather than a physical division on the epitaxial layer 10.

[0042] Step S120: Perform trench etching on the epitaxial layer of the device using a first preset process to etch several main trenches in the cell region.

[0043] It should be noted that after dividing the device epitaxial layer 10 into cell regions 11 and auxiliary current sharing regions 12 through the above-described steps, trench etching can be performed on the device epitaxial layer 10 using a first preset process to etch several main trenches 111 in the cell regions 11. This method is essentially the same as the method for fabricating main trenches 111 in a typical SiC MOSFET device; that is, trench etching can be performed on the device epitaxial layer 10 using a conventional etching process to complete the fabrication of several main trenches 111. Generally, the preferred number of main trenches 111 is three, and the preferred depth of the main trenches 111 is 0.8 μm to 2 μm.

[0044] Step S130: Perform trench etching on the device epitaxial layer again through the second preset process to etch several shallow trenches in the auxiliary current equalization region.

[0045] It should be noted that after the fabrication of several main trenches 111 is completed through the above-described steps, a second preset process can be used to perform trench etching on the epitaxial layer 10 again to etch several shallow trenches 121 in the auxiliary current equalization region 12. The purpose of this method is to etch several shallow trenches 121 in the auxiliary current equalization region 12. The difference between the shallow trenches 121 and the main trenches 111 lies mainly in the opening area and the trench depth. That is, the shallow trenches 121 are opened in the auxiliary current equalization region 12 on one side edge of the epitaxial layer 10, and the trench depth of the shallow trenches 121 is less than that of the main trenches 111. Therefore, the same or similar etching process can be used to perform trench etching on the epitaxial layer 10 to complete the fabrication of several shallow trenches 121. Generally, the number of shallow trenches 121 is preferably two, and the depth of the shallow trenches 121 is preferably 0.6 μm to 1 μm.

[0046] Step S140: Lightly dop the bottom of each shallow trench to form a dynamic flow uniformity structure in the shallow trenches.

[0047] It should be noted that after the fabrication of several main trenches 111 is completed through the above-described steps, the bottom of each shallow trench 121 can be further lightly doped to form a dynamic current-sharing structure. The light doping process mentioned in this method mainly refers to introducing specific types of impurity atoms (such as nitrogen or phosphorus impurity atoms) into the epitaxial layer 10 material at a lower concentration (compared to the source region 52), thereby forming a semiconductor thin layer 122 with a specific and controllable resistivity at the bottom region of the shallow trench 121. During device switching, this lightly doped layer works in conjunction with the trench gate structure to automatically adjust the local potential and electric field distribution according to the current magnitude, thus dynamically balancing the current between parallel branches.

[0048] Step S150: The gate, source and drain are fabricated sequentially on the device epitaxial layer through the third preset process to obtain a parallel SiC MOSFET device.

[0049] It should be noted that after lightly doping the bottom of each shallow trench 121 using the above-described steps, the gate, source, and drain can be sequentially fabricated on the epitaxial layer 10 using the third preset process to obtain a parallel SiC MOSFET device. The purpose of this method is to complete the main structure of the parallel SiC MOSFET device, namely the fabrication of the gate, source, and drain, on the epitaxial layer 10. This process is largely the same as that of a typical SiC MOSFET device; the gate, source, and drain can be sequentially fabricated on the epitaxial layer 10 using conventional processes to ultimately obtain the parallel SiC MOSFET device.

[0050] In this way, the parallel SiC MOSFET device fabrication method of this application embodiment, through the above method steps, produces a parallel SiC MOSFET device with a shallow trench 121 and a lightly doped dynamic current sharing structure at the device edge, compared to the traditional structure. This structure design can act as a capacitor buffer between the gate and source when an external voltage is suddenly applied to the gate and source (i.e., in the transient state, the rate of change of voltage over time dv / dt is a high value), mitigating the impact of excessively large rate of change of voltage over time dv / dt during voltage surges. This provides additional charge regulation capability for the parallel SiC MOSFET device, thereby alleviating the direct impact of voltage surges on the cell structure of the parallel SiC MOSFET device, i.e., avoiding the problem of premature channel turn-on caused by reaching the threshold voltage early. This makes the turn-on time of each parallel SiC MOSFET device more uniform when multiple parallel SiC MOSFET devices are used in parallel. As can be seen, the parallel SiC MOSFET devices prepared by this technical solution can achieve dynamic current sharing by adjusting the internal structure of the device when used in parallel, without the need to design complex external circuits.

[0051] In some examples, such as Figure 2 , Figure 3 , Figure 4 as well as Figure 16 As shown, the specific process of performing the above method step "performing trench etching on the device epitaxial layer through a first preset process to etch several main trenches in the cell region" can be as follows: Step S121: Deposit a hard mask layer on the surface of the device epitaxial layer using a chemical vapor deposition process.

[0052] Step S122: Spin-coat the first photoresist layer on the side of the hard mask layer away from the device epitaxial layer.

[0053] Step S123: By combining photolithography and dry etching processes, the first photomask information containing the main trench region information is sequentially transferred to the first photoresist layer, the hard mask layer, and the device epitaxial layer to etch several main trenches in the cell region.

[0054] It should be noted that, in the above method steps, when depositing the hard mask layer 20 on the surface of the device epitaxial layer 10 using chemical vapor deposition, a hard mask layer 20 with a preferred thickness of 2μm to 10μm can be deposited on the upper surface of the device epitaxial layer 10 to ensure that the hard mask layer 20 can provide good etching protection in the subsequent etching process of the main trench 111. The first photomask information containing the main trench region information mentioned in the above method steps specifically refers to the planar pattern, size, and positional distribution of all main trenches 111 that need to be etched within the unit region 11 of the device epitaxial layer 10, which can be precisely defined by the first photomask information. This first photomask information, with the light-shielding / light-transmitting pattern on the photomask as a carrier, is the direct basis and spatial positioning template for the subsequent photolithography and etching processes to physically transfer the design blueprint of the main trenches 111 sequentially to the first photoresist layer 31, the hard mask layer 20, and the device epitaxial layer 10.

[0055] In this way, by using the above methods and steps, the corresponding number and location of main trenches 111 can be etched in the cell region 11.

[0056] In some examples, the specific process of performing the above method step "by combining photolithography and dry etching processes, the first photomask information containing the main trench region information is sequentially transferred to the first photoresist layer, the hard mask layer, and the device epitaxial layer to etch several main trenches in the cell region" can be as follows: First, the first photomask information is transferred to the first photoresist layer 31 through photolithography (that is, the first photoresist layer 31 is formed as shown in the figure). Figure 2 The structure shown has several first notches 311. Then, the first photomask information on the first photoresist layer 31 is transferred to the hard mask layer 20 using a dry etching process (so that the hard mask layer 20 is formed as shown). Figure 3After the structure shown has several second notches 21, the remaining portion of the first photoresist layer 31 is removed. Finally, the first photomask information on the hard mask layer 20 is transferred to the device epitaxial layer 10 using a dry etching process to etch several main trenches 111 in the cell region 11, after which the hard mask layer 20 is removed. In this way, through the precise combination of photolithography and dry etching processes, the pattern of the first photomask information is first copied to the first photoresist layer 31 with high fidelity, and then the pattern is precisely transferred to the hard mask layer 20 using the first photoresist layer 31 as a mask. Finally, the hard mask layer 20 acts as a durable mask to complete the etching of the device epitaxial layer 10. This layer-by-layer transfer process, utilizing the excellent etching resistance of the hard mask layer 20, effectively ensures the uniformity of the etching depth of the main trenches 111 and the vertical regularity of the sidewall morphology, thereby providing a key process guarantee for the consistency and reliability of device performance.

[0057] It should be noted that after etching several main trenches 111 in the cell region 11 using the above method steps, the hard mask layer 20 can be removed specifically by wet etching during the removal process. This allows for rapid, uniform, and selective removal of the hard mask layer 20, while avoiding physical damage or erosion to the formed main trench 111 structure. This process is simple to operate and highly efficient, facilitating surface cleaning after the formation of critical structures. It provides a smooth, residue-free starting interface for subsequent shallow trench 121 etching and the fabrication of dynamic current-equalizing structures, ensuring smooth process flow and stable device performance.

[0058] In some examples, such as Figure 5 , Figure 6 as well as Figure 17 As shown, the specific process of performing the above method step "to perform trench etching on the device epitaxial layer again through a second preset process to etch several shallow trenches in the auxiliary current equalization region" can be as follows: Step S131: Spin-coat a second photoresist layer onto the surface of the device epitaxial layer.

[0059] Step S132: By combining photolithography and dry etching processes, the second photomask information containing shallow trench region information is sequentially transferred to the second photoresist layer and the device epitaxial layer to etch several shallow trenches in the auxiliary current equalization region 12.

[0060] It should be noted that the second photomask information containing shallow trench region information mentioned in the above method steps specifically refers to the planar pattern, size, and positional distribution of all shallow trenches 121 that need to be etched within the auxiliary current equalization region 12 of the device epitaxial layer, which can be precisely defined by the second photomask information. This second photomask information, with the light-blocking / light-transmitting pattern on the photomask as a carrier, is the direct basis and spatial positioning template for the subsequent photolithography and etching processes to physically transfer the design blueprint of the shallow trenches 121 sequentially to the second photoresist layer 32 and the device epitaxial layer.

[0061] In this way, by using the above methods and steps, the corresponding number and location of shallow trenches 121 can be etched in the auxiliary current equalization region 12.

[0062] In some examples, the specific process of performing the above method step "by combining photolithography and dry etching processes, the second photomask information containing shallow trench region information is sequentially transferred to the second photoresist layer and the device epitaxial layer to etch several shallow trenches in the auxiliary current equalization region" can be as follows: the second photomask information is transferred to the second photoresist layer 32 by photolithography (that is, the second photoresist layer 32 is formed as shown in the figure). Figure 5 The structure shown has several third notches 321. The second photomask information on the second photoresist layer 32 is transferred to the device epitaxial layer 10 using a dry etching process to etch several shallow trenches 121 in the auxiliary current equalization region 12 (at this time, the remaining portion of the second photoresist layer 32 is not removed, so that the bottom of each shallow trench 121 can be lightly doped later by the masking effect of the second photoresist layer 32). Thus, the second photomask information is precisely transferred to the second photoresist layer 32 through photolithography, defining the pattern position of the shallow trenches 121 on the auxiliary current equalization region 12. Subsequently, the pattern is precisely etched into the auxiliary current equalization region 12 of the device epitaxial layer 10 using a dry etching process, forming a shallow trench 121 structure with controllable depth and consistent morphology. This process combination achieves precise machining of the size and distribution of the shallow trenches 121, laying a reliable physical foundation for the subsequent formation of the dynamic current equalization functional region and ensuring the controllability and consistency of the current equalization effect.

[0063] In some examples, such as Figure 7 and Figure 8 As shown, the specific process of performing the above method step "lightly doping the bottom of each shallow trench to form a dynamic current-equalizing structure for several shallow trenches 121" can be as follows: The bottom of each shallow trench 121 is lightly doped using an ion implantation process to form a dynamic current-equalizing structure for several shallow trenches 121. This process can be performed under the cover of the second photoresist layer 32. After the corresponding light doping treatment is completed, the remaining portion of the second photoresist layer 32 can be removed to form... Figure 8 The structure is shown. Thus, by lightly doping the bottom of the shallow trench 121 through ion implantation, the type, dosage, and depth of impurities can be precisely controlled, forming a semiconductor thin layer 122 with engineered resistivity at the bottom of the trench. This step is the core of constructing the dynamic current sharing functional region. The introduced controlled resistor can automatically adjust the potential and current distribution of each parallel branch during switching, thereby achieving efficient and adaptive dynamic current sharing within the device, significantly improving the stability and reliability of parallel operation.

[0064] In some examples, such as Figures 9 to 15 , Figure 18 As shown, the specific process of performing the above method step "to sequentially fabricate the gate, source, and drain on the device epitaxial layer through a third preset process to obtain a parallel SiC MOSFET device" can be as follows: Step S151: By combining thermal oxidation and chemical vapor deposition processes, gate oxide layer growth and gate metal filling processes are performed on several main trenches and several shallow trenches in sequence, so as to complete the gate fabrication at several main trenches and the filling process of several shallow trenches at the same time.

[0065] It should be noted that the purpose of this method is to simultaneously fabricate the gate and fill several shallow trenches 121. The specific process is as follows: First, a gate oxide layer 41 is grown on the sidewalls of several main trenches 111 and several shallow trenches 121 using a thermal oxidation process. Then, a gate metal 42 is filled into the interior of several main trenches 111 and several shallow trenches 121 using a chemical vapor deposition process. This completes the fabrication of the gate (i.e., the gate metal 42 located in the cell region 11) in several main trenches 111 while simultaneously filling several shallow trenches 121. Since the thermal oxidation process lacks regional selectivity, the gate oxide layer 41 will also grow on the surface of the device epitaxial layer 10. Similarly, since the chemical vapor deposition process also lacks regional selectivity, a layer of gate metal 42 will also be deposited on the surface of the device epitaxial layer 10. After completing the corresponding processes, the gate metal 42 on the surface of the device epitaxial layer 10 can be removed by chemical mechanical polishing, ensuring that it exists only inside the trenches. Since the main trench 111 and the shallow trench 121 are not connected by design, the gate metal 42 filled inside them is also insulated from each other. After the gate metal 42 on the surface of the device epitaxial layer 10 is removed, a wet etching process (e.g., using a diluted hydrofluoric acid solution) is then used to selectively remove the gate oxide layer 41 on the surface of the device epitaxial layer 10. This is because the etching rate of hydrofluoric acid on silicon oxide (gate oxide) is much higher than that on single-crystal silicon carbide (epitaxy layer) or metal, thus enabling precise removal of the oxide layer on the surface of the device epitaxial layer 10 without damaging the underlying SiC material or the gate structure within the trench.

[0066] Step S152: By combining photolithography and ion implantation processes, preset doping treatment is performed on preset positions of the cell region to define the bulk implantation region and the source region at the preset positions.

[0067] It should be noted that the purpose of this method is to complete the fabrication of the source electrode. The specific process is as follows: First, by combining photolithography and ion implantation, the first predetermined position of the cell region 11 is subjected to a first doping treatment (specifically, P-type doping treatment) to obtain the bulk implantation region 51, i.e., as shown below. Figure 11As shown, the fourth photomask information, containing the information of the first preset position area, is transferred to the fourth photoresist layer 34 through a photolithography process (that is, the fourth photoresist layer 34 is formed as shown). Figure 11 After the structure shown has several fifth notches 341, the first preset position of the cell region 11 is doped using an ion implantation process with the fourth photoresist layer 34 as a shield, to obtain the bulk implantation region 51. Then, by combining photolithography and ion implantation processes, the second preset position of the cell region 11 is doped (specifically, N-type doping) to obtain the source region 52 (i.e., the heavily doped source region), as shown. Figure 12 As shown, the fifth photomask information, containing information about the second preset location region, is transferred to the fifth photoresist layer 35 through a photolithography process (that is, the fifth photoresist layer 35 is formed as shown). Figure 12 After the structure shown has several sixth notches 351, the source region 52 is obtained by using the shielding of the fifth photoresist layer 35 to perform corresponding doping treatment on the second preset position of the cell region 11 through the ion implantation process.

[0068] Step S153: An insulating layer and several source contact holes are formed on the surface of the device epitaxial layer by combining chemical vapor deposition, photolithography and dry etching processes.

[0069] It should be noted that the purpose of this method is to complete the fabrication of the insulating layer 60. The specific process is as follows: First, the insulating layer 60 is deposited on the surface of the epitaxial layer 10 of the device using a chemical vapor deposition process. Then, a third photoresist layer 33 is spin-coated onto the surface of the insulating layer 60. Next, through a combination of photolithography and dry etching processes, the third photomask information, including contact hole area information, is sequentially transferred to the third photoresist layer (thus ensuring that the third photoresist layer 33 is formed as shown in the image). Figure 14 The structure shown has several fourth notches 331 and an insulating layer 60, to which several source contact holes 61 are etched. Generally, the thickness of the insulating layer 60 is preferably 40 nm to 1000 nm.

[0070] Step S154: After depositing a metal layer on the surface of the insulating layer and in several source contact holes through physical vapor deposition, passivation, device thinning and back-side metallization are carried out to complete the fabrication of the drain electrode and obtain a parallel SiC MOSFET device.

[0071] It should be noted that, in this method, while depositing a metal layer 70 with a preferred thickness of 4μm to 10μm on the surface of the insulating layer 60 using physical vapor deposition, the metal layer 70 also fills several source contact holes 61 to achieve the extraction of the source region 52, thereby enabling the extraction of the source region 52 on the front side of the device (i.e., Figure 15The source electrode (i.e., metal layer 70) is fabricated on the upper surface shown. Subsequently, conventional passivation is performed to protect the device surface from environmental influences, and conventional device thinning is used to optimize device thickness and thermal resistance. Then, low-resistance, reliable drain ohmic contacts are formed on the back side of the device (i.e., on the upper surface shown). Figure 15 The drain electrode (not shown) is fabricated on the lower surface shown. This series of processes fully constructs the electrode system and physical structure of the device, ensuring that the parallel SiC MOSFET device has good heat dissipation, electrical performance, and long-term operational reliability.

[0072] In this way, through the above-described steps, not only was the gate of the main trench 111 fabricated, but the shallow trench 121 of the auxiliary current sharing region 12 was also simultaneously filled with the gate material, simplifying the process steps. The precise patterning of the source region 52 and the insulating layer 60 ensures the functionality and isolation of critical areas of the device. Finally, through the combination of front-side metal layer deposition and back-side metallization, complete source and drain electrodes were efficiently constructed, thereby achieving the simultaneous manufacturing of high-performance parallel SiC MOSFET devices and their built-in dynamic current sharing structure, improving overall device performance and production efficiency.

[0073] In one embodiment, such as Figure 15 As shown, this application embodiment also provides a parallel SiC MOSFET device, which is prepared by the preparation method of the above embodiment. Therefore, since the parallel SiC MOSFET device of this application embodiment is prepared by the preparation method of the above embodiment, it enables the parallel SiC MOSFET device to achieve dynamic current sharing by adjusting the internal structure of the device when used in parallel, without the need for complex external circuit design.

[0074] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a parallel SiC MOSFET device, characterized in that, The preparation method includes: The epitaxial layer of the device is divided into a cell region and an auxiliary current sharing region, wherein the auxiliary current sharing region is located at one edge of the cell region; A trench etching process is performed on the epitaxial layer of the device using a first preset process to etch a number of main trenches in the cell region. The device epitaxial layer is subjected to trench etching again through a second preset process to etch several shallow trenches in the auxiliary current equalization region. The depth of the shallow trenches is less than the depth of the main trench. The bottom of each of the shallow trenches is lightly doped to form a dynamic flow-equalizing structure in the shallow trenches. The gate, source, and drain are sequentially fabricated on the epitaxial layer of the device using a third preset process to obtain the parallel SiC MOSFET device.

2. The preparation method according to claim 1, characterized in that, The process of performing trench etching on the epitaxial layer of the device through a first preset process to etch a plurality of main trenches in the cell region includes: A hard mask layer is deposited on the surface of the epitaxial layer of the device using a chemical vapor deposition process. A first photoresist layer is spin-coated on the side of the hard mask layer away from the epitaxial layer of the device. By combining photolithography and dry etching processes, the first photomask information containing the main trench region information is sequentially transferred to the first photoresist layer, the hard mask layer, and the device epitaxial layer to etch a plurality of the main trenches in the cell region.

3. The preparation method according to claim 2, characterized in that, The method of transferring first photomask information containing information about the main trench region sequentially to the first photoresist layer, the hard mask layer, and the device epitaxial layer through a combination of photolithography and dry etching processes to etch a plurality of the main trenches in the cell region includes: transferring the first photomask information to the first photoresist layer through photolithography; transferring the first photomask information on the first photoresist layer to the hard mask layer through dry etching, and then removing the remaining portion of the first photoresist layer; transferring the first photomask information on the hard mask layer to the device epitaxial layer through dry etching, and then removing the hard mask layer after etching a plurality of the main trenches in the cell region; and / or, The thickness of the hard mask layer is 2μm~10μm; and / or, The depth of the main trench is 0.8μm to 2μm.

4. The preparation method according to claim 1, characterized in that, The second preset process is used to perform trench etching on the epitaxial layer of the device again to etch several shallow trenches in the auxiliary current equalization region, including: A second photoresist layer is spin-coated onto the surface of the epitaxial layer of the device; By combining photolithography and dry etching processes, the second photomask information containing information about the shallow trench region is sequentially transferred to the second photoresist layer and the device epitaxial layer, so as to etch a plurality of the shallow trenches in the auxiliary current equalization region.

5. The preparation method according to claim 4, characterized in that, The method of transferring second photomask information containing shallow trench region information sequentially to the second photoresist layer and the device epitaxial layer through a combination of photolithography and dry etching processes to etch a plurality of shallow trenches in the auxiliary current equalization region includes: transferring the second photomask information to the second photoresist layer through photolithography; transferring the second photomask information on the second photoresist layer to the device epitaxial layer through dry etching processes to etch a plurality of shallow trenches in the auxiliary current equalization region; and / or, The depth of the shallow trench is 0.6μm to 1μm.

6. The preparation method according to claim 1, characterized in that, The step of lightly doping the bottom of each of the shallow trenches to form a dynamic flow-equalizing structure in the shallow trenches includes: The bottom of each of the shallow trenches is lightly doped using an ion implantation process to create a dynamic flow-equalizing structure in the shallow trenches.

7. The preparation method according to any one of claims 1-6, characterized in that, The process of sequentially fabricating the gate, source, and drain on the epitaxial layer of the device using a third preset process to obtain the parallel SiC MOSFET device includes: By combining thermal oxidation and chemical vapor deposition processes, gate oxide layer growth and gate metal filling processes are performed sequentially on several main trenches and several shallow trenches, so that the gate is fabricated in several main trenches while the shallow trenches are filled. By combining photolithography and ion implantation, a preset doping process is performed on a preset position of the cell region to define the bulk implantation region and the source region at the preset position. An insulating layer and several source contact holes are formed on the surface of the epitaxial layer of the device by combining chemical vapor deposition, photolithography and dry etching processes. After depositing a metal layer on the surface of the insulating layer and in several source contact holes using a physical vapor deposition process, passivation, device thinning, and back-side metallization are performed to complete the fabrication of the source and drain, thus obtaining the parallel SiC MOSFET device.

8. The preparation method according to claim 7, characterized in that, The process of simultaneously fabricating the gate at the main trenches and filling the shallow trenches includes: growing a gate oxide layer on the sidewalls of the main trenches and the sidewalls of the shallow trenches using a thermal oxidation process; and filling the interiors of the main trenches and the shallow trenches with gate metal using a chemical vapor deposition process, so as to simultaneously fabricate the gate at the main trenches and fill the shallow trenches; and / or, The step of defining the body implantation region and the source region at the preset positions includes: performing a first doping treatment on a first preset position of the cell region using a combination of photolithography and ion implantation processes to obtain the body implantation region; performing a second doping treatment on a second preset position of the cell region using a combination of photolithography and ion implantation processes to obtain the source region; and / or, The process of forming an insulating layer and a plurality of source contact holes on the surface of the epitaxial layer of the device includes: depositing the insulating layer on the surface of the epitaxial layer of the device by chemical vapor deposition; spin-coating a third photoresist layer on the surface of the insulating layer; and sequentially transferring third photomask information containing information about the contact hole region to the third photoresist layer and the insulating layer by a combination of photolithography and dry etching processes, so as to etch a plurality of the source contact holes on the insulating layer.

9. The preparation method according to claim 7, characterized in that, The thickness of the insulating layer is 40 nm to 1000 nm; and / or, The thickness of the metal layer is 4μm to 10μm.

10. A parallel SiC MOSFET device, characterized in that, The parallel SiC MOSFET device is prepared by the preparation method described in any one of claims 1-9.

Images