Semiconductor device and method of manufacturing the same
By employing a gate dielectric layer structure that is thin in the middle and thick at both ends in the medium-voltage device formation region and LDD injection, the GIDL leakage problem of medium-voltage MOS devices was solved, and stable operation of MOS devices with different operating voltages was achieved.
Patent Information
- Application Number
- CN202411117491.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-14
- Publication Date
- 2026-03-03
AI Technical Summary
In existing technologies, the GIDL leakage problem of medium-voltage MOS devices is difficult to solve effectively when integrating MOS devices with different operating voltages. Especially when the gate sidewall is thin, the overlapping area between the highly doped drain region and the gate is prone to forming a strong electric field, leading to serious leakage problems.
In the medium-voltage device formation region, a gate dielectric layer structure with a thinner middle and thicker ends along the channel length direction is adopted. By forming the first and second medium-voltage gate dielectric layers on the substrate surface and in the recess, combined with LDD implantation and sidewall formation, the electric field in the gate-drain overlap region is reduced.
It effectively reduces the risk of GIDL leakage in medium-voltage MOS devices and ensures the operational stability of MOS devices with different operating voltages under high voltage conditions.
Smart Images
Figure CN121604500A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing, and more particularly to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology
[0002] The GIDL (Gate-induced Drain Leakage) effect is the main leakage mechanism of MOSFETs (hereinafter referred to as MOS devices). When the gate is not charged or is negatively charged, and a high voltage is applied to the drain, the gate-drain voltage Vd increases. DG The field is very large. A strong electric field will be formed from the drain to the gate in the overlap region between the drain impurity diffusion layer (such as the drain LDD region) and the gate (i.e., the gate-drain overlap region). The energy band near the interface of the overlap region will be strongly bent and the depletion region will be very narrow. Carriers can easily tunnel and generate electron-hole pairs. Electrons flow to the drain and holes are swept into the base well, forming the drain-to-base well GIDL current.
[0003] To reduce GIDL current, the interface morphology of the gate-drain overlap region needs to be improved to avoid the distance between the gate and the highly doped drain region being too small, thus reducing the electric field formed in the gate-drain overlap region. However, some existing products integrate MOS devices with different operating voltages, such as simultaneously fabricating high-voltage (HV) MOS devices, medium-voltage (MV) MOS devices, and low-voltage (LV) MOS devices on a substrate. Among them, low-voltage MOS devices (such as logic devices) require thinner sidewalls on the gate side, but for medium-voltage MOS devices, the thinner sidewalls make the highly doped drain region closer to the gate and the gate-drain overlap region. When a high voltage is applied to the drain region, a strong electric field is easily formed in the gate-drain overlap region, resulting in a more serious GIDL leakage problem. Summary of the Invention
[0004] In order to simultaneously form MOS devices with different operating voltages on a substrate and reduce the risk of GIDL leakage of the medium-voltage MOS device, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device.
[0005] In one aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
[0006] A substrate is provided, wherein a high-voltage device formation region, a medium-voltage device formation region, and a low-voltage device formation region are laterally arranged on the surface region of the substrate;
[0007] A first recess and a second recess are formed at the two ends of the gate to be formed in the medium-voltage device formation region along the channel length direction, and a first medium-voltage gate dielectric layer is formed in the first recess and the second recess.
[0008] Corresponding gate stacks, including gate dielectric layers and gates, are formed in the high-voltage device formation region, the medium-voltage device formation region, and the low-voltage device formation region, respectively. In the medium-voltage device formation region, the gate dielectric layer includes a first medium-voltage gate dielectric layer and a second medium-voltage gate dielectric layer between the substrate and the corresponding gate, wherein the second medium-voltage gate dielectric layer covers the first medium-voltage gate dielectric layer.
[0009] Sidewalls are formed on the side of the gate stack, and source and drain regions are formed on the side of the sidewall opposite to the gate stack, respectively, located on both sides of the corresponding gate stack.
[0010] Optionally, forming the first recess and the second recess includes:
[0011] A pad oxide layer and a patterned first mask layer are formed on the substrate surface, such that in the intermediate voltage device formation region, the first mask layer has a first opening and a second opening corresponding to the formation regions of the respective two ends of the gate; and
[0012] A first oxidation process is performed to oxidize the substrate below the first opening and the second opening to a set depth, thereby forming a first recess below the first opening and a second recess below the second opening in the substrate of the medium-voltage device forming region.
[0013] Optionally, the first oxide formed in the substrate of the medium-voltage device formation region by the first oxidation process is used as the first medium-voltage gate dielectric layer.
[0014] Optionally, after patterning the first mask layer, a third opening is formed in the high-voltage device formation region corresponding to the formation region of the corresponding gate in the first mask layer, and after performing the first oxidation process, a third recess is formed in the substrate of the high-voltage device formation region below the third opening.
[0015] Optionally, forming the first medium-voltage gate dielectric layer includes:
[0016] Remove the oxide formed in the substrate by the first oxidation process to expose the first recess, the second recess, and the third recess;
[0017] A second oxidation process is performed to form a second oxide, which fills the third recess and extends above it, fills the first recess and extends above it, and fills the second recess and extends above it.
[0018] Remove the first mask layer, wherein the portion of the second oxide filling the third recess and extending onto the third recess is a high-voltage gate dielectric layer, and the second oxide in the first recess and the second recess is a first medium-voltage gate dielectric layer.
[0019] Optionally, forming the second medium-voltage gate dielectric layer includes:
[0020] A patterned second mask layer is formed on the substrate, the openings in the second mask layer corresponding to the formation of the first and second recesses, respectively, to expose the second oxide formed at the first and second recesses; and
[0021] Using the second mask layer, the exposed second oxide is etched to thin the second oxide at the first and second recesses while still filling the first and second recesses;
[0022] LDD implantation is performed to form an LDD region within the substrate of the medium-voltage device formation region;
[0023] Remove the pad oxide layer and the second oxide layer from the substrate located in the medium-voltage device formation region; and
[0024] A gate dielectric material layer and a gate material layer are sequentially stacked on the substrate of the medium-voltage device formation region, and the gate dielectric material layer and the gate material layer are etched to form a second medium-voltage gate dielectric layer from the gate dielectric material layer. A gate located on the second medium-voltage gate dielectric layer is formed from the gate material layer. The two ends of the gate have the second medium-voltage gate dielectric layer and the first medium-voltage gate dielectric layer located below the second medium-voltage gate dielectric layer.
[0025] Optionally, in the medium-voltage device forming region, the two LDD regions are respectively located on both sides of the corresponding gate, and both LDD regions overlap with the corresponding gate, and the width of the overlapping area is greater than or equal to the width of the first recess and the second recess.
[0026] Optionally, forming sidewalls on the sides of each of the gate stacks includes:
[0027] A first sidewall material layer is formed conformally on the substrate;
[0028] The first sidewall material layer is etched using an anisotropic etching process to form a first sidewall located on the side of each of the gate stacks;
[0029] LDD implantation is performed to form a corresponding LDD region in the substrate of the low-voltage device formation region;
[0030] A second sidewall material layer is formed conformally on the substrate; and
[0031] The second sidewall material layer is etched using an anisotropic etching process to form a second sidewall located on the side of each of the gate stacks.
[0032] On the other hand, the present invention provides a semiconductor device, the semiconductor device comprising:
[0033] The substrate has a surface region laterally arranged with a high-voltage device formation region, a medium-voltage device formation region, and a low-voltage device formation region;
[0034] A gate stack comprising a gate dielectric layer and a gate is formed in the high-voltage device formation region, the medium-voltage device formation region, and the low-voltage device formation region, respectively. In the medium-voltage device formation region, the gate includes two ends arranged along the channel length direction and a gate middle portion located between the two ends. A first recess and a second recess are formed in the substrate corresponding to the two ends of the gate. The gate dielectric layer includes a first medium-voltage gate dielectric layer formed in the first recess and the second recess and a second medium-voltage gate dielectric layer formed on the surface of the substrate and covering the first medium-voltage gate dielectric layer.
[0035] Sidewalls formed on the sides of each of the gate stacks; and
[0036] Source and drain regions are formed on the sides of the sidewall opposite to the gate stack, respectively, on both sides of the corresponding gate stack.
[0037] Optionally, the semiconductor substrate further includes:
[0038] The medium-voltage LDD region is formed in the substrate of the medium-voltage device formation region, wherein, in the medium-voltage device formation region, the two medium-voltage LDD regions are respectively located on both sides of the corresponding gate, and both LDD regions overlap with the corresponding gate, and the width of the overlapping area is greater than or equal to the width of the first recess and the second recess.
[0039] Optionally, the semiconductor device further includes:
[0040] A third recessed hole is formed in the substrate corresponding to the gate of the high-voltage device formation region, wherein the gate dielectric layer formed in the high-voltage device formation region fills the third recessed hole and extends above the third recessed hole.
[0041] Using the semiconductor device manufacturing method provided by the present invention, a high-voltage MOS device, a medium-voltage MOS device, and a low-voltage MOS device can be formed in a high-voltage device formation region, a medium-voltage device formation region, and a low-voltage device formation region, respectively. In the medium-voltage device formation region, the gate dielectric layer has a structure that is thinner in the middle and thicker at both ends along the channel length direction. In addition to a second medium-voltage gate dielectric layer located on the substrate surface, the two ends of the gate dielectric layer also have a first medium-voltage gate dielectric layer filled in the first and second recesses. When a high voltage is applied to the drain region, the thicker end of the gate dielectric layer can weaken the electric field from the drain end to the gate in the gate-drain overlap region, reducing the risk of GIDL leakage.
[0042] The semiconductor device provided by the present invention includes a high-voltage MOS device, a medium-voltage MOS device, and a low-voltage MOS device formed in the high-voltage device formation region, the medium-voltage device formation region, and the low-voltage device formation region, respectively. Furthermore, the gate dielectric layer in the medium-voltage device formation region has a structure that is thinner in the middle and thicker at both ends along the channel length direction. In addition to a second medium-voltage gate dielectric layer located on the substrate surface, the two ends of the gate dielectric layer also have a first medium-voltage gate dielectric layer filled in the first and second recesses. When a high voltage is applied to the drain region, the thicker end of the gate dielectric layer can weaken the electric field from the drain end to the gate in the gate-drain overlap region, thereby reducing the risk of GIDL leakage. Attached Figure Description
[0043] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0044] Figures 2A to 2L This is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation
[0045] The semiconductor device and its manufacturing method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be understood that the accompanying drawings are in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order in which these steps are performed; some steps may be omitted and / or other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation other than the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or otherwise positioned (e.g., rotated), the exemplary term "on" may also include "below" and other orientational relationships.
[0046] The following first combines Figures 1 to 2L This invention describes a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0047] Reference Figure 1 and Figure 2A According to the semiconductor device manufacturing method of the present invention, in step S1, a substrate 100 is provided, wherein a high voltage device formation region 10, a medium voltage device formation region 20 and a low voltage device formation region (not shown) are arranged laterally on the surface region of the substrate 100.
[0048] The substrate 100 may be a silicon substrate, a germanium silicon substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-on-insulator silicon substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or other substrates known to those skilled in the art for carrying MOS devices. Furthermore, doped regions and / or isolation structures may be formed in the substrate 100. In the following embodiments, the substrate 100 is, for example, a silicon substrate.
[0049] The high-voltage device formation region 10, the medium-voltage device formation region 20, and the low-voltage device formation region are arranged laterally on the surface of the substrate 100. The high-voltage device formation region 10 is used to form high-voltage MOS devices with high operating voltages. The low-voltage device formation region is used to form low-voltage MOS devices with lower operating voltages. The medium-voltage device formation region 20 is used to form medium-voltage MOS devices with operating voltages lower than the high-voltage MOS devices but higher than the low-voltage MOS devices. For example, the operating voltage of the low-voltage MOS device is less than 3V, the operating voltage of the medium-voltage MOS device is approximately 3V to 10V, and the operating voltage of the high-voltage MOS device is greater than 10V. This invention is not limited to this; the operating voltages of the low-voltage MOS devices, the medium-voltage MOS devices, and the high-voltage MOS devices can be set according to actual conditions. For example, a high-voltage device formation region 10 is used to form a high-voltage MOS device, a medium-voltage device formation region 20 is used to form a medium-voltage MOS device, and a low-voltage device formation region is used to form a low-voltage MOS device. At least one high-voltage device formation region 10, at least one medium-voltage device formation region 20, and at least one low-voltage device formation region may be arranged on the surface region of the same substrate 100.
[0050] Reference Figure 2A As an example, in a high-voltage device formation region 10, an N-channel MOS device is to be formed. Corresponding to this high-voltage device formation region 10, a high-voltage P-well (shown as HVPW) may be formed in the substrate 100, the upper part of which is surrounded by a shallow trench isolation (STI). The N-channel MOS device is, for example, an LDMOS device or other types of high-voltage MOS devices. Figure 2AAs shown, before proceeding to subsequent steps, a first drift region 11, a second drift region 12, and a guard ring region 13 can be formed on the upper part of the high-voltage P-well by ion implantation. The first drift region 11 and the second drift region 12 extend from the interior of the substrate 100 to the surface of the substrate 100 and overlap with the gate of the high-voltage MOS device to be formed. The guard ring region 13 extends from the interior of the substrate 100 to the surface of the substrate 100 and surrounds the regions of the first drift region 11, the second drift region 12, and the gate of the high-voltage MOS device to be formed. The first drift region 11 and the second drift region 12 are, for example, N-type doped, and the guard ring region 13 is, for example, P-type doped. Furthermore, the guard ring region 13 is isolated from the first drift region 11 and from the second drift region 12 by shallow trench isolation (STI). A shallow trench isolation (STI) is provided on the outer side of the guard ring region 13 to isolate the guard ring region 13 from other surrounding structures. Subsequently, high-voltage source / drain regions are formed in the first drift region 11 and the second drift region 12, respectively. To alleviate the electric field between the high-voltage source / drain regions and the corresponding gates, shallow trench isolation (STI) regions are formed in both the first drift region 11 and the second drift region 12. As an example, if a P-channel MOS device is to be formed in a medium-voltage device formation region 20, a deep N-well (denoted as DNW) can be formed in the substrate 100 corresponding to the medium-voltage device formation region 20, and the upper part of the deep N-well is surrounded by shallow trench isolation (STI). A medium-voltage N-well can also be formed on the upper part of the deep N-well. In other embodiments, a P-channel MOS device can also be formed in a high-voltage device formation region 10, and an N-channel MOS device can also be formed in a medium-voltage device formation region 10. In this case, the doping type of the well region formed in the substrate 100 can be adjusted according to the type of device to be formed.
[0051] Reference Figure 1 , Figures 2A to 2E According to the semiconductor device manufacturing method of the present invention, in step S2, a first recess H1 and a second recess H2 are formed at the two ends of the gate to be formed in the medium-voltage device forming region 20 along the channel length direction, and a first medium-voltage gate dielectric layer 110 is formed in the first recess H1 and the second recess H2.
[0052] To form the first recess H1 and the second recess H2, a corresponding mask can be formed on the surface of the substrate 100, and the corresponding area of the substrate 100 can be etched to form the first recess H1 and the second recess H2. In this embodiment, the process of forming the gate dielectric layer in the medium-voltage device formation region 20 is compatible with the process of forming the gate dielectric layer in the high-voltage device formation region 10, which can save process steps. In this embodiment, while forming the first recess H1 and the second recess H2 in the medium-voltage device formation region 20, a third recess is also formed in the high-voltage device formation region 10 to facilitate the subsequent formation of a thicker gate dielectric layer in the high-voltage device formation region 10 that meets the requirements of high-voltage MOS devices.
[0053] As an example, step S2 may include the following process.
[0054] First, refer to Figure 2A A pad oxide layer 101 (e.g., silicon oxide) and a patterned first mask layer 102 (e.g., silicon nitride) are formed on the surface of the substrate 100. In the medium-voltage device formation region 20, the first mask layer 102 forms a first opening 102a and a second opening 102b corresponding to the formation regions at both ends of the gate along the channel length direction. Optionally, in the high-voltage device formation region 10, the first mask layer 102 forms a third opening 102c corresponding to the formation region of the gate.
[0055] Next, refer to Figure 2B A first oxidation process (such as thermal oxidation) is performed to oxidize the substrate 100 below the first opening 102a and the second opening 102b of the first mask layer 102 to a set depth, forming a first recess H1 below the first opening 102a and a second recess H2 below the second opening 102b in the substrate 100 of the medium-voltage device formation region 20. Optionally, a third recess H3 below the third opening 102c is also formed in the substrate 100 of the high-voltage device formation region 10.
[0056] After the first oxidation process, the substrate 100 below the first opening 102a and the second opening 102b is oxidized, that is, a first oxide OX1 is formed embedded in the surface of the substrate 100 corresponding to the first opening 102a and the second opening 102b, respectively. The thickness of the first oxide OX1 is, for example, [missing information]. For example, In some embodiments, the first oxide OX1 formed in the substrate 100 below the first opening 102a and the second opening 102b is used as part of the gate dielectric layer to be formed in the corresponding medium voltage device formation region 20 (i.e., as the first medium voltage gate dielectric layer). Subsequently, a second medium voltage gate dielectric layer can be formed on the surface of the substrate 100 and the surface of the first oxide OX1 in the medium voltage device formation region 20, so that the gate dielectric layer formed below both ends of the gate is a thicker stack of the first oxide OX1 and the second medium voltage gate dielectric layer.
[0057] In this embodiment, the process of forming a gate dielectric layer in the medium-voltage device formation region 20 is combined with the process of forming a gate dielectric layer in the high-voltage device formation region 10. After the first oxidation process, the first oxide OX1 formed is not used to form a gate dielectric layer, but is removed to regenerate the gate dielectric material, so as to form a thicker gate dielectric layer in the high-voltage device formation region 10 that is higher than the surface of the substrate 100.
[0058] Specifically, in this embodiment, after the first oxidation process, firstly, referring to... Figure 2C The oxide (i.e., the first oxide OX1) formed in the substrate 100 by the first oxidation process is removed, exposing the first recess H1, the second recess H2, and the third recess H3; then, referring to Figure 2D A second oxidation process (such as thermal oxidation) is performed to form a second oxide OX2. The second oxide OX2 fills the third recess H3 and extends above the third recess H3, thereby also filling the third opening 102c; it fills the first recess H1 and extends above the first recess H1, thereby also filling the first opening 102a; and it fills the second recess H2 and extends above the second recess H2, thereby also filling the second opening 102b. Then, refer to... Figure 2E Remove the first mask layer 102, wherein the second oxide OX2 formed in the high-voltage device formation region 10 corresponding to the third recess H3 is the gate dielectric layer of the high-voltage MOS device to be fabricated, and its thickness is, for example, [missing information]. The second oxide OX2 formed in the medium-voltage device formation region 20 corresponding to the first recess H1 and the second recess H2 is too thick for the medium-voltage MOS device to be manufactured, so it is subsequently thinned. The second oxide OX2 filled in the first recess H1 and the second recess H2 is part of the gate dielectric layer of the medium-voltage MOS device, namely the first medium-voltage gate dielectric layer 110.
[0059] Reference Figure 1 , Figures 2F to 2J According to the semiconductor device manufacturing method of the present invention, in step S3, corresponding gate stacks including a gate dielectric layer and a gate are formed in the high voltage device formation region 10, the medium voltage device formation region 20 and the low voltage device formation region, respectively. In the medium voltage device formation region 20, the gate dielectric layer includes a first medium voltage gate dielectric layer 110 and a second medium voltage gate dielectric layer 120 between the substrate 100 and the corresponding gate, and the second medium voltage gate dielectric layer 120 covers the first medium voltage gate dielectric layer 110.
[0060] In this embodiment, the gate dielectric layer formed in the high voltage device formation region 10 is the second oxide OX2 formed in the high voltage device formation region 10 corresponding to the third concave hole H3 in step S2. The gate to be formed in the high voltage device formation region 10 can be formed synchronously with the gate in the medium voltage device formation region 20 and the gate in the low voltage device formation region. The following mainly describes the process of forming the gate dielectric layer and the gate in the medium voltage device formation region 20.
[0061] like Figure 2EAs shown, in this embodiment, the second oxide OX2 formed in the medium-voltage device formation region 20 includes a first medium-voltage gate dielectric layer 110 located in the first recess H1 and the second recess H2. In order to reduce the thickness of the second oxide OX2 in the medium-voltage device formation region 20 and further form the second medium-voltage gate dielectric layer and the gate in the medium-voltage device formation region 20, step S3 may include the following process.
[0062] First, refer to Figure 2F A patterned second mask layer is formed on the substrate 100, with openings in the second mask layer corresponding to the formation of a first recess H1 and a second recess H2, respectively, to expose a second oxide OX2 formed at the first recess H1 and the second recess H2. The second mask layer includes, for example, a hard mask layer 103 (e.g., silicon nitride) and a photoresist layer 104, wherein the hard mask layer 103 helps to improve etching accuracy.
[0063] Then, refer to Figure 2G Using the second mask layer, the exposed second oxide OX2 is etched to thin the second oxide OX2 at the first recess H1 and the second recess H2 while still filling the first recess H1 and the second recess H2. For example, the upper surface of the thinned second oxide OX2 can be made substantially flush with the upper surface of the pad oxide layer 101 by controlling the etching time.
[0064] Then, remove the second mask layer, as follows: Figure 2H As shown.
[0065] Next, refer to Figure 2I LDD implantation is performed within the substrate 100 of the medium-voltage device formation region 20 to form a medium-voltage LDD region. Optionally, a medium-voltage well can be formed in the substrate 100 corresponding to the medium-voltage device formation region 20 before or after this LDD implantation. Figure 2J The medium-voltage well (represented as MVNW) is, for example, N-type doped and located within the deep N-well (DNW) formed corresponding to the medium-voltage device formation region 20. As an example, if a P-channel medium-voltage MOS device is to be fabricated in the medium-voltage device formation region 20, the LDD implantation is, for example, P-type LDD implantation (e.g., implantation of boron (B) or boron fluoride (BF2)). It should be understood that when the medium-voltage device formation region 20 is to be fabricated as an N-channel medium-voltage MOS device, N-type LDD implantation (e.g., implantation of phosphorus (P) or arsenic (As)) is performed; when the medium-voltage device formation region 20 is to form both an N-channel and a P-channel medium-voltage MOS device, N-type LDD implantation and P-type LDD implantation are performed in the corresponding regions respectively.
[0066] Then, refer to Figure 2JWet etching or other suitable processes can be used to remove the pad oxide layer 101 and the second oxide OX2 on the substrate 100 located in the medium voltage device formation region 20.
[0067] In this embodiment, when removing the pad oxide layer 101 on the substrate 100 of the intermediate voltage device formation region 20, a mask layer is used to protect the high voltage device formation region 10, so that the pad oxide layer 101 and the second oxide OX2 on the substrate 100 of the high voltage device formation region 10 are retained. However, this is not the only embodiment. For example, in some other embodiments, when removing the pad oxide layer 101 on the substrate 100 of the intermediate voltage device formation region 20, the pad oxide layer 101 on the substrate 100 of the high voltage device formation region 10 may also be removed simultaneously, but the second oxide OX2, which serves as the gate dielectric layer in the high voltage device formation region 10, is retained. For clarity, Figure 2J Only the medium-voltage device formation area 20 is shown.
[0068] Next, refer to Figure 2K On the substrate 100 of the medium-voltage device formation region 20, a gate dielectric material layer (such as silicon oxide, which can be formed by one or two depositions) and a gate material layer (such as polysilicon) are stacked sequentially, and the gate dielectric material layer and the gate material layer are etched to form a second medium-voltage gate dielectric layer 120 from the gate dielectric material layer, and a gate G1 located on the second medium-voltage gate dielectric layer 120 is formed from the gate material layer.
[0069] The thickness of the gate dielectric material layer and the gate material layer can be specifically set according to the device design. For example, the thickness of the second medium-voltage gate dielectric layer 120 can be set according to the threshold voltage requirements of the medium-voltage MOS device to be formed in the medium-voltage device formation region 20.
[0070] In this embodiment, the substrate 100 further includes a low-voltage device formation region. When the gate dielectric material layer is formed on the substrate 100, the gate dielectric material layer can also be formed in the low-voltage device formation region. After the gate dielectric material layer is formed, the gate dielectric material layer deposited in the low-voltage device formation region can be removed, and a new gate dielectric layer that meets the requirements of the low-voltage device formation region can be formed. When the gate material layer is formed, it is also formed in the high-voltage device formation region 10 and the low-voltage device formation region. In the step of etching the gate dielectric material layer and the gate material layer, a pattern mask defining the gate of the high-voltage device formation region 10, the medium-voltage device formation region 20, and the low-voltage device formation region can be provided. The gate dielectric material layer and the gate material layer can be etched using this pattern mask, so that after etching is completed, in addition to... Figure 2J In addition to the stacked layer including the second medium-voltage gate dielectric layer 120 and the gate G1 formed in the medium-voltage device formation region 20, corresponding gate stacked layers including the gate dielectric layer and the gate can also be formed in the high-voltage device formation region 10 and the low-voltage device formation region, respectively.
[0071] like Figure 2J As shown, the gate G1 has two ends arranged along the channel length direction and a gate middle portion located between the two ends. The gate middle portion is separated from the substrate 100 by a second medium-voltage gate dielectric layer 120. The two ends are separated from the substrate 100 by the second medium-voltage gate dielectric layer 120 and a first medium-voltage gate dielectric layer 110 located below the second medium-voltage gate dielectric layer 120. That is, the gate dielectric layer formed in the medium-voltage device formation region 20 includes a first medium-voltage gate dielectric layer 110 embedded in the surface of the substrate 100 and a second medium-voltage gate dielectric layer 120 formed on the surface of the substrate 100 and covering the first medium-voltage gate dielectric layer 110. The gate dielectric layer has a structure that is thinner in the middle and thicker at both ends along the channel length direction. In this way, for the medium-voltage MOS device formed in the medium-voltage device formation region 20, when a high voltage is applied to the drain region, the thicker ends of the gate dielectric layer can weaken the electric field from the drain end to the gate in the gate-drain overlap region, reducing the risk of GIDL leakage.
[0072] Still refer to Figure 2K Since the first intermediate-voltage gate dielectric layer 110 is located below the end of the gate G1, its impact on the threshold voltage of the corresponding intermediate-voltage MOS device is relatively small. Alternatively, to prevent the first intermediate-voltage gate dielectric layer 110 from exceeding the drain doped region and occupying the channel region, which might affect the threshold voltage of the intermediate-voltage MOS device, such as... Figure 2K As shown, in the medium-voltage device formation region 20, two LDD regions are located on both sides of the corresponding gate G1, and both LDD regions overlap with the corresponding gate G1. The width of the overlapping area is greater than or equal to the width of the first recess H1 and the second recess H2. For example, the inner boundary of the first recess H1 is flush with the side of the LDD region on the same side located below the gate G1, and the inner boundary of the second recess H2 is flush with the side of the LDD region on the same side located below the gate G1.
[0073] Reference Figure 1 and Figure 2L According to the semiconductor device manufacturing method of the present invention, in step S4, a sidewall SP is formed on the side of the gate stack, and a source region S and a drain region D located on both sides of the corresponding gate stack are formed on the side of the sidewall SP opposite to the gate stack.
[0074] The sidewall SP may include at least one dielectric material such as silicon nitride, silicon oxide, and silicon oxynitride, and may be formed as a single layer or multiple layers (i.e., two or more layers, the same below). As an example, the sidewall SP is a double-layer sidewall, and the formation of the sidewall SP may include the following process: forming a first sidewall material layer on the substrate 100 in a conformal manner; etching the first sidewall material layer using an anisotropic etching process to form a first sidewall located on the side of the gate stack; performing LDD implantation to form the LDD region of the corresponding low-voltage MOS device in the substrate 100 of the low-voltage device formation region; then, forming a second sidewall material layer on the substrate 100 in a conformal manner; etching the second sidewall material layer using an anisotropic etching process to form a second sidewall located on the side of the gate stack, wherein the first sidewall and the second sidewall constitute the sidewall SP.
[0075] In this embodiment, the sidewall SP structures formed in the medium-voltage device formation region 20 and the low-voltage device formation region are identical and have the same thickness. The thickness of the sidewall SP can be set according to the requirements of the low-voltage MOS device to be formed in the low-voltage device formation region. For example, when the thickness of the first sidewall and / or the second sidewall is thinner according to the requirements of the low-voltage MOS device, and thus the sidewall SP is thinner, the sidewall thickness of the medium-voltage MOS device formed in the medium-voltage device formation region 20 is also thinner.
[0076] When forming the source region S and drain region D, n-type or p-type source / drain ion implantation can be performed first, depending on the type of device to be fabricated. When the types of devices to be formed in the high-voltage device formation region 10, the medium-voltage device formation region 20, and the low-voltage device formation region are different, n-type source / drain ion implantation and p-type source / drain ion implantation can be performed respectively. After the source / drain ion implantation is completed, annealing is performed, and the corresponding source region S and drain region D are formed in the high-voltage device formation region 10, the medium-voltage device formation region 20, and the low-voltage device formation region.
[0077] Using the semiconductor device manufacturing method described in the above embodiments, a high-voltage MOS device, a medium-voltage MOS device, and a low-voltage MOS device can be formed in the high-voltage device formation region 10, the medium-voltage device formation region 20, and the low-voltage device formation region, respectively. In the medium-voltage device formation region 20, the gate dielectric layer has a structure that is thinner in the middle and thicker at both ends along the channel length direction. The two ends of the gate dielectric layer have a first medium-voltage gate dielectric layer 110 located in the first recess H1 and the second recess H2 on the surface of the substrate 100, and a second medium-voltage gate dielectric layer 120 located on the first medium-voltage gate dielectric layer 110, respectively. When a high voltage is applied to the drain region D, the thicker end of the gate dielectric layer can weaken the electric field from the drain end to the gate G1 in the gate-drain overlap region, thereby reducing the risk of GIDL leakage.
[0078] This invention also relates to a semiconductor device. The semiconductor device can be formed using the manufacturing method of the semiconductor device described in the above embodiments or other methods. (Refer to...) Figure 2A and Figure 2L The semiconductor device includes:
[0079] Substrate 100, wherein a high voltage device formation region 10, a medium voltage device formation region 20 and a low voltage device formation region are laterally arranged on the surface region of the substrate 100;
[0080] Gate stacks including a gate dielectric layer and a gate are formed respectively in the high-voltage device formation region 10, the medium-voltage device formation region 20, and the low-voltage device formation region. In the medium-voltage device formation region 20, the gate (e.g., ...) Figure 2L The G1 shown includes two ends arranged along the length of the channel and a gate middle portion located between the two ends. Corresponding to the two ends of the gate, a first recess H1 and a second recess H2 are respectively formed in the substrate 100. The gate dielectric layer of the medium voltage device formation region 20 includes a first medium voltage gate dielectric layer 110 formed in the first recess H1 and the second recess H2 and a second medium voltage gate dielectric layer 120 formed on the substrate 100 and covering the first medium voltage gate dielectric layer 110.
[0081] Sidewalls SP formed on the side of the gate stack;
[0082] Source region S and drain region D are formed on the side of the sidewall SP opposite to the gate stack on both sides of the corresponding gate stack.
[0083] The substrate 100 is, for example, a silicon substrate. In this embodiment, at least one doped well region may be formed in the substrate 100. The high-voltage device formation region 10 is used to form a high-voltage MOS device with a high operating voltage, the low-voltage device formation region 20 is used to form a low-voltage MOS device with a lower operating voltage, and the medium-voltage device formation region is used to form a medium-voltage MOS device with an operating voltage lower than that of the high-voltage MOS device and higher than that of the low-voltage MOS device.
[0084] like Figure 2L As shown, the semiconductor substrate may further include an LDD region formed in the substrate 100 of the medium-voltage device formation region 20, wherein the two LDD regions are respectively located on both sides of the corresponding gate G1, and the two LDD regions overlap with the corresponding gate G1, and the width of the overlapping area is greater than or equal to the width of the first recess H1 and the second recess H2.
[0085] Reference Figures 2B to 2IThe semiconductor device may further include a third recess H3, which corresponds to the gate (not shown) of the high-voltage device formation region 10 formed in the substrate 100, wherein the gate dielectric layer formed in the high-voltage device formation region 10 fills the third recess H3 and extends above the third recess H3, for example, as shown in the figure. Figure 2I The second oxide OX2 shown in the high voltage device formation region 10 is the gate dielectric layer of the high voltage device formation region 10.
[0086] As an example, an HVMOS device is formed in the high-voltage device formation region 10. (Refer to...) Figures 2A to 2I In the substrates 100 on both sides of the gate stack of the high-voltage device formation region 10, a first drift region 11 and a second drift region 12 may be formed respectively. The first drift region 11 and the second drift region 12 extend from the substrate 100 to the surface of the substrate 100 and overlap with the gate of the corresponding high-voltage device formation region 10. The source region of the high-voltage device formation region 10 is disposed, for example, on top of the first drift region 11 and at a predetermined distance from the corresponding gate stack. The drain region of the high-voltage device formation region 10 is disposed, for example, on top of the second drift region 12 and at a predetermined distance from the corresponding gate stack. In addition, a guard ring region 13 may also be formed in the substrates 100 on both sides of the gate stack of the high-voltage device formation region 10. The guard ring region 13 surrounds the first drift region 11, the second drift region 12 and the corresponding gate stack.
[0087] The semiconductor device described in the above embodiments includes a high-voltage MOS device, a medium-voltage MOS device, and a low-voltage MOS device formed in a high-voltage device formation region 10, a medium-voltage device formation region 20, and a low-voltage device formation region, respectively. In the medium-voltage device formation region 20, the gate dielectric layer has a structure that is thinner in the middle and thicker at both ends along the channel length direction. In addition to having a second medium-voltage gate dielectric layer 120 located on the surface of the substrate 100, the two ends of the gate dielectric layer also have a first medium-voltage gate dielectric layer 110 filled in the first recess H1 and the second recess H2. When a high voltage is applied to the drain region D, the thicker end of the gate dielectric layer can weaken the electric field from the drain end to the gate in the gate-drain overlap region, thereby reducing the risk of GIDL leakage.
[0088] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.
[0089] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, wherein a high-voltage device formation region, a medium-voltage device formation region, and a low-voltage device formation region are laterally arranged on the surface region of the substrate; A first recess and a second recess are formed at the two ends of the gate to be formed in the medium-voltage device formation region along the channel length direction, and a first medium-voltage gate dielectric layer is formed in the first recess and the second recess. A gate stack including a gate dielectric layer and a gate is formed in the high voltage device formation region, the medium voltage device formation region and the low voltage device formation region respectively. In the medium voltage device formation region, the gate dielectric layer includes a first medium voltage gate dielectric layer and a second medium voltage gate dielectric layer between the substrate and the corresponding gate. The second medium voltage gate dielectric layer covers the first medium voltage gate dielectric layer. as well as Sidewalls are formed on the side of the gate stack, and source and drain regions are formed on the side of the sidewall opposite to the gate stack, respectively, located on both sides of the corresponding gate stack.
2. The manufacturing method as described in claim 1, characterized in that, Forming the first recess and the second recess includes: A pad oxide layer and a patterned first mask layer are formed on the substrate surface, such that in the intermediate voltage device formation region, the first mask layer has a first opening and a second opening corresponding to the formation regions of the respective two ends of the gate; and A first oxidation process is performed to oxidize the substrate below the first opening and the second opening to a set depth, thereby forming a first recess below the first opening and a second recess below the second opening in the substrate of the medium-voltage device forming region.
3. The manufacturing method as described in claim 2, characterized in that, The first oxide formed in the substrate of the medium-voltage device formation region by the first oxidation process is the first medium-voltage gate dielectric layer.
4. The manufacturing method as described in claim 2, characterized in that, After patterning the first mask layer, a third opening is formed in the high-voltage device formation region corresponding to the formation region of the corresponding gate in the first mask layer. After performing the first oxidation process, a third recess is formed in the substrate of the high-voltage device formation region below the third opening.
5. The manufacturing method as described in claim 4, characterized in that, The formation of the first medium-voltage gate dielectric layer includes: Remove the oxide formed in the substrate by the first oxidation process to expose the first recess, the second recess, and the third recess; A second oxidation process is performed to form a second oxide, which fills the third recess and extends above it, fills the first recess and extends above it, and fills the second recess and extends above it. Remove the first mask layer, wherein the portion of the second oxide filling the third recess and extending onto the third recess is a high-voltage gate dielectric layer, and the second oxide in the first recess and the second recess is a first medium-voltage gate dielectric layer.
6. The manufacturing method as described in claim 5, characterized in that, The formation of the second medium-voltage gate dielectric layer includes: A patterned second mask layer is formed on the substrate, wherein openings in the second mask layer correspond to the formation of the first and second recesses, respectively, to expose the second oxide formed at the first and second recesses; and Using the second mask layer, the exposed second oxide is etched to thin the second oxide at the first and second recesses while still filling the first and second recesses; LDD implantation is performed to form an LDD region within the substrate of the medium-voltage device formation region; Remove the pad oxide layer and the second oxide layer from the substrate located in the medium-voltage device formation region; and A gate dielectric material layer and a gate material layer are sequentially stacked on the substrate of the medium-voltage device formation region, and the gate dielectric material layer and the gate material layer are etched to form a second medium-voltage gate dielectric layer from the gate dielectric material layer. A gate located on the second medium-voltage gate dielectric layer is formed from the gate material layer. The two ends of the gate have the second medium-voltage gate dielectric layer and the first medium-voltage gate dielectric layer located below the second medium-voltage gate dielectric layer.
7. The manufacturing method as described in claim 6, characterized in that, In the medium-voltage device forming region, the two LDD regions are respectively located on both sides of the corresponding gate, and both LDD regions overlap with the corresponding gate, and the width of the overlapping area is greater than or equal to the width of the first recess and the second recess.
8. The manufacturing method as described in claim 1, characterized in that, Forming sidewalls on the side surfaces of the gate stack includes: A first sidewall material layer is formed conformally on the substrate; The first sidewall material layer is etched using an anisotropic etching process to form a first sidewall located on the side of each of the gate stacks; LDD implantation is performed to form a corresponding LDD region in the substrate of the low-voltage device formation region; A second sidewall material layer is formed conformally on the substrate; and The second sidewall material layer is etched using an anisotropic etching process to form a second sidewall located on the side of each of the gate stacks.
9. A semiconductor device, characterized in that, include: A substrate, wherein a high-voltage device formation region, a medium-voltage device formation region, and a low-voltage device formation region are arranged laterally on the surface region of the substrate; A gate stack comprising a gate dielectric layer and a gate is formed in the high-voltage device formation region, the medium-voltage device formation region, and the low-voltage device formation region, respectively. In the medium-voltage device formation region, the gate includes two ends arranged along the channel length direction and a gate middle portion located between the two ends. A first recess and a second recess are formed in the substrate corresponding to the two ends of the gate. The gate dielectric layer includes a first medium-voltage gate dielectric layer formed in the first recess and the second recess and a second medium-voltage gate dielectric layer formed on the surface of the substrate and covering the first medium-voltage gate dielectric layer. Sidewalls formed on the sides of each of the gate stacks; as well as Source and drain regions are formed on the sides of the sidewall opposite to the gate stack, respectively, on both sides of the corresponding gate stack.
10. The semiconductor device as claimed in claim 9, characterized in that, Also includes: An LDD region is formed in the substrate of the medium-voltage device formation region, wherein, in the medium-voltage device formation region, the two LDD regions are respectively located on both sides of the corresponding gate, and both LDD regions overlap with the corresponding gate, and the width of the overlapping area is greater than or equal to the width of the first recess and the second recess.
11. The semiconductor device as claimed in claim 9, characterized in that, Also includes: A third recessed hole is formed in the substrate corresponding to the gate of the high-voltage device formation region, wherein the gate dielectric layer formed in the high-voltage device formation region fills the third recessed hole and extends above the third recessed hole.