Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device may include: a first impurity pattern and a second impurity pattern spaced apart from each other in a first direction on a substrate, where the first direction may be parallel to an upper surface of the substrate, and where the first impurity pattern and the second impurity pattern may include impurities having different conductivity types; a first semiconductor pattern between the first impurity pattern and the second impurity pattern; and a first gate pattern intersecting the first semiconductor pattern. The first gate pattern may include a gate region and an extension region. The gate region may extend in a second direction, which may intersect the first direction. The extension region may extend from the gate region in a first direction.

Description

Intersection of related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0112992, filed on August 22, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and / or a method for manufacturing the semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor and / or a method for manufacturing the semiconductor device. Background Technology

[0003] Semiconductor devices can include integrated circuits with metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to shrink, the miniaturization of MOSFETs is also accelerating. However, as MOSFETs become increasingly miniaturized, the operating characteristics of semiconductor devices may deteriorate. Accordingly, various methods are being investigated to overcome the limitations caused by the high integration density of semiconductor devices and / or to form semiconductor devices with improved performance. Summary of the Invention

[0004] This disclosure provides a semiconductor device with improved electrical properties and / or a method for manufacturing the semiconductor device.

[0005] This disclosure also provides a semiconductor device with improved productivity and / or integration and / or a method for manufacturing the semiconductor device.

[0006] The inventive concept is not limited to the aspects described above, and other technical aspects not mentioned may be understood by those skilled in the art from the following description.

[0007] According to embodiments of the present invention, a semiconductor device may include: a first impurity pattern and a second impurity pattern, spaced apart from each other on a substrate along a first direction parallel to an upper surface of the substrate, wherein the first impurity pattern includes impurities of a different conductivity type than those in the second impurity pattern; a first semiconductor pattern, located between the first and second impurity patterns; and a first gate pattern intersecting the first semiconductor pattern. The first gate pattern may include a gate region extending along a second direction and an extension region extending from the gate region in the first direction. The second direction may intersect the first direction.

[0008] According to embodiments of the present invention, a semiconductor device may include: a first impurity pattern and a second impurity pattern, spaced apart from each other on a substrate along a first direction parallel to an upper surface of the substrate; the first impurity pattern including impurities of a different conductivity type than those in the second impurity pattern; a first semiconductor pattern between the first and second impurity patterns; and a first gate pattern intersecting the first semiconductor pattern. The first gate pattern may include gate regions adjacent to each other along the first direction. Each gate region may extend in a second direction. The second direction may intersect the first direction. The first gate pattern may also include extended regions between the gate regions of the first gate pattern.

[0009] According to embodiments of the present invention, a semiconductor device may include: a first impurity pattern and a second impurity pattern, spaced apart from each other on a substrate along a first direction parallel to an upper surface of the substrate, wherein the first impurity pattern includes impurities of a different conductivity type than those in the second impurity pattern; a first semiconductor pattern, between the first and second impurity patterns; a second semiconductor pattern, spaced apart from the first semiconductor pattern, wherein the first impurity pattern is between the second and first semiconductor patterns, each of the first and second semiconductor patterns including a plurality of semiconductor layers stacked on the substrate; a first gate pattern intersecting the first semiconductor pattern; a second gate pattern intersecting the second semiconductor pattern; an inner gate spacer, between the first impurity pattern and the first gate pattern; and a rear surface active contact, below at least one of the first and second impurity patterns. The first gate pattern may include gate regions and extended regions between gate regions. Gate regions may be adjacent to each other in the first direction. Each gate region may extend in a second direction. The second direction may intersect the first direction. Attached Figure Description

[0010] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0011] Figure 1 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention;

[0012] Figure 2 It is along Figure 1 A cross-sectional view taken by line A-A';

[0013] Figure 3A It is along Figure 1 A cross-sectional view taken by line A-A';

[0014] Figure 3B It is along Figure 1 A cross-sectional view taken by line A-A';

[0015] Figure 4 It is along Figure 1 A cross-sectional view taken by line A-A';

[0016] Figure 5 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention;

[0017] Figure 6 It is along Figure 5 A cross-sectional view taken by line A-A';

[0018] Figure 7 It is along Figure 5 A cross-sectional view taken by line A-A';

[0019] Figure 8 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention;

[0020] Figure 9 It is along Figure 8 A cross-sectional view taken by line A-A';

[0021] Figure 10 It is along Figure 8 A cross-sectional view taken by line A-A';

[0022] Figure 11 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention;

[0023] Figure 12 It is along Figure 11 A cross-sectional view taken by line A-A';

[0024] Figure 13 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention;

[0025] Figure 14 It is along Figure 13 A cross-sectional view taken by line A-A';

[0026] Figure 15 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention;

[0027] Figure 16 It is along Figure 15 A cross-sectional view taken by line A-A';

[0028] Figure 17 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention;

[0029] Figures 18 to 21 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention;

[0030] Figure 22 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention;

[0031] Figure 23 These are diagrams illustrating methods for manufacturing semiconductor devices according to some embodiments of the present invention; and

[0032] Figure 24 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept of the present invention. Detailed Implementation

[0033] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the associated numerical value is intended to include manufacturing or operational tolerances (e.g., ±10%) near the value. Furthermore, when the terms “generally” and “substantially” are used in conjunction with geometry, it is intended not to require precision of the geometry, but rather a tolerance of the shape within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified to “about” or “substantially,” it should be understood that these values ​​and shapes should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) near the value or shape. When a range is specified, the range includes all values ​​within that range, such as increments of 0.1%.

[0034] The concept of "substantially identical" components can mean that components can be completely identical, or it can mean that components can be determined to be identical considering errors or deviations that occur during the process.

[0035] In the following description, embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings, so as to more specifically illustrate the inventive concept.

[0036] Figure 1 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0037] Reference Figure 1 and Figure 2A substrate 100 comprising a first region PR1, a second region PR2, and a third region PR3 may be provided. For example, the substrate 100 may be a semiconductor substrate or a compound semiconductor substrate comprising at least one of silicon, germanium, or silicon-germanium. In this disclosure, each of the terms “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C” may include any one or all possible combinations of the items listed together with the corresponding phrase. For example, “at least one of A, B, and C” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC. For example, the substrate 100 may have a plate-like shape extending along a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may be parallel to the upper surface of the substrate 100 and may intersect each other. Regions PR1, PR2, and PR3 from the first region to the third region can be adjacent to each other in the first direction D1.

[0038] The active pattern ACT may be defined by a trench (not shown) on the upper part of the substrate 100. The active pattern ACT may extend on the substrate 100 along a first direction D1. The active pattern ACT may be a portion of the substrate 100. For example, this portion of the substrate 100 may protrude in a third direction D3. The third direction D3 may be a direction perpendicular to the upper surface of the substrate 100. For ease of description, in this specification, unless otherwise described separately, the substrate 100 is defined as any portion of the substrate 100 other than this portion (in other words, the active pattern ACT).

[0039] The active pattern ACT may include a well region WE. The well region WE may include at least one of N-type or P-type conductive impurities. The well region WE may include a first well region WE1 on each of a first region PR1 and a third region PR3, and a second well region WE2 on a second region PR2. For example, the first well region WE1 may include an N-type conductive impurity, and the second well region WE2 may include a P-type conductive impurity. Accordingly, a PN junction may be formed between the first well region WE1 on the first region PR1 and the second well region WE2 on the second region PR2. Similarly, a PN junction may be formed between the second well region WE2 on the second region PR2 and the first well region WE1 on the third region PR3.

[0040] Component isolation patterns (not shown) including insulating material can be disposed on substrate 100 and can fill trenches.

[0041] Each of the first semiconductor pattern CH1 and the second semiconductor pattern CH2 can be disposed on the active pattern ACT. Each of the first semiconductor pattern CH1 and the second semiconductor pattern CH2 can be multiple. The first semiconductor patterns CH1 can be disposed spaced apart from each other along a first direction D1. The second semiconductor patterns CH2 can be disposed spaced apart from each other along the first direction D1.

[0042] Each of the first semiconductor pattern CH1 and the second semiconductor pattern CH2 may include a first semiconductor layer SP1, a second semiconductor layer SP2, and a third semiconductor layer SP3 that are adjacent to each other along a third direction D3, but embodiments of the present invention are not limited thereto. For example, the first semiconductor pattern CH1 may include at least four semiconductor layers. Each of the first to third semiconductor layers SP1, SP2, and SP3 may include crystalline silicon. Relative to the first direction D1, at the same vertical height, the first semiconductor pattern CH1 may have a wider width than the second semiconductor pattern CH2.

[0043] The first groove RS1 can be defined between the first semiconductor pattern CH1 and the second semiconductor pattern CH2. The second groove RS2 can be defined between the first semiconductor patterns CH1.

[0044] A first impurity pattern SD1 and a second impurity pattern SD2 can be disposed on an active pattern ACT. The first impurity pattern SD1 can fill a first groove RS1, and the second impurity pattern SD2 can fill a second groove RS2. Each of the first impurity pattern SD1 and the second impurity pattern SD2 can be connected to a first semiconductor layer to a third semiconductor layer SP1, SP2, and SP3. The first impurity pattern SD1 and the second impurity pattern SD2 can be disposed spaced apart from each other in a first direction D1.

[0045] The first impurity pattern SD1 and the second impurity pattern SD2 may include different materials. For example, the first impurity pattern SD1 may include the same semiconductor element as the first semiconductor pattern CH1 (e.g., Si). For example, the second impurity pattern SD2 may include a semiconductor element having a larger lattice parameter than the semiconductor element of the first semiconductor pattern CH1 (e.g., SiGe).

[0046] The first impurity pattern SD1 and the second impurity pattern SD2 may include different conductive impurities. For example, the first impurity pattern SD1 may include N-type conductive impurities, and the second impurity pattern SD2 may include P-type conductive impurities.

[0047] Although not shown, the first impurity patterns SD1 may be spaced apart from each other, with the second semiconductor pattern CH2 located therebetween. In other words, the first impurity patterns SD1 and SD2, which are spaced apart from each other and have the first semiconductor pattern CH1 therebetween, may include different conductive impurities. Furthermore, the first impurity pattern SD1, which is spaced apart from each other and has the second semiconductor pattern CH2 therebetween, may include the same conductive impurity.

[0048] The first region PR1 can form a logic unit together with the second region PR2 and the third region PR3. In this disclosure, a logic unit can represent a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In this specification, the logic unit formed by the first to third regions PR1, PR2, and PR3 is referred to as the first logic unit. The first logic unit may include diodes for forming logic elements and lines connecting the diodes to each other. Specifically, the first impurity pattern SD1, the second impurity pattern SD2, the first well region WE1, and the second well region WE2 can form diodes, and the active contact CA, described later, can partially form the lines.

[0049] The figure shows a first logic unit, but embodiments of the present invention are not limited thereto. For example, a second logic unit, comprising logic elements that perform functions different from the first logic unit, may be positioned adjacent to the first logic unit. The second logic unit may include transistors for constituting logic elements and lines connecting the transistors to each other. Two logic units have been described above, but embodiments of the present invention are not limited thereto, and those skilled in the art can make various changes to the function, number, and arrangement of the logic units.

[0050] A first gate pattern GE1 may be disposed on a first semiconductor pattern CH1 and may intersect with the first semiconductor pattern CH1. A second gate pattern GE2 may be disposed on a second semiconductor pattern CH2 and may intersect with the second semiconductor pattern CH2. The first gate pattern GE1 and the second gate pattern GE2 may be spaced apart from each other in a first direction D1 and may each extend along a second direction D2. Each of the first gate pattern GE1 and the second gate pattern GE2 may be multiple. The first gate pattern GE1 may be spaced apart from each other in the first direction D1, and the second gate pattern GE2 may be spaced apart from each other in the first direction D1.

[0051] The first gate pattern GE1 may include a gate region GR extending along a second direction D2 and an extension region CR extending from the gate region GR along a first direction D1. The gate regions GR may include adjacent gate regions GR along the first direction D1. The extension region CR may be located between the gate regions GR and may connect to the gate regions GR. Accordingly, in a plan view, the first gate pattern GE1 may have an H-shape. The extension region CR may have a shape integral with the gate region GR. For example, relative to the first direction D1, at the same vertical height, the extension region CR may have a width substantially the same as or greater than the width of the gate region GR. For example, relative to the second direction D2, at the same vertical height, the extension region CR may have a width smaller than the width of the gate region GR.

[0052] One of the gate regions GR can be closer to the first impurity pattern SD1 than the extended region CR. The other gate region GR can be closer to the second impurity pattern SD2 than the extended region CR. The gate region GR and the extended region CR can be located between the first impurity pattern SD1 and the second impurity pattern SD2.

[0053] The extended region CR can be disposed on the PN junction. That is, the extended region CR can be disposed on the boundary where the first well region WE1 and the second well region WE2 meet. A portion of the extended region CR can be disposed on the first well region WE1, and another portion of the extended region CR can be disposed on the second well region WE2. The extended region CR can be disposed on the boundary where the first well region WE1 and the second well region WE2 meet to form a larger width of the first semiconductor pattern CH1 along the first direction D1. Accordingly, the distance between the first impurity pattern SD1 and the second impurity pattern SD2 can be increased. Therefore, the leakage current through the first semiconductor pattern CH1 between the first impurity pattern SD1 and the second impurity pattern SD2 can be reduced. Consequently, the electrical characteristics of the semiconductor device can be improved.

[0054] The extended region CR can be disposed on the first semiconductor pattern CH1 and can vertically overlap with the first semiconductor pattern CH1. Relative to the second direction D2, the extended region CR can have a width substantially the same as or smaller than the width of the first semiconductor pattern CH1. Relative to the second direction D2, the gate region GR can have a width greater than the width of the first semiconductor pattern CH1.

[0055] Relative to the first direction D1, at the same vertical height, the first gate pattern GE1 may have a width greater than that of the second gate pattern GE2. For example, relative to the first direction D1, at the same vertical height, the extension region CR may have a width substantially the same as or greater than that of the second gate pattern GE2. Relative to the second direction D2, at the same vertical height, the extension region CR may have a width smaller than that of the second gate pattern GE2.

[0056] The gate region GR and extended region CR of the first gate pattern GE1, and the second gate pattern GE2, may each include an inner PO1 and an outer PO2. The inner PO1 may be located between the uppermost semiconductor layer SP3 and the active pattern ACT among the multiple semiconductor layers SP1, SP2, and SP3. The outer PO2 may be disposed on the uppermost semiconductor layer. For example, the inner PO1 may include three inner PO1s, but embodiments of the present invention are not limited thereto. For example, the inner PO1 may include at least four inner PO1s.

[0057] Each of the first gate pattern GE1 and the second gate pattern GE2 may include a first metal pattern and a second metal pattern on the first metal pattern. For example, the first metal pattern may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). For example, the first metal pattern may also include carbon (C). For example, the first metal pattern may include metallic materials having different work functions from each other.

[0058] For example, the second metal pattern may include a metal material with a lower resistance than the first metal pattern (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0059] For example, the inner PO1 may include a first metal pattern. For example, the outer PO2 may include a first metal pattern and a second metal pattern.

[0060] For example, when the first logic cell is used as a diode through the PN junction between the first well region WE1 and the second well region WE2, the channel formation of the first semiconductor pattern CH1 can be controlled by controlling the voltage applied to the first gate pattern GE1. Accordingly, the leakage current through the first semiconductor pattern CH1 between the first impurity pattern SD1 and the second impurity pattern SD2 can be controlled.

[0061] The gate capping pattern GC can be disposed on the upper surface of each of the first gate pattern GE1 and the second gate pattern GE2. For example, the gate capping pattern GC may include at least one of SiON, SiCN, SiOCN or SiN.

[0062] The outer gate spacer OGS can be disposed on the side surface of the outer PO2 of the first gate pattern GE1 and the second gate pattern GE2, and can extend to each side surface of the gate cap pattern GC.

[0063] The inner gate spacer IGS may be located between the inner PO1 of the first impurity pattern SD1 and the first gate pattern GE1, between the inner PO1 of the first impurity pattern SD1 and the second gate pattern GE2, and between the inner PO1 of the second impurity pattern SD2 and the first gate pattern GE1. For example, each of the outer gate spacer OGS and the inner gate spacer IGS may include an insulating material.

[0064] The gate insulating pattern (not shown) may be located between the first gate pattern GE1 and the first to third semiconductor layers SP1, SP2, and SP3, and between the second gate pattern GE2 and the first to third semiconductor layers SP1, SP2, and SP3. For example, the gate insulating pattern may include at least one of silicon oxide (SiO2), silicon oxynitride (SiON), or a high-dielectric material. In this disclosure, a high-dielectric material is defined as a material with a dielectric constant higher than that of silicon oxide.

[0065] An interlayer insulating layer (ILD) may be disposed on the substrate 100. The ILD may cover the outer gate spacer (OGS), the first impurity pattern (SD1), and the second impurity pattern (SD2). For example, the ILD may comprise silicon oxide (SiO2).

[0066] The active contact CA can penetrate the interlayer insulating layer (ILD). The lower portion of the active contact CA can be buried in the upper portion of at least one of the first impurity pattern SD1 or the second impurity pattern SD2. For example, the active contact CA can include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal silicide (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, etc.), or a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). The voltage applied to the active contact CA can be transmitted to the first well region WE1 through the first impurity pattern SD1. The voltage applied to the active contact CA can be transmitted to the second well region WE2 through the second impurity pattern SD2.

[0067] Gate contacts (not shown) may penetrate the gate cap pattern GC. Each of the gate contacts may be buried in the upper portion of the outer PO2 of each of the first gate pattern GE1 and the second gate pattern GE2. For example, the gate contacts may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) or a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0068] Although not shown, individual lines comprising conductive material can be configured in multiple layers. The lines can be connected to active contacts CA and gate contacts (not shown). Some lines can apply voltage to the first impurity pattern SD1 through the active contacts CA, and other lines can apply voltage to the second impurity pattern SD2 through the active contacts CA. The first logic unit can be used as a logic element that performs the function of a diode by controlling the voltage.

[0069] The back surface active contact BCA can penetrate the substrate 100, and the back surface active contact BCA can be partially buried within the first well region WE1 on the third region PR3. For example, the back surface active contact BCA can include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal silicide (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, etc.), or a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0070] A power transmission network layer (not shown) may be disposed on the lower surface of substrate 100. The power transmission network layer may include multiple lower lines (not shown) electrically connected to the active contact BCA on the rear surface. The voltage applied to the active contact BCA on the rear surface can be transmitted through the power transmission network layer to the first well region WE1 on the third region PR3.

[0071] In the following text, reference will be made to Figures 3A to 17 Semiconductor devices according to other embodiments of the present invention will be described. For the sake of simplicity, descriptions that are repeated above will be omitted, and the main differences from the above description will be described.

[0072] Figure 3A It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 3B It is along Figure 1 A cross-sectional view taken from line A-A'.

[0073] Reference Figure 1 , Figure 3A and Figure 3B For example, besides referencing Figure 1 and Figure 2 In addition to the methods described, methods for supplying voltage to the first well region WE1 and the second well region WE2 can also be performed in various ways.

[0074] First, refer to Figure 3A References can be omitted. Figure 1 and Figure 2 The rear surface active contact BCA is described. Conversely, the active contact CA can be disposed on the first impurity pattern SD1 on the third region PR3. Accordingly, the voltage applied to the active contact CA and the first impurity pattern SD1 can be transmitted to the first well region WE1 on the third region PR3 via the upper line.

[0075] Next, refer to Figure 3B References can be omitted. Figure 1 and Figure 2 The active contact CA is described. Conversely, the rear surface active contact BCA can be disposed below the first well region WE1 on the first region PR1 and below the second well region WE2 on the second region PR2. Accordingly, the voltage applied to the rear surface active contact BCA can be transmitted to the first well region WE1 on the first region PR1 and the second well region WE2 on the second region PR2 through the power transmission network layer.

[0076] The presence, location, quantity, and arrangement of each of the active contact CA and the rear surface active contact BCA are not limited to the above and can be modified in various ways by those skilled in the art.

[0077] Figure 4 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0078] Reference Figure 1 and Figure 4 You don't need to set a reference. Figure 2 The inner PO1 of each of the gate region GR and the extended region CR in the first gate pattern GE1 is described. Accordingly, an inner PO1 between the active pattern ACT and the first semiconductor layer SP1 can be provided therein (see...). Figure 2 A first additional semiconductor layer ASP1 is disposed in the region of ), and an inner PO1 (see) may be disposed therein between the first semiconductor layer SP1 and the second semiconductor layer SP2. Figure 2 A second additional semiconductor layer ASP2 is disposed in the region of ), and an internal PO1 (see) may be disposed therebetween the second semiconductor layer SP2 and the third semiconductor layer SP3. Figure 2 A third additional semiconductor layer ASP3 is set in the area.

[0079] The first to third additional semiconductor layers ASP1, ASP2, and ASP3 can together with the first to third additional semiconductor layers SP1, SP2, and SP3 to form a first semiconductor pattern CH1. For example, each of the first to third additional semiconductor layers ASP1, ASP2, and ASP3 may include a semiconductor element (e.g., SiGe) having a lattice parameter larger than that of the semiconductor element in each of the first to third additional semiconductor layers SP1, SP2, and SP3.

[0080] First to third additional semiconductor layers ASP1, ASP2, and ASP3 can be provided to increase the area where current can flow between the active contact CA and the well region WE. Specifically, current can flow through the portion of each of the first to third additional semiconductor layers ASP1, ASP2, and ASP3 adjacent to the first impurity pattern SD1, and through the first impurity pattern SD1 between the active contact CA and the first well region WE1. Similarly, current can flow through another portion of each of the first to third additional semiconductor layers ASP1, ASP2, and ASP3 adjacent to the second impurity pattern SD2, and through the second impurity pattern SD2 between the active contact CA and the second well region WE2. Accordingly, the electrical characteristics of the semiconductor device can be improved by increasing the area where current can flow between the active contact CA and the well region WE.

[0081] Figure 5 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 6 It is along Figure 5 A cross-sectional view taken from line A-A'.

[0082] Reference Figure 5 and Figure 6 , and reference Figure 1 and Figure 2 As described, the inner PO1 and outer PO2 of the extended region CR may include insulating material. A portion of each of the inner PO1 and outer PO2 of the gate region GR may include insulating material. This portion of the outer PO2 of the gate region GR may be adjacent to the outer PO2 of the extended region CR in the first direction D1.

[0083] Figure 7 It is along Figure 5 A cross-sectional view taken from line A-A'.

[0084] Reference Figure 5 and Figure 7Each of the gate region GR and the extended region CR can penetrate the first semiconductor pattern CH1. Accordingly, the first semiconductor pattern CH1 can be separated into a pair of first semiconductor patterns CH1 between the first impurity pattern SD1 and the second impurity pattern SD2.

[0085] With reference Figure 6 Unlike the description, each of the gate region GR and the extended region CR may not be separated into an internal PO1 (see [link to relevant documentation]). Figure 6 ) and external PO2 (see Figure 6 ), and can extend along a third party to D3.

[0086] With reference Figure 1 and Figure 2 As described, a portion of the gate region GR and the extended region CR may include insulating material. Accordingly, leakage current through the first semiconductor pattern CH1 between the first impurity pattern SD1 and the second impurity pattern SD2 can be blocked. Consequently, the electrical characteristics of the semiconductor device can be improved.

[0087] Figure 8 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 9 It is along Figure 8 A cross-sectional view taken from line A-A'. Figure 10 It is along Figure 8 A cross-sectional view taken from line A-A'. Figure 11 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 12 It is along Figure 11 A cross-sectional view taken from line A-A'.

[0088] Reference Figures 8 to 12 References can be omitted. Figure 1 and Figure 2 The substrate 100 and active pattern ACT are described. Conversely, an insulating substrate 200 and an insulating pattern IP on the insulating substrate 200 can be provided. The features of the insulating substrate 200 can be compared with those of the reference. Figure 3B The description is identical or similar. The insulating pattern IP may include insulating material. The insulating pattern IP may extend along the first direction D1. Trap area WE (see...) Figure 2 The PN junction may not be formed in the insulating pattern IP. Accordingly, the PN junction may not be formed in the insulating pattern IP (in other words, below the first impurity pattern SD1 and the second impurity pattern SD2).

[0089] The back surface active contact BCA can penetrate the insulating substrate 200 and each of the insulating patterns IP. The upper part of the back surface active contact BCA can be buried in the lower part of the first impurity pattern SD1.

[0090] For example, when each of the first logic cell and the second logic cell adjacent to the first logic cell is powered through the rear surface of the insulating substrate 200, as described above, the insulating substrate 200 and the insulating pattern IP can be used instead of the substrate 100 (see [link]). Figure 2 ) and active patterned ACT (see Figure 2 Accordingly, the first logic unit may not include the well region WE containing the PN junction (see [link to relevant documentation]). Figure 2 (And, it can also be used without being a diode.) Accordingly, by allowing current to flow through another region between the first impurity pattern SD1 and the second impurity pattern SD2, the first logic cell can be used as a diode, and the freedom of arrangement design of the semiconductor device can be increased. This will be described in detail below.

[0091] Reference Figure 8 and Figure 9 By allowing current to flow through the first semiconductor layer to the third semiconductor layers SP1, SP2 and SP3 between the inner PO1 and outer PO2 of the first gate pattern GE1 and between the first impurity pattern SD1 and the second impurity pattern SD2, the first logic cell can be used as a diode.

[0092] Reference Figure 8 and Figure 10 The first logic cell can be used as a diode by allowing current to flow between the first additional semiconductor layer to the third additional semiconductor layer ASP1, ASP2 and ASP3 between the insulating pattern IP and the first gate pattern GE1, and between the first semiconductor layer to the third semiconductor layer SP1, SP2 and SP3 between the first impurity pattern SD1 and the second impurity pattern SD2.

[0093] Reference Figure 11 and Figure 12 The first logic cell can be used as a diode by allowing current to flow between the first semiconductor layer to the third semiconductor layers SP1, SP2 and SP3 between the inner PO1 and the outer PO2 of the first gate pattern GE1, which includes insulating material, and between the first impurity pattern SD1 and the second impurity pattern SD2.

[0094] Figure 13 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 14 It is along Figure 13 A cross-sectional view taken from line A-A'. Figure 15 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 16 It is along Figure 15 A cross-sectional view taken from line A-A'.

[0095] Reference Figures 13 to 16 , and reference Figure 1 and Figure 2 The different descriptions suggest that the trap regions WE on the first to third regions PR1, PR2 and PR3 can be set up in various ways.

[0096] First, refer to Figure 13 and Figure 14 The second well region WE2 can be disposed on the first region PR1 and the second region PR2. The first well region WE1 can be disposed on the third region PR3. Accordingly, a PN junction can be formed on the first region PR1 between the first impurity pattern SD1 and the second well region WE2. Furthermore, a PN junction can be formed between the second well region WE2 on the second region PR2 and the first well region WE1 on the third region PR3.

[0097] Next, refer to Figure 15 and Figure 16 A second well region WE2 can be formed on the first to third regions PR1, PR2, and PR3. Correspondingly, a PN junction can be formed on the third region PR3 between the first impurity pattern SD1 and the second well region WE2. Furthermore, a PN junction can be formed on the first region PR1 between the first impurity pattern SD1 and the second well region WE2.

[0098] The arrangement of the trap area WE is not limited to Figures 13 to 16 The arrangement shown is illustrated, and various changes can be made by those skilled in the art to the arrangement of the trap regions WE on the first to third regions PR1, PR2 and PR3.

[0099] Figure 17 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention.

[0100] Reference Figure 17 ,and Figure 1 Unlike other regions, the extended regions CR can be multiple. The extended regions CR can be spaced apart from each other in the second direction D2 between the gate regions GR. Two extended regions CR are shown in the figure, but embodiments of the present invention are not limited thereto.

[0101] Although not shown, it is referenced Figure 2 The external gate spacer OGS described (see Figure 2 It can be located between the extended regions CR. External gate spacer OGS (see...) Figure 2 It can cover the first semiconductor pattern CH1 (see...) Figure 2 The upper surface of ).

[0102] In the following text, reference will be made to Figures 18 to 24Methods for manufacturing semiconductor devices according to some embodiments of the present invention are described. For the sake of simplicity, descriptions that are repeated above will be omitted, and the main differences from the above description will be described.

[0103] Figures 18 to 21 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Specifically, Figure 18 This is a plan view illustrating some embodiments of a semiconductor device according to the present invention. Figure 19 It is along Figure 18 A cross-sectional view taken from line A-A'. Figure 20 and Figure 21 They are along Figure 1 A cross-sectional view taken from line A-A'.

[0104] Reference Figure 18 and Figure 19 A substrate 100 may be configured to include an active pattern ACT, which includes each of a first well region WE1 and a second well region WE2.

[0105] A stacked pattern STP can be formed on an active pattern ACT. For example, forming a stacked pattern STP may include: alternately stacking a semiconductor layer SL and a sacrificial layer SAL on a substrate 100 to form a mask pattern (not shown) extending along a first direction D1, and performing a patterning process by using the mask pattern as an etch mask. When performing the patterning process, the substrate 100 may be partially removed together, and trenches (not shown) may be formed. Element isolation patterns (not shown) may be formed to fill the trenches (not shown).

[0106] The sacrificial layer SAL can comprise a material capable of etch selectivity against the semiconductor layer SL. Accordingly, when performing the process for removing the sacrificial layer SAL, as described later, the sacrificial layer SAL can be removed, but the semiconductor layer SL may not be removed, or a smaller amount may be removed than the sacrificial layer SAL. For example, the semiconductor layer SL can comprise one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the sacrificial layer SAL can comprise another of silicon (Si), germanium (Ge), and silicon-germanium (SiGe) different from the semiconductor layer SL.

[0107] The sacrificial pattern PP can be formed to extend along a second direction D2 on the substrate 100. The sacrificial pattern PP can be formed to cover the upper surface of the element isolation pattern and the side and upper surfaces of the stacked pattern. For example, forming the sacrificial pattern PP may include: forming a sacrificial film (not shown) on the front side of the substrate 100, forming a hard mask pattern MP on the sacrificial film, and forming the sacrificial pattern PP by partially removing the sacrificial film using the hard mask pattern MP as an etch mask. For example, the sacrificial pattern PP may include polysilicon. Subsequently, an external gate spacer OGS may be formed on the side surface of the sacrificial pattern PP.

[0108] The sacrificial pattern PP may include a first sacrificial pattern PP1 formed on the boundary between the first well region WE1 and the second well region WE2, and a second sacrificial pattern PP2 adjacent to the first sacrificial pattern PP1 in the first direction D1. The hard mask pattern MP may include the first hard mask pattern MP1 on the first sacrificial pattern PP1 and the second hard mask pattern MP2 on the second sacrificial pattern PP2. Each of the first sacrificial pattern PP1 and the first hard mask pattern MP1 may be formed to cover the upper surface of the stacked pattern STP disposed on the boundary between the first well region WE1 and the second well region WE2.

[0109] The first sacrificial pattern PP1 may include regions extending along the second direction D2 and another region extending between regions along the first direction D1. Accordingly, in a plan view, the first sacrificial pattern PP1 may have an H-shape. The width of the first sacrificial pattern PP1 relative to the first direction D1 may be greater than the width of the second sacrificial pattern PP2.

[0110] Reference Figure 1 and Figure 20 The first groove RS1 and the second groove RS2 can be formed by partially removing the stacked pattern STP using a hard mask pattern MP and a sacrificial pattern PP as masks. The semiconductor layer SL can be separated by the first groove RS1 and the second groove RS2 into a first semiconductor pattern CH1 and a second semiconductor pattern CH2 spaced apart from each other in a first direction D1.

[0111] The sacrificial layer SAL exposed by the first groove RS1 and the second groove RS2 can be partially replaced by an insulating material. Accordingly, inner gate spacers IGS can be formed on both side surfaces of the sacrificial layer SAL.

[0112] Subsequently, a first impurity pattern SD1 can be formed on the first groove RS1, and a second impurity pattern SD2 can be formed on the second groove RS2.

[0113] According to the present invention, when performing a process to remove the stacked pattern STP to form the first groove RS1 and the second groove RS2, the stacked pattern STP covered by the extended region of the first sacrificial pattern PP1 extending along the first direction D1 can be omitted. Accordingly, another separate groove can be omitted at the boundary between the first well region WE1 and the second well region WE2. Therefore, during the process of forming the first impurity pattern SD1 and the second impurity pattern SD2, another separate impurity pattern can be unnecessarily formed at the boundary between the first well region WE1 and the second well region WE2. Accordingly, functional degradation of the first logic cell caused by unnecessarily formed impurity patterns can be limited and / or prevented, and the electrical characteristics of the semiconductor device can be improved.

[0114] Reference Figure 1 and Figure 21 An interlayer insulating layer (ILD) can be formed to cover the first impurity pattern SD1, the second impurity pattern SD2, the hard mask pattern MP, and the outer gate spacer OGS. Subsequently, the ILD on the upper surface of the sacrificial pattern PP can be removed. During the removal process, the hard mask pattern MP can be removed together, exposing the sacrificial pattern PP.

[0115] Subsequently, the exposed sacrificial pattern PP can be removed, and an external region ORG can be formed in the area where the sacrificial pattern PP has been removed. The first semiconductor pattern CH1, the second semiconductor pattern CH2, and the sacrificial layer SAL can be exposed to the outside through the external region ORG.

[0116] Subsequently, the exposed sacrificial layer SAL can be selectively removed. In this case, due to the high etch selectivity for the sacrificial layer SAL, the first to third semiconductor layers SP1, SP2 and SP3 may not be removed or may be removed less.

[0117] The internal region IRG can be formed in the region where the sacrificial layer SAL is removed. Specifically, the internal region IRG can be formed between the first semiconductor layer and the third semiconductor layers SP1, SP2 and SP3.

[0118] Return to reference Figure 1 and Figure 2 Gate insulating patterns (not shown) can be formed in the outer region ORG and each inner region IRG. The first gate pattern GE1 and the second gate pattern GE2 can be formed to fill the inner region IRG and the outer region ORG. Thereafter, a gate capping pattern GC can be formed on the outer PO2 of each of the first gate pattern GE1 and the second gate pattern GE2.

[0119] The active contact CA can be formed to penetrate the interlayer insulating layer (ILD) and can be connected to the first impurity pattern SD1 and the second impurity pattern SD2. The gate contact (not shown) can be formed to penetrate the gate cap pattern GC and can be connected to the first gate pattern GE1 and the second gate pattern GE2.

[0120] Although not shown, individual lines comprising conductive material can be formed on the interlayer insulating layer (ILD), and a reference can be manufactured. Figure 1 and Figure 3A The semiconductor device described.

[0121] After completing the BEOL process, a process of flipping the substrate 100 vertically can be performed. After flipping the substrate 100 vertically, an active contact portion BCA penetrating the back surface of the substrate 100 can be formed. Accordingly, a reference can be fabricated. Figure 1 , Figure 2 and Figure 3B The semiconductor device described.

[0122] After flipping the substrate 100 upside down, an insulating substrate 200 can be formed in the region where both the substrate 100 and the active pattern ACT are removed (see [reference]). Figure 9 ) and insulating pattern IP (see Figure 9 In this case, a reference can be created. Figure 8 and Figure 9 The semiconductor device described.

[0123] Figure 22 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Specifically, Figure 22 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0124] Reference Figure 1 and Figure 22 In forming a reference Figure 1 and Figure 21 After describing the external region ORG, the sacrificial layer SAL can be retained instead of removed. The sacrificial layer SAL can form a reference. Figure 4 The first to third additional semiconductor layers ASP1, ASP2 and ASP3 are described.

[0125] Subsequently, the reference can be manufactured using the methods described above for manufacturing semiconductor devices. Figure 1 and Figure 4 The semiconductor device described.

[0126] Figure 23 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Specifically, Figure 23 It is along Figure 5 A cross-sectional view taken from line A-A'.

[0127] Reference Figure 5 and Figure 23 In forming a reference Figure 1 and Figure 2 After the first gate pattern GE1 and the second gate pattern GE2 are described, a portion of the first gate pattern GE1 can be removed (in other words, the area where the first gate pattern GE1 overlaps with the first semiconductor pattern CH1). Accordingly, an additional internal region AIRG can be formed between the first semiconductor layer and the third semiconductor layers SP1, SP2 and SP3. Furthermore, an additional external region AORG can be formed on the third semiconductor layer SP3.

[0128] Reference Figure 5 and Figure 6 Additional internal region AIRG (see Figure 23 ) and additional external region AORG (see Figure 23 Each of the gates can be filled with insulating material, and thus can form part of the extension region CR and the gate region GR of the first gate pattern GE1.

[0129] Subsequently, the reference can be manufactured using the methods described above for manufacturing semiconductor devices. Figure 5 and Figure 6 The semiconductor device described.

[0130] Figure 24 This is a diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Specifically, Figure 24 It is along Figure 5 A cross-sectional view taken from line A-A'.

[0131] Reference Figure 5 and Figure 24 In forming a reference Figure 1 and Figure 2 After the first gate pattern GE1 and the second gate pattern GE2 are described, a portion of the first gate pattern GE1 can be removed (in other words, the area where the first gate pattern GE1 overlaps with the first semiconductor pattern CH1). When this portion of the first gate pattern GE1 is removed, the first semiconductor pattern CH1 can also be removed together. Accordingly, an additional recess ARS can be formed between the first impurity pattern SD1 and the second impurity pattern SD2.

[0132] Reference Figure 5 and Figure 7 The interior of the additional groove ARS can be filled with insulating material, and thus, an extension region CR of the first gate pattern GE1 and a portion of the gate region GR can be formed.

[0133] Subsequently, the reference can be manufactured using the methods described above for manufacturing semiconductor devices. Figure 5 and Figure 7 The semiconductor device described.

[0134] According to the inventive concept, when performing a process to remove the stacked pattern used to form the groove in which the impurity pattern is formed, the stacked pattern covered by the extended region of the first sacrificial pattern can be omitted. Accordingly, another separate groove can be omitted at the boundary between well regions comprising impurities of different conductivity types. Therefore, during the impurity patterning process, another separate impurity pattern can be unnecessarily formed at the boundary between well regions. Accordingly, functional degradation of logic cells caused by unnecessarily formed impurity patterns can be limited and / or prevented, and the electrical characteristics of the semiconductor device can be improved.

[0135] The foregoing description of embodiments of the inventive concept provides examples for illustrating the inventive concept. Therefore, the inventive concept is not limited to the above embodiments, and it is obvious that those skilled in the art can make various modifications and changes within the technical spirit of the inventive concept, for example, by combining it with the above embodiments.

Claims

1. A semiconductor device, comprising: A first impurity pattern and a second impurity pattern are spaced apart from each other on a substrate along a first direction parallel to the upper surface of the substrate, and the first impurity pattern includes impurities of a different conductivity type than the impurities in the second impurity pattern. A first semiconductor pattern is located between the first impurity pattern and the second impurity pattern; and The first gate pattern intersects with the first semiconductor pattern, wherein... The first gate pattern includes a gate region extending along a second direction and an extension region extending from the gate region in the first direction, and The second direction intersects with the first direction.

2. The semiconductor device according to claim 1, further comprising: Active pattern, including well regions on the substrate, wherein, The well region includes a first well region below the first impurity pattern and a second well region below the second impurity pattern. A first portion of the extended region of the first gate pattern is on the first well region, and A second portion of the extended region of the first gate pattern is on the second well region.

3. The semiconductor device according to claim 1, further comprising: A second semiconductor pattern is spaced apart from the first semiconductor pattern, and the first impurity pattern is located between the second semiconductor pattern and the first semiconductor pattern. as well as The second gate pattern intersects with the second semiconductor pattern, wherein... The width of the first gate pattern in the first direction is greater than the width of the second gate pattern in the first direction.

4. The semiconductor device according to claim 1, wherein, The first semiconductor pattern includes multiple semiconductor layers stacked on the substrate. The interior of the extended region of the first gate pattern is between the semiconductor layers, and The outer portion of the extended region of the first gate pattern is on the uppermost semiconductor layer within the semiconductor layer.

5. The semiconductor device according to claim 4, wherein, The interior and exterior of the extended region of the first gate pattern both comprise conductive material.

6. The semiconductor device according to claim 4, wherein, The interior of the extended region of the first gate pattern comprises semiconductor material, and The exterior of the extended region of the first gate pattern comprises a conductive material.

7. The semiconductor device according to claim 4, wherein, Both the interior and exterior of the extended region of the first gate pattern comprise an insulating material, and The gate region of the first gate pattern comprises an insulating material and a conductive material.

8. The semiconductor device according to claim 1, wherein, The gate region of the first gate pattern lies between the first impurity pattern and the extended region of the first gate pattern.

9. The semiconductor device according to claim 1, wherein, The gate region of the first gate pattern includes a pair of gate regions adjacent to each other along the first direction. The extended region of the first gate pattern is between the pair of gate regions, and The gate regions of the first gate pattern are connected to each other through the extended regions of the first gate pattern.

10. The semiconductor device according to claim 1, wherein, In the plan view, the first gate pattern has an H-shape.

11. The semiconductor device according to claim 1, wherein, The width of the extended region of the first gate pattern in the second direction is less than or equal to the width of the first semiconductor pattern in the second direction.

12. The semiconductor device according to claim 1, wherein, The width of the extended region of the first gate pattern in the second direction is smaller than the width of the gate region in the second direction.

13. The semiconductor device according to claim 1, wherein, The extended region of the first gate pattern includes a plurality of extended regions that are adjacent to each other along the second direction.

14. A semiconductor device, comprising: A first impurity pattern and a second impurity pattern are spaced apart from each other on a substrate along a first direction parallel to the upper surface of the substrate. The first impurity pattern includes impurities of a different conductivity type than the impurities in the second impurity pattern. A first semiconductor pattern is located between the first impurity pattern and the second impurity pattern; and The first gate pattern intersects with the first semiconductor pattern, wherein... The first gate pattern includes gate regions that are adjacent to each other along the first direction. Each gate region in the gate region extends in the second direction. The second direction intersects with the first direction, and The first gate pattern also includes an extension region between the gate regions of the first gate pattern.

15. The semiconductor device according to claim 14, wherein, The extended region of the first gate pattern extends in the first direction, and The gate regions of the first gate pattern are connected to each other through the extended regions.

16. The semiconductor device of claim 14, further comprising: Active pattern, including well regions on the substrate, wherein, The well region includes a first well region below the first impurity pattern and a second well region below the second impurity pattern. A first portion of the extended region of the first gate pattern is on the first well region, and A second portion of the extended region of the first gate pattern is on the second well region.

17. The semiconductor device of claim 14, further comprising: A second semiconductor pattern is spaced apart from the first semiconductor pattern, and the first impurity pattern is located between the second semiconductor pattern and the first semiconductor pattern. as well as The second gate pattern intersects with the second semiconductor pattern. Wherein, the width of the first gate pattern in the first direction is greater than the width of the second gate pattern in the first direction.

18. The semiconductor device according to claim 14, wherein, The width of the extended region of the first gate pattern in the second direction is smaller than the width of the gate region in the second direction.

19. The semiconductor device according to claim 14, wherein, One of the gate regions of the first gate pattern is adjacent to the first impurity pattern, and Another gate region in the gate region of the first gate pattern is adjacent to the second impurity pattern.

20. A semiconductor device, comprising: A first impurity pattern and a second impurity pattern are spaced apart from each other on a substrate along a first direction parallel to the upper surface of the substrate, and the first impurity pattern includes impurities of a different conductivity type than the impurities in the second impurity pattern. A first semiconductor pattern is located between the first impurity pattern and the second impurity pattern; A second semiconductor pattern is spaced apart from the first semiconductor pattern, and the first impurity pattern is located between the second semiconductor pattern and the first semiconductor pattern. Each of the first semiconductor pattern and the second semiconductor pattern includes a plurality of semiconductor layers stacked on the substrate. The first gate pattern intersects with the first semiconductor pattern; The second gate pattern intersects with the second semiconductor pattern; An inner gate spacer is located between the first impurity pattern and the first gate pattern; as well as The rear surface has an active contact portion, located below at least one of the first impurity pattern and the second impurity pattern, wherein, The first gate pattern includes a gate region and an extension region between the gate region. The gate regions are adjacent to each other in the first direction. Each gate region in the gate region extends in the second direction, and The second direction intersects with the first direction.

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