Red light vertical chip assembly and manufacturing method thereof
By using a transparent conductive layer to form ohmic contacts in the red light vertical chip to replace metal electrodes, the problems of low quantum efficiency and uneven light emission outside the red light epitaxial layer are solved, improving brightness and light emission intensity while reducing cost.
Patent Information
- Application Number
- CN202411112032.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-14
- Publication Date
- 2026-03-03
AI Technical Summary
The low external quantum efficiency of the red epitaxial layer, the reflection of light from the light-emitting layer by the N-electrode metal leading to low brightness of the normal light of the Micro LED, and the severe light blocking by the metal electrode resulting in uneven light emission.
An ohmic contact is formed using a transparent conductive layer to replace the metal electrode. The transparent conductive layer is formed by doping on the surface of the second semiconductor layer and then bonded to the target substrate to optimize the light emission distribution.
The brightness and normal luminescence intensity of the red vertical chip were improved, while the precious metal content was reduced, thus lowering the cost.
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Figure CN121604573A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of LED chip technology, and in particular to a red vertical chip assembly and its manufacturing method. Background Technology
[0002] Currently, high-brightness AlGaInP light-emitting diodes (LEDs) are widely used. They are electronic devices that directly convert electrical energy into light energy by generating photons through the radiative recombination of conduction band electrons and valence band holes in semiconductor materials. Compared with traditional light sources, they have advantages such as high efficiency, energy saving, environmental friendliness, and long lifespan, playing a vital role in energy conservation, emission reduction, and green development. They are widely recognized as the next generation of green lighting sources for the 21st century. The development and application of semiconductors are further solidifying this concept, making increasing LED brightness an inevitable choice for the current semiconductor market.
[0003] However, since the red LED epitaxial layer is typically an AlGaInP quaternary deposition on the GaAs surface, with each layer having a different composition and an n-value between 2.5 and 3.3, the external quantum efficiency (EQE) of the LED is very low. Furthermore, the N-electrode metal reflects the light generated by the light-emitting layer, resulting in low normal brightness in the vertical Micro LED, with most light emitted outside the chip electrodes, affecting the final visual effect. Additionally, conventional P-type quaternary red LED N-side ohmic contacts must use metal, which is replaced by semiconductor metal through annealing. This results in severe light blocking by the metal electrodes, leading to extremely low EQE and uneven light emission in the final quaternary red LED vertical Micro LED chip. Summary of the Invention
[0004] In view of the shortcomings of the prior art, the purpose of this application is to provide a red light vertical chip component and its manufacturing method, in order to solve the above problems.
[0005] In a first aspect, this application provides a method for fabricating a red light vertical chip assembly, comprising:
[0006] An epitaxial wafer is provided, the epitaxial wafer comprising a substrate and a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially deposited on the substrate, wherein the surface of the second semiconductor layer is doped with a doping element;
[0007] A transparent conductive layer is deposited on the second semiconductor layer to form an ohmic contact;
[0008] The transparent conductive layer is bonded to a temporary substrate, and the substrate is then removed.
[0009] A first electrode is deposited on the first semiconductor layer to form an ohmic contact;
[0010] The target substrate is bonded to the first electrode, and the temporary substrate is removed;
[0011] The bonding structure on the target substrate is patterned to obtain multiple red vertical chip components bonded to the target substrate.
[0012] In one possible embodiment, depositing a first electrode and forming an ohmic contact on the first semiconductor layer includes:
[0013] A first electrode is deposited on the first semiconductor layer;
[0014] Annealing is performed at a temperature of 300-500℃ for 10-60 seconds to form an ohmic contact between the first electrode and the first semiconductor layer.
[0015] In one possible embodiment, the material of the first electrode includes at least one of Au, Al, Ag, Cu, Ni, AuZn, AuBe, AuGe, and AuGeNi.
[0016] In one possible embodiment, bonding the target substrate to the first electrode includes:
[0017] A target substrate is provided, on which a metal layer is deposited by vapor deposition;
[0018] The first electrode is gold-bonded to the metal layer.
[0019] In one possible embodiment, the target substrate is a CMOS substrate.
[0020] In one possible embodiment, the material of the metal layer includes at least one of Au, Al, Sn, In, Cu, and Pt.
[0021] In one possible embodiment, the doping element is carbon.
[0022] In one possible embodiment, the carbon doping concentration is greater than 1E20.
[0023] In one possible embodiment, the second semiconductor layer is an N-type layer.
[0024] Secondly, this application also provides a red light vertical chip assembly, which is fabricated using the red light vertical chip assembly fabrication method as described in any one of the first aspects.
[0025] Beneficial effects
[0026] This application provides a red light vertical chip component and its fabrication method. By employing surface doping of the second semiconductor layer, it is possible to form an ohmic contact with the transparent conductive layer. Since the transparent electrode does not obstruct the light pattern, the brightness can be effectively improved. In addition, by replacing the metal electrode with the transparent electrode, the light emission distribution is optimized and the normal light emission intensity is improved. On the other hand, since there is no need to prepare the metal electrode on the second semiconductor layer, there is no need for metal photoluminescence process, which can effectively reduce the precious metal content and thus reduce the cost. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of the structure of a traditional red LED chip;
[0028] Figure 2 for Figure 1 The diagram shows the light emission of a red LED chip.
[0029] Figure 3 for Figure 1 The diagram shows the light emission distribution of the red LED chip.
[0030] Figure 4 This application provides a schematic flowchart of a method for fabricating a red light vertical chip assembly.
[0031] Figure 5 for Figure 4 A schematic diagram of the epitaxial wafer structure in a method for fabricating a red light vertical chip assembly is shown.
[0032] Figure 6 for Figure 4 A schematic diagram of the structure after vapor deposition of a transparent conductive layer in a method for fabricating a red light vertical chip component;
[0033] Figure 7 for Figure 4 A schematic diagram of the structure after bonding to a temporary substrate in a method for fabricating a red light vertical chip assembly.
[0034] Figure 8 for Figure 4 A schematic diagram of the structure after substrate removal in a method for fabricating a red light vertical chip assembly;
[0035] Figure 9 for Figure 4 This is a schematic diagram of the structure after bonding to the target substrate and peeling off the temporary substrate in a method for fabricating a red light vertical chip assembly.
[0036] Figure 10 for Figure 4 A schematic diagram of the patterned structure in a method for fabricating a red light vertical chip component is shown.
[0037] Figure 11for Figure 4 The diagram shows the light emission distribution of a red vertical chip component prepared by a method for fabricating a red vertical chip component.
[0038] Explanation of reference numerals in the attached figures:
[0039] 10-Substrate; 20-First semiconductor layer; 30-Light-emitting layer; 40-Second semiconductor layer; 50-Transparent conductive layer; 60-First electrode; 70-Target substrate; 71-Metal layer; 90-Temporary substrate. Detailed Implementation
[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0041] This invention discloses many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described herein. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.
[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Generally, terms can be understood at least in part according to their usage in accordance with the invention. For example, the term "one or more" as used herein, depending at least in part on the invention, can be used to describe any component, structure, or feature in the singular or in the plural form to describe a combination of components, structures, or features. Similarly, terms such as "a," "an," or "the" can also be understood, depending at least in part on the invention, to convey either a singular or a plural usage. Furthermore, the term "based on..." can be understood not necessarily to convey an exclusive set of factors, but rather, depending at least in part on the invention, can alternatively allow for additional factors that do not necessarily have to be explicitly described.
[0043] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this invention should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including the presence of an intermediate component or layer between the two, and “on something” or “above something” means not only “on something” or “above something,” but also “on something” or “above something” where no intermediate component or layer between the two exists.
[0044] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used in this invention to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways, rotated 90°, or otherwise oriented, and the spatial relative descriptive terms used in this invention can be interpreted accordingly.
[0045] As used in this invention, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.
[0046] refer to Figure 1 This is a schematic diagram of a traditional red-light vertical Micro LED structure. Figure 1 As shown, an N-electrode is deposited on the N-type semiconductor of the epitaxial layer EPI, followed by an annealing process to form an ohmic contact between the metal and the N-type semiconductor. Figure 2 As shown, the light generated by electron-hole recombination in the EPI layer (as indicated by the arrows in the figure) passes through the semiconductor layer and is reflected to the outside of the LED. Its light emission distribution is as follows: Figure 3 As shown. From Figure 2 and Figure 3 It can be seen that due to the severe light blocking by the metal electrodes, the final EQE of the quaternary red light vertical Micro chip is extremely low and the light emission is uneven.
[0047] Therefore, this application aims to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in subsequent embodiments.
[0048] refer to Figure 4 This is a schematic flowchart of a method for fabricating a red vertical chip assembly according to an embodiment of this application. The method includes:
[0049] 101: Provide an epitaxial wafer.
[0050] like Figure 5 As shown, the epitaxial wafer includes a substrate and a first semiconductor layer 20, a light-emitting layer 30 and a second semiconductor layer 40 sequentially deposited on the substrate 10, wherein the surface of the second semiconductor layer 40 is doped with doping elements.
[0051] The first semiconductor layer 20 and the second semiconductor layer 40 are doped semiconductor layers of different types.
[0052] The first semiconductor layer 20 can be a P-type semiconductor layer or an N-type semiconductor layer, and the second semiconductor layer 40 can be an N-type semiconductor layer or a P-type semiconductor layer.
[0053] Optionally, in this embodiment, the second semiconductor layer 40 is an N-type semiconductor layer, and the first semiconductor layer 20 is a P-type semiconductor layer, that is, the epitaxial wafer adopts an N-up structure epitaxy. The following description will use an N-type semiconductor layer as an example to illustrate this.
[0054] The aforementioned light-emitting layer 30 can be a multiple quantum well (MQW) structure. A multiple quantum well structure can include one, two, three, four, five, six, seven, or eight quantum wells (or at least one quantum hole).
[0055] In this embodiment, the epitaxial wafer can be a red-light-emitting epitaxial wafer of the indium gallium aluminum phosphide system, and the substrate 10 is GaAs.
[0056] In the embodiments of this application, the doping element is carbon, and its doping concentration is greater than 1E20.
[0057] Of course, in practical applications, the doping element can also be Mg, but no specific limitation is made here.
[0058] 102: A transparent conductive layer is deposited on the second semiconductor layer to form an ohmic contact.
[0059] like Figure 6 As shown, a transparent conductive layer 50 with high C doping is deposited on the surface of the second semiconductor layer (N-type semiconductor layer) 40.
[0060] Optionally, the transparent conductive layer 50 can be made of transparent materials with low sheet resistance, such as ITO, IGO, or IZO.
[0061] 103: Bond the transparent conductive layer to the temporary substrate and remove the substrate.
[0062] For example, such as Figure 7 As shown, a temporary bonding material is applied to the surface of the transparent conductive layer 50 and the temporary substrate 90 (the material can be a transparent substrate such as sapphire or glass), and the epitaxial wafer is transferred onto the temporary substrate 90.
[0063] The temporary bonding material can be a pyrolytic adhesive, a photolytic adhesive, etc.
[0064] 104: A first electrode is deposited on the first semiconductor layer to form an ohmic contact.
[0065] For example, such as Figure 8 As shown, a first electrode 60 is deposited on the first semiconductor layer 20; annealing is performed at a temperature of 300-500°C for 10-60 seconds to make the first electrode 60 form an ohmic contact with the first semiconductor layer 20.
[0066] In this embodiment, the first electrode 60 is one or more metals that can form an ohmic contact with the LED epitaxial structure to conduct current. For example, the first electrode 60 can be Au, Al, Ag, Cu, Ni, AuZn, AuBe, AuGe, AuGeNi, etc. (similar conductive metals).
[0067] Among them, the first electrode 60 is a P electrode.
[0068] 105: Bond the target substrate to the first electrode and remove the temporary substrate.
[0069] In one embodiment, 105 includes: providing a target substrate on which a metal layer is deposited; and bonding the first electrode to the metal layer using gold-to-gold bonding.
[0070] Optionally, the target substrate is a CMOS (Complementary Metal Oxide Semiconductor) substrate.
[0071] Optionally, the material of the metal layer includes at least one of Au, Al, Sn, In, Cu, and Pt.
[0072] For example, such as Figure 9 As shown, the epitaxial layer is bonded to the metal layer 71 on the target substrate 70 via the first electrode 60. After bonding, the temporary substrate is removed by a stripping process.
[0073] 106: Pattern the bonding structure on the target substrate to obtain multiple red vertical chip components bonded to the target substrate.
[0074] It should be noted that the bonding structure refers to the structure on the target substrate.
[0075] For example, such as Figure 10 As shown, the bonding structure on the target substrate is etched into individual Micro LEDs through processes such as masking and etching.
[0076] like Figure 11 As shown, experiments have verified that the emission distribution of this red vertical chip component is significantly better than that of other components. Figure 3 The existing emission distribution is shown.
[0077] It should be noted that, Figure 11 and Figure 3 The horizontal axis in the figure represents the light emission angle.
[0078] Based on the same inventive concept, this application also provides a red light vertical chip assembly, which is prepared using the method described in the above-described method embodiments.
[0079] In summary, the red vertical chip component and its fabrication method provided in this application, by employing surface doping of the second semiconductor layer, enables it to form an ohmic contact with the transparent conductive layer. Since the transparent electrode does not obstruct the light pattern, the brightness can be effectively improved. In addition, by replacing the metal electrode with a transparent electrode, the light emission distribution is optimized, and the normal light emission intensity is improved. On the other hand, since there is no need to prepare a metal electrode on the second semiconductor layer, there is no need for a metal photoluminescence process, thus effectively reducing the precious metal content and reducing costs.
[0080] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A method for fabricating a red light vertical chip assembly, characterized in that, include: An epitaxial wafer is provided, the epitaxial wafer comprising a substrate and a first semiconductor layer, a light-emitting layer and a second semiconductor layer sequentially deposited on the substrate, wherein the surface of the second semiconductor layer is doped with a doping element; A transparent conductive layer is deposited on the second semiconductor layer to form an ohmic contact; The transparent conductive layer is bonded to a temporary substrate, and the substrate is then removed. A first electrode is deposited on the first semiconductor layer to form an ohmic contact; The target substrate is bonded to the first electrode, and the temporary substrate is removed; The bonding structure on the target substrate is patterned to obtain multiple red vertical chip components bonded to the target substrate.
2. The method for fabricating a red vertical chip assembly as described in claim 1, characterized in that, The deposition of a first electrode on the first semiconductor layer and the formation of an ohmic contact includes: A first electrode is deposited on the first semiconductor layer; Annealing is performed at a temperature of 300-500℃ for 10-60 seconds to form an ohmic contact between the first electrode and the first semiconductor layer.
3. The method for fabricating a red vertical chip assembly as described in claim 1 or 2, characterized in that, The material of the first electrode includes at least one of Au, Al, Ag, Cu, Ni, AuZn, AuBe, AuGe, and AuGeNi.
4. The method for fabricating a red vertical chip assembly as described in claim 1, characterized in that, The bonding of the target substrate to the first electrode includes: A target substrate is provided, on which a metal layer is deposited by vapor deposition; The first electrode is gold-bonded to the metal layer.
5. The method for fabricating a red vertical chip assembly as described in claim 4, characterized in that, The target substrate is a CMOS substrate.
6. The method for fabricating a red vertical chip assembly as described in claim 4 or 5, characterized in that, The material of the metal layer includes at least one of Au, Al, Sn, In, Cu, and Pt.
7. The method for fabricating a red vertical chip assembly as described in claim 1, characterized in that, The doping element is carbon.
8. The method for fabricating a red vertical chip assembly as described in claim 7, characterized in that, The carbon doping concentration is greater than 1E20.
9. The method for fabricating a red vertical chip assembly as described in claim 1, characterized in that, The second semiconductor layer is an N-type layer.
10. A red light vertical chip assembly, characterized in that, It is prepared using the red light vertical chip assembly fabrication method as described in any one of claims 1-9.