Electrode structure, LED chip and manufacturing method thereof

Abstract

The invention provides an electrode structure, an LED chip and a manufacturing method thereof. The electrode structure comprises a first conductive layer and a second conductive layer, the first conductive layer is provided with a box dam with a gap, and the gap is located at the outer edge of the box dam; the thickness of the box dam is reduced inwards from the outer edge of the box dam to form a flow guide wall for guiding flow to the notch; the second conductive layer is laminated on the diversion wall of the first conductive layer; the hardness of the first conductive layer is greater than that of the second conductive layer. When a welding wire of the second conductive layer deforms, the welding wire is blocked by a box dam formed by the first conductive layer with higher hardness, and the first conductive layer guides metal overflowing due to deformation to the gap through the arrangement of the flow guide wall, so that the randomness of the overflowing direction when a gold extrusion phenomenon occurs is solved, and corresponding measures can be better adopted for prevention; and the orientation of the gap can be adjusted according to the position of the electrode structure, so that the overflowing metal overflows towards the direction causing low short circuit risk, the short circuit risk caused by the gold extrusion phenomenon during wire welding is reduced, and the reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically, to an electrode structure, an LED chip, and a method for manufacturing the same. Background Technology

[0002] With the maturity of LED chip (light-emitting diode) technology, LED displays are constantly developing. Due to the advantages of LED chips such as small size, rich color, high resolution, long life and fast response, they are widely used in various fields. As a result, the number of LED suppliers has also increased, and the market has experienced oversupply. How to ensure the reliability of LED chips while pursuing improved optoelectronic performance is an important challenge in seizing market share.

[0003] During the wire bonding process of existing LED chips, a phenomenon known as "gold extrusion" easily occurs. This phenomenon arises when excessive bonding pressure or ultrasonic energy causes excessive plastic deformation of the conductive layer (e.g., Au layer) on the electrode surface. The deformed metal is "squeezed" out and accumulates, overflowing around the electrode. If the overflowing metal from the N electrode electrically contacts the P-type semiconductor layer, or vice versa, a short circuit can occur, affecting chip reliability. Therefore, reducing the short circuit risk caused by "gold extrusion" during wire bonding is a pressing issue that needs to be addressed. Summary of the Invention

[0004] In view of this, the present invention provides an electrode structure, an LED chip and a method for manufacturing the same, which can reduce the risk of short circuits caused by the "gold extrusion" phenomenon during wire bonding.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] An electrode structure comprising:

[0007] A first conductive layer has a notched dam, the notch being located at the outer edge of the dam; the thickness of the dam decreases from its outer edge inward to form a guide wall leading to the notch;

[0008] The second conductive layer is stacked on the current-conducting wall of the first conductive layer;

[0009] The hardness of the first conductive layer is greater than that of the second conductive layer.

[0010] Furthermore, the second conductive layer fills the dam;

[0011] The second conductive layer completely covers the surface of the dam on the side with the flow guide wall, or the second conductive layer partially covers the surface of the dam on the side with the flow guide wall.

[0012] Furthermore, it also includes an adhesive layer;

[0013] The adhesion layer is located on the side of the first conductive layer that is opposite to the second conductive layer.

[0014] Furthermore, the dam forms N steps with progressively decreasing thickness from the outer edge inwards, where N ≥ 2 and N is a positive integer.

[0015] Furthermore, the second conductive layer includes an i-th sub-layer located on the i-th step of the dam, where 1 ≤ i ≤ N; the total thickness of the first and second conductive layers is T, and the thickness of the first conductive layer on the i-th step is H. i The thickness of the i-th sublayer is M. i M i =TH i .

[0016] Furthermore, the dam has a hollow area in the middle, and the second conductive layer also includes a filling sub-layer that fills the hollow area, the thickness of which is T.

[0017] Furthermore, the second conductive layer includes the i-th sub-layer located on the i-th step of the first conductive layer, where 1≤i≤N;

[0018] By alloying the i-th step and the i-th sublayer, the stress between different film layers is reduced.

[0019] Furthermore, the first conductive layer comprises one or more of titanium, aluminum, copper, nickel, silver, platinum, palladium, and tungsten;

[0020] The second conductive layer includes one or more of gold, silver, copper, and aluminum;

[0021] The adhesive layer includes one or more of nickel, aluminum, and titanium.

[0022] The present invention also provides an LED chip, comprising:

[0023] Substrate;

[0024] An epitaxial stack is disposed on one side surface of the substrate and includes a first type semiconductor layer, an active layer and a second type semiconductor layer sequentially stacked in a direction away from the substrate.

[0025] A first electrode, which is electrically connected to the first type of semiconductor layer;

[0026] The second electrode is electrically connected to the second type of semiconductor layer;

[0027] The first electrode and / or the second electrode adopt the electrode structure described above; the current-conducting wall of the first conductive layer is away from the epitaxial stack.

[0028] Furthermore, the epitaxial stack includes grooves exposing a portion of the surface of the first type semiconductor layer;

[0029] The first electrode is disposed in the groove, and the second electrode is located on the surface of the second type semiconductor layer away from the substrate and is disposed near the edge of the second type semiconductor layer;

[0030] When the first electrode is any of the electrode structures described above, the notch of the first electrode faces away from the groove wall.

[0031] When the second electrode is any of the electrode structures described above, the notch of the second electrode is oriented away from the edge adjacent to the second type semiconductor layer.

[0032] This invention also provides a method for manufacturing an LED chip, characterized by comprising:

[0033] Provide a substrate;

[0034] An epitaxial stack is grown on one side of a substrate; the epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked in a direction away from the substrate;

[0035] A first electrode is fabricated, which is electrically connected to the first type of semiconductor layer;

[0036] A second electrode is fabricated, and the second electrode is electrically connected to the second type of semiconductor layer;

[0037] The first electrode and / or the second electrode are electrode structures as described above; the current-conducting walls of the first conductive layer are away from the epitaxial stack.

[0038] Furthermore, the dam of the electrode structure forms N steps with progressively decreasing thickness from the outer edge inwards, where N ≥ 2 and N is a positive integer:

[0039] The second conductive layer includes the i-th sub-layer located on the i-th step, where 1 ≤ i ≤ N;

[0040] The steps for fabricating the electrode structure include:

[0041] Step 1: Perform the i-th photolithography and the i-th metal evaporation to create the i-th step, and then create the i-th sublayer on the i-th step; after forming the i-th step and the i-th sublayer, perform alloying to reduce the stress between different film layers;

[0042] The temperature of the subsequent alloying is higher than that of the previous alloying, the time of the subsequent alloying is shorter than that of the previous alloying, and the temperature difference between two adjacent alloying processes is greater than or equal to 5℃.

[0043] Furthermore, the electrode structure fabrication steps also include: fabricating an adhesion layer that contacts the epitaxial stack before step one, and then performing step one on the surface of the adhesion layer away from the epitaxial stack.

[0044] Compared with existing technologies, the technical solution provided by this invention has at least the following advantages:

[0045] 1. To address the problem of short-circuit risk caused by "gold squeezing" during wire bonding, this application provides an electrode structure. The electrode structure includes a first conductive layer and a second conductive layer; the first conductive layer has a notched dam, the notch being located at the outer edge of the dam; the thickness of the dam decreases from its outer edge inwards to form a flow-guiding wall that directs flow to the notch; a second conductive layer is stacked on the flow-guiding wall of the first conductive layer; the hardness of the first conductive layer is greater than the hardness of the second conductive layer. With this configuration, when the second conductive layer deforms during wire bonding, it can be blocked by the dam formed by the harder first conductive layer, and the first conductive layer, through the flow-guiding wall, guides the overflowing metal to the notch, solving the randomness of the overflow direction when "gold squeezing" occurs. This allows for better preventative measures, and the orientation of the notch can be adjusted according to the electrode structure's location, directing the overflowing metal towards a direction with lower short-circuit risk, reducing the short-circuit risk caused by "gold squeezing" during wire bonding and increasing reliability.

[0046] 2. The height difference of the first conductive layer's guide wall is filled by the second conductive layer to increase surface flatness, which can reduce the difficulty of detecting defects in the appearance of the electrode structure, avoid the inability to distinguish dirt or scratches during testing, and reduce the difficulty of probe alignment during performance testing.

[0047] 3. An adhesive layer is provided on the side of the first conductive layer opposite to the second conductive layer to increase the adhesion of the electrode structure and prevent it from falling off.

[0048] 4. The dam is constructed by forming N progressively thinner steps from the outer edge inwards, thus reducing the thickness from the outer edge to the inner edge and achieving drainage. The stepped structure allows for more precise control of the step height and steepness through processes such as photolithography, deposition, and etching, which better prevents deformed metal from overflowing and allows for better integration with the LED chip manufacturing process when used in LED chips.

[0049] 5. By alloying the i-th step and the i-th sublayer, the stress between different film layers is reduced, stress accumulation is avoided to prevent stress concentration, and local metal deformation is improved, thus reducing the probability of "gold extrusion" phenomenon.

[0050] 6. The first electrode and / or the second electrode of the LED chip adopt any of the electrode structures described above, and therefore have any of the beneficial effects described above.

[0051] 7. When the first electrode is placed in the groove, if the deformed metal overflows toward the side wall of the groove, there is a high risk of it contacting the second type semiconductor layer and causing a short circuit. Therefore, when the first electrode adopts the above-mentioned electrode structure, the notch is away from the groove wall, which can reduce the risk of the overflowing metal contacting the second type semiconductor layer and causing a short circuit.

[0052] Considering the photoelectric performance of LED chips and the ease of wire bonding, the second electrode is generally located near the edge of the second type semiconductor layer. Therefore, the second electrode will be close to at least one edge of the second type semiconductor layer. If deformed metal overflows towards this edge line, there is a high risk of short circuit caused by contact with the first type semiconductor layer. Therefore, when the second electrode adopts the above-mentioned electrode structure, the notch of the second electrode is oriented away from the edge adjacent to the second type semiconductor layer, which can reduce the risk of short circuit caused by overflowing metal contacting the second type semiconductor layer.

[0053] 8. During electrode fabrication, alloying is performed after the formation of the i-th step and the i-th sublayer, with gradient differences in alloying conditions. Multiple alloying processes gradually release the stress in each metal layer, preventing stress accumulation and concentration, and improving local metal deformation, thus reducing the probability of "gold extrusion." Gradual heating ensures that the stress direction caused by differences in thermal expansion coefficients between layers is aligned, and the accumulation of compressive stress helps suppress tensile cracking of the electrode structure during wire bonding. The duration of the high-temperature section is shortened by gradually reducing the time required, controlling the total thermal budget (TBB) (the sum of the cumulative heat effects of all high-temperature process steps experienced by the wafer during manufacturing), preventing negative effects caused by an excessively high TTB. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0055] Figure 1 A structural diagram illustrating the "gold rush" phenomenon;

[0056] Figure 2 This is a schematic diagram of one embodiment of the electrode structure;

[0057] Figure 3 for Figure 2 Top view of the first conductive layer in the middle;

[0058] Figure 4 A schematic diagram of another embodiment of the electrode structure;

[0059] Figure 5 A schematic diagram of another embodiment of the electrode structure;

[0060] Figure 6 for Figure 5 Top view of the first conductive layer in the middle;

[0061] Figure 7 A schematic diagram of another embodiment of the electrode structure;

[0062] Figure 8 A schematic diagram of another embodiment of the electrode structure;

[0063] Figure 9 A schematic diagram of another embodiment of the electrode structure;

[0064] Figure 10 A schematic diagram of another embodiment of the electrode structure;

[0065] Figure 11 for Figure 10 Top view of the first conductive layer in the middle;

[0066] Figure 12 A schematic diagram of another embodiment of the electrode structure;

[0067] Figure 13 A schematic diagram of one embodiment of an LED chip;

[0068] Figure 14 A schematic diagram of another embodiment of an LED chip;

[0069] Figure 15 A schematic diagram of another embodiment of an LED chip;

[0070] Figure 16 This is a top view of an LED chip using ordinary electrodes.

[0071] Figure 17 A schematic diagram showing the orientation of the notch in the first conductive layer of an LED chip;

[0072] Figure 18-20 A schematic diagram illustrating the steps involved in LED chip manufacturing;

[0073] Figure 21 A schematic diagram illustrating the steps involved in fabricating the first conductive layer in the first electrode.

[0074] Figure 22 A schematic diagram illustrating the steps involved in fabricating the first conductive layer in the second electrode;

[0075] Figure 23-24 A schematic diagram illustrating the steps involved in fabricating the electrode structure.

[0076] First conductive layer 1; Notch 11; Hollow area 12; Second conductive layer 2; Adhesion 3; Substrate 4; First type semiconductor layer 5; Active layer 6; Second type semiconductor layer 7; Transparent conductive layer 8; First electrode 9; Second electrode 10; Groove 20; Electrode structure 100; Bonding wire 200. Detailed Implementation

[0077] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0078] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0079] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included. In this application, unless specifically stated otherwise, all numerical ranges include endpoint values.

[0080] like Figure 1 As shown, during the fabrication of the bonding wire 200, excessive bonding pressure or ultrasonic energy can cause excessive plastic deformation of the conductive layer on the surface of the electrode structure 100. The deformed metal is "squeezed" and accumulates, overflowing around the electrode. Furthermore, the direction of metal overflow is equally probable and random. Therefore, the electrode is prone to "gold extrusion" during wire bonding, leading to a short circuit risk. To address this, this application provides an electrode structure 100.

[0081] Combination Figure 2-3 , Figure 2 This is a cross-sectional view of one embodiment of the electrode structure 100. Figure 3 for Figure 2 A top view of the first conductive layer 1. The electrode structure 100 includes a first conductive layer 1 and a second conductive layer 2. The first conductive layer 1 has a dam with a notch 11 located at the outer edge of the dam; the thickness of the dam decreases from its outer edge inward to form a flow-guiding wall leading to the notch 11. The second conductive layer 2 is stacked on the flow-guiding wall of the first conductive layer 1; the hardness of the first conductive layer 1 is greater than the hardness of the second conductive layer 2.

[0082] With this configuration, when the second conductive layer 2 wire bonding deforms, it can be blocked by the dam formed by the first conductive layer 1, which has higher hardness. Furthermore, the first conductive layer 1 guides the deformed and overflowing metal to the notch 11 through the setting of the flow guide wall, which solves the randomness of the overflow direction when the "gold squeezing" phenomenon occurs. It can better take corresponding measures to prevent it, and the orientation of the notch 11 can be adjusted according to the position of the electrode structure 100, so that the overflowing metal overflows in the direction with low risk of short circuit, reducing the risk of short circuit caused by the "gold squeezing" phenomenon during wire bonding and increasing reliability.

[0083] Optionally, such as Figure 2 , 3 As shown, the first conductive layer 1 can be configured with a non-perforated structure in the center. Alternatively, it can be configured as follows: Figure 5 , 6 As shown, the first conductive layer 1 can be configured with a central hollow structure, that is, a hollow area 12 in the center, wherein... Figure 6 for Figure 5 Top view of the first conductive layer 1.

[0084] Based on the above embodiments, in a preferred embodiment of this application, the second conductive layer 2 fills the dam. The height difference of the first conductive layer 1's guiding wall is filled by the second conductive layer 2 to increase surface flatness, which can reduce the difficulty of detecting appearance defects of the electrode structure 100, avoid the inability to distinguish dirt or scratches during detection, and reduce the difficulty of probe alignment during performance testing.

[0085] Optionally, such as Figure 2 As shown, the second conductive layer 2 completely covers the surface of the dam on the side with the flow guide wall, that is, the entire upper surface of the electrode structure 100 is the second conductive layer 2. Or as... Figure 4 As shown, the second conductive layer 2 covers the surface of the dam on the side where the guide wall is located, that is, the upper surface of the electrode structure 100 includes the surface of the first conductive layer 1 and the surface of the second conductive layer 2. The upper and lower directions of the electrode structure 100 are... Figure 2 The direction indicated by the middle arrow.

[0086] for Figure 2 In the illustrated embodiment, although a portion of the second conductive layer 2 at the edge of the upper surface of the electrode structure 100 is not enclosed by the first conductive layer 1, its thin thickness makes it unlikely to cause a short circuit when it overflows. Figure 4 In the embodiment shown, the surface of the first conductive layer 1 on the upper surface of the electrode structure 100 is configured to be located on the periphery of the surface of the second conductive layer 2, which can better prevent the second conductive layer 2 from overflowing.

[0087] Based on any of the above embodiments, in a preferred embodiment, the electrode structure 100 further includes an adhesion layer 3, which is located on the side of the first conductive layer 1 opposite to the second conductive layer 2. Providing the adhesion layer 3 on the side of the first conductive layer 1 opposite to the second conductive layer 2 increases the adhesion of the electrode structure 100, making it less prone to detachment. Figure 7-9 They are shown respectively Figure 2 , 4 Schematic diagrams of the structures where adhesion layers 3 are respectively set at points 5 and 6. Figure 7-9 The schematic diagram shows that the thickness of the first conductive layer 1 decreases from its outer edge inwards by forming a stepped structure. Combined with... Figure 10 , 11 , Figure 10 This is a cross-sectional view of electrode structure 100. Figure 11 for Figure 10 A top view of the first conductive layer 1; the first conductive layer 1 can also achieve a decrease in the thickness of the dam from its outer edge inward by setting an inclined surface. Since the stepped structure has a higher steepness and better containment effect, this application preferably uses a stepped structure, and the following illustrations will all use a stepped structure. When the dam is a stepped structure, the surface of the stepped structure is the guide wall; when the dam is an inclined structure, the inclined surface is the guide wall. Based on any of the above embodiments, in a preferred embodiment, such as... Figure 7-9 As shown, the first conductive layer 1 forms N progressively thinner steps from the outer edge inwards, where N ≥ 2 and N is a positive integer. This design allows the dam to channel current by forming N progressively thinner steps from the outer edge inwards. The stepped structure allows for more precise control of the step height and steepness through processes such as photolithography, deposition, and etching, better preventing deformed metal from overflowing. Furthermore, when used in LED chips, it integrates better with the LED chip manufacturing process.

[0088] In this preferred embodiment, the second conductive layer 2 includes an i-th sub-layer located on the i-th step of the first conductive layer 1, where 1 ≤ i ≤ N. For example, when N is 6, ... Figure 12As shown, the first conductive layer 1 has 6 steps with gradually decreasing thickness, namely A1-A6 in the figure; the second conductive layer 2 includes sub-layers 1-6 located on A1-A6, namely B1-B6 in the figure.

[0089] More preferably, by alloying the i-th step and the i-th sublayer, the stress between different film layers is reduced, stress accumulation causing stress concentration is avoided, and local metal deformation is improved, reducing the probability of "gold extrusion" phenomenon. Alloying can be performed after each formation of the i-th step and the i-th sublayer; multiple alloying operations result in better stress reduction. The aforementioned alloying is annealing.

[0090] More preferably, or optionally, as Figure 12 As shown, the total thickness of the first conductive layer 1 and the second conductive layer 2 is T, and the thickness of the i-th step of the first conductive layer 1 is H. i The thickness of the i-th sublayer is M. i M i =TH i That is, the thickness of the first sub-layer is the total thickness T minus the thickness of the first step, the thickness of the second sub-layer is the total thickness T minus the thickness of the second step, the thickness of the third sub-layer is the total thickness T minus the thickness of the third step, and so on. Setting the total thickness to a fixed value makes the upper surface of the electrode structure 100 smoother. The thickness mentioned above refers to the thickness along the thickness direction shown in the figure. The specific value of the total thickness T can be set according to actual needs.

[0091] Based on the previous embodiment, in a preferred embodiment, the dam has a hollow area in the middle, and the second conductive layer 2 further includes a filling sub-layer that fills the hollow area, the filling sub-layer having a thickness of T. That is, as... Figure 5 , 6 As shown in Figures 9 and 1, a hollow area 12 is provided in the middle of the dam. In this case, the second conductive layer 2 includes not only the i-th sub-layer located on the i-th step of the first conductive layer 1, but also a filling sub-layer filling the hollow area 12. Based on any of the above embodiments, in a preferred embodiment, the first conductive layer 1 includes one or more of titanium, aluminum, copper, nickel, silver, platinum, palladium, and tungsten. The second conductive layer 2 includes one or more of gold, silver, copper, and aluminum. The adhesion layer 3 includes one or more of nickel, aluminum, and titanium. The materials of the first and second conductive layers can be selected from the above materials, as long as the hardness of the first conductive layer is greater than the hardness of the second conductive layer.

[0092] This application also provides an LED chip, which includes a substrate 4, an epitaxial stack, a first electrode 9, and a second electrode 10.

[0093] An epitaxial layer is disposed on one side surface of the substrate 4, and includes a first type semiconductor layer 5, an active layer 6, and a second type semiconductor layer 7 sequentially stacked in a direction away from the substrate 4; a first electrode 9 is electrically connected to the first type semiconductor layer 5; a second electrode 10 is electrically connected to the second type semiconductor layer 7; as shown Figure 13-15 As shown, the first electrode 9 and / or the second electrode 10 adopt the electrode structure 100 described in any of the above embodiments; the current-guiding wall of the first conductive layer 1 is away from the epitaxial stack, that is, the lower surface of the electrode structure 100 is in contact with the epitaxial stack. Figure 13 The first electrode 9 adopts the above-described electrode structure 100; Figure 14 The first electrode 9 and the second electrode 10 adopt the above-described electrode structure 100; Figure 15 The second electrode 10 adopts the above-described electrode structure 100.

[0094] In this design, one of the first type semiconductor layer 5 and the second type semiconductor layer 7 is N-type doped and the other is P-type doped; for example, the first type semiconductor layer 5 is N-type GaN and the second type semiconductor layer 7 is P-type GaN, but the materials are not limited to these and can be adjusted according to the light emission requirements of the LED chip. The substrate 4 includes, but is not limited to, a sapphire substrate 4. The active layer 6 can adopt a multi-quantum-well structure, such as a multi-quantum-well structure composed of InGaN and GaN, but the materials are not limited to these and can be adjusted according to the light emission requirements of the LED chip.

[0095] Optionally, this application uses an LED chip with a horizontal structure as an example. When the LED chip has a horizontal structure, such as... Figure 13 The epitaxial stack shown includes a groove 20 that exposes a portion of the surface of the first type semiconductor layer 5; the first electrode 9 is disposed in the groove 20, and the second electrode 10 is located on the surface of the second type semiconductor layer 7 away from the substrate 4 and is disposed close to the edge of the second type semiconductor layer 7. Figure 17 The orientation of the notch 11 in the dam is illustrated. When the first electrode 9 is the electrode structure 100 described in any of the above embodiments, the notch 11 of the first electrode 9 is oriented away from the groove wall of the groove 20. When the second electrode 10 is the electrode structure 100 described in any of the above embodiments, the notch 11 of the second electrode 10 is oriented away from the edge adjacent to the second type semiconductor layer 7.

[0096] Figure 16The diagram shows a top view of an LED chip using conventional electrodes. When the first electrode 9 overflows into the groove wall of the recess 20, there is a high risk of short circuit due to contact with the second semiconductor layer 7. When the second electrode 10 overflows in the X and Y directions (as shown in the diagram), it overflows towards the edge adjacent to the second semiconductor layer 7, posing a high risk of short circuit due to contact with the first semiconductor layer 5. Existing technologies typically increase the spacing between L1, L2, L3, L4, and L5 to prevent this, but the effect is limited, and such a design can negatively impact the product's photoelectric performance. Therefore, when the first electrode 9 uses the aforementioned electrode structure 100, the notch 11 is positioned away from the groove wall of the recess 20, reducing the risk of short circuit caused by overflowing metal contacting the second semiconductor layer 7.

[0097] Considering the photoelectric performance of LED chips and the ease of wire bonding, the second electrode 10 is generally located near the edge of the second type semiconductor layer 7. Therefore, the second electrode 10 will be close to at least one edge of the second type semiconductor layer 7. If deformed metal overflows towards this edge line, there is a high risk of short circuit caused by contact with the first type semiconductor layer 5. Therefore, when the second electrode 10 adopts the above-mentioned electrode structure 100, the notch 11 of the second electrode 10 is oriented away from the edge adjacent to the second type semiconductor layer 7, which can reduce the risk of overflowing metal contacting the second type semiconductor layer 7 and causing a short circuit.

[0098] The first electrode 9 and / or the second electrode 10 of the LED chip adopt the electrode structure 100 of any of the above embodiments. Therefore, any parts not mentioned can refer to the electrode structure 100 of any of the above embodiments and have any of the above-mentioned beneficial effects, which will not be repeated here. This application also provides a method for manufacturing an LED chip, which can be used to manufacture the above-mentioned LED chip, including the following steps:

[0099] S01: Provide a substrate 4.

[0100] S02: An epitaxial stack is grown on one side of the substrate 4; the epitaxial stack includes a first-type semiconductor layer 5, an active layer 6, and a second-type semiconductor layer 7 sequentially stacked along a direction away from the substrate 4. Taking an LED chip as a horizontal structure as an example, as... Figure 18 , 19 As shown, after the epitaxial stack is grown, the grooves 20 for exposing the first type semiconductor layer 5 need to be created through photolithography and etching processes.

[0101] Optionally, after the groove 20 is fabricated, a transparent conductive layer 8 is formed on the surface of the second type semiconductor layer 7 facing away from the substrate 4. The transparent conductive layer 8 can be a single metal thin film such as gold, silver, platinum, copper, aluminum, chromium, palladium, etc., or a metal oxide such as indium oxide, indium tin oxide, zirconium oxide, cadmium oxide, titanium nitride, etc., or a mixture of multiple oxides doped in different proportions.

[0102] S03: Fabricate a first electrode 9, which is electrically connected to the first type of semiconductor layer 5.

[0103] S04: Fabricate a second electrode 10, which is electrically connected to the second type semiconductor layer 7; the first electrode 9 and / or the second electrode 10 are electrode structures 100 as described in any of the above embodiments; the current-conducting walls of the first conductive layer 1 are away from the epitaxial stack. After fabricating the first electrode 9 and the second electrode 10, a... Figure 13-15 The chip shown.

[0104] More preferably, in step S03 and / or step S04, such as Figure 12 As shown, the dam of the electrode structure 100 forms N steps with progressively decreasing thickness from the outer edge inward, where N ≥ 2 and N is a positive integer; the second conductive layer 2 includes the i-th sub-layer located on the i-th step, where 1 ≤ i ≤ N;

[0105] The fabrication steps of the electrode structure 100 include:

[0106] Step 1: Perform the i-th photolithography and the i-th metal evaporation to create the i-th step, and create the i-th sublayer on the i-th step; after forming the i-th step and the i-th sublayer, perform alloying to reduce the stress between different film layers; the temperature of the subsequent alloying is higher than the temperature of the previous alloying, the time of the subsequent alloying is shorter than the time of the previous alloying, and the temperature difference between two adjacent alloying operations is greater than or equal to 5°C.

[0107] This configuration allows for alloying of the electrode structure 100 after the formation of the i-th step and the i-th sublayer, with gradient differences in alloying conditions. Multiple alloying processes gradually release stress in each metal layer, preventing stress accumulation and concentration, and improving local metal deformation, thus reducing the probability of "gold extrusion." Gradual heating ensures that the stress direction caused by differences in thermal expansion coefficients among layers is aligned, and the accumulation of compressive stress helps suppress tensile cracking of the electrode structure 100 during wire bonding. By gradually reducing the time spent in the high-temperature phase, the total thermal budget (TBB) (the sum of the cumulative heat effects of all high-temperature process steps experienced by the wafer during manufacturing) is controlled, preventing negative effects caused by an excessively high TTB.

[0108] More preferably, the fabrication steps of the electrode structure 100 further include: fabricating an adhesion layer 3 in contact with the epitaxial stack before step one, and then performing step one on the surface of the adhesion layer 3 away from the epitaxial stack.

[0109] like Figure 23As shown, a first photolithography and a first metal evaporation are performed on the adhesion layer 3 to create the first step, and the first sublayer is created on the first step; after the formation of the first step and the first sublayer, alloying is performed to reduce the stress between different film layers.

[0110] like Figure 24 As shown, a second photolithography and a second metal evaporation are performed on the adhesion layer 3 to create the second step, and then the second sublayer is created on the second step; after the formation of the second step and the second sublayer, alloying is performed to reduce the stress between different film layers.

[0111] And so on, with Figure 7 Taking the electrode structure 100 shown as an example, the first conductive layer 1 has 6 steps. The electrode structure 100 is completed after the 6th step and the 6th sub-layer are fabricated and alloyed. A total of 6 alloying operations are performed. In each of the 6 alloying operations, the temperature of the later alloying operation is higher than the temperature of the previous alloying operation, the time of the later alloying operation is shorter than the time of the previous alloying operation, and the temperature difference between two adjacent alloying operations is greater than or equal to 5°C.

[0112] Figure 21 A schematic diagram showing the fabrication process of the first conductive layer 1 of the second electrode 10 is shown. Figure 21 (a) The dashed area is the fabrication area of ​​the second electrode 10. Figure 21 (b)-(d) show the structural diagrams after the fabrication of the first step of the first conductive layer 1, the structural diagram after the fabrication of the second step of the first conductive layer 1, and the structural diagram after the fabrication of the first to sixth steps of the first conductive layer 1, respectively. The fabrication area of ​​the second electrode 10 is not limited to the circle shown in the figures, but can be any shape.

[0113] Figure 22 A schematic diagram showing the fabrication process of the first conductive layer 1 of the first electrode 9 is shown. Figure 22 (a) The dashed area is the fabrication area of ​​the first electrode 9. Figure 22 (b)-(d) show the structural diagrams after the fabrication of the first step of the first conductive layer 1, the structural diagram after the fabrication of the second step of the first conductive layer 1, and the structural diagram after the fabrication of the first to sixth steps of the first conductive layer 1, respectively. The fabrication area of ​​the second electrode 10 is not limited to the polygonal shape shown in the diagrams; it can be any shape.

[0114] right Figure 7 In addition to the above method, the electrode structure 100 shown can also be fabricated by first depositing a whole layer of first conductive layer 1 material with the same thickness as the 6th step, and then forming the 1st to 5th steps of the first conductive layer 1 and the 5th sublayer of the second conductive layer 2 by 5 photolithography and 5 vapor deposition, and then fabricating the 6th sublayer.

[0115] right Figure 8 The electrode structure 100 shown differs from the above-described fabrication method in that the second conductive layer 2 is not deposited on the first step of the first conductive layer 1, while the fabrication steps of the second to sixth steps and the second conductive layer 2 on the second to sixth steps are the same as those described above.

[0116] right Figure 9 The electrode structure 100 shown differs from the above fabrication method in that, after the first to fifth steps and the first to fifth sub-layers are fabricated by five photolithography and five vapor deposition processes, the second conductive layer 2 is then fabricated by photolithography and vapor deposition.

[0117] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0118] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0119] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electrode structure, characterized in that, include: A first conductive layer has a notched dam, the notch being located at the outer edge of the dam; the thickness of the dam decreases from its outer edge inward to form a guide wall leading to the notch; The second conductive layer is stacked on the current-conducting wall of the first conductive layer; The hardness of the first conductive layer is greater than that of the second conductive layer.

2. The electrode structure as described in claim 1, characterized in that, The second conductive layer fills the dam; The second conductive layer completely covers the surface of the dam on the side with the flow guide wall, or the second conductive layer partially covers the surface of the dam on the side with the flow guide wall.

3. The electrode structure as described in claim 1, characterized in that, It also includes an adhesive layer; The adhesion layer is located on the side of the first conductive layer that is opposite to the second conductive layer.

4. An electrode structure as described in claim 1 or 3, characterized in that, The dam consists of N steps with progressively decreasing thickness from the outer edge inwards, where N ≥ 2 and N is a positive integer.

5. An electrode structure as described in claim 4, characterized in that, The second conductive layer includes the i-th sub-layer located on the i-th step of the dam, where 1≤i≤N; The total thickness of the first conductive layer and the second conductive layer is T, and the thickness of the i-th step of the first conductive layer is H. i The thickness of the i-th sublayer is M. i M i =TH i .

6. The electrode structure as described in claim 5, characterized in that, The dam has a hollowed-out area in the middle. The second conductive layer further includes a filler sublayer that fills the cutout area, and the thickness of the filler sublayer is T.

7. An electrode structure as described in claim 4, characterized in that, The second conductive layer includes the i-th sub-layer located on the i-th step of the first conductive layer, where 1≤i≤N; By alloying the i-th step and the i-th sublayer, the stress between different film layers is reduced.

8. An electrode structure as described in claim 1, characterized in that, The first conductive layer comprises one or more of titanium, aluminum, copper, nickel, silver, platinum, palladium, and tungsten; The second conductive layer includes one or more of gold, silver, copper, and aluminum; The adhesive layer includes one or more of nickel, aluminum, and titanium.

9. An LED chip, characterized in that, include: Substrate; An epitaxial stack is disposed on one side surface of the substrate and includes a first type semiconductor layer, an active layer and a second type semiconductor layer sequentially stacked in a direction away from the substrate. A first electrode, which is electrically connected to the first type of semiconductor layer; The second electrode is electrically connected to the second type of semiconductor layer; The first electrode and / or the second electrode adopt the electrode structure described in any one of claims 1-8; the current-conducting wall of the first conductive layer is away from the epitaxial stack.

10. An LED chip as described in claim 9, characterized in that, The epitaxial stack includes grooves that expose a portion of the surface of the first type semiconductor layer; The first electrode is disposed in the groove, and the second electrode is located on the surface of the second type semiconductor layer away from the substrate and is disposed near the edge of the second type semiconductor layer; When the first electrode is the electrode structure described in any one of claims 1-8, the notch of the first electrode faces away from the groove wall. When the second electrode is the electrode structure described in any one of claims 1-8, the notch of the second electrode is oriented away from the edge adjacent to the second type semiconductor layer.

11. A method for manufacturing an LED chip, characterized in that, include: Provide a substrate; An epitaxial stack is grown on one side of the substrate; The epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked along a direction away from the substrate; A first electrode is fabricated, which is electrically connected to the first type of semiconductor layer; A second electrode is fabricated, and the second electrode is electrically connected to the second type of semiconductor layer; The first electrode and / or the second electrode are electrode structures as described in any one of claims 1-8; the current-conducting walls of the first conductive layer are away from the epitaxial stack.

12. The method for manufacturing an LED chip as described in claim 11, characterized in that, The dam of the electrode structure forms N steps with progressively decreasing thickness from the outer edge inwards, where N ≥ 2 and N is a positive integer. The second conductive layer includes the i-th sub-layer located on the i-th step, where 1 ≤ i ≤ N; The steps for fabricating the electrode structure include: Step 1: Perform the i-th photolithography and the i-th metal evaporation to create the i-th step, and then create the i-th sublayer on the i-th step; after forming the i-th step and the i-th sublayer, perform alloying to reduce the stress between different film layers; The temperature of the subsequent alloying is higher than that of the previous alloying, the time of the subsequent alloying is shorter than that of the previous alloying, and the temperature difference between two adjacent alloying processes is greater than or equal to 5℃.

13. The method for manufacturing an LED chip as described in claim 12, characterized in that, The electrode structure fabrication steps further include: fabricating an adhesion layer that contacts the epitaxial stack before step one, and then performing step one on the surface of the adhesion layer away from the epitaxial stack.

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