Three-dimensional core particle stacked system-on-chip and manufacturing method thereof

Abstract

The invention discloses a three-dimensional core particle stacked system chip and a manufacturing method thereof, the three-dimensional core particle stacked system chip comprises a main core particle, a sub core particle and an interconnection adapter, the interconnection adapter comprises an adapter sheet body, the adapter sheet body is bonded on the surface of the main core particle through a bonding body, and the adapter sheet body and the sub core particle are in the same plane; a first interconnection adapter body is arranged on the edge of one side, close to the sub-core particles, of the adapter sheet body, and the first interconnection adapter body is connected with the sub-core particles; the bottom of the first interconnection adapter is provided with a first bottom metal micro-bump, and a first top metal micro-bump is arranged between the first bottom metal micro-bump and the sub-core particle I / O bonding pad. According to the invention, the processing technology of the cell array memory core particles is simplified, and the overall packaging technology difficulty of a system chip is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip manufacturing, and in particular to a three-dimensional stacked system-on-a-chip and its manufacturing method. Background Technology

[0002] System-in-Package (SiP) combines multiple active components with different functions, as well as passive components, microelectromechanical systems (MEMS), optical components, and other components, into a single unit to form a system or subsystem that can provide multiple functions, allowing for the integration of heterogeneous ICs. It effectively solves the problem that System-on-Chip (SoC) cannot integrate analog, radio frequency, and digital functions. SiP integration is relatively simple, with shorter design and time-to-market cycles, lower costs, and the ability to implement more complex systems.

[0003] In existing technologies, during chip packaging, the chip is first bonded to one side of a wafer without being electrically connected to the wafer. Then, a molding process is performed to seal and fix the chip. Finally, a via (with a conductive structure within it) is formed on the other side of the wafer to allow the chip's electrical signals to be led out. However, existing technologies suffer from low system-level packaging integration. Summary of the Invention

[0004] To address the aforementioned problems, the present invention aims to provide a three-dimensional stacked chip system-on-a-chip comprising: The main chip 900 includes main chip I / O pads 911 disposed on the surface; Sub-core 100 includes a sub-core I / O pad 111 disposed on the front side, which is bonded to the surface of the main core 900 by a bonding body 101, and the corresponding sub-core I / O pad is perpendicular to the main core I / O pad 911. Interconnect adapter 180 includes an adapter body 199, which is bonded to the surface of the main core 900 via a bonding body 101 and is on the same plane as the sub-core 900; a first interconnect adapter 192 is provided on the edge of the adapter body 199 near the sub-core 100, and the first interconnect adapter 192 is connected to the sub-core 100; the bottom of the first interconnect adapter 192 has a first bottom metal microbump 151B, and a first top metal microbump 151T is also provided between the first bottom metal microbump 151B and the sub-core I / O pad; the adapter body 199 The back side is provided with a second interconnecting adapter pad 191, and a vertical conductive plug 181 is also provided therein. The front side of the adapter body 199 corresponding to the bottom of the vertical conductive plug 181 is provided with a first adapter I / O pad 112. A second top metal microbump 161T is provided below the first adapter I / O pad 112. A second bottom metal microbump 161B is provided below the second top metal microbump 161T. The second bottom metal microbump 161B is located on the main chip I / O pad 911 and is electrically interconnected with the main chip I / O pad 911.

[0005] In addition, the present invention also provides a method for manufacturing a three-dimensional stacked system-on-a-chip, comprising the following steps: S10: Provide a wafer comprising at least two identical master dies arranged in an array, the master dies comprising master die I / O pads disposed on a surface; Several sub-cores are provided, including sub-core I / O pads disposed on the front side; Several adapter plates are provided, each containing a vertical conductive plug. A first interconnect adapter I / O pad is provided on the front of the adapter plate corresponding to the bottom of the vertical conductive plug. A bonding assembly is formed on the wafer, exposing the main die I / O pads; S20: The sub-core and the adapter body are bonded to the main core with the front side of the bonding body facing the main core. There is a gap between the sub-core and the adapter body. The I / O pads of the sub-core and the I / O pads of the main core are perpendicular to each other and there is a first cavity between them that communicates with the gap. The I / O pads of the first adapter body and the I / O pads of the main core are perpendicular to each other and there is a second cavity. S30: A first top metal microbump is formed on the surface of the sub-core I / O pad through the gap, and a first bottom metal microbump is formed on the surface of the main core I / O pad. The first top metal microbump covers part of the surface of the first bottom metal microbump and is electrically interconnected. A second top metal microbump is formed on the surface through the gap or the outside of the interconnect adapter body, and a second bottom metal microbump is formed on the surface of the main core I / O pad. The second top metal microbump covers the surface of the second bottom metal microbump and is electrically interconnected. S40: Fill the gap with an insulating medium to form a first interconnecting adapter; S50: A second interconnection adapter pad is formed on the surface of the back side of the adapter body and interconnected with the vertical conductive plug. The three-dimensional stacked high-bandwidth memory system chip provided by this invention fundamentally eliminates the need for vertical embedding of silicon through-hole metal interconnect pillars into each chip to achieve vertical interconnection between chips. This not only significantly simplifies the manufacturing process of cell array memory chip wafers but also eliminates the need for chip stacking and micro-bump array flip-chip bonding or copper-copper micro-solder hybrid bonding interconnection. Simultaneously, it allocates the chip area required for embedding the silicon through-hole metal interconnect pillar array to the cell array memory, providing an effective technical approach to simplify the cell array memory chip processing technology, reduce the overall packaging difficulty of the system chip, improve the overall yield of the system chip, and reduce the overall manufacturing cost. This invention, through three-dimensional chip stacking, solves the problem that chips with different process technologies cannot be formed on the same production line, and the problem of increased volume caused by packaging chips with different processes. This results in larger computing chips with higher integration, lower power consumption, and faster speed. Attached Figure Description

[0006] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0007] Figure 1 This is a cross-sectional schematic diagram of a three-dimensional stacked system-on-a-chip according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of a method for manufacturing a three-dimensional stacked system-on-a-chip according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a method for manufacturing a three-dimensional stacked system-on-a-chip according to an embodiment of the present invention.

[0008] For ease of understanding and explanation, the labels in the diagram are as follows: Main chip - 900 Main chip I / O pads - 911 Sub-core chip-100 Adapter chip-199 Sub-core I / O pad-111 First adapter I / O pad-112 Bonding body-101 Interconnector-180 Vertical Conductive Plug-181 Adapter Plate-182 First bottom metal microbump - 151B First top metal microbump - 151T Second bottom metal microbump - 161B Second top metal microbump - 161T Second interconnect adapter pad -191 First interconnect adapter -192 Second vertical dielectric adapter 161 Second adapter I / O pad 113 Third sub-core 300 layers; Second sub-core 200 layers Gap 210 First cavity -220 Second cavity -230 Detailed Implementation

[0009] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0010] In this invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower parts of the device in its normal operating state, while "inner" and "outer" refer to the parts relative to the outline of the device. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. This invention pertains to electrical devices; therefore, connection and interconnection both refer to conductive interconnection. Since the accompanying drawings describe the same device, the same reference numerals denote the same components. The term "chip front" as used herein refers to the side of the wafer used to form the device during chip manufacturing, and "back" refers to the substrate side of the wafer.

[0011] like Figure 1 As shown, one embodiment of the present invention provides a three-dimensional stacked system-on-a-chip, comprising: The main chip 900 includes main chip I / O pads 911 disposed on the surface; Sub-core 100 includes a sub-core I / O pad 111 disposed on the front side, which is bonded to the surface of the main core 900 by a bonding body 101, and the corresponding sub-core I / O pad is perpendicular to the main core I / O pad 911. Interconnect adapter 180 includes an adapter body 199, which is bonded to the surface of the main core 900 via a bonding body 101 and is on the same plane as the sub-core 900; a first interconnect adapter 192 is provided on the edge of the adapter body 199 near the sub-core 100, and the first interconnect adapter 192 is connected to the sub-core 100; the bottom of the first interconnect adapter 192 has a first bottom metal microbump 151B, and a first top metal microbump 151T is also provided between the first bottom metal microbump 151B and the sub-core I / O pad; the adapter body 199 The back side is provided with a second interconnecting adapter pad 191, and a vertical conductive plug 181 is also provided therein. The front side of the adapter body 199 corresponding to the bottom of the vertical conductive plug 181 is provided with a first adapter I / O pad 112. A second top metal microbump 161T is provided below the first adapter I / O pad 112. A second bottom metal microbump 161B is provided below the second top metal microbump 161T. The second bottom metal microbump 161B is located on the main chip I / O pad 911 and is electrically interconnected with the main chip I / O pad 911.

[0012] In one embodiment, such as Figure 1 The first bottom metal microbump 151B and the second bottom metal microbump 161B shown in the right-hand region are a single unit. That is, the first top metal microbump 151T and the second top metal microbump 161T are interconnected with the same bottom metal microbump.

[0013] In one embodiment, the outer side of the adapter body 199 and the outer side of the second bottom metal microbump 161B and the second top metal microbump 161T are filled with an insulating dielectric material of the same material as the first interconnect adapter 192 to form a second vertical dielectric adapter 161. That is, the first bottom metal microbump 151B and the second bottom metal microbump 161B are independent structures, and the second bottom metal microbump 161B and the second top metal microbump 161T are located in the edge region on the side of the back ion core of the adapter body 199.

[0014] In one embodiment, the main chip 900 is the main control logic chip, and the sub-chips 100 are storage unit chips, which are stacked in an array on the main chip 900. Each main control logic chip is connected to the array of storage unit chips. This constitutes a chip system that can meet a large computing power requirement.

[0015] In one embodiment, several sub-core layers are further bonded to the back side of the sub-core 100, such as a second sub-core layer 200, a third sub-core layer, etc. The specific number of layers can be set as needed, and the function and type of each sub-core layer can be set as needed without limitation. Sub-cores in the same layer can also be sub-cores with different functions and types. The interconnection method between sub-core layers is the same as the interconnection method between sub-core layers and main core layers. In other words, the second sub-core layer 200 can adopt the same structure as the sub-core layer, that is, it can include the first sub-core disposed on the front side. I / O pads 111 are bonded to the surface of the main chip 900 via bonding bodies 101, and the corresponding first sub-chip I / O pads are perpendicular to the main chip I / O pads 911. The same interconnect adapters 180 are used to achieve interconnection between the second sub-chip layer and the sub-chip layer. Similarly, the third sub-chip layer can adopt the same structure as the second sub-chip layer 200. The second sub-chip layer 200 is also interconnected with the third sub-chip layer 300 using the same interconnect adapters 180. Multi-layer stacked chip systems formed in this way are all within the protection scope of this invention.

[0016] In one embodiment, the insulating medium is composed of one or a mixture of silicon-containing dielectric compounds, carbon compounds, and nitrogen compounds. This forms vertical interconnect dielectric sidewalls 161 and first interconnect adapters 192 made of the same material.

[0017] In one embodiment, the vertical conductive plug 181 is made of, for example, silicon or one of copper, aluminum, tungsten, molybdenum, nickel, tantalum, titanium or their alloys, or polycrystalline silicon or SeGe.

[0018] In one embodiment, the first top metal microbump 151T and the first bottom metal microbump 151B, as well as the second top metal microbump 161T and the second bottom metal microbump 161B, are made of one or an alloy of copper, aluminum, tungsten, molybdenum, nickel, tin, cobalt, tantalum, silver, and gold, or of polycrystalline silicon or SeGe.

[0019] In one embodiment, the I / O pads 911 of the main chip, the I / O pads of the sub-chip, the first interconnect I / O pad 112, and the second interconnect I / O pad 191 are made of one of aluminum, copper, nickel, titanium, tungsten, cobalt, tantalum, silver, gold, or an alloy thereof, or of polysilicon or SeGe.

[0020] In one embodiment, the sub-chip array is one or a combination of DRAM based on charge storage cells, NOR and NAND based on floating gate charge type memory, RRAM based on resistive cells, and MRAM based on magnetoresistive cells.

[0021] The embodiments will now be described in detail with reference to the accompanying drawings. Figure 2A flowchart illustrating a three-dimensional stacked system-on-a-chip according to an embodiment of the present invention is provided below. Figures 1 to 3 The manufacturing method of the three-dimensional stacked system-on-a-chip includes the following steps: S10: Provide a wafer 10, the wafer 10 including at least two identical master dies 900 arranged in an array, the master dies including master die I / O pads 911 disposed on the surface; Several adapter plates 199 are provided, and a vertical conductive plug 181 is also provided inside the adapter plate 199. A first interconnect adapter I / O pad 112 is provided on the front side of the adapter plate 199 corresponding to the bottom of the vertical conductive plug 181. A bonding body 101 is formed on the wafer, exposing the main die I / O pads 911.

[0022] Specifically, in this embodiment, such as Figure 3 As shown, wafer 10 includes a semiconductor substrate 100, which is silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. In this embodiment, a silicon substrate is used. An epitaxial layer is formed on the silicon substrate, and multiple bare chips, i.e., main chips 900, consisting of an array of semiconductor devices, are formed in the epitaxial layer and the silicon substrate. An insulating layer is also formed on the epitaxial layer. The insulating layer is made of materials such as silicon dioxide and silicon nitride. The insulating layer covers the semiconductor devices and has main chip I / O metal pads 911 on the insulating layer that are interconnected with the semiconductor devices.

[0023] In this embodiment, the sub-chip 100 is a memory cell chip, specifically a bare chip. It has I / O pads on its front side. The first sub-chip I / O pad 111 has through-holes penetrating the sub-chip, and the bottom of the second sub-chip I / O pad 111 is interconnected with vertical conductive plugs 181 penetrating the sub-chip. Besides memory cells, the sub-chip can also be logic circuits composed of MOS transistors, or semiconductor devices such as MEMS and sensors. Furthermore, different sub-chips can be of different types, containing different semiconductor devices. The sub-chip can be the same bare chip located on the same wafer, or it can be a device formed using a different semiconductor process than the main chip. Therefore, this invention solves the problem that chips with different process processes cannot be formed on the same production line, and the problem of increased size caused by packaging chips with different processes.

[0024] The bonded material can be a bonding dielectric sheet, such as dielectric silicon dioxide or silicon nitride. It will become molten upon heating.

[0025] S20: The sub-core 100 and the adapter plate are bonded to the main core with the front side facing the main core via a bonding body. There is a gap 210 between the sub-core 100 and the adapter plate. The sub-core I / O pad 111 and the main core I / O pad 911 are perpendicular to each other and have a first cavity 220 communicating with the gap 210. The first adapter I / O pad 112 and the main core I / O pad 911 are perpendicular to each other and have a second cavity 230.

[0026] Specifically, the main chip is the main control logic chip, and the sub-chips are memory cell chips. The sub-chips are stacked in an array on the main chip, with one main control logic chip corresponding to the array of memory cell chips. In one embodiment, the sub-chips can be an array of sub-chips located on the same wafer. The sub-chip array is one or a combination of DRAM based on charge storage cells, NOR and NAND based on floating gate charge type memory, RRAM based on resistive cells, and MRAM based on magnetoresistive cells.

[0027] S30: A first top metal microbump 151T is formed on the surface of the sub-core I / O pad 111 through the gap 210, and a first bottom metal microbump 151B is formed on the surface of the main core I / O pad 911. The first top metal microbump 151T covers a portion of the surface of the first bottom metal microbump 151B and is electrically interconnected. A second top metal microbump 161T is formed on the surface of the first adapter I / O pad 112 through the gap 210 or the outside of the adapter body 199, and a second bottom metal microbump 161B is formed on the surface of the main core I / O pad 911. Two top metal microbumps 161T cover the surface of the second bottom metal microbump 161B and are electrically interconnected. In this embodiment, electroplating or chemical plating can be used to grow metal from the surface of the metal pad until the metals come into contact together to form the first top metal microbump 151T and the first bottom metal microbump 151B, and the second top metal microbump 161T and the second bottom metal microbump 161B. In this embodiment, the metal microbumps are made of one or an alloy of copper, aluminum, tungsten, molybdenum, nickel, tin, cobalt, tantalum, silver, and gold, or polycrystalline silicon or SeGe.

[0028] S40: Reference Figure 3 An insulating medium is filled into the gap to form a first interconnecting adapter 192.

[0029] The insulating medium is composed of one or a mixture of silicon-containing dielectric compounds, carbon compounds, and nitrogen compounds.

[0030] S50: A second interconnecting adapter pad 191 is formed on the surface of the back side of the adapter body 199 and interconnected with the vertical conductive plug.

[0031] The second interconnect pad 191 is made of one of the following metals: aluminum, copper, molybdenum, nickel, titanium, tungsten, cobalt, tantalum, silver, gold, or an alloy thereof, or of polysilicon or SeGe.

[0032] Formed by physical vapor deposition (PVD) methods such as magnetron sputtering or evaporation, or chemical vapor deposition. It is composed of silicon or one of copper, aluminum, tungsten, molybdenum, nickel, tantalum, titanium, or their alloys, or of polycrystalline silicon or SeGe.

[0033] In one embodiment, such as Figure 3 As shown on the right, the first cavity 220 and the second cavity 230 are connected; the first bottom metal microbump 151B and the second bottom metal microbump 161B are a single unit. A second top metal microbump 161T is formed on the surface of the second adapter I / O pad 113 through the gap 210, and a second bottom metal microbump 161B is formed on the surface of the main chip I / O pad 911. The second top metal microbump 161T covers the surface of the second bottom metal microbump 161B and is electrically interconnected; the first bottom metal microbump 151B and the second bottom metal microbump 161B are a single unit.

[0034] In one embodiment, such as Figure 3 As shown in the left region, a bonding body 101 is isolated between the first cavity 220 and the second cavity 230. The second cavity 220 is connected to the outside of the adapter body 100. A second top metal microbump 161T is formed on the surface of the first adapter body I / O pad 112 through the outside, and a second bottom metal microbump 161B is formed on the surface of the main core I / O pad 911. The second top metal microbump 161T covers the surface of the second bottom metal microbump 161B and is electrically interconnected. An insulating medium is filled on the outside of the adapter body 199 to form a second vertical dielectric adapter body 161.

[0035] In one embodiment, the process further includes forming I / O pads on the back side of the sub-core, continuing the bonding, and then using steps S20 to S50 to continue bonding several sub-core layers. The functional devices of each sub-core layer can be the same or different, thereby forming a multi-layer stacked structure. The specific number of stacked layers is determined as needed.

[0036] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A three-dimensional stacked chip system-on-a-chip, characterized in that, include: The main chip 900 includes main chip I / O pads 911 disposed on the surface; Sub-core 100 includes a sub-core I / O pad 111 disposed on the front side, which is bonded to the surface of the main core 900 by a bonding body 101, and the corresponding sub-core I / O pad is perpendicular to the main core I / O pad 911. Interconnect adapter 180 includes an adapter body 199, which is bonded to the surface of the main core 900 via a bonding body 101 and is on the same plane as the sub-core 900; a first interconnect adapter 192 is provided on the edge of the adapter body 199 near the sub-core 100, and the first interconnect adapter 192 is connected to the sub-core 100; the bottom of the first interconnect adapter 192 has a first bottom metal microbump 151B, and a first top metal microbump 151T is also provided between the first bottom metal microbump 151B and the sub-core I / O pad; the adapter body 199 The back side is provided with a second interconnecting adapter pad 191, and a vertical conductive plug 181 is also provided therein. The front side of the adapter body 199 corresponding to the bottom of the vertical conductive plug 181 is provided with a first adapter I / O pad 112. A second top metal microbump 161T is provided below the first adapter I / O pad 112. A second bottom metal microbump 161B is provided below the second top metal microbump 161T. The second bottom metal microbump 161B is located on the main chip I / O pad 911 and is electrically interconnected with the main chip I / O pad 911.

2. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The first bottom metal microbump 151B and the second bottom metal microbump 161B are a single unit.

3. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The outer side of the adapter body 199 and the outer side of the second bottom metal microbump 161B and the second top metal microbump 161T are filled with an insulating medium of the same material as the first interconnect adapter 192 to form a second vertical dielectric adapter 161.

4. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The main chip is the main control logic chip, and the sub-chips are storage unit chips, which are stacked in an array on the main chip. One main control logic chip is connected to the array of storage unit chips.

5. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, Several sub-core layers are also bonded on the back side of the sub-core, and the interconnection method between the sub-core layers is the same as the interconnection method between the sub-core layers and the main core layer; an interconnection adapter 180 located on the same layer as the sub-core is provided on the periphery of each sub-core layer.

6. The three-dimensional stacked system-on-a-chip as described in claim 3, characterized in that, The insulating medium is composed of one or a mixture of silicon-containing dielectric compounds, carbon compounds, and nitrogen compounds.

7. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The vertical conductive plug is made of silicon or one of copper, aluminum, tungsten, molybdenum, cobalt, nickel, tantalum, titanium or their alloys, or of polycrystalline silicon or SeGe.

8. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The first top metal microbump 151T and the first bottom metal microbump 151B, the second top metal microbump 161T and the second bottom metal microbump 161B are made of one or an alloy of copper, aluminum, tungsten, titanium, nickel, tin, cobalt, tantalum, silver and gold, or are made of polycrystalline silicon or SeGe.

9. The three-dimensional stacked system-on-a-chip as described in claim 1, characterized in that, The I / O pads of the main chip, the I / O pads of the sub-chip, and the interconnect pads are made of one of the following metals: aluminum, copper, nickel, titanium, tungsten, cobalt, tantalum, silver, gold, or an alloy thereof, or of polysilicon or SeGe.

10. The three-dimensional stacked system-on-a-chip as described in claim 4, characterized in that, The sub-core array is one or a combination of DRAM based on charge storage cells, NOR and NAND based on floating gate charge memory, RRAM based on resistive cells, and MRAM based on magnetoresistive cells.

11. A method for manufacturing a three-dimensional stacked system-on-a-chip according to claims 1 to 10, characterized in that, Including the following steps: S10: Provide a wafer comprising at least two identical master dies arranged in an array, the master dies comprising master die I / O pads disposed on a surface; Several sub-cores are provided, including sub-core I / O pads disposed on the front side; Several adapter plates are provided, each containing a vertical conductive plug. A first interconnect adapter I / O pad is provided on the front of the adapter plate corresponding to the bottom of the vertical conductive plug. A bonding assembly is formed on the wafer, exposing the main die I / O pads; S20: The sub-core and the adapter body are bonded to the main core with the front side of the bonding body facing the main core. There is a gap between the sub-core and the adapter body. The I / O pads of the sub-core and the I / O pads of the main core are perpendicular to each other and there is a first cavity between them that communicates with the gap. The I / O pads of the first adapter body and the I / O pads of the main core are perpendicular to each other and there is a second cavity. S30: A first top metal microbump is formed on the surface of the sub-core I / O pad through the gap, and a first bottom metal microbump is formed on the surface of the main core I / O pad. The first top metal microbump covers part of the surface of the first bottom metal microbump and is electrically interconnected. A second top metal microbump is formed on the surface through the gap or the outside of the interconnect adapter body, and a second bottom metal microbump is formed on the surface of the main core I / O pad. The second top metal microbump covers the surface of the second bottom metal microbump and is electrically interconnected. S40: Fill the gap with an insulating medium to form a first interconnecting adapter; S50: A second interconnecting adapter pad is formed on the surface of the back side of the adapter body and interconnected with the vertical conductive plug.

12. The manufacturing method as described in claim 11, characterized in that, The first cavity and the second cavity are connected; the first bottom metal micro-bump and the second bottom metal micro-bump are a whole.

13. The manufacturing method as described in claim 11, characterized in that, A bonding body 101 is isolated between the first cavity and the second cavity. The second cavity is connected to the outside of the adapter body 199. A second top metal microbump is formed on the surface of the first adapter body I / O pad through the outside, and a second bottom metal microbump is formed on the surface of the main core I / O pad 911. The second top metal microbump covers the surface of the second bottom metal microbump and is electrically interconnected. An insulating medium is filled on the outside of the adapter body to form a second vertical dielectric adapter body 161.

14. The manufacturing method as described in claim 11, characterized in that, It also includes continuing to form a bond on the back side of the sub-core and the adapter sheet, and continuing to bond several layers of sub-core and adapter sheets using steps S20 to S50.

15. The manufacturing method as described in claim 11, characterized in that, The method for forming the metal microbumps is electroplating.

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