Chip vertical power supply framework and electronic equipment

Abstract

The embodiment of the invention discloses a chip vertical power supply framework and electronic equipment. The vertical power supply framework comprises a chip, a capacitor sub-module, an inductor sub-module and a voltage conversion sub-module, the capacitor sub-module, the inductor sub-module and the voltage conversion sub-module are electrically connected to form a voltage regulation module, and the chip comprises a power supply pin; the capacitor sub-module is adjacent to the chip, and the output pin of the capacitor sub-module is electrically connected with the power supply pin of the chip. Through the arrangement, the output end of the voltage regulation module is directly connected with the power supply pin of the chip to construct the power supply path, and the possibility of generating parasitic resistance and parasitic inductance on the power supply path is reasonably controlled, so that the voltage drop generated on the power supply path can be improved, and the power supply efficiency of the power supply link is improved. Besides, on the basis of reasonably controlling the loss of the power supply path, the amplitude of voltage drop on the power supply path under the chip large-current dynamic state can be effectively reduced, good power supply stability is obtained, and the power consumption of the chip is effectively reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip vertical power supply architecture and electronic device. Background Technology

[0002] In vertical power supply schemes for chips, the voltage regulator module (VRM) is typically placed on the back of the chip, and the VRM is connected to the chip via a system board. The system board contains a number of capacitors and other components, electrically connected via on-board traces and vias to form a power delivery network (PDN). With the development of chip applications, high-performance chips require larger currents and faster current responses. However, due to the large parasitic parameters of the system board's vias and traces, the capacitors cannot quickly release their capacity to the load, directly affecting power supply efficiency and chip power consumption. Summary of the Invention

[0003] This application provides a chip vertical power supply architecture and electronic device. By optimizing the chip vertical power supply architecture, the impact of link parasitics is effectively mitigated, providing technical support for improving power supply efficiency and reducing chip power consumption.

[0004] The first aspect of this application provides a vertical power supply architecture, which includes a chip, a capacitor sub-module, an inductor sub-module, and a voltage conversion sub-module. The capacitor sub-module, inductor sub-module, and voltage conversion sub-module are electrically interconnected to form a voltage regulation module. The chip includes power supply pins. The capacitor sub-module is disposed adjacent to the chip, and the output pin of the capacitor sub-module is electrically connected to the power supply pin of the chip. In this way, the output terminal of the voltage regulation module is directly connected to the power supply pin of the chip to form a power supply path. Compared with traditional optimization measures such as reducing system board trace length, increasing trace width, and reducing the number of vias, this application embodiment can eliminate the parasitic effects of the system board. This configuration, by reasonably controlling the possibility of parasitic resistance and parasitic inductance in the power supply path, can improve the voltage drop generated in the power supply path and enhance the power supply efficiency of the power link.

[0005] In addition, by reasonably controlling the power supply path loss, the voltage drop on the power supply path under high current dynamics can be effectively reduced, resulting in good power supply stability. There is no need to increase the current to compensate for the voltage drop, which effectively reduces the actual power consumption of the chip.

[0006] Furthermore, thanks to the rational control of the power supply path and chip power consumption, the overall heat dissipation effect has been effectively improved, providing technical assurance for ensuring the chip's performance and reliability.

[0007] Based on the first aspect, this application also provides a first implementation of the first aspect: the chip vertical power supply architecture further includes a circuit board and a front-end voltage divider module, the front-end voltage divider module is mounted on the circuit board and electrically connected to the voltage regulation module through the circuit board. The overall architecture is more compact and reasonable.

[0008] Based on the first implementation of the first aspect, this application also provides a second implementation of the first aspect: the capacitor sub-module, the inductor sub-module and the voltage conversion sub-module are stacked to form a voltage regulation module, and the voltage regulation module is disposed on a circuit board.

[0009] For example, a capacitor sub-module, a voltage conversion sub-module, and an inductor sub-module are stacked sequentially to form a voltage regulation module, which is connected to the circuit board via the inductor sub-module. In other examples, a capacitor sub-module, an inductor sub-module, and a voltage conversion sub-module are stacked sequentially to form a voltage regulation module, which is connected to the circuit board via the voltage conversion sub-module. Comparatively, the stacking order where the voltage conversion sub-module is connected to the circuit board results in a relatively superior power supply path.

[0010] Based on the second implementation of the first aspect, this application also provides a third implementation of the first aspect: the circuit board includes a first circuit board and a second circuit board. The signal pins of the chip are electrically connected to the second circuit board and are communicatively interconnected with the system board through the second circuit board. The voltage divider module is connected to the input terminal of the voltage regulation module through the first circuit board. That is, the first circuit board is used to supply power to the voltage regulation module, and the second circuit board is used to realize the vertical power supply architecture of the chip and the communicative interconnection with the system board. In practical applications, each board independently implements the wiring layout, further reducing the impact of possible signal noise on the basis of constructing power supply links and communication links.

[0011] Based on the third implementation of the first aspect, this application also provides a fourth implementation of the first aspect: the second circuit board is positioned close to the chip, and the second circuit board has a through hole penetrating its body. At least the capacitor sub-module of the voltage regulation module is inserted into the through hole and electrically connected to the power supply pin of the chip through the output pin on the capacitor sub-module. The overall structure is more compact and meets the design requirements of the trend of high-density layout.

[0012] In practical applications, the pre-stage voltage divider module can be set on the second circuit board, which has a first connector and a second connector, and the first circuit board has a third connector. The first connector is used for communication interconnection with the system board, and the second and third connectors are connected for power supply and communication interconnection between the first and second circuit boards.

[0013] In another practical application, the pre-stage voltage divider module can also be mounted on a first circuit board, with a first connector and a second connector mounted on a second circuit board, and a third connector mounted on the first circuit board. The first connector is used for communication interconnection with the system board, while the second and third connectors are connected for communication interconnection between the first and second circuit boards. Compared to the case where the pre-stage voltage divider module is mounted on the second circuit board, the connected second and third connectors are used for signal communication between the first and second circuit boards, without needing to also function as a power supply link. This results in a more rational and reliable power supply path.

[0014] Based on the first aspect, this application also provides a fifth implementation of the first aspect: the capacitor sub-module is located on the side of the circuit board closer to the chip, while the inductor sub-module and voltage conversion sub-module are located on the other side of the circuit board away from the chip. This arrangement allows for a further reduction in the thickness of the architecture.

[0015] In practical applications, the capacitor sub-module can be embedded in a circuit board, with the output pins exposed on the board surface near the chip for electrical connection to the chip's power supply pins.

[0016] For example, the inductor sub-module can be connected to a circuit board, that is, the inductor sub-module is positioned close to the circuit board.

[0017] Alternatively, the voltage conversion submodule can also be connected to a circuit board, i.e., the voltage conversion submodule is positioned close to the circuit board.

[0018] Based on the fifth implementation of the first aspect, this application also provides a sixth implementation of the first aspect: a first connector is provided on the circuit board for communication interconnection with the system board. Thus, on the one hand, the front-end voltage divider module can supply power to the chip side through the circuit board and the voltage regulation module; on the other hand, the chip's signal pins can also achieve communication interconnection with the system board side through the first connector on the circuit board. Overall, the length of the power supply and communication links can be further shortened.

[0019] Based on the first aspect, or the first embodiment of the first aspect, this application also provides a sixth embodiment of the first aspect: the chip is packaged on a substrate, the substrate is provided with a first connector and a second connector, and the circuit board is provided with a third connector; wherein, the first connector is used for communication interconnection with the system board, and the second connector and the third connector are connected for communication interconnection between the substrate and the second circuit board. This configuration can further optimize and shorten the length of the communication link, reduce insertion loss of high-speed signals and other signal links, and meet signal integrity requirements. Furthermore, by achieving communication interconnection with the system board through the chip's substrate, the overall architecture is more concise.

[0020] For example, the chip's core power supply pin can be directly electrically connected to the output pin of the capacitor sub-module.

[0021] In practical applications, the chip can be interconnected with the system board via a capacitor sub-module. In other practical applications, the chip is a silicon photonic chip and is interconnected with the system board via optical fiber in a light-emitting manner.

[0022] A second aspect of this application provides an electronic device, which includes a system board and a chip vertical power supply architecture, wherein the chip vertical power supply architecture is as described above.

[0023] In practical applications, this electronic device can be a server, computer, or high-performance computing cluster, such as a high-power, highly integrated, and ultra-large-scale data center server; in addition, this electronic device can also be a switch, router, or edge device, etc. Attached Figure Description

[0024] Figure 1 A schematic diagram of a vertical power supply architecture for a chip provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of a voltage regulation module provided in an embodiment of this application;

[0026] Figure 3 This is a schematic diagram of another voltage regulation module provided in an embodiment of this application;

[0027] Figure 4 A schematic diagram of yet another voltage regulation module provided in the embodiments of this application;

[0028] Figure 5 A schematic diagram of another vertical power supply architecture for a chip provided in an embodiment of this application;

[0029] Figure 6 A schematic diagram of yet another chip vertical power supply architecture provided in an embodiment of this application;

[0030] Figure 7 A schematic diagram of another vertical power supply architecture for a chip provided in an embodiment of this application;

[0031] Figure 8 This is a schematic diagram of an electronic device provided as a utility example of this application. Detailed Implementation

[0032] This application provides a chip vertical power supply architecture implementation scheme that can improve parasitic effects, and can be applied to different chip power supply application scenarios.

[0033] An integrated circuit (IC) is a miniature structure that uses specific processes to interconnect transistors, resistors, capacitors, or inductors, and other components required for a circuit, and deploys them on at least one semiconductor wafer or substrate to form a miniature structure with the desired circuit function. ICs can include processors, microprocessors, controllers, controller hubs, field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), microcontrollers, advanced programmable interrupt controllers (APICs), or other semiconductor or electronic devices. In this application, the structure formed after IC packaging is referred to as a chip.

[0034] The bottom of the chip has pins that serve as input / output terminals for the circuit. These pins can be soldered onto a printed circuit board, allowing the chip to connect to other chips or devices and transmit signals between them. The pins on the bottom of the chip can have different functions; for example, they can include signal pins for transmitting signals and power supply pins for transmitting voltage.

[0035] In vertical power supply schemes for chips, the power module is typically placed on the back of the chip. The power module and the chip are connected via a system board, and electrical connections are made through traces and vias on the board. These traces and vias on the system board contain parasitic parameters (parasitic inductance and resistance), and losses along the power supply path cause voltage drops, affecting power supply efficiency and the chip's total power consumption. As chip power consumption and current increase, the increased losses along the power supply path and the increased actual power consumption of the chip become detrimental to system heat dissipation requirements.

[0036] Based on this, this application provides a vertical power supply architecture for a chip. This architecture includes a chip, a capacitor sub-module, an inductor sub-module, and a voltage conversion sub-module. The chip includes power supply pins. The capacitor sub-module, inductor sub-module, and voltage conversion sub-module are electrically interconnected to form a voltage regulation module. The capacitor sub-module is disposed adjacent to the chip, and its output pin is electrically connected to the chip's power supply pins. In this way, the output of the voltage regulation module is directly connected to the chip's power supply pins to form a power supply path. This allows for reasonable control of the possibility of parasitic resistance and inductance generated on the power supply path, and the capacity of the capacitor sub-module can be quickly released to the chip side, effectively reducing the impact of parasitic effects. Overall, this improves the power supply efficiency of the power link and reduces the voltage drop generated on the power supply path.

[0037] In particular, when the chip-side current demand changes, especially when large currents occur dynamically, the voltage drop along the power supply path can be reduced. Furthermore, based on the reasonable control of parasitic effects along the power supply path, the embodiments of this application exhibit good power supply stability, enabling the chip to operate under a relatively stable current, further reducing chip power consumption compared to traditional vertical power supply architectures.

[0038] Furthermore, thanks to the rational control of the power supply path and chip power consumption, the overall heat dissipation effect has been effectively improved, providing technical assurance for ensuring the chip's performance and reliability.

[0039] To better understand the technical solutions and effects of this application, and without loss of generality, specific embodiments will be described in detail below with reference to the accompanying drawings. Please refer to... Figure 1 The figure is a schematic diagram of a chip vertical power supply architecture provided in an embodiment of this application.

[0040] like Figure 1 As shown, the vertical power supply architecture 100 of the chip includes a chip 10, a voltage regulation module 20, a first circuit board 30 and a second circuit board 40. The voltage regulation module 20 can convert the DC voltage into the low DC voltage required by the chip 10 side and adjust it through a feedback mechanism to meet the voltage requirements of the powered chip side under different working loads.

[0041] In this embodiment, the chip 10's core 11 is packaged on a substrate 12, and power supply and signal connections are achieved through pins formed on the bottom of the substrate 12. Specifically, the pins of the chip 10 include power supply pins and signal pins.

[0042] Please see also Figure 2 The figure is a schematic diagram of a voltage regulation module 20 provided in an embodiment of this application.

[0043] The voltage regulation module 20 includes a capacitor sub-module 21, a voltage conversion sub-module 22, and an inductor sub-module 23, which are stacked and interconnected in sequence to form the voltage regulation module 20. The capacitor sub-module 21 is disposed adjacent to the chip 10. The output terminal of the voltage regulation module 20 is located on the outer surface of the capacitor sub-module 21 away from the voltage conversion sub-module 22, and the input terminal of the voltage regulation module 20 is located on the outer surface of the inductor sub-module 23 away from the voltage conversion sub-module 22.

[0044] The capacitor sub-module 21 may include multiple output capacitors, which can be PCB (Printed Circuit Board) capacitors such as ceramic capacitors, aluminum capacitors, and silicon capacitors. The output pin 211, which serves as the output terminal of the voltage regulation module 20, can adopt different structural forms, such as, but not limited to, pin pads.

[0045] The voltage conversion sub-module 22 may include a power driver chip. In specific implementations, this power driver chip can be in different forms, such as embedded component package (ECP), die-on-PCB assembly, or packaged chip mounted on a PCB. Of course, the voltage conversion sub-module 22 may also include metal-oxide-semiconductor field-effect transistors (MOSFETs) or gallium nitride (GaN) switching devices, and may also include matched passive devices, such as, but not limited to, the input capacitor of the voltage regulation module 20, etc., which can be determined according to the overall product design requirements. This application does not limit the scope of the embodiments.

[0046] The inductor in the inductor sub-module 23 can be integrally formed using processes such as copper-iron co-firing, or it can be fabricated using processes such as magnetic film, magnetic slurry, or magnetic encapsulation. The input pins, serving as the input terminals, can also adopt different structural forms, which are not limited in this embodiment.

[0047] In practical implementation, the capacitor sub-module 21, voltage conversion sub-module 22, and inductor sub-module 23 can be formed into a three-layer stacked structure using a molding process; alternatively, they can be formed into a three-layer stacked structure using an ECP process; or, some sub-modules can be formed into a three-layer stacked structure using a molding process and others using an ECP process. Simulation tests show that the power supply density of the voltage regulation module 20 based on this stacking configuration can be increased by at least 30%.

[0048] In this embodiment, the first circuit board 30 is used to supply power to the voltage regulation module 20, and the second circuit board 40 is used to realize the communication interconnection between the chip vertical power supply architecture 100 and the system board (not shown in the figure).

[0049] The signal pins of chip 10 are electrically connected to the second circuit board 40 and are interconnected with the system board via the first connector 61 on the second circuit board 40 for transmitting high-speed serial signals (Serdes) and signals for communication with other devices such as the processor on the system board.

[0050] The second circuit board 40 has a through hole 41 that penetrates its body. At least the capacitor sub-module 21 of the voltage regulation module 20 is inserted into the through hole 41 and is electrically connected to the power supply pin of the chip 10 through the output pin 211 on the capacitor sub-module 21. The voltage regulation module 20 is electrically connected to the first circuit board 30 through the input pin on the inductor sub-module 23. In the power supply path of the powered chip 10, the output terminal of the voltage regulation module 20 is directly connected to the chip 10, which can avoid the parasitic effects generated by the system board, improve the power supply efficiency of the power link, and reduce the voltage drop generated in the power supply path.

[0051] Compared to traditional optimization measures such as reducing system board trace length, increasing trace width, and reducing via count, the chip vertical power supply architecture 100 provided in this application can eliminate the parasitic effects of the system board and reduce the overall loss of the PDN network. Simultaneously, by reasonably controlling the power supply path loss, it can effectively reduce the voltage drop on the power supply path under high current dynamics, achieving good power supply stability. Thus, there is no need to increase current to compensate for voltage drop, effectively reducing the actual power consumption of the chip and further improving heat dissipation.

[0052] Simulation tests show that the vertical power supply architecture provided in this application can improve power supply efficiency by at least 2% and reduce chip power consumption by at least 10%. It can stably switch modes, meet the functional needs of different application scenarios, and has good adaptability. For high-performance chips with increasingly higher power consumption and current, these technical advantages are even more significant.

[0053] in addition, Figure 1 The second circuit board 40 shown is positioned close to the chip 10, located between the chip 10 and the first circuit board 30 in the direction perpendicular to the board surface. In other possible implementations, the capacitor sub-module 21 on the first circuit board 30 can also be offset from the second circuit board 40 in the direction perpendicular to the board surface. In this way, the signal pins of the second circuit board 40 can be reliably electrically connected to the chip 10 without the need for through holes 41. The specific configuration can be determined according to the overall product design requirements, and this application embodiment does not limit it.

[0054] In this embodiment, the voltage divider module (VDM) 50 is mounted on the second circuit board 40. Specifically, the second connector 62 on the second circuit board 40 is connected to the third connector 63 on the first circuit board 30, so that power is supplied from the first circuit board 30 to the voltage conversion sub-module 22 of the voltage regulation module 20. That is, in the distributed power system, the voltage divider module 50, as a secondary power supply, is used to convert a higher input voltage to a lower output voltage to meet the needs of the system and the powered chip 10.

[0055] Simultaneously, signal communication between the first circuit board 30 and the second circuit board 40 can be achieved through the connected second connector 62 and third connector 63. It is understood that the second connector 62 and third connector 63 can be connected by a cable, or they can be configured as interlocking on-board connectors. This application does not limit the scope of the embodiments.

[0056] Other structural forms can also be used for the voltage regulation module 20.

[0057] Please see Figure 3 This figure is a schematic diagram of another voltage regulation module provided in an embodiment of this application. To clearly illustrate the difference between this embodiment and... Figure 2 The differences and connections between the described schemes, as well as the components and structures with the same functions, are illustrated in the diagram using the same symbols.

[0058] like Figure 3 The voltage regulation module 20 shown includes a capacitor sub-module 21 comprising multiple multi-layer ceramic capacitors (MLCCs) 212, which are encapsulated into a single unit using a molding process. For example, but not limited to, epoxy resin molding compound can be used. As shown, each ceramic capacitor 212 can be a double-sided leaded device. The lead closer to the voltage conversion sub-module 22 is interconnected with the inductor sub-module 23, while the lead further away from the voltage conversion sub-module 22 has an external protective layer 213 (PI layer). The corresponding lead pads are exposed through openings in the PI layer, and output leads 211 are formed through a redistribution layer (RDL) 214. The overall structure is more compact and rational, meeting the trend of high-density layout.

[0059] Please see Figure 4 This figure is a schematic diagram of another voltage regulation module provided in the utility model of this application. To clearly illustrate the difference between this embodiment and... Figure 2 The differences and connections between the described schemes, as well as the components and structures with the same functions, are illustrated in the diagram using the same symbols.

[0060] like Figure 4 The voltage regulation module 20 shown employs a different stacking order. Its capacitor sub-module 21, inductor sub-module 23, and voltage conversion sub-module 22 are sequentially stacked and interconnected to form the voltage regulation module 20, meaning the inductor sub-module 23 is located in the middle layer of the structure. The output terminal of the voltage regulation module 20 is located on the outer surface of the capacitor sub-module 21, away from the inductor sub-module 23, and the input terminal of the voltage regulation module 20 is located on the outer surface of the voltage conversion sub-module 22, away from the inductor sub-module 23. Similarly, it can be directly connected to the power supply pins of the chip to form a power supply path.

[0061] In comparison, Figure 2 and Figure 3 The voltage regulation module 20, arranged in the stacking order shown, has its power supply path first passing through the inductor sub-module 23, then to the voltage conversion sub-module 22, then back to the inductor sub-module 23, and finally through the voltage conversion sub-module 22 to the capacitor sub-module 21. Figure 4 The voltage regulation module 20, which is stacked in the order shown, has a power supply path that passes through the voltage conversion sub-module 22, the inductor sub-module 23 and the capacitor sub-module 21 in sequence, which is relatively optimal.

[0062] Other functional components and connection methods can be the same as those described in the previous implementation. They will not be repeated here.

[0063] In the foregoing embodiment, the pre-stage voltage divider module 50 is disposed on the second circuit board 40. In other implementations, the pre-stage voltage divider module 50 may also be disposed on the first circuit board 30. Please refer to [link to previous document]. Figure 5 This figure is a schematic diagram of another vertical power supply architecture for a chip provided in an embodiment of this application. It is used to clearly illustrate the differences between this embodiment and... Figure 1 The differences and connections between the described schemes, as well as the components and structures with the same functions, are illustrated in the diagram using the same symbols.

[0064] like Figure 5 The illustrated vertical power supply architecture 100, with its pre-stage voltage divider module 50 serving as the secondary power supply, is mounted on the first circuit board 30. Power is directly supplied from the first circuit board 30 to the voltage conversion sub-module 22 of the voltage regulation module 20. Correspondingly, the connected second connector 62a and third connector 63a are solely for signal communication between the first circuit board 30 and the second circuit board 40. In other words, the connector between the second circuit board 40 and the first circuit board 30 does not need to also function as a power supply link. Overall, the structure is simpler and more rational.

[0065] Other functional components and connection methods can be the same as those described in the previous implementation. They will not be repeated here.

[0066] In the foregoing embodiments, the chip vertical power supply architecture 100 achieves communication interconnection with the system board side through the second circuit board 40. In other specific implementations, the chip vertical power supply architecture 100 can also achieve communication interconnection with the system board side through the substrate of the chip 10. Please refer to Figure 6 This figure is a schematic diagram of another vertical power supply architecture for a chip provided in an embodiment of this application. To clearly illustrate the differences between this embodiment and... Figure 5 The differences and connections between the described schemes, as well as the components and structures with the same functions, are illustrated in the diagram using the same symbols.

[0067] like Figure 6 The chip vertical power supply architecture 100 shown is, with Figure 5 Compared to the described vertical power supply architecture for the chip, the difference in this implementation is that: the first connector 61 and the second connector 62a are disposed on the substrate 12 of the chip 10, and are interconnected with the system board side through the first connector 61 on the second circuit board 40; at the same time, the connected second connector 62a and third connector 63a are only used to realize signal communication between the first circuit board 30 and the substrate 12.

[0068] Of course, in other possible implementations, the powered chip 10 can also be in the form of a chip 11 connected to a capacitor sub-module 21 (not shown in the figure), which can further shorten the power supply link. For example, but not limited to, a communication link can be built based on the capacitor sub-module 21, with the chip 11 communicating and interconnecting with the system board through the capacitor sub-module 21; or, a communication link can be built through optical fiber based on the light output of the silicon photonics chip, which can be implemented using existing technology. The embodiments in this application are not limited.

[0069] Compared to Figure 1 and Figure 5 The described vertical power supply architecture for the chip, in this embodiment, does not include a second circuit board 40. Communication and interconnection with the system board are achieved through the substrate 12 of the chip 10. The overall architecture is simpler, thereby further reducing the length of communication links, reducing insertion loss of high-speed signals, and meeting signal integrity requirements.

[0070] In addition, the communication interconnection between the chip vertical power supply architecture 100 and the system board side in the aforementioned embodiments is respectively achieved using a second circuit board 40. Figure 1 , Figure 5 ) and the substrate 12 of chip 10 Figure 6 ) Implementation. In other specific implementations, a single circuit board can also serve as both a power supply link and a communication link; please refer to [link to relevant documentation]. Figure 7 This figure is a schematic diagram of another vertical power supply architecture for a chip provided in an embodiment of this application. To clearly illustrate the differences and connections between this embodiment and the aforementioned embodiments, the same functional components and structures are shown in the figure using the same markings.

[0071] like Figure 7 The vertical power supply architecture 100 shown has a capacitor sub-module 21 of the voltage regulation module 20 embedded in a third circuit board 70, with its output pin 211 exposed on the side of the third circuit board 70 closest to the chip 10 and electrically connected to the power supply pins of the chip 10. The voltage conversion sub-module 22 and the inductor sub-module 23 of the voltage regulation module 20 are stacked on the side of the third circuit board 70 furthest from the chip 10.

[0072] As shown in the figure, the pre-stage voltage divider module 50 is mounted on the third circuit board 70, and the voltage conversion sub-module 22 is connected to the third circuit board 70. The pre-stage voltage divider module 50 supplies power to the chip 10 through the third circuit board 70 and the voltage regulation module 20. Simultaneously, the first connector 61 is mounted on the third circuit board 70, and the signal pins of the chip 10 are interconnected with the third circuit board 70, achieving communication interconnection with the system board through the first connector 61 on the third circuit board 70.

[0073] Of course, in other possible implementations, the stacking order of the voltage conversion sub-module 22 and the inductor sub-module 23 located on the side of the third circuit board 70 away from the chip 10 can also be adjusted. That is, the inductor sub-module 23 is connected to the third circuit board 70, which can be implemented using existing technology. This application does not limit the specific implementation.

[0074] Furthermore, the capacitor sub-module 21 of the voltage regulation module 20 can also be partially embedded in the third circuit board 70, or assembled on the side of the third circuit board 70 near the chip 10. It should be understood that as long as the capacitor sub-module 21 is located on the side of the third circuit board 70 near the chip 10, its output pin 211 can also be reliably electrically connected to the power supply pin on the chip 10 side. Compared to the structure that is completely embedded in the third circuit board 70, the thickness of the architecture is slightly increased. The specific dimensions can be determined according to the overall product design requirements, and this application embodiment does not limit this.

[0075] Other functional components and connection methods can be the same as those described in the previous implementation. They will not be repeated here.

[0076] In addition to the aforementioned vertical power supply architecture for the chip, this embodiment also provides an electronic device, please refer to [link to relevant documentation]. Figure 8 This figure is a schematic diagram of an electronic device provided in an embodiment of this application.

[0077] like Figure 8 As shown, the electronic device 1000 includes a housing 300, a system board 200 disposed within the housing 300, and a chip vertical power supply architecture 100. The chip vertical power supply architecture 100 can adopt the aforementioned... Figure 1 , Figure 5 , Figure 6 and Figure 7 The described chip vertical power supply architecture 100 is electrically connected to the system board 200 via a first connector 61 for communication and interconnection with the system board 200 and other devices on it. In specific implementations, this electronic device can be a server, computer, or high-performance computing cluster, particularly for high-power, highly integrated, and ultra-large-scale data center servers; alternatively, it can also be a switch, router, or edge device, etc., and this application embodiment does not limit the scope.

[0078] It should be understood that the other main functional components of this electronic device can be implemented using existing technologies, so they will not be described in detail here.

[0079] Furthermore, the ordinal numbers “first,” “second,” and “third,” etc., used herein are only for describing the composition or structure of the same function in the technical solution. It is understood that the use of these ordinal numbers does not constitute a limitation on the understanding of the technical solution for which protection is sought in this application.

[0080] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A vertical power supply architecture for a chip, characterized in that, The vertical power supply architecture of the chip includes a chip, a capacitor sub-module, an inductor sub-module, and a voltage conversion sub-module. The capacitor sub-module, the inductor sub-module, and the voltage conversion sub-module are electrically interconnected to form a voltage regulation module. The chip includes power supply pins. The capacitor sub-module is disposed adjacent to the chip, and the output pin of the capacitor sub-module is electrically connected to the power supply pin of the chip.

2. The chip vertical power supply architecture according to claim 1, characterized in that, The chip vertical power supply architecture also includes a circuit board and a pre-stage voltage divider module. The pre-stage voltage divider module is mounted on the circuit board and is electrically connected to the voltage regulation module through the circuit board.

3. The chip vertical power supply architecture according to claim 2, characterized in that, The capacitor sub-module, the inductor sub-module, and the voltage conversion sub-module are stacked to form the voltage regulation module, which is disposed on the circuit board.

4. The chip vertical power supply architecture according to claim 3, characterized in that, The capacitor sub-module, the voltage conversion sub-module, and the inductor sub-module are stacked sequentially to form the voltage regulation module, and the inductor sub-module is connected to the circuit board; or, the capacitor sub-module, the inductor sub-module, and the voltage conversion sub-module are stacked sequentially to form the voltage regulation module, and the voltage conversion sub-module is connected to the circuit board.

5. The chip vertical power supply architecture according to claim 2 or 3, characterized in that, The circuit board includes a first circuit board and a second circuit board. The signal pins of the chip are electrically connected to the second circuit board and are interconnected with the system board through the second circuit board. The voltage divider module is connected to the input terminal of the voltage regulation module through the first circuit board.

6. The chip vertical power supply architecture according to claim 5, characterized in that, The second circuit board is positioned close to the chip. The second circuit board has a through hole that penetrates its body. At least the capacitor sub-module of the voltage regulation module is inserted into the through hole and electrically connected to the power supply pin of the chip through the output pin of the capacitor sub-module.

7. The chip vertical power supply architecture according to claim 5 or 6, characterized in that, The pre-stage voltage divider module is mounted on the second circuit board, which has a first connector and a second connector, and the first circuit board has a third connector. The first connector is used for communication interconnection with the system board, and the second connector and the third connector are connected for power supply and communication interconnection between the first circuit board and the second circuit board.

8. The chip vertical power supply architecture according to claim 5 or 6, characterized in that, The pre-stage voltage divider module is mounted on the first circuit board, the second circuit board is provided with a first connector and a second connector, and the first circuit board is provided with a third connector; wherein, the first connector is used for communication interconnection with the system board, and the second connector and the third connector are connected for communication interconnection between the first circuit board and the second circuit board.

9. The chip vertical power supply architecture according to claim 2, characterized in that, The capacitor sub-module is located on the side of the circuit board closer to the chip, while the inductor sub-module and the voltage conversion sub-module are located on the other side of the circuit board away from the chip.

10. The chip vertical power supply architecture according to claim 9, characterized in that, The capacitor sub-module is embedded in the circuit board, and the output pin is exposed on the surface of the circuit board near the chip.

11. The chip vertical power supply architecture according to claim 9 or 10, characterized in that, The inductor sub-module is connected to the circuit board; or, the voltage conversion sub-module is connected to the circuit board.

12. The chip vertical power supply architecture according to any one of claims 9 to 11, characterized in that, The circuit board is provided with a first connector, which is used for communication interconnection with the system board.

13. The chip vertical power supply architecture according to claim 2 or 3, characterized in that, The chip is packaged on a substrate, on which a first connector and a second connector are disposed, and on the circuit board a third connector is disposed; wherein, the first connector is used for communication interconnection with the system board, and the second connector and the third connector are connected for communication interconnection between the substrate and the second circuit board.

14. The chip vertical power supply architecture according to claim 2 or 3, characterized in that, The power supply pins of the chip are electrically connected to the output pins of the capacitor sub-module.

15. The chip vertical power supply architecture according to claim 14, characterized in that, The core chip is interconnected with the system board via the capacitor sub-module; or, the core chip is a silicon photonics core chip and is interconnected with the system board via optical fiber in a light-emitting manner.

16. An electronic device, characterized in that, It includes a system board and a chip vertical power supply architecture, wherein the chip vertical power supply architecture is the chip vertical power supply architecture as described in any one of claims 1 to 15.

Images