MMC sub-module capacitor voltage detection circuit and detection method

Abstract

The invention discloses an MMC sub-module capacitor voltage detection circuit and detection method, and belongs to the technical field of voltage detection. The circuit comprises an analog quantity conversion circuit, a PWM (Pulse Width Modulation) generation circuit and an optical fiber transmitter, the analog quantity conversion circuit is used for carrying out voltage division, isolation and conditioning on the high voltage and outputting a conditioning voltage signal; the PWM generating circuit generates PWM waves with corresponding duty ratios according to the signals; the optical fiber transmitter transmits the PWM wave to an external processing unit through an optical fiber; a local amplification circuit can be connected after analog quantity conversion, and the detection precision of a specific voltage interval is improved; the method realizes voltage detection through the corresponding relation between the duty ratio and the voltage, has the advantages of simple circuit structure, low cost, strong anti-interference capability and easiness in integration and maintenance, and is suitable for real-time monitoring of the capacitor voltage of the high-voltage and high-power MMC system.

Description

Technical Field

[0001] This invention belongs to the field of voltage detection technology, and relates to a capacitor voltage detection circuit and detection method for an MMC submodule. Background Technology

[0002] Modular multilevel converters (MMCs) are widely used in high-power applications such as HVDC transmission. Their stable operation depends on the accurate detection and control of the capacitor voltages of submodules. Currently, the commonly used detection scheme in industry is to use direct voltage sensors combined with fiber optic communication. Each submodule needs to be equipped with an independent voltage sensor, signal conditioning circuit, analog-to-digital converter, and photoelectric conversion module. As the system voltage level increases, the number of submodules increases significantly, leading to a sharp increase in the number of sensors and optical devices. This results in high system hardware costs, large size, complex wiring, and difficult maintenance. In addition, traditional solutions have limited anti-interference capabilities and slow response speeds during signal acquisition and transmission. Therefore, there is an urgent need for a low-cost, simple, anti-interference, and easy-to-implement MMC submodule capacitor voltage detection scheme. Summary of the Invention

[0003] The technical solution of this invention is used to solve the problem that in the traditional MMC submodule capacitor voltage detection scheme, each submodule needs to be equipped with an independent voltage sensor and supporting circuit, which leads to high system hardware cost, large size and complicated wiring.

[0004] The present invention solves the above-mentioned technical problems through the following technical solutions: This invention provides an MMC submodule capacitor voltage detection circuit, comprising: an analog-to-analog converter circuit, a PWM generator circuit, and an optical fiber transmitter. The analog-to-analog converter circuit is used to divide, isolate, and condition the input high-voltage signal into a conditioned voltage signal suitable for processing. The PWM generation circuit is connected to the analog-to-analog converter circuit, and the PWM generation circuit generates the duty cycle according to the input conditioning voltage signal. The fiber optic transmitter is used to transmit the duty cycle through an isolated fiber to an external control unit for acquisition, and to obtain the input voltage signal to be detected based on the one-to-one correspondence between the input voltage signal and the duty cycle.

[0005] Furthermore, the analog-to-digital converter circuit includes: isolation operational amplifiers U1, U2, and U3; resistors R1, R2, R3, R4, R5, R6, R7, and R8; resistors R1 and R2 are connected in series, and the non-series terminal of resistor R1 serves as the input terminal of the analog-to-digital converter circuit, connected to the input voltage signal V. DCThe non-series terminal of resistor R2 is grounded. The common point of the series connection between resistors R1 and R2 is connected to the VINP pin of isolation operational amplifier U1. The VINN, GND1, and GND2 pins of isolation operational amplifier U1 are grounded. The VDD1 and VDD2 pins of isolation operational amplifier U1 are connected to the power supply. The VOUTP pin of isolation operational amplifier U1 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the non-inverting input of operational amplifier U2. The VOUTN pin of isolation operational amplifier U1 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the inverting input of operational amplifier U2. One end of resistor R5 is connected to the non-inverting input of operational amplifier U2, and the other end of resistor R5 is grounded. One end of resistor R6 is connected to the inverting input of operational amplifier U2, and the other end of resistor R6 is connected to the output of operational amplifier U2. The output of operational amplifier U2 is connected to the non-inverting input of operational amplifier U3. One end of resistor R7 is connected to the inverting input of operational amplifier U3, and the other end of resistor R7 is grounded. One end of resistor R8 is connected to the inverting input of operational amplifier U3, and the other end of resistor R8 is connected to the output of operational amplifier U3. The output of operational amplifier U3 serves as the output of the analog-to-analog converter circuit, outputting the conditioned voltage signal V. o1 .

[0006] Further, the PWM generation circuit includes: resistors R9, R10, and R11, capacitor C1, and a 555 timer U4; resistors R9 and R10 are connected in series, the non-series end of resistor R9 is connected to the power supply, the common point of the series connection of resistors R9 and R10 is connected to the DIS pin of the 555 timer U4, the non-series end of resistor R10, the TH pin and the TRIGGER pin of the 555 timer U4 are all connected to one end of capacitor C1, the other end of capacitor C1 is grounded, the GND pin of the 555 timer U4 is grounded, one end of resistor R11 is connected to the OUTPUT pin of the 555 timer U4, the other end of resistor R11, the VDD pin and the RESET pin of the 555 timer U4 are connected to the power supply, the VCON pin of the 555 timer U4 serves as the input terminal of the PWM generation circuit and is connected to the output terminal of the analog-to-digital converter circuit, and the OUTPUT pin of the 555 timer U4 serves as the output terminal of the PWM generation circuit and is connected to the fiber optic transmitter.

[0007] Furthermore, the one-to-one correspondence between the input voltage signal and the duty cycle is as follows:

[0008]

[0009] Among them, V o1 To condition the voltage signal, V DC The input voltage signal is K1, the gain is D, the duty cycle is V. DDR1, R2, R7, R8, R9, and R10 are all resistors.

[0010] Furthermore, the MMC submodule capacitor voltage detection circuit also includes a partial amplification circuit, which includes: resistors R12, R13, R14, R15, R16, and R17; operational amplifier U5; and operational amplifier U6. One end of resistor R12 serves as the input terminal of the partial amplification circuit and is connected to the output terminal of operational amplifier U3. The other end of resistor R12 is connected to the non-inverting input terminal of operational amplifier U5. One end of resistor R13 is connected to the non-inverting input terminal of operational amplifier U5, and the other end of resistor R13 is grounded. One end of resistor R14 is connected to the inverting input terminal of operational amplifier U5, and the other end of resistor R14 is connected to the reference voltage V. ref One end of resistor R15 is connected to the inverting input of operational amplifier U5, and the other end is connected to the output of operational amplifier U5. The output of operational amplifier U5 is connected to the non-inverting input of operational amplifier U6. One end of resistor R16 is connected to the inverting input of operational amplifier U6, and the other end is grounded. One end of resistor R17 is connected to the inverting input of operational amplifier U6, and the other end is connected to the output of operational amplifier U6. The output of operational amplifier U6 serves as the output of a local amplifier circuit and is connected to the input of the next-stage PWM generation circuit, providing the PWM generation circuit with a locally amplified voltage signal V. o2 .

[0011] Preferably, the isolation operational amplifier U1 is an AMC1350DWVR.

[0012] Preferably, the 555 timer U4 is model NE555DR.

[0013] Preferably, the operational amplifiers U2, U3, U5 and U6 are all of model TLV3542IDR.

[0014] This invention also provides a method for detecting the capacitor voltage of an MMC submodule, comprising the following steps: The submodule capacitor voltage is converted into a conditioned voltage signal through voltage division and isolation conditioning; The conditioning voltage signal is input to the PWM generation circuit to generate the corresponding duty cycle; The duty cycle is transmitted to the external control unit via optical fiber; The external control unit obtains the input voltage signal to be detected based on the one-to-one correspondence between the voltage signal and the duty cycle.

[0015] Furthermore, the one-to-one correspondence between the input voltage signal and the duty cycle is as follows:

[0016]

[0017] Among them, V o1 To condition the voltage signal, V DC The input voltage signal is K1, the gain is D, the duty cycle is V. DD R1, R2, R7, R8, R9, and R10 are all resistors.

[0018] The beneficial effects of this invention are as follows: This invention achieves voltage detection through the correspondence between duty cycle and voltage. It eliminates the need for independent voltage sensors, ADCs, and complex conditioning circuits in each submodule, using general-purpose components (such as 555 timers and operational amplifiers) for voltage-duty cycle conversion, significantly reducing hardware costs. The circuit structure is simple, with fewer components, making it easy to implement and maintain, and improving system reliability. Fiber optic transmission of PWM signals achieves complete electrical isolation between high-voltage and low-voltage circuits, effectively suppressing electromagnetic interference. The PWM signal generation and transmission response are rapid, suitable for the real-time monitoring requirements of capacitor voltage in MMC systems. Furthermore, this invention can achieve high-precision detection within specific voltage ranges (such as near the rated voltage) by adding a local amplification circuit, improving system adaptability. Attached Figure Description

[0019] Figure 1 This is a structural block diagram of the MMC submodule capacitor voltage detection circuit according to Embodiment 1 of the present invention; Figure 2 This is a circuit diagram of the isolated analog-to-analog converter circuit of the MMC submodule capacitor voltage detection circuit in Embodiment 1 of the present invention. Figure 3 This is a circuit diagram of the PWM generation circuit of the MMC submodule capacitor voltage detection circuit in Embodiment 1 of the present invention. Figure 4 This is a graph showing the relationship between the output duty cycle of the PWM generation circuit of the MMC submodule capacitor voltage detection circuit in Embodiment 1 of the present invention and the conditioning voltage signal. Figure 5 This is a structural block diagram of the MMC submodule capacitor voltage detection circuit according to Embodiment 2 of the present invention; Figure 6 This is a circuit diagram of a partial amplification circuit of the MMC submodule capacitor voltage detection circuit in Embodiment 2 of the present invention; Figure 7 This is a photograph of the circuit board of the MMC submodule capacitor voltage detection circuit of Embodiment 2 of the present invention; Figure 8 The duty cycle D and the input voltage signal V of the MMC submodule capacitor voltage detection circuit in Embodiment 2 of the present invention were obtained by physical measurement of the circuit board. DC A scatter plot between them. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments: Example 1 like Figure 1 As shown, this embodiment provides an MMC submodule capacitor voltage detection circuit, including: an analog-to-analog converter circuit, a PWM generator circuit, and an optical fiber transmitter. The analog-to-analog converter circuit is used to divide, isolate, and condition the input high-voltage signal into a conditioned voltage signal suitable for processing. The PWM generator circuit is connected to the analog-to-analog converter circuit and is used to generate a duty cycle according to the input conditioned voltage signal. The optical fiber transmitter is used to transmit the duty cycle data to an external microcontroller for acquisition through an isolated optical fiber.

[0022] like Figure 2 As shown, the analog-to-digital converter circuit includes: isolation operational amplifiers U1, U2, and U3; resistors R1, R2, R3, R4, R5, R6, R7, and R8; resistors R1 and R2 are connected in series, and the non-series terminal of resistor R1 serves as the input terminal of the analog-to-digital converter circuit, connected to the input voltage signal V. DCThe non-series terminal of resistor R2 is grounded. The common point of the series connection between resistors R1 and R2 is connected to the VINP pin of isolation operational amplifier U1. The VINN, GND1, and GND2 pins of isolation operational amplifier U1 are grounded. The VDD1 and VDD2 pins of isolation operational amplifier U1 are connected to the power supply. The VOUTP pin of isolation operational amplifier U1 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the non-inverting input of operational amplifier U2. The VOUTN pin of isolation operational amplifier U1 is connected to one end of resistor R4, and the other end of resistor R4 is connected to the inverting input of operational amplifier U2. One end of resistor R5 is connected to the non-inverting input of operational amplifier U2, and the other end of resistor R5 is grounded. One end of resistor R6 is connected to the inverting input of operational amplifier U2, and the other end of resistor R6 is connected to the output of operational amplifier U2. The output of operational amplifier U2 is connected to the non-inverting input of operational amplifier U3. One end of resistor R7 is connected to the inverting input of operational amplifier U3, and the other end of resistor R7 is grounded. One end of resistor R8 is connected to the inverting input of operational amplifier U3, and the other end of resistor R8 is connected to the output of operational amplifier U3. The output of operational amplifier U3 serves as the output of the analog-to-analog converter circuit, outputting the conditioned voltage signal V. o1 .

[0023] Preferably, the isolation operational amplifier U1 is an isolation operational amplifier chip used to isolate high voltage and low voltage, thereby reducing electromagnetic interference.

[0024] like Figure 3 As shown, the PWM generation circuit includes: resistors R9, R10, and R11, capacitor C1, and a 555 timer U4. Resistors R9 and R10 are connected in series. The non-series end of resistor R9 is connected to the power supply. The common point of the series connection between resistors R9 and R10 is connected to the DIS pin of the 555 timer U4. The non-series end of resistor R10, the TH pin and the TRIGGER pin of the 555 timer U4 are all connected to one end of capacitor C1. The other end of capacitor C1 is grounded. The GND pin of the 555 timer U4 is grounded. One end of resistor R11 is connected to the OUTPUT pin of the 555 timer U4. The other end of resistor R11, the VDD pin and the RESET pin of the 555 timer U4 are connected to the power supply. The VCON pin of the 555 timer U4 serves as the input terminal of the PWM generation circuit and is connected to the output terminal of the analog-to-digital converter circuit. The OUTPUT pin of the 555 timer U4 serves as the output terminal of the PWM generation circuit and is connected to the fiber optic transmitter.

[0025] The detection principle of the MMC submodule capacitor voltage detection circuit in this embodiment is as follows: The voltage signal V DCThe input signal is amplified by the isolation operational amplifier U1 with a fixed gain K1. The amplified signal is then passed through the difference circuit composed of operational amplifier U2 to obtain a single-ended voltage signal V1. Finally, the signal is conditioned by the conditioning circuit composed of operational amplifier U3 to output the conditioned voltage signal V. o1 .

[0026] The conditioning voltage signal V o1 The calculation formula is as follows: (1) The 555 timer U4 contains two precision comparators. The toggling thresholds for these two comparators are provided by three 5K resistors within the 555 timer U4, corresponding to 1 / 3VDD and 2 / 3VDD respectively. Now, the conditioned voltage signal V... o1 When the control pin VCON of the 555 timer U4 is connected, the two toggling thresholds of the 555 timer U4 become... and When the control pin VCON is high, the capacitor... Through resistance , from Charging to Charging time The calculation formula is as follows: (2) When the control pin VCON is low, the capacitor... Through resistance from Discharge to Discharge time The calculation formula is as follows: (3) The duty cycle D of the 555 timer U4 is expressed as: (4) when Sometimes: (5) As shown in formula (5), when At that time, the duty cycle D and the conditioning voltage signal V are obtained. o1 Relationship curves as follows Figure 4 As shown.

[0027] from Figure 4 As can be seen from this, the duty cycle D is related to the conditioning voltage signal V. o1 The relationship curve is monotonic, meaning the duty cycle D and the conditioning voltage signal V are related. o1 There is a one-to-one correspondence between them; therefore, the duty cycle can be used to represent the conditioning voltage signal V. o1According to formula (1), the conditioning voltage signal V o1 And with the input voltage signal V DC The relationship between them is linear; therefore, by acquiring the duty cycle D of the 555 timer U4, the input voltage signal V to be detected can be obtained. DC .

[0028] In this embodiment, an optical fiber transmitter is connected to the OUTPUT pin of the 555 timer U4. The duty cycle D data of the 555 timer U4 is transmitted to an external microcontroller for acquisition through an isolated optical fiber. This enables real-time detection of the capacitor voltage of the MMC submodule. Compared with the traditional detection scheme based on voltage sensors and optical fiber communication, the circuit structure of this invention is simple and reliable, greatly reducing circuit complexity, improving safety, and significantly reducing costs.

[0029] Example 2 like Figure 5 As shown, the MMC submodule capacitor voltage detection circuit provided in this embodiment of the invention further includes a local amplification circuit based on Embodiment 1.

[0030] The MMC submodule capacitor voltage detection circuit in Example 1 can detect voltage across the entire range (e.g., from 0-750V), but its resolution is not high. However, in some cases, only a certain range of voltage values ​​is needed, such as when the MMC submodule capacitor voltage fluctuates within a rated value. In this case, only the fluctuation range needs to be monitored, and full-range detection is not required, thereby improving detection accuracy. In this case, a local amplification circuit can be added after the analog-to-digital converter circuit.

[0031] like Figure 6 As shown, the local amplifier circuit includes: resistors R12, R13, R14, R15, R16, and R17; operational amplifier U5; and operational amplifier U6. One end of resistor R12 serves as the input terminal of the local amplifier circuit and is connected to the output terminal of operational amplifier U3. The other end of resistor R12 is connected to the non-inverting input terminal of operational amplifier U5. One end of resistor R13 is connected to the non-inverting input terminal of operational amplifier U5, and the other end of resistor R13 is grounded. One end of resistor R14 is connected to the inverting input terminal of operational amplifier U5, and the other end of resistor R14 is connected to the reference voltage V. refOne end of resistor R15 is connected to the inverting input of operational amplifier U5, and the other end is connected to the output of operational amplifier U5. The output of operational amplifier U5 is connected to the non-inverting input of operational amplifier U6. One end of resistor R16 is connected to the inverting input of operational amplifier U6, and the other end is grounded. One end of resistor R17 is connected to the inverting input of operational amplifier U6, and the other end is connected to the output of operational amplifier U6. The output of operational amplifier U6 serves as the output of a local amplifier circuit and is connected to the input of the next-stage PWM generation circuit, providing the PWM generation circuit with a locally amplified voltage signal V. o2 .

[0032] Operational amplifier U5 in the local amplifier circuit forms a subtraction circuit, which receives the conditioning voltage signal V from the local amplifier circuit. o1 With reference voltage V ref The difference is calculated to obtain the desired local voltage signal. Operational amplifier U6 forms a linear amplifier circuit to amplify this local voltage signal, resulting in the amplified local voltage signal V. o2 Then, the locally amplified voltage signal V o2 The input is fed into the PWM generation circuit to control the PWM generation circuit to generate the duty cycle D.

[0033] Here, the voltage signal is locally amplified. Conditioning voltage signal The relationship with duty cycle D is expressed as follows: (6) (7) As shown in formula (7), when At that time, the duty cycle D and the locally amplified voltage signal V o2 The relationship curve is monotonic, meaning the duty cycle D and the locally amplified voltage signal V are related. o2 There is a one-to-one correspondence between them; therefore, the duty cycle can be used to represent the locally amplified voltage signal V. o2 According to formula (6), the locally amplified voltage signal V o2 And with the conditioning voltage signal V o1 The relationship curve is monotonic, meaning the conditioning voltage signal V... o1 With the locally amplified voltage signal V o2 There is a one-to-one correspondence between them. Furthermore, according to formula (1), the conditioning voltage signal V can be obtained. o1 With input voltage signal V DC The relationship between them is linear; therefore, by acquiring the duty cycle D of the 555 timer U4, the input voltage signal V to be detected can be obtained. DC .

[0034] Experimental verification The component selection is shown in the table below:

[0035] The parameters are given in the table below:

[0036] Resistors R3=R4=R5=R6=R9=R10=R11=R12=R13=R14=R15=R16=5KΩ, K1=0.4.

[0037] The designed circuit physical example Figure 7 As shown, the duty cycle D and the input voltage signal V were obtained after measurement. DC The actual scatter plot between them is as follows Figure 8 As shown, Figure 8 The 600V-650V and 850V-900V ranges are too flat and not applicable.

[0038] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An MMC sub-module capacitor voltage detection circuit, characterized in that, The application relates to a high-voltage signal detection system, which comprises an analog quantity conversion circuit, a PWM generation circuit and a fiber transmitter. The analog quantity conversion circuit is used for dividing, isolating and conditioning an input high-voltage signal into a conditioning voltage signal suitable for processing. The PWM generation circuit is connected with the analog quantity conversion circuit, and the PWM generation circuit generates a duty cycle according to the input conditioning voltage signal. The fiber transmitter is used for transmitting the duty cycle to an external control unit through a fiber for collection, and obtaining the input voltage signal to be detected according to the one-to-one correspondence between the input voltage signal and the duty cycle. The PWM generation circuit comprises a resistor R9, a resistor R10, a resistor R11, a capacitor C1 and a 555 timer U4; the resistor R9 is connected with the resistor R10 in series, the non-series end of the resistor R9 is connected with a power supply, the series connection point of the resistor R9 and the resistor R10 is connected with a DIS pin of the 555 timer U4, the non-series end of the resistor R10, a TH pin and a TRIGGER pin of the 555 timer U4 are all connected with one end of the capacitor C1, the other end of the capacitor C1 is grounded, a GND pin of the 555 timer U4 is grounded, one end of the resistor R11 is connected with an OUTPUT pin of the 555 timer U4, the other end of the resistor R11, a VDD pin and a RESET pin of the 555 timer U4 are connected with the power supply, a VCON pin of the 555 timer U4 is connected with an output end of the analog quantity conversion circuit as an input end of the PWM generation circuit, and an OUTPUT pin of the 555 timer U4 is connected with the fiber transmitter as an output end of the PWM generation circuit.

2. The MMC sub-module capacitor voltage detection circuit according to claim 1, characterized in that, The analog quantity conversion circuit comprises isolation operational amplifier U1, operational amplifier U2, operational amplifier U3, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R7 and resistor R8; resistor R1 and resistor R2 are connected in series, the non-series end of resistor R1 is connected with input voltage signal V DC as the input end of the analog quantity conversion circuit, the non-series end of resistor R2 is connected with ground, the common point of resistor R1 and resistor R2 in series is connected with the VINP pin of isolation operational amplifier U1, the VINN pin, GND1 pin and GND2 pin of isolation operational amplifier U1 are connected with ground, the VDD1 pin and VDD2 pin of isolation operational amplifier U1 are connected with power supply, the VOUTP pin of isolation operational amplifier U1 is connected with one end of resistor R3, the other end of resistor R3 is connected with the non-inverting input end of operational amplifier U2, the VOUTN pin of isolation operational amplifier U1 is connected with one end of resistor R4, the other end of resistor R4 is connected with the inverting input end of operational amplifier U2, one end of resistor R5 is connected with the non-inverting input end of operational amplifier U2, the other end of resistor R5 is connected with ground, one end of resistor R6 is connected with the inverting input end of operational amplifier U2, the other end of resistor R6 is connected with the output end of operational amplifier U2, the output end of operational amplifier U2 is connected with the non-inverting input end of operational amplifier U3, one end of resistor R7 is connected with the inverting input end of operational amplifier U3, the other end of resistor R7 is connected with ground, one end of resistor R8 is connected with the inverting input end of operational amplifier U3, the other end of resistor R8 is connected with the output end of operational amplifier U3, the output end of operational amplifier U3 outputs regulating voltage signal V o1 as the output end of the analog quantity conversion circuit.

3. The MMC sub-module capacitor voltage detection circuit of claim 2, wherein, The one-to-one correspondence between the input voltage signal and the duty cycle is as follows:

4. The MMC sub-module capacitor voltage detection circuit of claim 3, wherein, The model of the isolation operational amplifier U1 is AMC1350DWVR. Wherein, V o1 is a regulated voltage signal, V DC is an input voltage signal, K1 is a gain, D is a duty cycle, V DD is a power supply voltage, R1, R2, R7, R8, R9, R10 are resistors.

5. The MMC sub-module capacitor voltage detection circuit of claim 3, wherein, The MMC submodule capacitor voltage detection circuit further comprises a local amplification circuit, the local amplification circuit comprising: resistors R12, R13, R14, R15, R16, R17, operational amplifier U5, and operational amplifier U6; one end of the resistor R12 is connected with the output end of the operational amplifier U3 as the input end of the local amplification circuit, the other end of the resistor R12 is connected with the positive input end of the operational amplifier U5, one end of the resistor R13 is connected with the positive input end of the operational amplifier U5, the other end of the resistor R13 is grounded, one end of the resistor R14 is connected with the negative input end of the operational amplifier U5, the other end of the resistor R14 is connected with a reference voltage V ref , one end of the resistor R15 is connected with the negative input end of the operational amplifier U5, the other end of the resistor R15 is connected with the output end of the operational amplifier U5, the output end of the operational amplifier U5 is connected with the positive input end of the operational amplifier U6, one end of the resistor R16 is connected with the negative input end of the operational amplifier U6, the other end of the resistor R16 is grounded, one end of the resistor R17 is connected with the negative input end of the operational amplifier U6, the other end of the resistor R17 is connected with the output end of the operational amplifier U6, the output end of the operational amplifier U6 is connected with the input end of the next stage PWM generation circuit as the output end of the local amplification circuit, and a local amplification voltage signal V o2 is input to the PWM generation circuit.

6. The MMC sub-module capacitor voltage detection circuit of claim 3, wherein, The model of the 555 timer U4 is NE555DR.

7. The MMC sub-module capacitor voltage detection circuit of claim 3, wherein, The models of the operational amplifier U2, the operational amplifier U3, the operational amplifier U5 and the operational amplifier U6 are TLV3542IDR.

8. The MMC sub-module capacitor voltage detection circuit of claim 3, wherein, The application further relates to a high-voltage signal detection method, which comprises the following steps:

9. A method for detecting a voltage of a capacitor of an MMC sub-module, characterized in that, Converting a sub-module capacitor voltage into a conditioning voltage signal through voltage division and isolation conditioning; Inputting the conditioning voltage signal into a PWM generation circuit to generate a corresponding duty cycle; Transmitting the duty cycle to an external control unit through a fiber; The external control unit obtains the input voltage signal to be detected according to the one-to-one correspondence between the voltage signal and the duty cycle. The one-to-one correspondence between the input voltage signal and the duty cycle is as follows:

10. The method of claim 9, wherein, ​ Wherein, V o1 is a regulated voltage signal, V DC is an input voltage signal, K1 is a gain, D is a duty cycle, V DD is a power supply voltage, R1, R2, R7, R8, R9, R10 are resistors.

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