Low dropout linear regulator, cmos analog-to-digital converter and cis chip

Abstract

The application relates to the field of integrated circuits, in particular to a low-dropout linear voltage regulator, a CMOS analog-to-digital converter and a CIS chip. The low-dropout linear voltage regulator comprises an error amplifier, a transient feedback circuit and a basic circuit. The basic circuit comprises a power tube, a capacitor and a current source; the transient feedback circuit is composed of multiple transistors and a capacitor, wherein one PMOS tube serves as a discharge detection unit to provide a fast discharge path when the load current changes; the capacitor is connected to the output end of the error amplifier to form the main pole of the circuit, and the remaining devices are used for dynamically adjusting the gate voltage of the power tube. The application also introduces an overvoltage feedback circuit which only consumes the drain current, and then rapidly cuts off the power tube when overvoltage occurs. The application can effectively optimize the defects of long recovery time and large output voltage fluctuation of the existing LDO circuit under the load mutation working condition, so that the application can better adapt to the application requirements of the CIS circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a low dropout linear regulator, and its corresponding CMOS analog-to-digital converter and CIS chip. Background Technology

[0002] Image sensors (CIS) are divided into CMOS image sensors and CCD image sensors. Before the 21st century, CCD image sensors, with their high resolution, excellent image quality, and high stability, became the mainstream image sensors. After the 1980s, with the successful development of active pixels, CIS entered a period of rapid development. Today, CMOS image sensors are developing towards higher resolution, higher dynamic range, higher sensitivity, and higher signal-to-noise ratio, which places higher design requirements on CIS high-performance readout circuits, especially analog-to-digital converters (ADCs).

[0003] With the development of active pixel technology in CIS (CMOS Image Sensor), its exposure mode has gradually shifted from global exposure to drum shutter exposure. In this mode, CIS does not consume current at a constant rate, but follows a pulsed operating mode synchronized with line scanning: when a row of pixels is selected for readout, the current davits (DACs) in all ADCs of that row switch synchronously, generating a sharp and rapid instantaneous current spike. Once the data for that row is read out, the relevant circuitry enters standby or low-power state before the next row is selected, causing the current to drop rapidly. This periodic, high-peak-current operating characteristic poses a severe challenge to the response speed and stability of the power supply system. The poor transient performance of traditional low-dropout linear regulators (LDOs) is no longer sufficient to meet the stringent requirements of CIS for ADCs. Their slow voltage regulation is coupled into the ADC signal chain as power supply noise, causing a decrease in signal-to-noise ratio and increased harmonic distortion, ultimately manifesting as column inconsistencies in the image; and forming visible horizontal stripe noise, severely affecting image quality. Therefore, designing LDO circuits with high transient response has become crucial for improving the image quality of CIS circuit output. Summary of the Invention

[0004] To effectively improve the transient performance of existing LDO circuits and better meet the application requirements of CIS circuits, this invention provides a low dropout linear regulator, and its corresponding CMOS analog-to-digital converter and CIS chip.

[0005] The technical solution provided by this invention is as follows:

[0006] A low-dropout linear regulator includes: a basic circuit, an error amplifier, and a transient feedback circuit.

[0007] The basic circuit includes power transistor M. P Capacitor CL and current source I L M P The source is connected to the input signal V. IN The gate is connected to the gate voltage V. G The drain is connected to the output signal V. OUT C L one end and I L The input terminal is connected to V OUT C L The other end and I L The output terminal is grounded. The error amplifier is used to convert V... OUT With reference signal V REF The two are compared to calculate the error and an amplified error signal V is generated. SET .

[0008] The transient feedback circuit includes four PMOS transistors P1~P4, four NMOS transistors N1~N4, and capacitor C1. The sources of P1 and P4 are connected to V. IN The drains of P1 and N4, the source of P2, and M P The gate is connected to output V G The gates of P2 and P4 are connected to the drains of P3 and N3; the gate of N4 is connected to the drain of P2 and N1; the source of N1 is connected to the drain of N2. The sources of N2 to N4 are grounded to one end of C1; the other end of C1 is connected to the gate of P3. SET The gates of N2 and N3 are biased by voltage V. B5 The gate of N1 is connected to a bias voltage V. B6 The gate of P1 is connected to a bias voltage V. B7 The source of P3 is connected to P4 and M. P The drain is connected and serves as V. OUT The output port.

[0009] As a further improvement of this invention, the transient feedback circuit consists of six PMOS transistors P1~P4, P12, and P13, four NMOS transistors N1~N4, and a capacitor C1. The sources of P1, P4, and P13 are connected to V. IN The drains of P13 and N2 are connected to the gate of N4; the drains of N4 and P12 are connected to the source of P2. P The gates of P2 and N1 are connected to the source of N2; the gates of P2 and P4 are connected to the drains of P3 and N3. The gate of P3 is connected to one end of C1 and serves as V. SET The input port of C1; the other end of C1 is connected to the source of N1, N3, and N4 and grounded. The gate of N3 is connected to the bias voltage V. B5 The gate of N1 is connected to a bias voltage V. B6 The gate of P1 is connected to a bias voltage V. B7 The gates of P12 and P13 are connected to a bias voltage V.B8 The gate of N2 is connected to a bias voltage V. B9 .

[0010] As a further improvement of the present invention, in the transient feedback circuit, P4 serves as a discharge detection unit to provide a fast discharge path when the load current changes; C1 is connected between the error amplifier and the transient feedback circuit and constitutes the dominant pole of the circuit; the remaining components are used to dynamically adjust M. P The gate voltage, which in turn causes V OUT It is precisely and stably maintained at the preset voltage value.

[0011] As a further improvement of the present invention, the low-dropout linear regulator also includes an overvoltage feedback circuit, which is used to identify the output signal V. OUT It generates an adaptive regulating voltage based on fluctuations and outputs it to the power transistor M. P The gate.

[0012] In a typical embodiment of the present invention, the overvoltage feedback circuit consists of three PMOS transistors P5~P7, two NMOS transistors N5 and N6, and one coupling capacitor C. F Composition. The source and gate of P7 are connected to C. F One end connected to V OUT The drains of P7 and N5, the gates of N5 and N6, and C F The other end is connected; the sources of N5 and N6 are grounded. The drains of N6 and P6 are connected to the gates of P5 and P6; the sources of P5 and P6 are connected to V. IN The drain of P5 and M P The gates are connected. In this overvoltage feedback circuit, P6 and P5 form a current mirror structure, and the width-to-length ratio of P6 and P5 is 1:6.

[0013] In another embodiment of the invention, the overvoltage feedback circuit consists of five PMOS transistors P5~P7, P14, and P15, two NMOS transistors N5 and N6, and one coupling capacitor C. F Composition. The source and gate of P7 are connected to C. F One end connected to V OUT The drains of P7 and N5, the gates of N5 and N6, and C F The other end is connected; the sources of N5 and N6 are grounded; the drains of N6 and P15 are connected; the gates of P15 and P14 are connected; the source of P15 is connected to the drain of P6 and the gates of P5 and P6; the drain of P5 is connected to the source of P14; the sources of P5 and P6 are connected to V. IN The drain of P14 is connected to M. P The gate of the device; wherein P14, P15 and P5, P6 constitute a cascaded current mirror structure.

[0014] As a further improvement of the present invention, the error amplifier is composed of four PMOS transistors P8~P11 and eight NMOS transistors N7~N14. The sources of P8 and P9 are connected to V. IN The drains of P8 and N12 are connected to the source of P10; the drains of P9 and N11 are connected to the source of P11; the drains of P11 and N11 are connected and serve as V. SET The output ports are connected as follows: The drains of P11 and N8 are connected to the gates of N9 and N10; the source of N7 is connected to the drain of N9; the source of N8 is connected to the drain of N10; the sources of N9, N10, and N14 are connected together. The sources of N11 and N12 are connected to the drain of N13; the source of N13 is connected to the drain of N14. The gate of N14 is connected to the bias voltage V. B1 The gates of N7, N8, and N13 are connected to a bias voltage V. B2 The gates of P10 and P11 are connected to a bias voltage V. B3 The gates of P8 and P9 are connected to a bias voltage V. B4 The gate of N11 is connected to the reference signal V. REF The gate of N12 is connected to the output signal V. OUT .

[0015] In the error amplifier of this invention, P8~P11 and N7~N10 constitute a folded common-source cascode operational amplifier; N11 and N12 constitute a differential input pair transistor; N13 and N14 constitute a tail current source; the differential input pair transistor and the tail current source realize the input V OUT and V REF Perform continuous comparisons and difference calculations; using the configured bias voltage V B1 V B2 V B3 With V B4 This allows the operational amplifier to operate in its normal state, thereby amplifying the difference signal and using it as the error signal V. SET .

[0016] The present invention also includes a CMOS analog-to-digital converter that employs the low-dropout linear regulator as described above.

[0017] The present invention also includes a CIS chip, the readout circuit of which employs a CMOS analog-to-digital converter as described above.

[0018] The present invention has the following beneficial effects:

[0019] This invention provides a low dropout linear regulator consisting of a power transistor, an error amplifier, and a transient feedback circuit. The error amplifier is a folded common-source common-gate power amplifier with high gain, wide input common-mode range, large output voltage swing, and good stability. It works with a comparator circuit to continuously compare the output signal of the circuit with the reference signal, and works with the transient feedback circuit to achieve feedback regulation of the power transistor.

[0020] This invention optimizes the transient feedback circuit. In the new circuit structure, the discharge transistor provides a fast current discharge path for the output node when the load current changes abruptly, thereby improving the transient response from large to small load current. The newly added capacitor configures a new dominant pole for the circuit, placing the dominant pole at the output of the error amplifier to ensure system stability. The remaining components form a fast local negative feedback loop by introducing local current feedback, reducing the output impedance at the output terminal while ensuring accurate voltage tracking characteristics.

[0021] A further optimized solution of this invention introduces an overvoltage feedback circuit that consumes only leakage current, thereby enabling rapid disconnection of the power transistor in the event of overvoltage. This circuit, in conjunction with the transient feedback circuit, significantly improves the output stability of the circuit under overshoot and undershoot conditions.

[0022] Combining the above multiple improvements, the novel LDO provided by this invention can quickly adjust the output voltage and significantly suppress voltage drops or overshoot, thereby achieving better transient response characteristics and stability while maintaining a high power supply rejection ratio. Attached Figure Description

[0023] Figure 1 This is a circuit diagram of the low-dropout linear regulator provided in Embodiment 1 of the present invention.

[0024] Figure 2 This is a circuit diagram of a low-dropout linear regulator using an improved transient feedback circuit in Embodiment 1 of the present invention.

[0025] Figure 3 Showing Figure 1 The circuit structure of the error amplifier used in the low dropout linear regulator.

[0026] Figure 4 This is a circuit diagram of a low-dropout linear regulator using an overvoltage feedback circuit in Embodiment 1 of the present invention.

[0027] Figure 5 This is a circuit diagram of a low-dropout linear regulator using an improved overvoltage feedback circuit in Embodiment 1 of the present invention.

[0028] Figure 6 The simulation results of the overall loop gain and bandwidth of the low dropout linear regulator of the present invention under different loads are shown in the test experiment.

[0029] Figure 7 The simulation results of the phase margin of the low-dropout linear regulator of the present invention under different loads are shown in the test experiment.

[0030] Figure 8The figure shows the simulation results of the power supply rejection ratio of the low dropout linear regulator of the present invention under different loads in the test experiment.

[0031] Figure 9 The figure shows the simulation results of the overshoot transient response process of the low dropout linear regulator of the present invention in the test experiment.

[0032] Figure 10 The figure shows the simulation results of the undershoot transient response process of the low dropout linear regulator of the present invention in the test experiment.

[0033] Figure 11 The simulation results of the linear regulation and load regulation of the low-dropout linear regulator of this invention are shown in the test experiment. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] Example 1

[0037] This embodiment provides a low-dropout linear regulator, such as... Figure 1 As shown, it includes a basic circuit, an error amplifier, and a transient feedback circuit. The basic circuit includes a power transistor M. P Capacitor C L and current source I L M P The source is connected to the input signal V. IN The gate is connected to the gate voltage V. G The drain is connected to the output signal V. OUT C L one end and I L The input terminal is connected to V OUT C L The other end and I L The output terminal is grounded. The error amplifier is used to convert V... OUT With reference signal V REF The two are compared to calculate the error, and an amplified error signal V is generated.SET The transient feedback circuit is used to establish a feedback loop between the power transistor and the error amplifier, thereby enabling a rapid response to the error between the real-time detected output signal and the reference signal, and generating an adaptive gate voltage V. G And output to power transistor M P The gate, to M P The operating state is adjusted to adjust the output voltage V. OUT Maintain stability.

[0038] To achieve nanosecond-level transient response, the transient feedback circuit of the low-dropout linear regulator provided in this embodiment consists of four PMOS transistors P1~P4, four NMOS transistors N1~N4, and one capacitor C1. Specifically, the sources of P1 and P4 are connected to V... IN The drains of P1 and N4, the source of P2, and M P The gate is connected to output V G The gates of P2 and P4 are connected to the drains of P3 and N3; the gate of N4 is connected to the drain of P2 and N1; the source of N1 is connected to the drain of N2. The sources of N2 to N4 are grounded to one end of C1; the other end of C1 is connected to the gate of P3. SET The gates of N2 and N3 are biased by voltage V. B5 The gate of N1 is connected to a bias voltage V. B6 The gate of P1 is connected to a bias voltage V. B7 The source of P3 is connected to P4 and M. P The drain is connected and serves as V. OUT The output port.

[0039] In the transient feedback circuit of this embodiment, P4 is a discharge detection unit to provide a fast discharge path when the load current changes, thereby improving the transient response when the load current decreases. C1 is connected between the error amplifier and the transient feedback circuit and forms the dominant pole of the circuit; the remaining components form a feedback loop and are used to dynamically adjust M. P The gate voltage, which in turn causes V OUT The voltage remains precisely and stably at the preset value. Specifically, large-signal analysis of the discharge detection unit reveals that when the load current decreases, the output signal V... OUT As the voltage increases, the source voltage of P3 increases, and consequently, the drain voltage of P3 increases. When the drain voltage of P3 increases, the gate voltage of P4 increases, which in turn decreases the drain voltage of P4, ultimately affecting the output voltage V. OUT It gets smaller.

[0040] The transient feedback circuit realizes the error signal V detected and generated by the error amplifier. SET The gate voltage of the power transistor, i.e., V G To regulate and thus make V OUTThe circuit accurately stabilizes at the preset voltage value; during this process, the circuit's output impedance... R It can be represented as follows:

[0041] ;

[0042] In the above formula, , These represent the transconductance of P10 and N7, respectively; , , , , These represent the equivalent resistances of P10, P8, N12, N7, and N9, respectively.

[0043] Due to the relatively high output impedance, to ensure stability, the transient feedback circuit in this embodiment adds a capacitor C1 at the output of the error amplifier to form the dominant pole of the entire system; while the original basic circuit's C... L and I L This forms the secondary pole. The novel transient feedback circuit pushes the pole at the power transistor's gate outside the unity-gain bandwidth, improving the error amplifier's driving capability of the power transistor's gate. To achieve the design goal of high transient response, this embodiment requires that the circuit's major and secondary poles be at the highest possible frequency to achieve a larger bandwidth, thereby meeting the requirements of rapid response to load changes and improving charging and discharging capabilities. The transient feedback circuit provided in this embodiment introduces local current feedback to form a fast local negative feedback loop, reducing the output impedance at the output terminal while ensuring accurate voltage tracking characteristics.

[0044] Based on the same design concept, in the further optimized solution of this embodiment, the transient feedback circuit in the provided low-dropout linear regulator can also adopt, as shown in... Figure 2 The improved circuit structure is shown. Specifically, the transient feedback circuit consists of six PMOS transistors P1~P4, P12, and P13, four NMOS transistors N1~N4, and capacitor C1. The sources of P1, P4, and P13 are connected to V. IN The drains of P13 and N2 are connected to the gate of N4; the drains of N4 and P12 are connected to the source of P2. P The gates of P2 and N1 are connected to the source of N2; the gates of P2 and P4 are connected to the drains of P3 and N3. The gate of P3 is connected to one end of C1 and serves as V. SET The input port of C1; the other end of C1 is connected to the source of N1, N3, and N4 and grounded. The gate of N3 is connected to the bias voltage V. B5 The gate of N1 is connected to a bias voltage V. B6 The gate of P1 is connected to a bias voltage V. B7 The gates of P12 and P13 are connected to a bias voltage V. B8The gate of N2 is connected to a bias voltage V. B9 .

[0045] and Figure 1 Compared to the circuit, Figure 2 The transient feedback circuit in the scheme can achieve higher frequency subpole positions, lower power transistor gate and output node output impedance; after the pole is moved to a higher frequency, the bandwidth can be increased and the transient response capability of the circuit can be improved.

[0046] Among them, Figure 1 or Figure 2 In the circuit scheme shown, the error amplifier can be composed of four PMOS transistors P8~P11 and eight NMOS transistors N7~N14. For example... Figure 3 As shown, the sources of P8 and P9 are connected to V. IN The drains of P8 and N12 are connected to the source of P10; the drains of P9 and N11 are connected to the source of P11; the drains of P11 and N11 are connected and serve as V. SET The output ports are connected as follows: The drains of P11 and N8 are connected to the gates of N9 and N10; the source of N7 is connected to the drain of N9; the source of N8 is connected to the drain of N10; the sources of N9, N10, and N14 are connected together. The sources of N11 and N12 are connected to the drain of N13; the source of N13 is connected to the drain of N14. The gate of N14 is connected to the bias voltage V. B1 The gates of N7, N8, and N13 are connected to a bias voltage V. B2 The gates of P10 and P11 are connected to a bias voltage V. B3 The gates of P8 and P9 are connected to a bias voltage V. B4 The gate of N11 is connected to the reference signal V. REF The gate of N12 is connected to the output signal V. OUT .

[0047] In the error amplifier provided in this embodiment, P8~P11 and N7~N10 constitute a folded cascode operational amplifier; N11 and N12 constitute a differential input pair; N13 and N14 constitute a tail current source; the differential input pair and the tail current source realize the input V OUT and V REF Perform continuous comparisons and difference calculations; using the configured bias voltage V B1 V B2 V B3 With V B4 This allows the operational amplifier to operate in its normal state, thereby amplifying the difference signal and using it as the error signal V. SETThe error amplifier circuit structure used in this embodiment gives the amplifier advantages such as high gain, wide input common-mode range, large output voltage swing, and good stability. Of course, in other embodiments, the operational amplifier in the error amplifier can also adopt other circuit schemes with similar or better performance.

[0048] exist Figure 1 Based on the plan, such as Figure 4 As shown, the low-dropout linear regulator provided in this embodiment may further include an overvoltage feedback circuit, which is used to identify the output signal V. OUT It generates an adaptive regulating voltage based on fluctuations and outputs it to the power transistor M. P The gate of the circuit. Specifically, the overvoltage feedback circuit in this embodiment consists of three PMOS transistors P5~P7, two NMOS transistors N5 and N6, and one coupling capacitor C. F Composition. The source and gate of P7 are connected to C. F One end connected to V OUT The drains of P7 and N5, the gates of N5 and N6, and C F The other end is connected; the sources of N5 and N6 are grounded. The drains of N6 and P6 are connected to the gates of P5 and P6; the sources of P5 and P6 are connected to V. IN The drain of P5 and M P The gates are connected. In this overvoltage feedback circuit, P6 and P5 form a current mirror structure, and the width-to-length ratio of P6 and P5 is 1:6.

[0049] Analyzing the circuit principle of the overvoltage feedback circuit provided in this embodiment reveals that: since the gate and source of P7 are connected, when V OUT When there is no overcharge voltage, the MOSFET is in the off state and does not generate additional quiescent current. When V OUT When an overcharge voltage is generated, due to the large aspect ratio of P7, the leakage current of P7 sets the bias voltage of N6 through N5, keeping it near the threshold region. The overcharge voltage is then released through capacitor C. F The voltage is coupled to the gate of N5. When the gate of N5 detects a voltage fluctuation, N5 generates a large dynamic current. This dynamic current is then amplified again by a current mirror composed of P5 and P6 and transmitted to the power transistor M. P At the gate, for V G It performs charging to suppress overcharge voltage in order to achieve a fast response.

[0050] In practical applications, Figure 4 The overvoltage feedback circuit in the middle can be applied to Figure 1 The circuit shown can also be applied to Figure 2 The circuit shown. Figure 4Based on the previous solution, this embodiment further provides an improved overvoltage feedback circuit for application in [the following context is missing from the original text]. Figure 2 Taking the circuit shown as an example, the improved overvoltage feedback circuit consists of five PMOS transistors P5~P7, P14, and P15, two NMOS transistors N5 and N6, and one coupling capacitor C. F Composition. The source and gate of P7 are connected to C. F One end connected to V OUT The drains of P7 and N5, the gates of N5 and N6, and C F The other end is connected; the sources of N5 and N6 are grounded; the drains of N6 and P15 are connected; the gates of P15 and P14 are connected; the source of P15 is connected to the drain of P6 and the gates of P5 and P6; the drain of P5 is connected to the source of P14; the sources of P5 and P6 are connected to V. IN The drain of P14 is connected to M. P The gate.

[0051] and Figure 4 compared to, Figure 5 In the circuit design, P14, P15 and P5, P6 form a cascaded current mirror structure. Replacing the conventional current mirror structure with a cascaded structure can enhance the circuit's robustness and anti-interference capability, improve the accuracy and stability of the current mirror, ensure a more accurate overvoltage trigger point, and avoid malfunctions.

[0052] To further enhance the performance advantages of the low-dropout linear regulator provided in this embodiment, this embodiment uses... Figure 5 Taking a circuit as an example, the circuit principle of the present invention will be analyzed:

[0053] First, in the transient feedback circuit, transistor P4 provides a fast current discharge path for the output node when the load current changes abruptly. This is a response mechanism under large-signal operating mode. Since this path is only activated during large-signal transients, it does not significantly affect the small-signal characteristics of the system (such as zero-pole distribution and stability). Therefore, the circuit behavior introduced by P4 can be ignored when modeling and analyzing the small-signal equivalent circuit.

[0054] Next, for P3 and M P Small-signal model analysis was performed on N3, P1, P12, and P2. Starting from power transistor M... P gate V G Disconnect the loop, set the drain of P3 to point E, and output signal V. OUT The current and voltage are denoted as follows: I x and V x Because of M P Since P3 and N3 are in the same branch, the currents in the three are equal and satisfy the following equation:

[0055] = = ;

[0056] Among them, M P Current of P3 and N3 , and They are as follows:

[0057] ;

[0058] In the above formula, Indicates power transistor M P The equivalent impedance; and These represent the transconductance and equivalent impedance of P3, respectively. Indicates the transconductance of P4; This represents the equivalent impedance of N3; V e This represents the voltage at point E.

[0059] Combining these three factors yields the open-loop output impedance. R X for:

[0060] ;

[0061] Neglecting parasitic resistance, we get:

[0062] ;

[0063] Then the loop gain of this part T for:

[0064] ;

[0065] In the above formula, , , Let P2, P12 and M represent respectively. P transconductance; , , , These represent the equivalent resistances of P1, P12, P2, and N3, respectively.

[0066] Then the closed-loop output impedance R out for:

[0067] ;

[0068] Therefore, it can be seen that compared with traditional circuit schemes, the transient feedback circuit structure of this embodiment effectively reduces the equivalent impedance of the output node, which is at least [a certain percentage] lower than that of traditional circuits. At least times, while simultaneously enhancing the open-loop gain of the local feedback loop by at least This increases the overall loop gain-bandwidth product by a factor of two. This design shifts the secondary pole of the output node towards higher frequencies, thereby expanding the effective bandwidth of the circuit. When the output current changes abruptly, this structure can quickly adjust the output voltage, significantly suppressing voltage drops or overshoot, thus achieving superior transient response characteristics and stability while maintaining a high power supply rejection ratio.

[0069] Finally, a small-signal model analysis is performed on P1, P2, P12, P13, N1, and N2 in the transient feedback circuit. The source of N2 is denoted as node B, and the gate of N4 as node A. Using Kirchhoff's current law to analyze the two nodes, we obtain:

[0070] ;

[0071] In the above formula, V A , V B These represent the voltages at nodes A and B, respectively. , , , These represent the transconductances of N2, P2, P12, and N4, respectively. , , , , , These represent the equivalent resistances of P1, N2, P13, P2, N1, and P12, respectively. This indicates the output current at the gate of the management transistor.

[0072] Combining the above formulas, we can obtain the power transistor M. p Gate output impedance for:

[0073] ;

[0074] Analysis of the above formula shows that, compared to traditional solutions, the transient feedback circuit provided by this invention can reduce the impedance of the power transistor gate by at least This doubles the gain bandwidth, ensuring the power transistor's gate poles are far outside the gain bandwidth, thus providing a more powerful driving capability.

[0075] Further analysis of the circuit's power supply rejection ratio using the following formula PSRR :

[0076] ;

[0077] in, LG The loop gain is expressed as follows:

[0078] ;

[0079] In the above formula, A ea This indicates the gain of the error amplifier. A TFC This indicates the gain of the transient feedback circuit. g mp Indicates the transconductance of the power transistor. r op Indicates the output impedance of the power transistor. β This represents the feedback coefficient.

[0080] Analysis shows that if a feedback network is added, then β <1. However, when unit feedback is used, i.e. β =1 maximizes the loop gain, thereby improving the circuit's performance. PSRR Therefore, the low-dropout linear regulator in this embodiment adopts a direct feedback form, eliminating the resistive feedback network and directly connecting the system output to the input of the error amplifier, thereby improving the system's power supply rejection ratio.

[0081] In summary, the novel low-dropout linear regulator provided in this embodiment can achieve excellent power supply rejection ratio (PSRR) without the need for additional external components by reducing the feedback network and allowing the output to be directly fed back to the error amplifier. Furthermore, this embodiment utilizes a transient feedback circuit to construct a multi-loop control system between the error amplifier and the power transistor. The novel transient feedback circuit forms a high-speed local loop and, combined with the discharge transistor P4, enables rapid discharge under large-signal conditions. The error amplifier is responsible for slow loop regulation, ultimately achieving a high transient response speed of 413.6MHz unity-gain bandwidth, effectively improving the system's conduction performance. In addition, this embodiment introduces an overvoltage feedback circuit that consumes only leakage current, thereby rapidly cutting off the power transistor in the event of overvoltage. In a further optimized scheme, the overvoltage feedback circuit can also adopt a cascaded current mirror structure to overcome the problems of low current replication accuracy and weak anti-interference capability of traditional overvoltage detection modules, giving the circuit strong robustness and response consistency, making it suitable for CIS chips that are highly susceptible to environmental influences. Based on the above improvements, this embodiment can significantly reduce the recovery time of the LDO circuit under load change conditions and improve the output voltage overshoot problem.

[0082] Example 2

[0083] Based on the scheme in Embodiment 1, this embodiment further provides a CMOS analog-to-digital converter that employs the low-dropout linear regulator as described in Embodiment 1. Furthermore, this embodiment also provides a CIS chip whose readout circuit uses the analog-to-digital converter as described above.

[0084] To verify the performance of the low dropout linear regulator (LDO) provided by this invention, technicians simulated and tested the relevant circuit scheme on a 65nm CMOS process.

[0085] 1. Stability test:

[0086] This experiment first adjusts the output load of the circuit to heavy and light load states, and then tests the amplitude-frequency response curve and phase-frequency response curve of the circuit under the corresponding operating states. The two are shown below. Figure 6 and Figure 7 As shown.

[0087] analyze Figure 6 The data reveals that the circuit operates under different load currents I. Load At this speed, the maximum unity-gain bandwidth is 413.6MHz, and the maximum gain is 69.26dB; the minimum unity-gain bandwidth is 207.9MHz, and the minimum gain is 48.93dB.

[0088] analyze Figure 7 The data reveals that the circuit operates under heavy load (I LOAD The phase margin is largest at 20mA, at 73.92°, and is also largest at light load (I = 20mA). LOAD The phase margin is the smallest at 32.5° (e.g., 1mA). This indicates that the entire loop can remain stable within a load current range of 1mA to 20mA and has a high bandwidth.

[0089] 2. Power Supply Rejection Ratio Test

[0090] This experiment further tested the power supply rejection ratio of the LDO circuit under different loads, and the results are as follows: Figure 8 As shown in the figure. Analysis of the data in the figure reveals that when a 600mV AC voltage is applied to VDD, under heavy load (I... LOAD =20mA), the minimum power supply rejection ratio is -57.4dB; when the circuit is under light load (I LOAD =5mA), with the maximum power supply rejection being -65.8dB.

[0091] 3. Transient response jump test

[0092] This experiment tested the transient response of the LDO circuit and observed V. OUTThe transient response characteristics of the circuit were analyzed by measuring the pulse changes and using pulse amplitude and pulse recovery time as metrics, resulting in the following... Figure 9 and Figure 10 The output curve is shown.

[0093] analyze Figure 9 The data shows that when the load current jumps from 20mA to 1mA within 10ns, the output VOUT generates a charging voltage of 21.81mV, and the recovery time is 30.4ns; while according to Figure 10 It can be observed that when the load current jumps from 1mA to 20mA within 8ns, the output terminal VOUT generates an undershoot voltage of 23.16mV, and the recovery time is 32.93ns. Therefore, based on the above data, it can be seen that the LDO circuit of the present invention has a lower peak voltage and a shorter recovery time.

[0094] 4. Adjustment Rate Test

[0095] This experiment tests the regulation of the LDO circuit to verify the system's stability. Regulation includes line regulation and load regulation; a smaller line regulation indicates higher circuit accuracy and stronger stability; a smaller load regulation also indicates stronger circuit stability. The experimental results are as follows: Figure 11 As shown.

[0096] in, Figure 11 The upper part represents the linear regulation. When the power supply VDD changes from 1.72V to 2.45V, and the load current remains constant at 20mA, the LDO circuit can generally maintain a stable output of around 1.6V. The output change (ΔV) is minimal. out The voltage rating is 533.68µV, and the linear regulation is 0.731mV / V, which is a relatively excellent level.

[0097] Figure 11 The lower half represents the load regulation. When the load changes linearly from light load (1mA) to heavy load (20mA), the LDO output changes by 242.89µV, and the load regulation is 0.0127mV / mA, which is also a relatively excellent level.

[0098] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A low-dropout linear regulator, characterized in that, It includes: The basic circuit includes the power transistor M. P Capacitor C L and current source I L M P The source is connected to the input signal V. IN The gate is connected to the gate voltage V. G The drain is connected to the output signal V. OUT C L one end and I L The input terminal is connected to V OUT C L The other end and I L The output terminal is grounded; Error amplifier, its calculation V OUT With reference signal V REF The error is calculated and an error signal V is generated. SET ; The transient feedback circuit includes four PMOS transistors P1~P4, four NMOS transistors N1~N4, and a capacitor C1; the sources of P1 and P4 are connected to V. IN The drains of P1 and N4, the source of P2, and M P The gate is connected to output V G The gates of P2 and P4 are connected to the drains of P3 and N3; the gate of N4 is connected to the drain of P2 and N1; the source of N1 is connected to the drain of N2; the sources of N2 to N4 are grounded at one end of C1; the other end of C1 is connected to the gate of P3. SET The gates of N2 and N3 are connected to a bias voltage V. B5 The gate of N1 is connected to a bias voltage V. B6 The gate of P1 is connected to a bias voltage V. B7 The source of P3 is connected to P4 and M. P The drain is connected and serves as V. OUT The output port; Alternatively, the transient feedback circuit consists of six PMOS transistors P1~P4, P12, and P13, four NMOS transistors N1~N4, and a capacitor C1; the sources of P1, P4, and P13 are connected to V. IN The drains of P13 and N2 are connected to the gate of N4; the drains of N4 and P12 are connected to the source of P2. P The gate of P2 and N1 is connected to the source of N2; the gates of P2 and P4 are connected to the drains of P3 and N3; the gate of P3 is connected to one end of C1 and serves as V. SET The input port of C1; the other end of C1 is connected to the source of N1, N3, and N4 and grounded; the gate of N3 is connected to the bias voltage V. B5 The gate of N1 is connected to a bias voltage V. B6 The gate of P1 is connected to a bias voltage V. B7 The gates of P12 and P13 are connected to a bias voltage V. B8 The gate of N2 is connected to a bias voltage V. B9 ; In the transient feedback circuit, P4 serves as a discharge detection unit to provide a fast discharge path when the load current changes; C1 is connected between the error amplifier and the transient feedback circuit and forms the dominant pole of the circuit; the remaining components are used to dynamically adjust M. P The gate voltage, which in turn causes V OUT It is precisely and stably maintained at the preset voltage value.

2. The low-dropout linear regulator as described in claim 1, characterized in that: It also includes an overvoltage feedback circuit, which is used to identify the output signal V. OUT It generates an adaptive regulating voltage based on fluctuations and outputs it to the power transistor M. P The gate; The overvoltage feedback circuit consists of three PMOS transistors P5~P7, two NMOS transistors N5 and N6, and one coupling capacitor C. F Composition; the source and gate of P7 are connected to C F One end connected to V OUT The drains of P7 and N5, the gates of N5 and N6, and C F The other end is connected; the sources of N5 and N6 are grounded; the drains of N6 and P6 are connected to the gates of P5 and P6; the sources of P5 and P6 are connected to V. IN The drain of P5 and M P The gate is connected.

3. The low-dropout linear regulator as described in claim 2, characterized in that: In the overvoltage feedback circuit, P6 and P5 form a current mirror structure, and the width-to-length ratio of P6 and P5 is 1:

6.

4. The low-dropout linear regulator as described in claim 1, characterized in that: It also includes an overvoltage feedback circuit, which is used to identify the output signal V. OUT It generates an adaptive regulating voltage based on fluctuations and outputs it to the power transistor M. P The gate; The overvoltage feedback circuit consists of five PMOS transistors (P5-P7, P14, P15), two NMOS transistors (N5, N6), and one coupling capacitor C. F Composition; the source and gate of P7 are connected to C F One end connected to V OUT The drains of P7 and N5, the gates of N5 and N6, and C F The other end is connected; the sources of N5 and N6 are grounded; the drains of N6 and P15 are connected; the gates of P15 and P14 are connected; the source of P15 is connected to the drain of P6 and the gates of P5 and P6; the drain of P5 is connected to the source of P14; the sources of P5 and P6 are connected to V. IN The drain of P14 is connected to M. P The gate of the gate; P14, P15 and P5, P6 form a cascaded current mirror structure.

5. The low-dropout linear regulator as described in claim 1, characterized in that: The error amplifier consists of four PMOS transistors P8~P11 and eight NMOS transistors N7~N14; the sources of P8 and P9 are connected to V. IN The drains of P8 and N12 are connected to the source of P10; the drains of P9 and N11 are connected to the source of P11; the drains of P11 and N11 are connected and serve as V. SET The output ports of N11 and N8 are connected; the drains of N11 and N8 are connected to the gates of N9 and N10; the source of N7 is connected to the drain of N9; the source of N8 is connected to the drain of N10; the sources of N9, N10, and N14 are connected; the sources of N11 and N12 are connected to the drain of N13; the source of N13 is connected to the drain of N14; the gate of N14 is connected to the bias voltage V. B1 The gates of N7, N8, and N13 are connected to a bias voltage V. B2 The gates of P10 and P11 are connected to a bias voltage V. B3 The gates of P8 and P9 are connected to a bias voltage V. B4 The gate of N11 is connected to the reference signal V. REF The gate of N12 is connected to the output signal V. OUT .

6. The low-dropout linear regulator as described in claim 5, characterized in that: In the error amplifier, P8~P11 and N7~N10 constitute a folded cascode operational amplifier; N11 and N12 constitute a differential input pair; N13 and N14 constitute a tail current source; the differential input pair and the tail current source realize the input V OUT and V REF Perform continuous comparisons and difference calculations; using the configured bias voltage V B1 V B2 V B3 With V B4 This allows the operational amplifier to operate in its normal state, thereby amplifying the difference signal and using it as the error signal V. SET .

7. A CMOS analog-to-digital converter, characterized in that: It employs a low-dropout linear regulator as described in any one of claims 1-6.

8. A CIS chip, characterized in that, Its readout circuit uses the CMOS analog-to-digital converter as described in claim 7.

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