Information detection method and electronic device

Abstract

The application discloses an information detection method and an electronic device, relates to the technical field of servers, and comprises the following steps: a processor synchronizes an initialization instruction to a baseboard management controller, and then responds to a request of the baseboard management controller to obtain and returns first storage information in an initialization stage, and a cooperative monitoring logic of the processor and the baseboard management controller is constructed. According to the information detection method, the baseboard management controller can detect storage information of a detector in the initialization stage of the memory, so that the baseboard management controller can actively obtain the running state of the initialization stage of the memory, and key data support is provided for subsequent stable operation of the memory and full-stage coverage of a whole memory monitoring system of the server.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to an information detection method and electronic device. Background Technology

[0002] Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5) is a fifth-generation standard for synchronous dynamic random-access memory developed by the world's leading standards organization in the microelectronics industry. In some scenarios, the board management controller needs to monitor information such as the temperature and power management integrated circuit (PMIC) of the DDR5.

[0003] In related technologies, a server includes a processor, a baseboard management controller (BMD), and a DDR5 memory chip. The processor and BMD cannot directly communicate with the DDR5. The DDR5 is equipped with a temperature sensor and a power management module. The temperature sensor detects the DDR5's temperature, and the power management module detects its power parameters. If the temperature sensor determines that the DDR5's temperature is greater than or equal to a temperature threshold, and / or the power management module determines that the DDR5 has a power failure, it triggers an in-band interrupt to indicate that the DDR5 is overheating and / or has a power failure. The processor then sends an indication to the BMD indicating the overheating and / or power failure of the DDR5.

[0004] However, the above method mainly detects DDR5 fault information during normal DDR5 operation and cannot detect DDR5 information during the initialization phase. Summary of the Invention

[0005] This application provides an information detection method and electronic device to detect DDR5 information during the initialization phase.

[0006] This application provides an information detection method applied to a processor, comprising:

[0007] An initialization command is sent to the baseboard management controller via the first link; the initialization command is used to instruct the memory to enter the initialization phase, and the first link is the communication link between the processor and the baseboard management controller for transmitting the initialization command;

[0008] The processor receives a first acquisition request sent by the baseboard management controller via a second link. The first acquisition request is used to request the processor to acquire the memory's stored information at the current moment. The second link is a communication link between the processor and the baseboard management controller for transmitting the first acquisition request and the stored information.

[0009] Obtain the first stored information from the memory; the first stored information is the information stored in the memory during the initialization phase.

[0010] The first storage information is sent to the baseboard management controller via the second link.

[0011] This application provides an information detection method applied to a baseboard management controller, comprising:

[0012] The processor sends an initialization command via the first link. The initialization command is used to instruct the memory to enter the initialization phase. The first link is a communication link between the processor and the baseboard management controller for transmitting the initialization command.

[0013] A first acquisition request is sent to the processor via a second link. The first acquisition request is used to request the processor to acquire the memory's stored information at the current moment. The second link is a communication link between the processor and the baseboard management controller for transmitting the first acquisition request and the stored information.

[0014] The first storage information is the storage information of the memory during the initialization phase, which is received by the processor through the second link.

[0015] This application provides an information detection method applied to a data forwarding module, including:

[0016] The fifth acquisition request is received from the baseboard management controller via the fifth link. The fifth acquisition request is used to request the data forwarding module to acquire the storage information of the memory at the current moment. The fifth link is the communication link between the baseboard management controller and the data forwarding module.

[0017] Obtain the second stored information from the memory, which is the stored information of the memory during the running phase;

[0018] The second storage information is sent to the baseboard management controller via the fifth link.

[0019] This application also provides an information detection device, including:

[0020] The first transmitting module is used to send an initialization command to the baseboard management controller via a first link; the initialization command is used to instruct the memory to enter the initialization phase, and the first link is a communication link between the processor and the baseboard management controller for transmitting the initialization command;

[0021] The first receiving module is used to receive a first acquisition request sent by the baseboard management controller via a second link. The first acquisition request is used to request the processor to acquire the memory's stored information at the current moment. The second link is a communication link between the processor and the baseboard management controller for transmitting the first acquisition request and the stored information.

[0022] The first acquisition module is used to acquire the first stored information of the memory; the first stored information is the stored information of the memory during the initialization phase.

[0023] The second sending module is used to send the first stored information to the baseboard management controller via the second link.

[0024] This application also provides an information detection device, including:

[0025] The second receiving module is used to receive an initialization command sent by the processor through the first link. The initialization command is used to instruct the memory to enter the initialization stage. The first link is a communication link between the processor and the baseboard management controller for transmitting the initialization command.

[0026] The third sending module is used to send a first acquisition request to the processor via the second link. The first acquisition request is used to request the processor to acquire the memory's stored information at the current moment. The second link is a communication link between the processor and the baseboard management controller for transmitting the first acquisition request and the stored information.

[0027] The third receiving module is used to receive the first storage information sent by the processor through the second link. The first storage information is the storage information of the memory during the initialization phase.

[0028] This application also provides an information detection device, including:

[0029] The fourth receiving module is used to receive the fifth acquisition request sent by the baseboard management controller through the fifth link. The fifth acquisition request is used to request the data forwarding module to acquire the storage information of the memory at the current moment. The fifth link is the communication link between the baseboard management controller and the data forwarding module.

[0030] The second acquisition module is used to acquire the second storage information of the memory, which is the storage information of the memory during the running phase.

[0031] The fourth transmission module is used to send the second stored information to the baseboard management controller via the fifth link.

[0032] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the above-described information detection method.

[0033] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described information detection method.

[0034] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described information detection method.

[0035] This application establishes a collaborative monitoring logic between the processor and the baseboard management controller by first sending a synchronous initialization instruction to the baseboard management controller, then responding to its acquisition request and returning the first storage information of the initialization phase. The information detection method provided in this application allows the baseboard management controller to detect the storage information of the detector during the memory initialization phase, enabling the baseboard management controller to proactively acquire the operating status of the memory during the initialization phase (such as temperature, PMIC power supply data, etc.), providing crucial data support for the subsequent stable operation of the memory and full-stage coverage of the overall server memory monitoring system. Attached Figure Description

[0036] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram illustrating an application scenario provided in the embodiments of this application;

[0038] Figure 2 A flowchart illustrating an information detection method provided in an embodiment of this application;

[0039] Figure 3 This application provides a schematic diagram of a process for obtaining target memory information in an embodiment of the present application.

[0040] Figure 4 A schematic diagram illustrating the connection between a processor, a baseboard management controller, and a memory provided in an embodiment of this application;

[0041] Figure 5 A flowchart illustrating another information detection method provided in an embodiment of this application;

[0042] Figure 6 This is a schematic diagram of the structure of an information detection device provided in an embodiment of this application;

[0043] Figure 7 This is a schematic diagram of another information detection device provided in an embodiment of this application;

[0044] Figure 8 This is a schematic diagram of the structure of another information detection device provided in the embodiments of this application;

[0045] Figure 9 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0047] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0048] With the continuous updates and iterations of memory technology, Double Data Rate (DDR) synchronous dynamic random access memory technology has become a common memory in everything from high-performance data centers to mobile applications where power consumption and area are critical.

[0049] The latest DDR memory currently available is DDR5, designated by the world's leading standards organization for the microelectronics industry. Compared to fourth-generation Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR4), DDR5 features lower input / output (I / O) voltages, higher density, and support for higher data rates.

[0050] Meanwhile, compared to DDR4's Dual In-line Memory Module (DIMM), DDR5 DIMMs deploy more critical chips related to data transmission. For example, DDR5 DIMMs include a Registering Clock Driver (RCD), a Data Buffer (DB), a Serial Presence Detect Hub and Memory, and multiple Temperature Sensors (TS). Taking the TS as an example, it can detect and record the temperature data of the DDR5. This allows system designers to calculate the heat dissipation distribution based on the DDR5's temperature when designing system airflow, avoiding excessive heat buildup that could affect system stability.

[0051] In addition, to better manage memory power consumption, the voltage regulator module (VRM) on the motherboard was moved to the DDR5 DIMM, meaning that the DDR5 has a power management integrated circuit (PMIC) controller.

[0052] In addition, another significant change in DDR5 compared to DDR4 is the introduction of support for the Improved Inter-Integrated Circuit (I3C) bus. DDR5 memory upgrades the system bus from the I2C bus of DDR4 memory to the I3C bus, thus achieving a tenfold increase in operating frequency from 1MHz to 10MHz. To support this higher speed, a Serial Presence Detect Hub (SPD Hub) supporting the I3C interface is required for communication. Besides the increased transmission speed, the I3C bus also changes the appearance of the DIMM compared to the I2C bus. Previously, the SPD and temperature sensor TS were connected side-by-side to the I2C; now, the SPD in DDR5 memory operates in a new Hub mode, becoming an SPD Hub. The temperature sensor TS has also been moved to the DIMM, called the Temperature Sensor on the DIMM (TSOD).

[0053] In some embodiments, the baseboard management controller in the server needs to detect storage information such as the temperature and power supply voltage of the memory.

[0054] Taking DDR4 temperature detection as an example, the processor or board management controller can obtain data from the temperature sensor TS via the System Management Bus (SMBus). When the temperature sensor TS detects that the memory temperature exceeds the threshold, it triggers an interrupt from the memory power controller via the EVENT_N pin. The server or processor can use the detected temperature information to manage fan speed / noise and the Dynamic Random-Access Memory (DRAM) refresh rate to improve performance or retention time.

[0055] Because DDR5 incorporates I3C, the processor or board management controller cannot communicate directly with the DDR5. The TS (Transmission Switch) mounted on the DDR5 determines that the DDR5's temperature is greater than or equal to a temperature threshold, and / or the PMIC (Power Management Controller) determines that the DDR5 has a power failure. In these cases, the processor triggers an in-band interrupt to indicate that the DDR5 is overheating and / or has a power failure. The processor then sends an indication message to the board management controller indicating the overheating and / or power failure of the DDR5.

[0056] However, the above methods mainly detect DDR5 fault information during normal DDR5 operation, and cannot detect DDR5 information during the initialization phase, nor can they achieve active detection of DDR5 storage information.

[0057] Based on this, this application provides an information detection method. The processor first sends a synchronous initialization instruction to the baseboard management controller, then responds to its acquisition request and returns the first storage information of the initialization phase, thus constructing a collaborative monitoring logic between the processor and the baseboard management controller. The information detection method provided by this application allows the baseboard management controller to detect the storage information of the detector during the memory initialization phase, enabling the baseboard management controller to proactively acquire the operating status of the memory during the initialization phase (such as temperature, PMIC power supply data, etc.), providing crucial data support for the subsequent stable operation of the memory and full-stage coverage of the overall server memory monitoring system.

[0058] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] This section describes the specific application environment architecture or hardware architecture upon which the information detection method depends. (References) Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application. For example... Figure 1As shown, it includes a server 11, in which a processor, a baseboard management controller and DDR5 are deployed.

[0060] In practical applications, the baseboard management controller can detect storage information such as the DDR5 temperature and PMIC through the processor. For example, the baseboard management controller can send a first acquisition request to the processor, requesting the processor to acquire the storage information of the memory at the current moment. After receiving the first acquisition request, the processor acquires the first storage information of the DDR5 and sends the first storage information to the baseboard management controller.

[0061] It should be noted that the execution subject in each embodiment of this application can be a processor, microprocessor, or a device integrating the aforementioned processor or microprocessor, such as a terminal device. The specific execution subject in each embodiment of this application is not limited and can be selected and set according to actual needs. In the following embodiments, a terminal device integrating the aforementioned processor or microprocessor is used as an example for description, which does not constitute a limitation on the actual execution subject.

[0062] It should be noted that, Figure 1 This is merely an example to illustrate one application scenario, and is not intended to limit the application scenario.

[0063] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0064] Figure 2 This is a flowchart illustrating an information detection method provided in an embodiment of this application. Figure 2 As shown, the method may include the following steps:

[0065] S201. Send an initialization command to the baseboard management controller via the first link; the initialization command is used to instruct the memory to enter the initialization stage, and the first link is a communication link between the processor and the baseboard management controller for transmitting the initialization command.

[0066] In some embodiments, the server is equipped with a processor, a baseboard management controller, and a memory. The processor is used to perform core computing, instruction scheduling, and memory initialization functions of the server. The processor may be, for example, a central processing unit (CPU).

[0067] The baseboard management controller is a dedicated management and monitoring chip independent of the processor. It is mainly used for remote management and hardware status monitoring of servers. For example, the baseboard management controller can be a controller that uses ASPEED 2600 as the main control chip.

[0068] Memory is the core data storage component of a server; memory can be, for example, a DDR5 DIMM.

[0069] The first link is a communication link specifically used by the processor to send initialization commands to the baseboard management controller. In some embodiments, the first link is a communication connection established between the baseboard management controller and the processor via gold fingers and a standard GenZ 4C connector.

[0070] In some embodiments, the processor can detect the state of the memory, which is either an initialization state or an operating state. If the processor detects that the memory is in an initialization state, it sends an initialization command to the baseboard management controller via a first link to instruct the memory to enter the initialization phase.

[0071] S202. Receive a first acquisition request sent by the baseboard management controller via the second link. The first acquisition request is used to request the processor to acquire the memory's storage information at the current moment. The second link is a communication link between the processor and the baseboard management controller for transmitting the first acquisition request and the storage information.

[0072] After receiving the initialization command from the processor via the first link, the baseboard management controller determines that the memory has entered the initialization phase. At this time, the baseboard management controller can send a first acquisition request to the processor via the second link.

[0073] The first fetch request is an instruction-type data frame actively sent by the baseboard management controller to the processor. Its core purpose is to instruct the processor to fetch the memory information stored at the current moment.

[0074] The second link is a communication link specifically used by the substrate management controller to obtain storage information from the memory. For example, the substrate management controller can send a first acquisition request to the processor via the second link, or the substrate management controller can receive storage information from the processor via the second link.

[0075] In some embodiments, the second link is a communication connection established between the baseboard management controller and the processor via gold fingers and a standard GenZ 4C connector.

[0076] In some embodiments, access to the I3C Controller can be granted in the processor's Basic Input / Output System (BIOS) code. This allows the processor to read and write to the I3C Controller via a second link. The I3C Controller, by default, supports data interaction with downstream I3C devices. Therefore, data transfer can occur between the processor and the board management controller via the second link.

[0077] The stored information consists of the memory's own status data and basic configuration data. For example, the stored information may include the memory's temperature, PMIC, and other information.

[0078] In some embodiments, during the memory initialization phase, the baseboard management controller can periodically send first acquisition information to the processor at preset time intervals to acquire the memory's storage information at different times.

[0079] S203. Obtain the first storage information of the memory; the first storage information is the storage information of the memory during the initialization phase.

[0080] After receiving the first acquisition request, the processor acquires the first storage information of the memory, which is the storage information of the memory at the current moment.

[0081] In some embodiments, the memory includes at least one memory module, and the processor has a communication link with each of the at least one memory module. The processor obtains the first storage information in the following manner: for each memory module in the at least one memory module, the processor performs the following operations: sends a second acquisition request to the memory management module corresponding to the memory module via a third link, the second acquisition request being used to request the acquisition of memory information of the memory module, the third link being the communication link between the processor and the memory management module corresponding to the memory module; receives the first memory information sent by the memory management module corresponding to the memory module via the third link, the first memory information being the memory information of the memory module during the initialization phase; wherein, the first storage information includes the first memory information of each of the at least one memory module.

[0082] In some embodiments, taking DDR5 DIMM memory as an example, at least one DDR5 DIMM memory module is deployed on the DIMM slot, and these DIMM memory modules integrate functional units such as PMIC and temperature sensors. At least one memory module is at least one DDR5 DIMM memory module deployed on the DIMM slot. It should be noted that each memory module in the at least one memory module includes a memory management module for centrally managing information such as the temperature and PMIC of that memory. A communication link exists between the processor and the memory management module corresponding to each of the at least one memory modules.

[0083] For each memory in at least one memory location, the third link is the communication link between the processor and the memory management module corresponding to that memory.

[0084] Therefore, for each memory in at least one memory location, the processor can send a second acquisition request to the memory management module corresponding to that memory via a third link to obtain the memory information of that memory. This memory information may include, for example, the memory's temperature, PMIC (Power Management Interface), and other similar information.

[0085] Upon receiving the second acquisition request, the memory management module corresponding to the memory sends the first memory information of that memory to the processor via the third link. The first memory information is the memory information of that memory at the current moment. The processor receives the first memory information sent by the memory via the third link.

[0086] S204. Send the first storage information to the baseboard management controller via the second link.

[0087] After receiving first memory information for each of at least one memory module, the processor determines first storage information based on the first memory information for each of the at least one memory module. Then, the processor sends the first storage information to the baseboard management controller via a second link.

[0088] exist Figure 2 In the illustrated embodiment, the processor first sends a synchronous initialization instruction to the baseboard management controller, then responds to its acquisition request and sends back the first storage information of the initialization phase, thus constructing a collaborative monitoring logic between the processor and the baseboard management controller. The information detection method provided in this application allows the baseboard management controller to detect the storage information of the detector during the memory initialization phase, enabling the baseboard management controller to proactively acquire the operating status of the memory during the initialization phase (such as temperature, PMIC power supply data, etc.), providing crucial data support for the subsequent stable operation of the memory and full-stage coverage of the overall server memory monitoring system.

[0089] exist Figure 2 Based on the embodiment shown, after the processor sends the first storage information to the baseboard management controller via the second link, it can also detect the state of the memory. If the state of the memory is running, it sends a running instruction to the baseboard management controller via the fourth link. The running instruction is used to instruct the memory to enter the running stage. The fourth link is a communication link between the processor and the baseboard management controller for transmitting the running instruction.

[0090] The fourth link is a communication link specifically used by the processor to send execution commands to the baseboard management controller. In some embodiments, the fourth link is a communication connection established between the baseboard management controller and the processor via gold fingers and a standard GenZ 4C connector.

[0091] In some embodiments, after the processor's online substrate management controller sends an initialization command, it continuously monitors the memory's status. When the memory's status changes from the initialization state to the running state, it determines that the memory is currently in the running phase. At this time, the processor sends a run command to the substrate management controller via the fourth link to instruct the memory to enter the running phase.

[0092] In some embodiments, the substrate management controller receives a running instruction sent by the processor via a fourth link; the running instruction is used to instruct the memory to enter the running phase, and the fourth link is a communication link between the processor and the substrate management controller for transmitting the running instruction; a fifth acquisition request is sent to the data forwarding module via a fifth link, the fifth acquisition request is used to request the data forwarding module to acquire the memory's storage information at the current moment; the fifth link is a communication link between the substrate management controller and the data forwarding module; and second storage information sent by the data forwarding module is received via the fifth link, the second storage information being the memory's storage information during the running phase.

[0093] After receiving the execution command from the processor via the fourth link, the baseboard management controller determines that the memory has entered the operation phase. Once the memory enters the operation phase, the processor needs to handle high-density tasks such as core server business operations and system instruction scheduling. Therefore, the processor load increases significantly. If the processor continues to handle memory information acquisition, it will affect the processor's business processing efficiency. Furthermore, if the baseboard management controller still obtains memory information through the processor after the memory enters the operation phase, the high processor load will lead to low efficiency in obtaining memory information.

[0094] Therefore, after determining that the memory has entered the operational phase, the baseboard management controller can obtain the memory's storage information through the data forwarding module. This data forwarding module can, for example, be an I3C Hub connected to the I3C server.

[0095] In some embodiments, a communication link exists between the baseboard management controller and the data forwarding module. Specifically, the fifth link is the communication link between the baseboard management controller and the forwarding module.

[0096] Specifically, the baseboard management controller sends a fifth acquisition request to the data forwarding module via the fifth link, and receives the second storage information sent by the data forwarding module via the fifth link. The second storage information refers to the storage information of the memory at the current moment.

[0097] In some embodiments, the data forwarding module receives a fifth acquisition request sent by the baseboard management controller via a fifth link. The fifth acquisition request is used to request the data forwarding module to acquire the storage information of the memory at the current moment. The fifth link is a communication link between the baseboard management controller and the data forwarding module. The module acquires the second storage information of the memory, which is the storage information of the memory during the running phase. The module then sends the second storage information to the baseboard management controller via the fifth link.

[0098] After receiving the fifth acquisition request sent by the baseboard management controller, the data forwarding module acquires the second storage information of the memory and sends the second storage information to the baseboard management controller through the fifth link.

[0099] In some embodiments, for each memory in at least one memory location, the communication connection between the data forwarding module and the memory management module corresponding to that memory is a sixth link. The data forwarding module can send a memory information retrieval request to the memory management module corresponding to that memory via the sixth link. After receiving the memory information retrieval request, the memory management module corresponding to that memory sends the memory information of that memory to the data forwarding module via the sixth link. The memory information of that memory includes the current temperature, PMIC information, etc.

[0100] The second storage information includes memory information for at least one memory location. Therefore, the data forwarding module can obtain the second storage information after receiving the memory information for each of the at least one memory location.

[0101] In the above embodiments, the information detection method provided in this application first involves the processor actively sending a run command to the baseboard management controller via a dedicated fourth link after completing the initialization phase storage information reporting. This explicitly instructs the memory to enter the running phase, providing a precise instruction basis for switching the monitoring phase. Then, upon receiving the run command, the baseboard management controller actively sends a fifth acquisition request to the data forwarding module via a fifth link, triggering the memory information acquisition process during the running phase, rather than passively waiting for fault reports. This achieves proactive acquisition of the memory's storage information.

[0102] Based on the above embodiments, the baseboard management controller can also obtain target memory information for each memory in the memory. Below, taking the memory during the initialization phase as an example, combined with... Figure 3 The method of obtaining target memory information in the embodiments of this application will be further explained.

[0103] Figure 3 This is a schematic diagram illustrating a process for obtaining target memory information, provided as an embodiment of this application. Figure 3 As shown, the process may include the following steps:

[0104] S301, the baseboard management controller sends a third acquisition request to the processor through the second link. The third acquisition request is used to request the processor to acquire target memory information.

[0105] The target memory information is a specific attribute of a memory within at least one memory location specified in the third acquisition request. For example, assuming that at least one memory location includes memory 1, memory 2, and memory 3, the target memory information could be, for example, the temperature information of memory 1.

[0106] In some embodiments, when the baseboard management controller needs to obtain certain storage information of a certain memory in at least one memory location, it can send a third acquisition request to the processor via a second link. The third acquisition request is a special instruction type data sent by the baseboard management controller to the processor, and includes an identifier of the target memory information, used to request the processor to obtain the target memory information.

[0107] S302, The processor receives a third acquisition request sent by the baseboard management controller through the second link.

[0108] After the baseboard management controller sends a third acquisition request to the processor through the second link, the processor can receive the third acquisition request sent by the baseboard management controller through the second link.

[0109] S303, The processor parses the third acquisition request and determines the identifier of the target memory information; the identifier of the target memory information is used to indicate the target memory corresponding to the target memory information and the attributes of the target memory information.

[0110] The identifier of the target memory information is a logical identifier extracted by the processor after parsing the third retrieval request and encapsulated within the third retrieval request.

[0111] Taking a DDR5 DIMM as an example, the target memory is the specific DIMM memory pointed to by the identifier of the target memory information, which is the memory object for the processor to collect target memory information.

[0112] The attributes of the target memory information are used to instruct the processor to collect specific memory information from the target memory. For example, the attributes of the target memory information may be temperature information or PMIC information.

[0113] In some embodiments, the identifier of the target memory information can be represented by 8 bits of data. The high 4 bits (bits 4-7) represent the attributes of the target memory information, the low 4 bits indicate whether it is a read or write operation, and bits 1-3 represent the target memory corresponding to the target memory information.

[0114] For example, suppose at least one memory includes memory 1, memory 2, and memory 3, and the attributes of the target memory information include temperature information, PMIC information, and RCD information. The identifiers of the target memory and the attributes of the target memory information can be shown in Table 1:

[0115] Table 1

[0116]

[0117] Assume the identifier of the target memory information is 00100100. Here, 0010 indicates that the baseboard management controller needs to collect temperature information, and 010 indicates that memory information for memory 2 needs to be collected. Therefore, the target memory is determined to be memory 2, and the attribute of the target memory information is temperature information.

[0118] S304. The processor obtains the target memory information based on the attributes of the target memory and the target memory information.

[0119] The processor can obtain target memory information in the following ways: Based on the attributes of the target memory and the target memory information, a fourth acquisition request is generated. The fourth acquisition request is used to request the acquisition of the target memory information. The fourth acquisition request is sent to the memory management module corresponding to the target memory through the target link. The target link is the communication link between the processor and the memory management module corresponding to the target memory. The target memory information sent by the memory management module corresponding to the target memory is received through the target link.

[0120] In some embodiments, after determining the attributes of the target memory and the target memory information, the processor generates a fourth acquisition request based on the target memory and the target memory information. The fourth acquisition request is a dedicated data acquisition instruction frame for the target memory, used to request the acquisition of the target memory information.

[0121] The target link is the communication link between the processor and the memory management module corresponding to the target memory. In some embodiments, the target link can be a third communication link between the processor and the target memory.

[0122] The processor sends a fourth retrieval request to the memory management module corresponding to the target memory via the target link. Upon receiving the fourth retrieval request, the memory management module corresponding to the target memory sends the target memory information to the processor via the target link.

[0123] S305, the processor sends the target memory information to the baseboard management controller via the second link.

[0124] After receiving the target memory information via the target link, the processor sends the target memory information to the baseboard management controller via the second link.

[0125] S306, The baseboard management controller receives the target memory information sent by the processor through the second link.

[0126] exist Figure 3 In the embodiment shown, the method first sends a third acquisition request to the processor through the second link to initiate a targeted memory information acquisition request. Then, the processor parses the request and accurately determines the identifier of the target memory information, thereby achieving dual precise locking of the "acquisition object (target memory)" and the "acquisition content (information attributes)" and reducing information confusion and resource waste in the batch acquisition mode.

[0127] Based on the above embodiments, the following, in conjunction with Figure 4 The specific embodiments shown further illustrate the information detection method provided in this application.

[0128] Figure 4 This is a schematic diagram illustrating the connection between a processor, a baseboard management controller, and a memory, provided as an embodiment of this application. Figure 4 As shown, the server includes a baseboard management controller, processor 1, processor 2, a data forwarding module, and at least one DIMM memory.

[0129] The communication links between the baseboard management controller and the processor include a first link, a second link, and a fourth link. The processor can send initialization commands to the baseboard management controller via the first link. The processor can send execution commands to the baseboard management controller via the fourth link. Therefore, the baseboard management controller can determine the memory's operational stage through communication with the processor via the first and fourth links.

[0130] The communication link between the baseboard management controller and the processor 2 is the seventh link. The function of the seventh link is similar to that of the second link. It is a communication link between the processor 2 and the baseboard management controller used to transmit the first acquisition request and store information.

[0131] In some embodiments, after receiving an initialization instruction sent by the processor 1 via the first link, the baseboard management controller can send a first acquisition request to the processor via the second link and a first acquisition request to the processor via the seventh link.

[0132] In some embodiments, the baseboard management controller can determine the memory state based on initialization instructions and execution instructions. Upon receiving an initialization instruction, it obtains first memory information from the processor via a second link. Upon receiving an execution instruction, it obtains second memory information from the data forwarding module connected to the I3C via a fifth link.

[0133] Taking processor 1 as an example, the DIMM includes at least one DIMM slot, and three memory modules are deployed on the DIMM slot. There is a communication link between processor 1 and each DIMM slot, and processor 1 can establish a third link with the memory management module corresponding to each of the three memory modules on the DIMM slot through the communication link.

[0134] For each memory location, after receiving a first acquisition request, processor 1 can send a second acquisition request to the memory management module corresponding to that memory location via a third link. Upon receiving the second acquisition request, the memory management module of that memory location sends the first memory information of that memory to processor 1 via the third link.

[0135] After receiving first memory information from at least one memory, processor 1 determines first storage information and sends the first storage information to the baseboard management controller via the second link.

[0136] In some embodiments, after receiving the running instruction sent by the processor 1 through the fourth link, the baseboard management controller can send a fifth acquisition request to the data forwarding module through the fifth link.

[0137] Assume that a DIMM includes at least one DIMM slot, and three memory modules are deployed on each DIMM slot. The data forwarding module has a communication link with each DIMM slot, and through this communication link, the data forwarding module can establish a sixth link with the memory management module corresponding to each of the three memory modules on the DIMM slot.

[0138] For each memory module, after receiving the fifth retrieval request, the data forwarding module can send a memory information retrieval request to the corresponding memory management module via the sixth link. Upon receiving the memory information retrieval request, the memory management module of that memory sends the second memory information of that memory to the data forwarding module via the sixth link. The second memory information includes the current temperature and PMIC information of that memory.

[0139] After receiving the second memory information of at least one memory module, the data forwarding module determines the second storage information and sends the second storage information to the baseboard management controller via the fifth link.

[0140] In summary, the information detection method provided in this application can be as follows: Figure 5 As shown. Figure 5 This is a flowchart illustrating another information detection method provided in an embodiment of this application. Figure 5 As shown, the information detection method provided in this application includes the following steps:

[0141] S501, the baseboard management controller receives the initialization command sent by the processor through the first link.

[0142] S502, the baseboard management controller obtains the first storage information of the memory through the processor.

[0143] S503, the baseboard management controller receives the running instructions sent by the processor through the fourth link.

[0144] S504, the baseboard management controller obtains the second storage information of the memory through the data forwarding module.

[0145] In some embodiments, a pin can be led out on the communication link between the processor and the DIMM slot, and on the communication link between the data forwarding module and the DIMM slot, and this pin can be connected to a host computer. In this way, after the processor obtains the first storage information, it can display the first storage information on the host computer. Similarly, after the data forwarding module obtains the second storage information, it can display the second storage information on the host computer. This allows staff to easily view the storage information of the memory at each stage.

[0146] exist Figure 4 In the illustrated embodiment, the processor first sends a synchronous initialization instruction to the baseboard management controller, then responds to its acquisition request and sends back the first storage information of the initialization phase, thus constructing a collaborative monitoring logic between the processor and the baseboard management controller. The information detection method provided in this application allows the baseboard management controller to detect the storage information of the detector during the memory initialization phase, enabling the baseboard management controller to proactively acquire the operating status of the memory during the initialization phase (such as temperature, PMIC power supply data, etc.), providing crucial data support for the subsequent stable operation of the memory and full-stage coverage of the overall server memory monitoring system.

[0147] Figure 6 This is a schematic diagram of the structure of an information detection device provided in an embodiment of this application. Figure 6 As shown in the figure, this application embodiment also provides an information detection device 60, which includes a first sending module 61, a first receiving module 62, a first acquiring module 63, and a second sending module 64, wherein:

[0148] The first sending module 61 is used to send an initialization command to the baseboard management controller via a first link; the initialization command is used to instruct the memory to enter the initialization stage, and the first link is a communication link between the processor and the baseboard management controller for transmitting the initialization command.

[0149] The first receiving module 62 is used to receive a first acquisition request sent by the baseboard management controller through the second link. The first acquisition request is used to request the processor to acquire the storage information of the memory at the current moment. The second link is a communication link between the processor and the baseboard management controller for transmitting the first acquisition request and the storage information.

[0150] The first acquisition module 63 is used to acquire the first storage information of the memory; the first storage information is the storage information of the memory during the initialization phase.

[0151] The second sending module 64 is used to send the first stored information to the baseboard management controller via the second link.

[0152] In one possible implementation, the memory includes at least one memory module, and the first acquisition module 63 is specifically used for:

[0153] For each memory location in at least one memory location, perform the following operations:

[0154] A second retrieval request is sent to the memory management module corresponding to the memory via the third link. The second retrieval request is used to request the memory information of the memory. The third link is the communication link between the processor and the memory management module corresponding to the memory.

[0155] The memory management module corresponding to the receiving memory sends the first memory information through the third link. The first memory information is the memory information during the initialization phase of the memory.

[0156] The first storage information includes first memory information for each of at least one memory.

[0157] In one possible implementation, the information detection device 60 further includes a first transceiver module, which is specifically used for:

[0158] The processor sends a running command to the baseboard management controller via the fourth link. The running command is used to instruct the memory to enter the running phase. The fourth link is a communication link between the processor and the baseboard management controller for transmitting running commands.

[0159] In one possible implementation, the first transceiver module is specifically used for:

[0160] The third acquisition request is sent by the baseboard management controller through the second link. The third acquisition request is used to request the processor to acquire target memory information.

[0161] The third acquisition request is parsed to determine the identifier of the target memory information; the identifier of the target memory information is used to indicate the target memory corresponding to the target memory information, as well as the attributes of the target memory information;

[0162] Obtain the target memory information based on the attributes of the target memory and the target memory information;

[0163] The target memory information is sent to the baseboard management controller via the second link.

[0164] In one possible implementation, the first transceiver module is specifically used for:

[0165] Based on the attributes of the target memory and the target memory information, a fourth retrieval request is generated. The fourth retrieval request is used to request the retrieval of the target memory information.

[0166] A fourth acquisition request is sent to the memory management module corresponding to the target memory via the target link; the target link is the communication link between the processor and the memory management module corresponding to the target memory.

[0167] Receive target memory information sent by the memory management module corresponding to the target memory via the target link.

[0168] For a description of the features in the embodiment corresponding to the information detection device 60, please refer to the relevant description of the embodiment corresponding to the information detection method with the processor as the execution subject, which will not be repeated here.

[0169] Figure 7 This is a schematic diagram of another information detection device provided in an embodiment of this application. Figure 7 As shown, this application embodiment also provides an information detection device 70, which includes a second receiving module 71, a third transmitting module 72, and a third receiving module 73, wherein:

[0170] The second receiving module 71 is used to receive an initialization instruction sent by the processor through the first link. The initialization instruction is used to instruct the memory to enter the initialization stage. The first link is a communication link between the processor and the baseboard management controller for transmitting the initialization instruction.

[0171] The third sending module 72 is used to send a first acquisition request to the processor via the second link. The first acquisition request is used to request the processor to acquire the memory's stored information at the current moment. The second link is a communication link between the processor and the baseboard management controller for transmitting the first acquisition request and the stored information.

[0172] The third receiving module 73 is used to receive the first storage information sent by the processor through the second link. The first storage information is the storage information of the memory during the initialization phase.

[0173] In one possible implementation, the information detection device 70 further includes a second transceiver module, which is specifically used for:

[0174] The processor sends execution instructions via the fourth link; the execution instructions are used to instruct the memory to enter the execution phase, and the fourth link is a communication link between the processor and the baseboard management controller for transmitting execution instructions.

[0175] A fifth acquisition request is sent to the data forwarding module via the fifth link. The fifth acquisition request is used to request the data forwarding module to acquire the storage information of the memory at the current moment. The fifth link is the communication link between the baseboard management controller and the data forwarding module.

[0176] The second storage information is the storage information of the memory during the operation phase, which is received by the data forwarding module through the fifth link.

[0177] In one possible implementation, the second transceiver module is specifically used for:

[0178] A third retrieval request is sent to the processor via the second link. The third retrieval request is used to request the processor to retrieve the target memory information.

[0179] The target memory information is received by the processor via the second link.

[0180] For a description of the features in the embodiment corresponding to the information detection device 70, please refer to the relevant description of the embodiment corresponding to the information detection method with the baseboard management controller as the execution subject, which will not be repeated here.

[0181] Figure 8 This is a schematic diagram of the structure of another information detection device provided in an embodiment of this application. Figure 8 As shown, this application embodiment also provides an information detection device 80, which includes a fourth receiving module 81, a second acquiring module 82, and a fourth sending module 83, wherein:

[0182] The fourth receiving module 81 is used to receive a fifth acquisition request sent by the baseboard management controller via the fifth link. The fifth acquisition request is used to request the data forwarding module to acquire the storage information of the memory at the current moment. The fifth link is the communication link between the baseboard management controller and the data forwarding module.

[0183] The second acquisition module 82 is used to acquire the second storage information of the memory, which is the storage information of the memory during the running phase.

[0184] The fourth transmitting module 83 is used to transmit the second stored information to the baseboard management controller via the fifth link.

[0185] For a description of the features in the embodiment corresponding to the information detection device 80, please refer to the relevant description of the embodiment corresponding to the information detection method with the data forwarding module as the execution subject, which will not be repeated here.

[0186] Figure 9 A schematic diagram of the structure of the electronic device provided in this application. Figure 9As shown, the electronic device 90 provided in this embodiment includes at least one processor 901 and a memory 902. Optionally, the electronic device 90 further includes a communication component 903. The processor 901, memory 902, and communication component 903 are connected via a bus.

[0187] In a specific implementation, at least one processor 901 executes computer execution instructions stored in memory 902, causing at least one processor 901 to execute the above-described information detection method embodiment.

[0188] The specific implementation process of the processor 901 execution information detection method can be found in the above method embodiment, and its implementation principle and technical effect are similar, so it will not be repeated here.

[0189] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0190] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0191] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0192] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described information detection method embodiments when it is run.

[0193] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0194] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described information detection method embodiments.

[0195] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described information detection method embodiments.

[0196] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0197] The above provides a detailed description of the information detection method and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An information detection method, characterized in that, Applied to a processor, the method includes: An initialization command is sent to the baseboard management controller via a first link; the initialization command is used to instruct the memory to enter the initialization phase, and the first link is a communication link between the processor and the baseboard management controller for transmitting the initialization command; The processor receives a first acquisition request sent by the baseboard management controller via a second link. The first acquisition request is used to request the processor to acquire the storage information of the memory at the current moment. The second link is a communication link between the processor and the baseboard management controller for transmitting the first acquisition request and the storage information. Obtain the first storage information of the memory; the first storage information is the storage information of the memory during the initialization phase; The first stored information is sent to the baseboard management controller via the second link; The memory includes at least one memory module, and obtaining the first storage information of the memory includes: For each memory location in the at least one memory location, the following operations are performed: A second acquisition request is sent to the memory management module corresponding to the memory via a third link. The second acquisition request is used to request the memory information of the memory. The third link is a communication link between the processor and the memory management module corresponding to the memory. The system receives first memory information sent by the memory management module corresponding to the memory through the third link. The first memory information is the memory information of the memory during the initialization phase. The first storage information includes the first memory information of each of the at least one memory.

2. The method according to claim 1, characterized in that, After sending the first stored information to the substrate management controller via the second link, the method further includes: The processor sends a running instruction to the baseboard management controller via a fourth link; the running instruction is used to instruct the memory to enter the running phase, and the fourth link is a communication link between the processor and the baseboard management controller for transmitting the running instruction.

3. The method according to claim 1, characterized in that, The method further includes: The processor receives a third acquisition request sent by the baseboard management controller via the second link. The third acquisition request is used to request the processor to acquire target memory information. The third acquisition request is parsed to determine the identifier of the target memory information; the identifier of the target memory information is used to indicate the target memory corresponding to the target memory information and the attributes of the target memory information; The target memory information is obtained based on the attributes of the target memory and the target memory information. The target memory information is sent to the baseboard management controller via the second link.

4. The method according to claim 3, characterized in that, The step of obtaining the target memory information based on the target memory and the attributes of the target memory information includes: Based on the attributes of the target memory and the target memory information, a fourth acquisition request is generated, the fourth acquisition request being used to request the acquisition of the target memory information; The fourth acquisition request is sent to the memory management module corresponding to the target memory via the target link; the target link is the communication link between the processor and the memory management module corresponding to the target memory. The target memory information is received through the target link from the memory management module corresponding to the target memory.

5. An information detection method, characterized in that, Applied to a baseboard management controller, the method includes: The processor sends an initialization command via a first link. The initialization command is used to instruct the memory to enter the initialization phase. The first link is a communication link between the processor and the baseboard management controller for transmitting the initialization command. A first acquisition request is sent to the processor via a second link. The first acquisition request is used to request the processor to acquire the storage information of the memory at the current moment. The second link is a communication link between the processor and the baseboard management controller for transmitting the first acquisition request and the storage information. The first storage information sent by the processor is received through the second link, and the first storage information is the storage information of the memory during the initialization phase. After receiving the first storage information sent by the processor via the second link, the method further includes: The processor sends an operation instruction via a fourth link; the operation instruction is used to instruct the memory to enter the operation phase, and the fourth link is a communication link between the processor and the baseboard management controller for transmitting the operation instruction; A fifth acquisition request is sent to the data forwarding module via the fifth link. The fifth acquisition request is used to request the data forwarding module to acquire the storage information of the memory at the current moment. The fifth link is the communication link between the baseboard management controller and the data forwarding module. The second storage information, which is the storage information of the memory during the operation phase, is received through the fifth link from the data forwarding module.

6. The method according to claim 5, characterized in that, The method further includes: A third acquisition request is sent to the processor via the second link, the third acquisition request being used to request the processor to acquire target memory information; The target memory information sent by the processor is received via the second link.

7. An information detection method, characterized in that, Applied to a data forwarding module, the method includes: The fifth acquisition request is received from the baseboard management controller via a fifth link. This fifth acquisition request requests the data forwarding module to acquire the memory's storage information at the current moment. The fifth link is a communication link between the baseboard management controller and the data forwarding module. The fifth acquisition request is sent by the baseboard management controller after receiving a run instruction from the processor via a fourth link. The fourth link is a communication link between the processor and the baseboard management controller for transmitting the run instruction. The run instruction instructs the memory to enter the running phase. This run instruction is sent by the baseboard management controller after receiving first storage information from the processor via a second link. The first storage information is... The memory stores information during the initialization phase; the first storage information is sent by the substrate management controller after sending a first acquisition request to the processor via the second link, the first acquisition request being used to request the processor to acquire the memory's storage information at the current moment; the second link is a communication link between the processor and the substrate management controller for transmitting the first acquisition request and the storage information; the first acquisition request is sent by the substrate management controller after receiving an initialization instruction sent by the processor via the first link, the initialization instruction being used to instruct the memory to enter the initialization phase, the first link being a communication link between the processor and the substrate management controller for transmitting the initialization instruction; Obtain the second storage information of the memory, wherein the second storage information is the storage information of the memory during the operation phase; The second storage information is sent to the baseboard management controller via the fifth link.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the information detection method as described in any one of claims 1 to 7 when executing the computer program.

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