FPGA-based chip high-speed interconnection multi-channel data synchronization method and system

Abstract

The application relates to a kind of FPGA-based chip high-speed interconnection multi-channel data synchronization method and system.The method comprises the following steps: configuring data sending end to output multiple parallel reference test data to FPGA, FPGA includes multiple high-speed receiving modules, multiple cache modules, shift control module and counting module, multiple parallel data are transmitted to corresponding cache module storage after being received by high-speed receiving module; with the cache data of main channel as reference, the offset of each slave channel cache data is calculated by counting module; when the offset is greater than or equal to the first threshold, the corresponding cache module byte-level shift is controlled by shift control module, and when the offset is less than the first threshold, the corresponding high-speed receiving module is controlled to finely shift at bit level, until the offset meets the synchronization threshold; switch the preset verification data output by the data sending end, and when the output data of each channel cache module is consistent with the verification data, the multi-channel synchronization is completed. The method can realize the accurate synchronization of multi-channel data.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of electronic engineering, in particular to a chip high-speed interconnection multi-channel data synchronization method and system based on FPGA. BACKGROUND

[0002] With the rapid development of high-end computing, high-speed data acquisition, data center, radar signal processing and medical imaging, etc., the bandwidth and real-time performance of data processing are increasingly demanding. In order to meet this demand, multiple application-specific integrated circuits or processors are usually used in traditional technology to exchange data through JESD204B / C, Aurora, PCIe and other high-speed serial interconnection protocols. Such interconnection technology has the characteristics of high transmission rate and large capacity data bearing, and has become the mainstream implementation method of multi-channel data interaction. However, in actual application, the traditional multi-channel data synchronization method is often difficult to realize the accurate time alignment of different chips or different source multi-channel parallel data channels of the same chip. Due to the difference in data transmission delay of each channel, data offset is easy to occur, which further affects the accuracy of subsequent collaborative operation and processing. At the same time, the traditional synchronization scheme is usually designed for a specific number of channels and clock frequency, and has poor adaptability and scalability, which cannot flexibly respond to parameter adjustment requirements in different application scenarios, and ultimately reduces the reliability and practicability of the entire data processing system. SUMMARY

[0003] Therefore, it is necessary to provide a chip high-speed interconnection multi-channel data synchronization method and system based on FPGA in view of the above technical problems.

[0004] A chip high-speed interconnection multi-channel data synchronization method based on FPGA, the method comprises:

[0005] The configuration data transmission end outputs multiple parallel reference test data to the FPGA, the FPGA comprises multiple high-speed receiving modules, multiple cache modules, a shift control module and a counting module, and the high-speed receiving module receives multiple parallel data and then transmits the data to the corresponding cache module for storage;

[0006] A master channel is selected from the multiple parallel channels, and the offset of each slave channel data stored in the remaining cache modules is calculated by the counting module based on the master channel data stored in the cache module;

[0007] When the offset is greater than or equal to a first threshold value, the corresponding cache module is controlled by the shift control module to perform byte-level shift adjustment;

[0008] When the offset is less than the first threshold value, the corresponding high-speed receiving module is controlled by the shift control module to perform bit-level fine shift adjustment until the offset meets the synchronization threshold value;

[0009] The data sending end outputs preset verification data, and when the data output by the buffer modules corresponding to each channel are all consistent with the verification data, the multi-channel synchronization is completed.

[0010] A multi-channel data synchronization system for high-speed interconnection of chips based on FPGA, comprising:

[0011] a data sending end and an FPGA; the FPGA comprises a plurality of high-speed receiving modules, a plurality of buffer modules, a shift control module and a counting module;

[0012] The data sending end is configured to output multi-channel parallel reference test data and switch to output preset verification data.

[0013] The high-speed receiving modules are connected to the data sending end and configured to receive multi-channel parallel data and transmit the data to corresponding buffer modules.

[0014] The buffer modules are configured to store the received data of corresponding channels and perform byte-level shift adjustment in response to the control of the shift control module.

[0015] The counting module is configured to take the data stored in the buffer module corresponding to the master channel as a reference, calculate the offset of the data stored in the buffer modules corresponding to the slave channels, and feed back the offset to the shift control module.

[0016] The shift control module is configured to receive the control data of each slave channel in real time, control the corresponding buffer module to perform byte-level shift adjustment when the offset is greater than or equal to a first threshold, control the corresponding high-speed receiving module to perform bit-level fine shift adjustment when the offset is less than the first threshold, and adjust until the offset meets a synchronization threshold.

[0017] When the data output by the buffer modules corresponding to all channels are all consistent with the preset verification data, the multi-channel synchronization is completed.

[0018] The FPGA-based chip high-speed interconnection multi-channel data synchronization method and system can lay a stable data foundation for multi-channel synchronization by corresponding receiving and storing the multi-parallel reference test data output by the data sending end through the multiple high-speed receiving modules and cache modules of the FPGA. Taking the main channel data as the reference, the offset of each slave channel data is accurately calculated through the counting module, and the target and direction of synchronization adjustment can be clearly determined. A step adjustment strategy is adopted according to the size of the offset, and when the offset is large, the byte-level shift adjustment is performed by the cache module controlled by the shift control module, and when the offset is small, the bit-level fine shift adjustment is performed by the high-speed receiving module, so that the time sequence offset of different degrees can be efficiently eliminated, and the offset can meet the synchronization requirement. The consistency of the output of each channel is verified by switching the preset verification data, and the synchronization effect can be accurately confirmed. The embodiment of the application can effectively solve the time dislocation problem of the multi-parallel data channels caused by transmission delay, realize accurate synchronization of multi-channel data, provide stable aligned input data for the collaborative operation of high-end computing, high-speed data acquisition and other fields, and significantly improve the reliability and correctness of the subsequent data processing module. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 FIG. 1 is a flowchart of a FPGA-based chip high-speed interconnection multi-channel data synchronization method according to an embodiment of the application;

[0020] Figure 2 FIG. 5 is a framework diagram of a FPGA implementation method for high-speed interconnection multi-channel data synchronization between a data sending chip and a FPGA chip according to an embodiment of the application;

[0021] Figure 3 FIG. 6 is a control flowchart of a FPGA implementation method for high-speed interconnection multi-channel data synchronization between a data sending chip and a FPGA chip according to an embodiment of the application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the application more clear, the application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and not to limit the application.

[0023] In one embodiment, as shown in FIG. 1, a FPGA-based chip high-speed interconnection multi-channel data synchronization method is provided, including the following steps: Figure 1

[0024] Step 102, configure the data sending end to output multi-parallel reference test data to the FPGA, the FPGA includes multiple high-speed receiving modules, multiple cache modules, a shift control module and a counting module, and the high-speed receiving module receives the multi-parallel data and then transmits it to the corresponding cache module for storage.

[0025] ​The benchmark test data refers to standardized data for multi-channel synchronous benchmark comparison, usually a stable and repeatable sequence (such as a PRBS11 pseudo-random sequence); the high-speed receiving module is a core component (such as a GTY module) in the FPGA for receiving high-speed parallel data, which is suitable for high-bandwidth data transmission requirements; the cache module is a component (such as a FIFO) for temporarily storing the received data of the corresponding channel to avoid overflow or delay during data transmission; the shift control module is a control core in the FPGA responsible for issuing shift adjustment instructions and coordinating the synchronous actions of each module; the counting module is a functional module for calculating the data offset between channels to provide data basis for shift adjustment.

[0026] It can be understood that by configuring uniform benchmark test data, a consistent comparison basis is provided for subsequent offset calculation, avoiding synchronization errors caused by benchmark differences. The corresponding configuration of the high-speed receiving module and the cache module ensures stable reception and storage of multi-channel parallel data, providing complete data support for subsequent synchronization processing, solving the problems of easy loss and uneven delay in the multi-channel data transmission process, and laying a foundation for synchronization adjustment.

[0027] Step 104: Selecting a master channel from the multi-channel parallel channels, taking the master channel data stored in the cache module as the benchmark, and calculating the offset of each slave channel data stored in the remaining cache modules through the counting module.

[0028] The master channel refers to the channel selected from the multi-channel parallel channels as the synchronization benchmark, and its data timing is the alignment standard for other channels. The slave channel refers to the remaining channels that need to be aligned with the master channel data timing, excluding the master channel. The offset refers to the misalignment difference (CNT) of each slave channel data and the master channel data in time, which directly reflects the degree of data synchronization deviation.

[0029] Step 106: When the offset is greater than or equal to the first threshold value, the corresponding cache module is controlled by the shift control module to perform byte-level shift adjustment.

[0030] The first threshold value refers to the critical value that distinguishes between byte-level coarse adjustment and bit-level fine adjustment, which is used to determine the processing method of the offset. Byte-level shift adjustment refers to the adjustment of data storage and output timing in units of bytes, which is achieved by controlling the read empty or write empty operation of the cache module, and is suitable for handling larger offsets.

[0031] Step 108: When the offset is less than the first threshold value, the corresponding high-speed receiving module is controlled by the shift control module to perform bit-level fine shift adjustment until the offset meets the synchronization threshold.

[0032] The synchronization threshold refers to a critical value for determining whether the data reaches a synchronization state, i.e., the offset needs to be reduced below this value to be considered as meeting the synchronization standard; the bit-level fine shift adjustment refers to a precise adjustment of the data receiving timing in units of bits, with a shift step of 1 bit each time, which is suitable for processing small offsets; the RXSLIDE shift function is a bit-level shift function built-in the high-speed receiving module, providing hardware support for fine adjustment.

[0033] It can be understood that for small offsets less than the first threshold, the bit-level fine shift adjustment can accurately eliminate residual deviations and ensure that the data timing of each channel is completely aligned, solving the problem that byte-level adjustment cannot handle small offsets. By implementing bit-by-bit adjustment through the RXSLIDE function, the synchronization accuracy is guaranteed, meeting the high-precision requirements of data synchronization in high-end computing, radar signal processing, and other fields, and providing time-consistent data input for subsequent collaborative operation.

[0034] In step 110, the data sending end switches to output preset verification data, and when the data output by each channel corresponding buffer module is consistent with the verification data, the multi-channel synchronization is completed.

[0035] The preset verification data refers to standardized fixed data used to verify the synchronization result, and its uniformity ensures the accuracy of the verification; the consistent verification data refers to the data output by each channel buffer module completely matching the preset verification data, which is the core determination standard for synchronization completion.

[0036] By switching the preset verification data for consistency verification, a closed-loop control of adjustment-verification is formed, avoiding the misjudgment problem caused by relying only on offset to determine synchronization; only when all channel data is consistent with the verification data can the synchronization be confirmed to be completed, ensuring the reliability of the synchronization result, solving the problem of incomplete synchronization caused by no verification after adjustment in traditional synchronization methods, and finally providing stable aligned data for subsequent data processing modules, ensuring the correctness of collaborative operation.

[0037] In the FPGA-based chip high-speed interconnection multi-channel data synchronization method, the multiple high-speed receiving modules and the cache modules of the FPGA correspondingly receive and store the multiple parallel reference test data output by the data sending end, which can lay a stable data foundation for multi-channel synchronization. Taking the main channel data as the reference, the offset of each slave channel data is accurately calculated by the counting module, and the target and direction of the synchronization adjustment can be clearly determined. A step adjustment strategy is adopted according to the size of the offset, when the offset is large, the byte-level shift adjustment of the cache module is controlled by the shift control module, when the offset is small, the bit-level fine shift adjustment of the high-speed receiving module is controlled, which can efficiently eliminate time offsets of different degrees and ensure that the offset meets the synchronization requirements. Then, the consistency of the output of each channel is verified by switching the preset verification data, and the synchronization effect can be accurately confirmed. The embodiment of the application can effectively solve the time dislocation problem of multiple parallel data channels caused by transmission delay, realize accurate synchronization of multi-channel data, provide stable and aligned input data for the collaborative operation of high-end computing, high-speed data acquisition and other fields, and significantly improve the reliability and correctness of the subsequent data processing module.

[0038] In one embodiment, the reference test data is a pseudo-random sequence; the pseudo-random sequence includes PRBS11, which is used to provide a stable and repeatable comparison reference for the counting module to calculate the offset.

[0039] In one embodiment, the byte-level shift adjustment of the corresponding cache module controlled by the shift control module includes: the shift control module outputs a read-write control signal to the corresponding cache module according to the offset value fed back by the counting module; the cache module responds to the read-write control signal to perform a read-empty or write-empty operation, and gradually reduces the offset by adjusting the time interval of data storage and output.

[0040] In one embodiment, the bit-level fine shift adjustment of the corresponding high-speed receiving module controlled by the shift control module until the offset meets the synchronization threshold includes: the shift control module sends a shift instruction to the high-speed receiving module according to the offset fed back by the counting module, controls the RXSLIDE shift function built-in the high-speed receiving module to adjust the data receiving time sequence bit by bit, and the shift step is 1 bit each time, until the counting module detects that the offset is reduced to the synchronization threshold.

[0041] In one embodiment, switching the preset verification data output by the data sending end includes: when the counting module detects that the offset of each slave channel meets the synchronization threshold, the shift control module sends a data switching instruction to the data sending end; the data sending end responds to the data switching instruction to stop outputting the reference test data and switches to output the unified preset verification data; the preset verification data is a fixed numerical combination, and the low 16-bit data is 0xABCD.

[0042] In one embodiment, when the output data of each channel corresponding cache module is consistent with the verification data, the multi-channel synchronization is completed, including: reading the output data of each cache module through the counting module channel by channel, comparing the data of each channel with the preset verification data for consistency, and feeding back the comparison result of each channel to the shift control module in real time; when the shift control module receives the comparison results of each channel, the shift adjustment process is terminated, and the multi-channel synchronization is completed; if there is any channel comparison result inconsistent, the corresponding high-speed receiving module is controlled by the shift control module to re-execute the bit-level fine shift adjustment until the counting module detects that the data of each channel is consistent with the verification data.

[0043] In one embodiment, the method further comprises: after completing the multi-channel synchronization, sending a service mode switching instruction to the data sending end through the shift control module to control the data sending end to switch back to the service data output mode; and the cache module corresponding to each channel outputs the service data according to the synchronized timing.

[0044] In one specific embodiment, as shown in Figure 2 , a FPGA implementation method framework diagram for multi-channel data synchronization of high-speed interconnection between a data sending chip and an FPGA chip is provided, which includes a data sending chip, a control module, a GTY module, a FIFO module, and a counting module. The data sending chip can output N-channel data, which is received by N GTYs and then transmitted to the FIFO, and the counting module counts the master-slave channel data offset and feeds back to the control module, which executes the control strategy according to the CNT value. The number of channels can be modified according to specific conditions, and the test data PATTERN can also be configured.

[0045] As shown in Figure 3 , a FPGA implementation method control flowchart for multi-channel data synchronization of high-speed interconnection between a data sending chip and an FPGA chip is provided, and the entire synchronization process is as follows: data is sent from the data sending chip, transmitted to the FPGA through the high-speed port GTY, and a certain channel in the N channels is selected as the master channel as the synchronization reference for other channels. The slave channel is compared with the master channel for offset and the offset CNT is recorded and output to the control module. First, it is judged whether CNT is less than 64, if greater than 64, the FIFO is controlled to perform byte-level shift until CNT is less than 64; then it is judged whether CNT is equal to 0, if not equal to 0, the GTY rxslide is controlled to perform bit-level shift until CNT is 0; then the data sending chip sends data as PATTERN (this case is set as 0xABCD), and the read data is judged whether it is 0xABCD, if not, bit-level shift is performed until the output is 0xABCD, and thus the synchronization is completed.

[0046] Taking the case of using 16 channels as an example, the method is described, the number of channels can be downward compatible or upwardly extended, the initial data sent by the data sending chip is prbs11, and the subsequent switching test data is 0xABCD.

[0047] Step one: the starting device switches the data sending chip output to prbs11, and the data enters the FPGA through GTY;

[0048] Step two: 16 FIFOs are instantiated, with a bit width of 64 bits, for receiving the downlink data of GTY.

[0049] Step three: the output data of the 16 FIFOs enters the counting module, taking the main channel as the reference, the offset CNT between each slave channel and the main channel is recorded, and the CNT is fed back to the control module.

[0050] Step four: the control module judges whether the value of CNT is greater than 64, if greater than 64, the read-write signal of the FIFO is controlled to perform the read empty or write empty operation on the FIFO, to realize byte-level shifting, so that the value of CNT is reduced. If CNT is less than 64, the control module controls the rxslide port of GTY to perform bit-level shifting on the data until CNT is equal to 0. At this time, CNT is equal to 0, the control module switches the data sent by the data sending chip to the test PATTERN, and reads whether the output data from the counting module is PATTERN, if not, continue to perform bit-level shifting until the output is the correct test PATTERN, thus, the synchronization is completed.

[0051] It can be understood that the method is aimed at providing stable synchronous data for subsequent data processing, and improving the reliability and correctness of the post-processing module. The core process is: first, the data sending chip is configured to output PRBS11 (period 2047) data, a main channel is selected from N channels, and the offset CNT of each slave channel and the main channel is calculated; when CNT≥64, byte-level shifting is performed to CNT<64 by controlling FIFO write empty, if CNT≠0, bit-level shifting is performed to CNT=0 by means of the RXSLIDE function of xxFPGA; then, the low 16 bits of the data sending chip output are switched to the specified PATTERN of 0xABCD, and the low 16 bits of the data output by each channel FIFO are verified to be consistent, that is, the synchronization is successful. In the method, the number of channels N can be configured (default 16), the data bit width of each channel is 64 bits, the related parameters and clock frequency can be flexibly adjusted, N (N>0) channel synchronization operations are supported, it is suitable for different clock and channel number scenes, and has good downward compatibility and expansion capability.

[0052] It should be understood that, although Figure 1The steps in the flowchart are shown in sequence according to the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the steps are not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, Figure 1 At least part of the steps in the flowchart can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or sub-steps or stages of other steps.

[0053] In one embodiment, a FPGA-based chip high-speed interconnection multi-channel data synchronization system is provided, comprising:

[0054] The data sending end and the FPGA; the FPGA includes a plurality of high-speed receiving modules, a plurality of cache modules, a shift control module and a counting module;

[0055] The data sending end is configured to output multiple parallel reference test data, and switch to output preset verification data;

[0056] The high-speed receiving module is connected to the data sending end, configured to receive multiple parallel data and transmit the data to the corresponding cache module;

[0057] The cache module is configured to store the received data of the corresponding channel and perform byte-level shift adjustment in response to the control of the shift control module;

[0058] The counting module is configured to take the data stored in the cache module corresponding to the master channel as a reference, calculate the offset of the data stored in the cache module corresponding to each slave channel, and feed back the offset to the shift control module;

[0059] The shift control module is configured to receive the control data of each slave channel in real time, control the corresponding cache module to perform byte-level shift adjustment when the offset is greater than or equal to a first threshold, control the corresponding high-speed receiving module to perform bit-level fine shift adjustment when the offset is less than the first threshold, and adjust until the offset meets the synchronization threshold;

[0060] When the data output by the cache modules corresponding to all channels are consistent with the preset verification data, the multi-channel synchronization is completed.

[0061] The specific definition of the FPGA-based chip high-speed interconnection multi-channel data synchronization system can refer to the definition of the FPGA-based chip high-speed interconnection multi-channel data synchronization method, which will not be repeated here. Each module in the FPGA-based chip high-speed interconnection multi-channel data synchronization system can be realized by software, hardware, and a combination thereof, in whole or in part. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0062] Each technical feature of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of each technical feature in the above embodiments are not described, but as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0063] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the application. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for FPGA-based chip high-speed interconnection multi-channel data synchronization, characterized in that, The method comprises: The method comprises: The method comprises: When the offset is greater than or equal to the first threshold, the corresponding cache module is controlled by the shift control module to perform byte-level shift adjustment; When the offset is less than the first threshold, the corresponding high-speed receiving module is controlled by the shift control module to perform bit-level fine shift adjustment until the offset meets the synchronization threshold; The data sending end outputs preset verification data, and when the output data of the cache modules corresponding to each channel are all consistent with the verification data, multi-channel synchronization is completed.

2. The method of claim 1, wherein, The data sending end outputs preset verification data, and when the output data of the cache modules corresponding to each channel are all consistent with the verification data, multi-channel synchronization is completed. The data sending end outputs preset verification data, and when the output data of the cache modules corresponding to each channel are all consistent with the verification data, multi-channel synchronization is completed. The method further comprises:

3. The method of claim 1, wherein, After multi-channel synchronization is completed, a service mode switching instruction is sent to the data sending end by the shift control module to control the data sending end to switch back to a service data output mode; The cache modules corresponding to each channel output service data according to the synchronized timing. The method further comprises: The shift control module outputs read-write control signals to the corresponding cache module according to the offset value fed back by the counting module; 4. The method of claim 1, wherein, The cache module responds to the read-write control signals to perform a read-empty or write-empty operation, and gradually reduces the offset by adjusting the timing interval of data storage and output. The shift control module outputs read-write control signals to the corresponding cache module according to the offset value fed back by the counting module; The cache module responds to the read-write control signals to perform a read-empty or write-empty operation, and gradually reduces the offset by adjusting the timing interval of data storage and output.

5. The method of claim 1, wherein, ​ ​ ​ 6. The method of claim 1, wherein, ​ The shift control module sends a shift instruction to the high-speed receiving module according to the offset fed back by the counting module, controls the RXSLIDE shift function built in the high-speed receiving module to adjust the data receiving timing bit by bit, and the shift step is 1 bit each time until the counting module detects that the offset decreases to a synchronization threshold.

7. The method of claim 1, wherein, The reference test data is a pseudo-random sequence; the pseudo-random sequence includes PRBS11, which is used to provide a stable and repeatable comparison reference for the counting module to calculate the offset.

8. A multi-channel data synchronization system based on FPGA chip high-speed interconnection, characterized in that, The system includes a data sending end and an FPGA; the FPGA includes a plurality of high-speed receiving modules, a plurality of cache modules, a shift control module, and a counting module. The data sending end is configured to output multiple parallel reference test data and switch to output preset verification data. The high-speed receiving module is connected with the data sending end, and is configured to receive the multiple parallel data and transmit the data to the corresponding cache module. The cache module is configured to store the received data of the corresponding channel and perform byte-level shift adjustment in response to the control of the shift control module. The counting module is configured to take the data stored in the cache module corresponding to the master channel as a reference, calculate the offset of the data stored in the cache module corresponding to each slave channel, and feed back the offset to the shift control module. The shift control module is configured to receive the control amount data of each slave channel in real time, control the corresponding cache module to perform byte-level shift adjustment when the offset is greater than or equal to a first threshold, control the corresponding high-speed receiving module to perform bit-level fine shift adjustment when the offset is less than the first threshold, and stop until the offset meets a synchronization threshold. When the data output by the cache modules corresponding to all channels are consistent with the preset verification data, the multi-channel synchronization is completed.

9. The system of claim 8, wherein, The high-speed receiving module is built-in RXSLIDE shift function, and the shift control module is signal connected with the high-speed receiving module. The shift control module sends a shift instruction to the high-speed receiving module according to the real-time offset fed back by the counting module, controls the RXSLIDE shift function to adjust the data receiving timing bit by bit, and the shift step is 1 bit each time.

10. The system of claim 8, wherein, The preset verification data is a fixed numerical combination, and the low 16-bit data is 0xABCD.

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