RC ring oscillation circuit, and self-adaption-based RC ring oscillation circuit PVT compensation method and device

Abstract

The invention belongs to the technical field of electronic circuits, and provides an RC ring oscillation circuit and a self-adaption-based RC ring oscillation circuit PVT compensation method and device.The RC ring oscillation circuit comprises a ring oscillation body, the ring oscillation body comprises a plurality of inverter units, and each inverter unit comprises a second type of device; the reference voltage generation module comprises a first type of device, and the first type of device has a matching relation with the phase inverter unit and is used for generating a reference voltage; the input end of the low-dropout linear regulator is connected with the output end of the reference voltage generation module, and the output end of the low-dropout linear regulator is connected with the ring oscillator main body; wherein the reference voltage generated by the reference voltage generation module changes along with the process corner, the power supply voltage and the temperature PVT of the ring oscillator main body, the low dropout linear regulator generates the power supply voltage based on the reference voltage and provides the power supply voltage to the ring oscillator main body, so that the characteristics of the second type device are adaptive to the change of the PVT, and the sensitivity of the output frequency of the ring oscillator main body to the PVT is reduced.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and more specifically, relates to an RC ring resonator circuit, an adaptive RC ring resonator circuit PVT compensation method and device. Background Technology

[0002] Due to its simple structure, low power consumption, and small area, the RC ring oscillator circuit is widely used in IoT devices, system clocks and sleep clocks of low-power chips, and is a key timing generation unit in integrated circuits.

[0003] However, as semiconductor processes evolve towards advanced nodes, process corner deviations, power supply voltage fluctuations (such as voltage decay when powered by battery), and operating temperature variations (-40℃ to 125℃ industrial-grade range) significantly affect the output frequency of the RC ring oscillator: when the process corner is Slow, the driving capability of the MOSFET weakens and the resistance value increases, resulting in a frequency reduction of 20% to 30%; when the temperature rises or the voltage fluctuates, the threshold voltage and carrier mobility of the MOSFET change, further aggravating the frequency offset, which cannot meet the system's clock accuracy requirements.

[0004] Existing solutions have significant drawbacks: some solutions adjust the RC range by integrating temperature / voltage sensors and digital calibration circuits, but this adds 15%~30% to the chip area and 20%~40% to the static power consumption, and the calibration algorithm is highly complex; some solutions use a fixed bandgap reference power supply, which reduces voltage sensitivity but cannot match the changes in device characteristics caused by process corners and temperature, resulting in limited compensation effects. Furthermore, existing technologies lack precise matching design between the core components of the ring oscillator (inverter MOSFET, load resistor) and the reference device, leading to asynchronous changes in the reference voltage and the characteristics of the ring oscillator, making efficient PVT compensation difficult to achieve. Summary of the Invention

[0005] The purpose of this application is to provide an RC ring resonator circuit, an adaptive RC ring resonator circuit PVT compensation method and device, which aims to solve the technical problem in the related art that the reference voltage change and the characteristic change of the ring resonator are not synchronized, making it difficult to achieve efficient PVT compensation.

[0006] To achieve the above objectives, according to a first aspect of this application, an RC ring resonator circuit is provided, the RC ring resonator circuit comprising: A ring resonator body, the ring resonator body comprising a plurality of inverter units, each of the inverter units comprising a second type of device; A reference voltage generation module, comprising a first type of device, which has a matching relationship with the inverter unit, for generating a reference voltage; A low-dropout linear regulator, wherein the input terminal of the low-dropout linear regulator is connected to the output terminal of the reference voltage generation module, and the output terminal is connected to the ring resonator body; The reference voltage generated by the reference voltage generation module varies with the process angle, power supply voltage, and temperature PVT of the ring resonator. The low dropout linear regulator generates a power supply voltage based on the reference voltage and provides it to the ring resonator, so that the characteristics of the second type of device adapt to the changes in PVT, thereby reducing the sensitivity of the output frequency of the ring resonator to PVT.

[0007] According to a second aspect of this application, an adaptive RC ring resonator circuit PVT compensation method is provided, the method comprising: A reference voltage is generated for an RC ring resonator circuit using a first type of device, wherein the first type of device has a matching relationship with the inverter unit of the RC ring resonator circuit; The reference voltage is input to the low dropout linear regulator, which generates a supply voltage and provides the supply voltage to the RC ring circuit. By varying the reference voltage with the process angle, power supply voltage, and temperature PVT of the RC ring resonator circuit, the characteristics of the second type of device in the RC ring resonator circuit adapt to the changes in PVT, thereby reducing the sensitivity of the output frequency of the RC ring resonator circuit to the PVT.

[0008] According to a third aspect of this application, an adaptive RC ring resonator circuit PVT compensation device is provided, the device comprising: The first generation unit is used to generate a reference voltage for the RC ring resonator circuit using a first type of device, wherein the first type of device has a matching relationship with the inverter unit of the RC ring resonator circuit. The second generation unit is used to input the reference voltage to the low dropout linear regulator, so that the low dropout linear regulator generates a supply voltage and provides the supply voltage to the RC ring circuit. An adaptive unit is used to adapt the characteristics of the second type of device in the RC ring resonator circuit to the changes in PVT by varying the reference voltage with the process angle, power supply voltage, and temperature PVT of the RC ring resonator circuit, thereby reducing the sensitivity of the output frequency of the RC ring resonator circuit to the PVT.

[0009] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides an RC ring resonator circuit, comprising: a ring resonator body containing multiple inverter units, each inverter unit including a second type of device; a reference voltage generation module including a first type of device, which is matched with the inverter units to generate a reference voltage; and a low-dropout linear regulator, the input of which is connected to the output of the reference voltage generation module, and the output of which is connected to the ring resonator body. The reference voltage generated by the reference voltage generation module varies with the process angle, power supply voltage, and temperature voltage variation (PVT) of the ring resonator body. The low-dropout linear regulator generates a power supply voltage based on the reference voltage and provides it to the ring resonator body, enabling the characteristics of the second type of device to adapt to changes in PVT, thereby reducing the sensitivity of the ring resonator body's output frequency to PVT. This aims to solve the technical problem in related technologies where the reference voltage change and the characteristic change of the ring resonator devices are not synchronized, making it difficult to achieve efficient PVT compensation. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1a This is a schematic diagram of an existing RC ring resonator circuit; Figure 1b This is a schematic diagram of another existing RC ring resonator circuit; Figure 2 This is a schematic diagram of an RC ring resonator circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of an optional RC ring resonator circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of an optional RC ring resonator circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram of an optional operational amplifier provided in an embodiment of this application; Figure 6 This is a schematic flowchart of an adaptive RC ring resonator circuit PVT compensation method provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an adaptive RC ring resonator circuit PVT compensation device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0013] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0014] It should also be understood that, in the description of this application, unless otherwise stated, the " / " used in the specification and appended claims indicates that the related objects are in an "or" relationship. For example, A / B can mean A or B. The "and / or" in this application is merely a description of the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0015] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, but are only used for distinguishing descriptions, and the terms "first" and "second" do not necessarily imply that they are different, nor should they be construed as indicating or implying relative importance.

[0016] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0017] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0018] First, some terms used in the embodiments of this application will be explained to facilitate understanding by those skilled in the art.

[0019] PVT stands for Process-Voltage-Temperature, a collective term for three core environmental factors affecting circuit performance stability during chip design and operation. P (Process) refers to process variations during chip manufacturing. V (Voltage) refers to fluctuations in the supply voltage during chip operation. Changes in supply voltage affect the charging and discharging speed of MOSFETs, causing a shift in the output frequency of the ring oscillator circuit, requiring additional circuitry for detection and calibration. T (Temperature) refers to temperature changes caused by the chip's operating environment or its own heat generation. Increased or decreased temperature alters the characteristics of semiconductor devices, also causing a shift in the output frequency of the ring oscillator circuit, increasing calibration costs.

[0020] The process corner refers to the range of extreme deviations in the characteristics of a MOSFET (such as carrier mobility and threshold voltage) caused by variations in materials, equipment, and environment during chip manufacturing. It is a specific manifestation of process (P) factors.

[0021] The reference supply voltage vdd_ref is a power supply voltage signal that provides a stable reference for the circuit. In the RC ring oscillator circuit, it is used to counteract the effects of PVT variations.

[0022] The above is a brief introduction to the terms used in the embodiments of this application, and will not be repeated below.

[0023] Among related technologies, RC ring oscillators are widely used in timing-related fields, such as system clocks and sleep clocks, due to their low power consumption and small area. As manufacturing processes become more advanced and product cost competition intensifies, clock applications are placing demands on the performance and cost of RC ring oscillators, aiming to achieve RC ring oscillators with better temperature and voltage coefficients at the cost of lower power consumption and smaller area.

[0024] like Figure 1a This is an existing RC ring oscillator circuit, where R0=R1=R, controlling the charging and discharging speed of capacitor C, thereby controlling the RC oscillation frequency. M0 and M1 act as selection switches for charging and discharging, where M0 is a PMOS transistor (P-type metal-oxide-semiconductor field-effect transistor) and M1 is an NMOS transistor (N-type metal-oxide-semiconductor field-effect transistor). The output frequency of this RC oscillator circuit is 1 / (R+Ron) / C, where R is the resistance value of the inverter connected in series, Ron is the on-resistance of the inverter MOS transistor, and C is the load capacitance of the inverter.

[0025] When the inverter input is a step signal from low to high, the NMOS transistor slowly turns on and the PMOS transistor slowly turns off. During this process, the NMOS transistor operates in the saturation region, and the discharge current of the inverter load capacitor is approximately vin / (R+1 / gm), where vin is the inverter input voltage and gm is the inverter transient admittance, inversely proportional to the MOSFET's vgs-vth. As the power supply voltage changes, the MOSFET's vgs changes accordingly, and the MOSFET's gm changes, causing a change in the charging current, which in turn affects the charging and discharging speed, thus affecting the maximum efficiency. The final ring oscillation frequency; when the temperature changes, vgs-vth changes (the difference between the gate-source voltage and the threshold voltage of the MOSFET; the magnitude of vgs-vth represents the driving capability of the MOSFET; the larger the voltage difference, the stronger the MOSFET driving capability, and the smaller the voltage difference, the weaker the MOSFET driving capability). The change in the MOSFET driving capability affects the charging and discharging speed, and ultimately affects the ring oscillation frequency. The process angle also affects the MOSFET driving capability, making the influence of the process angle on the output frequency of the RCRC ring oscillation circuit greater than the change caused by the process angle itself.

[0026] For the reasons mentioned above, resistors and capacitors are typically adjusted to different levels. When the PVT changes, the frequency can be adjusted back to the target value by adjusting the RC. However, since the adjustment of the RC must not only follow the changes in process angle, but also the changes in power supply voltage and temperature, it is necessary to monitor the power supply voltage and temperature in real time. This introduces additional monitoring circuitry, which increases the circuit cost and the complexity of the digital algorithm implementation.

[0027] In addition, such as Figure 1bThis is a ring oscillator circuit that uses a current source to charge and discharge a capacitor, thus creating oscillation. Ib is the unit that provides current to the loop. M0~M4 are PMOS transistors, M1~M5 are NMOS transistors, and M0&M1, M2&M3, and M4&M5 form three sets of inverters. C is the load capacitor of the inverters, and current charges and discharges C through the inverters. When the temperature rises, the Vgs of the inverter MOS transistors decreases, and the frequency increases; when the temperature decreases, the Vgs of the inverter MOS transistors increases, and the frequency decreases. Similarly, at the slow process corner, the Vgs of the MOS transistors increases, and the frequency decreases; at the fast process corner, the Vgs of the MOS transistors decreases, and the frequency increases. It can be seen that although this ring oscillator circuit reduces the sensitivity to power supply voltage through a current source, the MOS transistors are still very sensitive to temperature and process corner changes.

[0028] To address the aforementioned technical problems, this application provides an example of an RC ring resonator circuit, please refer to... Figure 2 As shown, Figure 2 A schematic structural diagram of an RC ring resonator circuit provided in this application is shown. The RC ring resonator circuit 200 includes: The ring resonator body 201 contains multiple inverter units, each of which includes a second type of device.

[0029] The reference voltage generation module 202 includes a first type of device that is matched with the inverter unit and is used to generate a reference voltage.

[0030] The low dropout linear regulator 203 has its input terminal connected to the output terminal of the reference voltage generation module and its output terminal connected to the ring resonator body. The reference voltage generated by the reference voltage generation module varies with the process angle, power supply voltage, and temperature PVT of the ring resonator. The low dropout linear regulator generates a power supply voltage based on the reference voltage and provides it to the ring resonator, so that the characteristics of the second type of device adapt to the changes in PVT, thereby reducing the sensitivity of the output frequency of the ring resonator to PVT.

[0031] The RC ring resonator circuit of the present invention will be described in detail below with reference to a specific circuit structure. This embodiment is intended to enable those skilled in the art to clearly understand the circuit composition, working principle, and PVT adaptive compensation mechanism. The output frequency of the RC ring resonator circuit provided in this application embodiment is almost unaffected by process angle, temperature, and voltage, reducing calibration costs and power consumption, and also reducing the area of ​​the RC ring resonator circuit.

[0032] In this embodiment, the RC ring resonator circuit mainly comprises the following three parts: the ring resonator body, the reference voltage generation module, and the low dropout linear regulator (LDO). The specific composition and connection relationship of each part are as follows: The ring oscillator body may, but is not limited to, consist of an odd number of inverter units connected in series (e.g., 5 or 7 inverter stages to ensure oscillation phase conditions are met). Each inverter unit contains a second type of device, specifically including: a pair of complementary driving MOSFETs (PMOS and NMOS, used to invert the signal), a load resistor connected in series in the MOSFET path (used to regulate the charge and discharge rate), and a load capacitor connected in parallel at the inverter output (used to store charge and determine the oscillation period). The output of the inverter unit is connected to the input of the next stage inverter, and the output of the last stage inverter is fed back to the input of the first stage inverter, forming a closed oscillation loop.

[0033] The reference voltage generation module generates a reference voltage (Vdd_ref) that varies with the PVT. Its core is a type-one device. This type-one device has a strict matching relationship with the inverter unit of the ring oscillator: specifically, if the driving MOSFET of the inverter unit is an NMOS (width / length ratio of W / L), then the MOSFET in the type-one device is also an NMOS of the same type, and its width / length ratio is fixed to that of the inverter MOSFET (e.g., 1:4, ensuring consistent characteristic trends). If the inverter unit includes a negative temperature resistor (polysilicon material), then the resistor in the type-one device is also a negative temperature resistor of the same material, and its resistance value is fixed to that of the inverter resistor (e.g., 1:2, ensuring synchronization of temperature coefficient and process deviation). The type-one devices form a voltage output node through series connection or a specific topology (e.g., a diode-connected MOSFET in series with a resistor). This voltage output node is the output terminal of the reference voltage Vdd_ref.

[0034] A low-dropout linear regulator (LDO) serves as the voltage regulation unit between the reference voltage and the ring resonator. The LDO's input is directly connected to the output of the reference voltage generation module (receiving Vdd_ref), and its output is connected to the power supply terminal of the ring resonator (providing the supply voltage V_ro). Internally, the LDO contains an error amplifier, a regulating transistor, and a feedback network. By dynamically adjusting the on-resistance of the regulating transistor, the output voltage V_ro always tracks the changes in the reference voltage Vdd_ref, maintaining a constant voltage difference between them (e.g., a fixed voltage difference of 0.3V, i.e., V_ro = Vdd_ref + 0.3V). This ensures that the supply voltage to the ring resonator adaptively adjusts with the reference voltage.

[0035] In some embodiments, the matching relationship between the first type of device and the inverter unit is a core prerequisite for achieving PVT adaptation, specifically reflected in the following three aspects: Process consistency specifically refers to the use of the same semiconductor process for the first type of device and the second type of device in the inverter unit (such as the same batch of CMOS processes), ensuring that the inherent deviations in their material parameters (such as silicon wafer doping concentration and gate oxide thickness) and device models (such as MOS transistor threshold voltage Vth and carrier mobility μ) are consistent. For example, if the NMOS transistor in the inverter has a higher Vth due to process deviation, the NMOS transistor in the first type of device will also exhibit a higher Vth characteristic simultaneously.

[0036] The structural parameter ratio specifically refers to the fixed ratio between the key structural parameters (such as the width-to-length ratio of MOSFETs and the resistance value) of the first type of devices and the second type of devices. Taking MOSFETs as an example, if the width-to-length ratio of the driving NMOS transistor in the inverter is 40μm / 1μm, then the width-to-length ratio of the NMOS transistor in the first type of device can be 10μm / 1μm (ratio 1:4), ensuring that the transconductance (gm) of both is proportional to the change in PVT (e.g., when the temperature rises, the gm of both increases by 20%). For resistors, if the load resistor in the inverter is 20kΩ, then the resistance value of the resistor in the first type of device can be 10kΩ (ratio 1:2), ensuring that the resistance value changes synchronously due to temperature or process (e.g., when the temperature rises by 100℃, the resistance value of both decreases by 20%).

[0037] Layout symmetry specifically refers to the symmetrical layout (e.g., common-center symmetry, parallel arrangement) of the first type of devices and the second type of devices in the inverter unit within the chip layout design, located in the same chip area, to avoid characteristic differences caused by local wafer process deviations (such as edge effects, temperature gradients). For example, the wiring length and metal layer thickness of the MOSFETs in the first type of devices and the MOSFETs in the inverter are exactly the same, and the parasitic resistance and capacitance have the same effect on both.

[0038] In some embodiments, the Vdd_ref generated by the reference voltage generation module is adaptively adjusted according to the PVT changes of the ring resonator. The supply voltage V_ro of the ring resonator is adjusted by the LDO, ultimately causing the characteristic changes of the second type of device to cancel each other out, reducing the sensitivity of the output frequency to PVT. The specific process is as follows: Firstly, regarding compensation for power supply voltage variations, when the system's main power supply voltage (VDD) fluctuates within the design range (e.g., 1.6V~2.0V), the first type of devices in the reference voltage generation module are powered by a temperature-controlled bias current source (whose current value is unaffected by VDD, such as being provided by a bandgap reference circuit). For the MOSFETs in the first type of devices, their gate-source voltage VGS is determined solely by the temperature-controlled current and their own characteristics (Vth, μ, width-to-length ratio) (satisfying VGS=Vth+√(2I / (μCox(W / L)))), and is independent of VDD; for the resistors in the first type of devices, their voltage is determined by the temperature-controlled current and their resistance value (V_R=I×R), and is similarly unaffected by VDD fluctuations. Therefore, Vdd_ref (such as the sum of VGS or the sum of V_R and VGS) remains stable, the V_ro output by the LDO is synchronously stable, the operating voltage of the second type of devices in the ring oscillator is unaffected by VDD changes, the charging and discharging speed is constant, and the output frequency has no offset.

[0039] Secondly, regarding compensation for temperature changes, when the temperature rises (e.g., from 25℃ to 125℃): in the second type of device of the inverter unit, the Vth of the MOS transistor decreases (e.g., the Vth of the NMOS transistor decreases from 0.7V to 0.5V), resulting in an increase in VGS-Vth, enhanced driving capability (transconductance gm), and a tendency for the charging and discharging speed to increase (frequency tends to increase); if a negative temperature resistor is included, its resistance decreases with increasing temperature (e.g., from 20kΩ to 16kΩ), further accelerating the charging and discharging speed. At this point, because the first type of device is matched with the second type of device, the Vth of its MOSFET decreases synchronously, VGS decreases, and the resistance value decreases synchronously, resulting in a decrease in Vdd_ref (e.g., from 1.0V to 0.8V); the V_ro output of the LDO decreases synchronously (e.g., from 1.3V to 1.1V), causing the VGS of the inverter MOSFET to decrease (counteracting the increasing trend of VGS-Vth), weakening the driving capability. At the same time, the actual operating voltage of the negative temperature resistor decreases (counteracting the effect of the decreased resistance value), ultimately stabilizing the charging and discharging speed, and the output frequency of the RC ring oscillator circuit does not change significantly. When the temperature decreases, the above process reverses: Vdd_ref increases, V_ro increases, enhancing the driving capability of the MOSFET and counteracting the effect of the increased resistance value, and the output frequency of the RC ring oscillator circuit remains stable.

[0040] Thirdly, regarding compensation for process angle changes, when the process angle is Slow (device characteristics are slower): In the second type of devices in the inverter unit, the Vth of the MOSFET increases (e.g., the Vth of the NMOS increases from 0.7V to 0.9V), μ decreases, the driving capability weakens, and the charging and discharging speed slows down (frequency is prone to decrease); the resistance increases due to process deviation (e.g., from 20kΩ to 24kΩ), further slowing down the charging and discharging speed. At this time, because the first type of devices are matched with the second type of devices, the Vth of their MOSFETs increases synchronously, VGS increases, and the resistance increases synchronously, resulting in an increase in Vdd_ref (e.g., from 1.0V to 1.2V); the V_ro output of the LDO increases synchronously (e.g., from 1.3V to 1.5V), causing the VGS of the inverter MOSFET to increase (offsetting the decreasing trend of VGS-Vth), enhancing the driving capability, and at the same time, the actual operating voltage of the resistor increases (offsetting the effect of the increased resistance), and finally the charging and discharging speed returns to the typical level, and the output frequency of the RC ring oscillator circuit stabilizes. When the process corner is Fast (device characteristics are relatively fast), the above process is reversed: Vdd_ref decreases, V_ro decreases, weakening the driving capability of the MOS transistor and offsetting the effect of the reduced resistor value, so that the output frequency of the RC ring oscillator circuit remains stable.

[0041] As can be seen from the above embodiments, the RC ring oscillator circuit provided in this application, through the matching design of the first type of device and the inverter unit, enables the reference voltage to adapt to the PVT change, and adjusts the power supply voltage of the ring oscillator body through the LDO, ultimately achieving dynamic compensation of the characteristics of the second type of device, significantly reducing the sensitivity of the output frequency to PVT changes, and is suitable for integrated circuit scenarios that are sensitive to clock accuracy, power consumption and area.

[0042] In one possible implementation, the first type of device includes a first MOS transistor and a second MOS transistor that are matched with each other. Both the first MOS transistor and the second MOS transistor are connected in a diode manner and are connected in series to form the core branch in the reference voltage generation module. The reference voltage is the sum of the gate-source voltage of the first MOS transistor and the gate-source voltage of the second MOS transistor.

[0043] In this embodiment, the first type of device in the reference voltage generation module uses a matched first MOSFET and a second MOSFET, connected in series with a diode to form the core branch, generating a reference voltage that adaptively changes with PVT, thereby achieving PVT compensation for the ring oscillation body. The circuit structure, matching relationship, and compensation mechanism are described in detail below: like Figure 3As shown, the reference voltage generation module consists of a constant current source Ib (which can be set to the nA or μA level according to power consumption and minimum operating voltage requirements; the larger the current, the higher the reference supply voltage and the stronger the MOS transistor driving capability; conversely, the lower and weaker the current, the weaker the driving capability), a PMOS transistor M0, and an NMOS transistor M1. M0 and M1 are connected by diodes (gate and drain shorted), and Ib flows through them to form the reference voltage vdd_ref (which is the sum of the gate-source voltage of M0 and the gate-source voltage of M1).

[0044] The input of a low-dropout linear regulator (LDO) is a non-driven voltage vdd_ref, and the output is a driven voltage vout, which powers the ring oscillator. The ring oscillator consists of three sets of inverter units. Each inverter set contains PMOS transistors M2 / M4 / M6 (size N times that of M0, where N is any natural number, including decimals and integers) and NMOS transistors M3 / M5 / M7 (size N times that of M1), and an external load capacitor C. M2 and M3, M4 and M5, and M6 and M7 form inverters, respectively. The LDO output voltage oscillates by charging and discharging capacitor C through the inverters.

[0045] The characteristics of Ib, M0, and M1 ensure that vdd_ref is unaffected by fluctuations in the power supply voltage Vdd, the LDO output vout remains synchronously stable, the ring oscillation supply voltage is constant, and the frequency remains unchanged. When the temperature rises, vgs-vth of M2~M7 would normally increase, strengthening their driving capability and causing the frequency to rise; however, vdd_ref of M0 and M1 decreases synchronously, causing vgs-vth of M2~M7 to decrease and their driving capability to weaken, with negative feedback offsetting the frequency increase trend. When the temperature decreases, the opposite adjustment occurs, and the final frequency remains almost unchanged. When the process angle slows down, the driving capability of M0~M7 weakens, and vdd_ref increases, offsetting the frequency slowdown caused by the weakened driving capability of M2~M7; when the process angle speeds up, vdd_ref decreases, offsetting the frequency speedup caused by the strengthened driving capability of M2~M7, significantly reducing the impact of the process angle on the frequency.

[0046] The first MOSFET (M1) is a PMOS transistor, and the second MOSFET (M2) is an NMOS transistor. They are complementary types and use the same manufacturing process (e.g., 180nm CMOS). Both M1 and M2 are connected in a diode configuration, with the gate and drain of M1 shorted, and the gate and drain of M2 shorted, creating a diode-like voltage-current characteristic (the voltage during forward conduction is the gate-source voltage VGS). The two transistors are connected in series to form the core branch of the reference voltage generation module: the source of M1 is connected to the system's main power supply voltage VDD (e.g., 1.8V), and the drain (gate) of M1 is connected to the drain (gate) of M2, forming the voltage output node (i.e., the output terminal of the reference voltage Vdd_ref); the source of M2 is grounded (GND). A constant-temperature bias current source (I_bias, typical output current 20μA) is connected in series in the core branch. This current source is provided by the bandgap reference circuit, and its output current is unaffected by changes in VDD, temperature, and process angle, ensuring a constant current flowing through M1 and M2.

[0047] In some embodiments, the ring oscillator body consists of 5 inverter units connected in series (odd-numbered stages ensure oscillation). The second type of device in each inverter unit includes: a pair of complementary drive transistors (PMOS transistor M11 and NMOS transistor M12, serving as the core switching devices of the inverter) and a load capacitor C (typically 5pF) connected in parallel at the output terminal. Among them, M11 and the first MOS transistor M1 are the same type of PMOS, and M12 and the second MOS transistor M2 are the same type of NMOS.

[0048] In some embodiments, the first MOSFET M1, the second MOSFET M2, and the inverter units M11 and M12 must meet a strict matching relationship to ensure that the impact of PVT changes on the two types of devices is synchronized. Specifically, this includes: Firstly, there is process consistency; M1 and M2 use the same wafer batch process parameters as M11 and M12 (e.g., the gate oxide layer thickness is 3nm, and the PMOS doping concentration is 1e17cm). -3 This ensures that the inherent deviations of the threshold voltage Vth and carrier mobility μ are consistent (for example, if Vth of M1 is 0.1V higher due to process deviation, then Vth of M11 will also be 0.1V higher).

[0049] Secondly, the width-to-length ratio is fixed between M1 and M11 (typically 1:4), and the width-to-length ratio between M2 and M12 is also 1:4. For example, if the W / L of M1 is 10μm / 1μm, then the W / L of M11 is 40μm / 1μm. This ratio design ensures that the transconductance gm of both (proportional to W / L) changes synchronously with the PVT (e.g., when the temperature increases, if the gm of M1 increases by 20%, the gm of M11 also increases by 20%).

[0050] Third, layout symmetry: M1, M2 and M11, M12 are arranged symmetrically in the chip layout. All four are located on the same metal layer, with a wiring length of 50μm and a spacing of 2μm, avoiding characteristic differences caused by local process deviations (such as uneven doping in edge areas).

[0051] There are also some embodiments regarding the generation principle of the reference voltage. The reference voltage Vdd_ref is generated by superimposing the gate-source voltage (VGS1) of the first MOSFET M1 and the gate-source voltage (VGS2) of the second MOSFET M2, that is, Vdd_ref = VGS1 + VGS2. Its value is determined by the isothermal current I_bias and the inherent characteristics of the two transistors. For PMOS transistor M1 (diode-connected), its gate-source voltage VGS1 = |Vth1| + √(2I_bias / (μ_pCox(W1 / L1))), where Vth1 is the threshold voltage (absolute value) of M1, μ_p is the hole mobility of the PMOS, Cox is the oxide capacitance, and W1 / L1 is the width-to-length ratio of M1. For NMOS transistor M2 (diode-connected), its gate-source voltage VGS2 = Vth2 + √(2I_bias / (μ_nCox(W2 / L2))), where Vth2 is the threshold voltage of M2, μ_n is the electron mobility of the NMOS, and W2 / L2 is the width-to-length ratio of M2. Since I_bias is constant, VGS1 and VGS2 are determined only by Vth, μ, and the width-to-length ratio of the two transistors. Therefore, the change in Vdd_ref only reflects the characteristic changes of the two transistors caused by PVT, providing an accurate reference for subsequent compensation.

[0052] In some embodiments, regarding compensation for power supply voltage variations, when the system main power supply VDD fluctuates from 1.6V to 2.0V, the isothermal bias current source I_bias maintains a constant current flowing through M1 and M2. According to the expressions for VGS1 and VGS2, their values ​​are independent of VDD (determined only by the device's inherent parameters and I_bias), therefore Vdd_ref remains stable (typically 1.0V). The low-dropout linear regulator (LDO) uses Vdd_ref as a reference, outputting a supply voltage V_ro (V_ro = Vdd_ref + 0.3V = 1.3V), which is unaffected by VDD fluctuations. The VGS of M11 and M12 in the ring resonator is determined by V_ro, thus ensuring stable charging and discharging currents and no output frequency shift.

[0053] In some embodiments, regarding compensation for temperature changes, when the temperature rises from 25°C to 125°C: the |Vth11| of M11 (PMOS) in the inverter decreases (from 0.7V to 0.5V), μ_p increases by 15%, and the driving capability is enhanced; the Vth12 of M12 (NMOS) decreases (from 0.7V to 0.5V), μ_n increases by 15%, the driving capability is enhanced, the charging and discharging speed is accelerated, and the output frequency of the RC ring resonator circuit is easily increased by 15%~20%.

[0054] Simultaneously, in the first type of device, |Vth1| of M1 decreases synchronously, μ_p increases synchronously, and VGS1 drops from 0.5V to 0.45V; Vth2 of M2 decreases synchronously, μ_n increases synchronously, and VGS2 drops from 0.5V to 0.45V, thus Vdd_ref drops to 0.9V. The V_ro output of the LDO drops synchronously to 1.2V, causing both VGS11 of M11 and VGS12 of M12 to decrease (e.g., from 0.6V to 0.5V), offsetting the increasing trend of VGS-Vth, restoring the driving capability to the room temperature level, stabilizing the charging and discharging speed, and showing no significant change in the output frequency of the RC ring resonator circuit.

[0055] When the temperature drops from 25℃ to -40℃, the above process is reversed: Vdd_ref increases to 1.1V and V_ro increases to 1.4V, enhancing the driving capability of M11 and M12, offsetting the effect of weakened driving capability at low temperature, and keeping the output frequency of the RC ring resonator circuit stable.

[0056] In other embodiments, regarding compensation for process angle variations: When the process angle is Slow (device characteristics are slower): In the inverter, |Vth11| of M11 increases (from 0.7V to 0.9V), μ_p decreases by 20%, and the driving capability weakens; Vth12 of M12 increases (from 0.7V to 0.9V), μ_n decreases by 20%, the driving capability weakens, the charging and discharging speed slows down, and the output frequency of the RC ring oscillator circuit is prone to decrease by 20%~25%. Simultaneously, in the first type of device, |Vth1| of M1 increases synchronously, μ_p decreases synchronously, and VGS1 increases from 0.5V to 0.6V; Vth2 of M2 increases synchronously, μ_n decreases synchronously, and VGS2 increases from 0.5V to 0.6V, therefore Vdd_ref increases to 1.2V. The LDO output V_ro synchronously rises to 1.5V, which increases both VGS11 of M11 and VGS12 of M12 (e.g., from 0.6V to 0.7V), offsetting the decreasing trend of VGS-Vth, restoring the driving capability to the level of a typical process corner, and stabilizing the output frequency of the RC ring resonator circuit.

[0057] When the process corner is Fast (device characteristics are too fast), the above process when the process corner is Slow is reversed: Vdd_ref is reduced to 0.8V and V_ro is reduced to 1.1V, the driving capability of M11 and M12 is weakened, the effect of excessive driving capability under Fast process corner is offset, and the output frequency of RC ring resonator circuit remains stable.

[0058] In summary, this implementation method forms a core branch by connecting a first MOSFET and a second MOSFET that are matched with each other in series. The reference voltage that adapts to the PVT is generated by superimposing the gate-source voltages of the two transistors. Then, the power supply voltage of the ring oscillator body is adjusted by the LDO, so that the driving capability of the MOSFET in the inverter cancels out the PVT change in the opposite direction, which significantly reduces the sensitivity of the ring oscillator output frequency to the PVT.

[0059] In one possible implementation, the second type of device includes multiple third MOS transistors, which are driving devices for the inverter unit; the width-to-length ratio of the third MOS transistors to the first MOS transistors and the second MOS transistors conforms to a predetermined ratio, and they are manufactured using the same process type.

[0060] In this embodiment, the inverter unit of the ring resonator uses multiple third MOSFETs as driving devices. The third MOSFETs are matched with the first and second MOSFETs in the reference voltage generation module through standardized process types and width-to-length ratios, ensuring accurate compensation when PVT changes. The following explanation focuses on the composition, matching relationship, and compensation logic of the third MOSFETs: The ring oscillator consists of 5 inverter units (odd-numbered units satisfy the oscillation phase condition). The core of the second type of device in each inverter unit is a pair of complementary third MOS transistors: the third PMOS transistor (denoted as M3P): as the pull-up driver of the inverter, its source is connected to the output of the low dropout linear regulator (LDO) (receiving the supply voltage V_ro), its drain is connected to the output of the inverter, and its gate is connected to the input of the inverter of this stage; the third NMOS transistor (denoted as M3N): as the pull-down driver of the inverter, its source is grounded (GND), its drain is connected to the output of the inverter, and its gate is connected to the input of the inverter of this stage.

[0061] The two transistors work together to invert the signal: when the input is low, M3P is on and M3N is off, and the output is pulled up to V_ro; when the input is high, M3P is off and M3N is on, and the output is pulled down to GND. The charging and discharging speed of the inverter (which determines the output frequency of the RC ring oscillator circuit) is determined by the driving capability (transconductance gm) of M3P and M3N, and gm is directly related to the device width-to-length ratio (W / L) and the difference between the gate-source voltage and the threshold voltage (VGS-Vth).

[0062] In some embodiments, the matching relationship between the third MOSFET (M3P, M3N) and the first MOSFET (M1, PMOS) and the second MOSFET (M2, NMOS) is reflected in both the uniformity of process type and the predetermined aspect ratio, ensuring that the influence trend of PVT on the three types of devices is completely synchronized: Firstly, regarding the same process type, M3P and M1 use the same type of PMOS process, and M3N and M2 use the same type of NMOS process. Specifically, the process technology is consistent: both are based on the 180nm CMOS standard process, the gate oxide layer thickness is 3.5nm, and the channel length is 180nm (minimum feature size). Secondly, regarding the uniformity of material parameters, the doping concentration of the P-type channel in PMOS is 1.2e17cm. -3 The N-type channel doping concentration of NMOS is 1.5e17cm. -3 To ensure that the temperature coefficient of the threshold voltage Vth (e.g., -2mV / ℃) and the process deviation range (±0.1V) are completely consistent; the device models are the same, and the same SPICE model parameters (e.g., the temperature coefficient of carrier mobility μ, the channel length modulation coefficient λ) are used to ensure that the characteristic change law is synchronized under the same PVT conditions (e.g., when the temperature increases by 100℃, μ of M1 and M3P both increase by 15%, and Vth both decrease by 0.2V).

[0063] Third, the width-to-length ratio conforms to a predetermined ratio. The width-to-length ratio (W / L) of the third MOSFET with the first and second MOSFETs is set to a fixed ratio (4:1 in this embodiment). Specifically, the W / L of M1 is 10μm / 1μm (10μm wide, 1μm long), the W / L of M3P is 40μm / 1μm (4 times that of M1), the W / L of M2 is 10μm / 1μm, and the W / L of M3N is 40μm / 1μm (4 times that of M2). The core logic of this ratio design is that the transconductance gm of the MOSFET is proportional to the W / L (gm∝(W / L)×(VGS-Vth)). When the width-to-length ratio is fixed, the gm changes synchronously with M3P and M1, and the gm changes synchronously with M3N and M2. For example, when the process angle is Slow, causing M1's gm to decrease by 20%, M3P's gm also decreases by 20% simultaneously, ensuring that the reference voltage generation module can accurately sense changes in the inverter's drive capability.

[0064] More importantly, the matching relationship between the third MOSFET and the first and second MOSFETs is key to the accurate compensation of PVT effects by the adaptive adjustment of the reference voltage, specifically in the following scenarios: Firstly, there is the synergistic compensation during temperature increases. When the temperature rises from 25℃ to 125℃: due to the same process type, the |Vth| of M1 (PMOS) and M3P decreases synchronously (|Vth1| of M1 decreases from 0.7V to 0.5V, and |Vth3P| of M3P decreases from 0.7V to 0.5V), and μ increases synchronously by 15%; the Vth of M2 (NMOS) and M3N decreases synchronously (Vth2 of M2 decreases from 0.7V to 0.5V, and |Vth3N| of M3N decreases from 0.7V to 0.5V), and μ increases synchronously by 15%. Without compensation, the VGS-Vth of M3P and M3N increases (e.g., the VGS3P-Vth3P of M3P increases from 0.5V to 0.7V), gm increases, driving capability is enhanced, charging and discharging speed is accelerated, and the output frequency of the RC ring oscillator circuit easily increases by 20%.

[0065] Because the width-to-length ratio is proportional, the VGS of M1 and M2 decreases synchronously with the increase of temperature (VGS1 decreases from 0.5V to 0.45V, and VGS2 decreases from 0.5V to 0.45V), and the reference voltage Vdd_ref = VGS1 + VGS2 decreases to 0.9V; the V_ro output of LDO decreases synchronously to 1.2V, which reduces the VGS3P of M3P and the VGS3N of M3N (from 0.6V to 0.5V), and the increasing trend of VGS-Vth is offset (actually stabilized at 0.5V), gm returns to the room temperature level, and the output frequency of the RC ring resonator circuit stabilizes.

[0066] Secondly, compensation coordination when the process angle is Slow: When the process angle is Slow: Due to the same process type, |Vth| of M1 and M3P increases synchronously (|Vth1| of M1 increases from 0.7V to 0.9V, and |Vth3P| of M3P increases from 0.7V to 0.9V), and μ decreases synchronously by 20%; Vth of M2 and M3N increases synchronously (Vth2 of M2 increases from 0.7V to 0.9V, and Vth3N of M3N increases from 0.7V to 0.9V), and μ decreases synchronously by 20%. If no compensation is provided, VGS-Vth of M3P and M3N decreases (e.g., VGS3P-Vth3P of M3P decreases from 0.5V to 0.3V), gm decreases, driving capability weakens, charging and discharging speed slows down, and the output frequency of the RC ring resonator circuit is prone to decrease by 25%.

[0067] Because the width-to-length ratio is proportional, the VGS of M1 and M2 increases synchronously with the Slow process angle (VGS1 increases from 0.5V to 0.6V, VGS2 increases from 0.5V to 0.6V), and Vdd_ref increases to 1.2V; the V_ro output of LDO increases synchronously to 1.5V, which increases the VGS3P of M3P and the VGS3N of M3N (from 0.6V to 0.7V), and the decreasing trend of VGS-Vth is offset (actually stabilized at 0.5V), gm recovers to the typical process angle level, and the output frequency of the RC ring resonator circuit is stable.

[0068] In summary, by using the same process type and width-to-length ratio matching between the third MOSFET and the first and second MOSFETs, the influence of PVT changes on the inverter's driving capability is accurately captured and compensated in reverse by the reference voltage generation module, ultimately achieving low sensitivity of the ring oscillation output frequency to PVT.

[0069] In one possible implementation, the reference voltage generation module further includes a constant temperature bias current source connected in series with the first MOSFET and the second MOSFET to provide a constant temperature current to the first MOSFET and the second MOSFET, so that the reference voltage is not affected by changes in the power supply voltage.

[0070] In this embodiment, the reference voltage generation module introduces a constant-temperature bias current source to provide a stable current to the first and second MOSFETs, unaffected by the power supply voltage, ensuring that the reference voltage remains stable when the power supply voltage fluctuates. The specific structure and working principle are as follows: I. Composition and Connection of the Constant-Temperature Bias Current Source Type of Current Source: The constant-temperature bias current source is based on a bandgap reference circuit design. Its core is to utilize the bandgap voltage (approximately 1.2V) of the bipolar junction transistor (BJT) and the threshold voltage characteristics of the MOSFET to generate a constant-temperature current (denoted as I_bias, such as 20nA) that is independent of the power supply voltage (VDD), temperature, and process angle. The circuit topology of this current source includes an error amplifier, a MOSFET current mirror, and a bandgap reference core, ensuring that the temperature coefficient of the output current is less than 50ppm / ℃ and the power supply rejection ratio (PSRR) is greater than 60dB (i.e., when the power supply voltage changes by 10%, the current change is less than 1%). Series connection with the first and second MOSFETs: The output of the temperature-controlled bias current source is connected in series with the source of the first MOSFET (M1, PMOS), the drain (gate) of M1 is connected to the drain (gate) of the second MOSFET (M2, NMOS), and the source of M2 is grounded. Current flow is as follows: the current source draws power from VDD, and the output I_bias flows sequentially through M1 and M2, eventually flowing to ground. This series structure ensures that the current in M1 and M2 is always equal to I_bias, unaffected by VDD fluctuations.

[0071] In summary, by providing a stable current to the first and second MOSFETs through a constant-temperature bias current source, the reference voltage is not affected by changes in the power supply voltage, thereby ensuring the stability of the power supply voltage of the ring oscillator and achieving desensitization to power supply voltage fluctuations.

[0072] In one possible implementation, the first type of device includes a negative temperature resistor and a MOSFET with a matching relationship. The negative temperature resistor and the MOSFET are connected in series to form the core branch of the reference voltage generation module. The reference voltage is the sum of the voltage across the negative temperature resistor and the gate-source voltage of the MOSFET.

[0073] In this embodiment, the reference voltage generation module uses a negative temperature resistor and a MOSFET as the core components to form the first type of device. These two components are connected in series to form the core branch, which, combined with a constant temperature bias current, generates a reference voltage that adapts to the PVT. Simultaneously, the negative temperature resistor and the MOSFET are matched with the second type of devices (load resistor and driving MOSFET) in the ring oscillator body to ensure accurate PVT compensation. The following explanation covers the circuit structure, matching relationships, reference voltage generation, and compensation mechanism: In some embodiments, the negative temperature resistor (denoted as R0) in the first type of device is made of polycrystalline silicon, which has a negative temperature coefficient characteristic, meaning that its resistance decreases as the temperature increases and increases as the temperature decreases (typical resistance of 10kΩ at room temperature, with a temperature coefficient of approximately -2000ppm / ℃; for example, the resistance decreases by 20% to 8kΩ when the temperature increases by 100℃). By adjusting its own resistance according to temperature and process variations, the voltage across its terminals is adjusted to provide a change in the reference voltage that is synchronized with the resistance of the ring-oscillating load.

[0074] Still Figure 3 As shown, the MOS transistor (denoted as M0) in the first type of device is an NMOS transistor, which is the same process type (such as 180nm CMOS process) as the driving MOS transistor of the inverter unit of the ring oscillator body (the second type of device, denoted as M4~M6). It adopts a diode connection method (gate and drain short-circuited), which can make the MOS transistor work stably in the saturation region. Its gate-source voltage (VGS0) is only determined by the current flowing through it and its own characteristics, and is not affected by the drain-source voltage fluctuation.

[0075] The negative temperature resistor R0 and the MOSFET M0 are connected in series to form the core branch of the reference voltage generation module. Specifically, one end of R0 is connected to the system main supply voltage VDD (typically 1.8V), and the other end is connected to the drain (gate) of M0, forming the output node of the reference voltage (Vdd_ref); the source of M0 is grounded (GND). At the same time, a constant temperature bias current source (denoted as I_bias, with a typical output current of 20nA, provided by the bandgap reference circuit) is connected in series in the core branch. This current source ensures that the current flowing through R0 and M0 remains constant and is not affected by VDD fluctuations.

[0076] The matching relationship between the first type of devices (R0, M0) and the second type of devices in the ring resonator (load resistors R1~R3, driving MOSFETs M4~M6) is the key to achieving PVT adaptive compensation, which is specifically reflected in three dimensions: Regarding process consistency, R0 and R1~R3 ​​(load resistors of the ring oscillator inverter) use the same polysilicon deposition process, with completely consistent doping concentration and film thickness (e.g., doping concentration 1e18cm). -3(50nm film thickness) to ensure that the temperature coefficients and process deviations of both are synchronized. For example, when the process angle is Slow, the resistance of R0 increases by 20% due to process deviation, and the resistances of R1~R3 ​​also increase by 20% synchronously. M0 and M4~M6 use the same NMOS process, with consistent gate oxide thickness and channel doping concentration, to ensure that the threshold voltage (Vth) and carrier mobility (μ) of both change with temperature and process in the same way. For example, when the temperature decreases, the Vth of M0 increases by 0.2V, and the Vth of M4~M6 also increases by 0.2V synchronously.

[0077] Regarding the parameter ratio design, the resistance values ​​of R0 and R1~R3 ​​are in a fixed ratio (1:2 in this embodiment), that is, the room temperature resistance of R1~R3 ​​is 20kΩ (twice that of R0). This ratio design ensures that the resistance changes of the two are synchronized. For example, when the temperature rises by 100℃, R0 decreases from 10kΩ to 8kΩ (a reduction of 2kΩ), and R1~R3 ​​decreases from 20kΩ to 16kΩ (a reduction of 4kΩ), both with a change of 20%, which can be precisely offset by adjusting the reference voltage. The width-to-length ratio (W / L) of M0 and M4~M6 is in a fixed ratio (1:5 in this embodiment), that is, the W / L of M4~M6 is 50μm / 1μm (the W / L of M0 is 5 times that of 10μm / 1μm), ensuring that the driving capability changes of the two are synchronized. For example, when the process angle is Fast, the driving capability of M0 is enhanced by 30%, and the driving capability of M4~M6 is also enhanced by 30% simultaneously.

[0078] Regarding layout symmetry, in chip layout design, R0 and R1~R3 ​​are arranged in parallel and located in the same chip area (away from the chip edge) to avoid resistance differences caused by local temperature gradients on the wafer and process edge effects; M0 and M4~M6 are arranged in a common center symmetric layout, with the wiring length and metal layer width being completely consistent, and the parasitic resistance and capacitance have the same effect on both, ensuring synchronous characteristic changes.

[0079] In some embodiments, the reference voltage Vdd_ref is generated by superimposing the voltage across the negative temperature resistor R0 (V_R0) and the gate-source voltage (VGS0) of the MOSFET M0, i.e., Vdd_ref = V_R0 + VGS0. Its generation process depends entirely on the isothermal bias current and the inherent characteristics of the device. When the isothermal bias current I_bias flows through R0, according to Ohm's law, a voltage V_R0 is generated across R0. Since I_bias is constant (unaffected by VDD), V_R0 is determined only by the resistance of R0. When R0 changes due to temperature or process variations, V_R0 changes synchronously (e.g., if the resistance of R0 increases, V_R0 increases; if the resistance of R0 decreases, V_R0 decreases). M0 uses a diode connection and operates in the saturation region, with a current flowing through it called I_bias. Its gate-source voltage VGS0 is determined by its own characteristics. When the temperature increases, the threshold voltage Vth of M0 decreases, and VGS0 decreases accordingly. When the process corner is Slow, Vth of M0 increases and the carrier mobility decreases. To maintain I_bias, VGS0 increases accordingly. Since both V_R0 and VGS0 change with PVT, and their changing patterns are synchronized with the characteristic changes of the second type of ring resonator devices (R1~R3, M4~M6), Vdd_ref can accurately reflect the PVT state of the ring resonator device, providing a reference for subsequent compensation.

[0080] In some embodiments, during the adaptive compensation process when PVT changes, the temperature change compensation is as follows: when the temperature rises from 25°C to 125°C: in the ring resonator body, the resistance of R1~R3 ​​(matched with R0) decreases by 20% (from 20kΩ to 16kΩ) as the temperature rises, the charging and discharging path resistance decreases, and the charging and discharging speed tends to increase; at the same time, the Vth of M4~M6 (matched with M0) decreases, the driving capability is enhanced, and the charging and discharging speed is further accelerated, and the output frequency of the RC ring resonator circuit is easy to increase by 20%~25%.

[0081] In the reference voltage generation module, the resistance of R0 is reduced by 20% (from 10kΩ to 8kΩ), and V_R0 drops from 0.2V (when I_bias=20μA) to 0.16V; Vth of M0 is reduced synchronously, and VGS0 drops from 0.5V to 0.45V, therefore Vdd_ref drops from 0.7V (0.2V+0.5V) to 0.61V (0.16V+0.45V). The low dropout linear regulator (LDO) uses Vdd_ref as a reference, and its output supply voltage V_ro (V_ro=Vdd_ref+0.3V) drops synchronously from 1.0V to 0.91V. The decrease in V_ro reduces the gate-source voltage of M4~M6, weakens the driving capability, and offsets the accelerated charging and discharging trend caused by the reduction in the resistance of R1~R3, ultimately stabilizing the frequency.

[0082] When the temperature drops from 25℃ to -40℃, the above heating process is reversed: the resistance values ​​of R0 and R1~R3 ​​increase, V_R0 and Vdd_ref increase, V_ro increases synchronously, the driving capability of M4~M6 is enhanced, the charging and discharging slows down due to the increase in the resistance value of the counteractor, and the output frequency of the RC ring oscillator circuit remains stable.

[0083] In some embodiments, regarding compensation for process angle variations, when the process angle is Slow, the resistance values ​​of R1~R3 ​​in the ring resonator body increase by 20% due to process deviation (from 20kΩ to 24kΩ), increasing the charging and discharging path resistance and slowing down the charging and discharging speed; the Vth of M4~M6 increases, the carrier mobility decreases, the driving capability weakens, further slowing down the charging and discharging speed, and the output frequency of the RC ring resonator circuit easily decreases by 25%~30%. In the reference voltage generation module, the resistance value of R0 increases by 20% synchronously (from 10kΩ to 12kΩ), and V_R0 increases from 0.2V to 0.24V; the Vth of M0 increases synchronously, the carrier mobility decreases, and VGS0 increases from 0.5V to 0.6V, therefore Vdd_ref increases from 0.7V to 0.84V. The LDO output V_ro synchronously increases from 1.0V to 1.14V. This increase in V_ro increases the gate-source voltage of M4~M6, enhancing the driving capability and offsetting the slowing charging and discharging trend caused by the increased resistance of R1~R3. The output frequency of the RC ring oscillator circuit returns to its typical level. When the process corner is Fast, the resistances of R0 and R1~R3 ​​decrease, and Vdd_ref and V_ro decrease synchronously. This weakens the driving capability of M4~M6, accelerating charging and discharging due to the reduced resistance, and stabilizing the output frequency of the RC ring oscillator circuit.

[0084] In some embodiments, regarding compensation for power supply voltage changes, when the system main power supply VDD fluctuates from 1.6V to 2.0V, the isothermal bias current I_bias remains stable, the resistance of R0 and the characteristics of M0 are not affected by VDD, so V_R0 and VGS0 remain unchanged, Vdd_ref is stable, the LDO output V_ro is synchronously stable, the charging and discharging speed of the ring resonator is not affected by VDD fluctuations, and the output frequency of the RC ring resonator circuit has no offset.

[0085] In summary, by using the core branch of the negative temperature resistor and MOSFET in series, precise matching with the ring oscillator, and constant temperature bias current supply, the reference voltage can be adaptively adjusted according to the PVT. Furthermore, by adjusting the ring oscillator supply voltage through the LDO, comprehensive compensation for PVT changes is achieved, ensuring the stability of the ring oscillator output frequency.

[0086] In one possible implementation, the second type of device includes a resistor matched with the negative temperature resistor and a MOSFET; the resistor is the load resistor of the inverter unit, the material and temperature coefficient of the load resistor are the same as those of the negative temperature resistor, and the resistance value of the load resistor is in a predetermined ratio to that of the negative temperature resistor; the MOSFET is the driving device of the inverter unit, which uses the same process type as the MOSFET in the first type of device, and the aspect ratio is in a predetermined ratio.

[0087] In this embodiment, the second type of device in the ring oscillator inverter unit includes two core components: a load resistor that matches the negative temperature resistance resistor in the first type of device, and a drive MOSFET that matches the MOSFET in the first type of device. Through the precise matching of these two types of components with the first type of device, it is ensured that when the PVT changes, the characteristic changes of the ring oscillator can be accurately captured and compensated in reverse by the reference voltage generation module, ultimately achieving stable output frequency. The following explanation focuses on the device composition, matching relationship, and compensation coordination mechanism: In some embodiments, the ring resonator is composed of 5 inverter units connected in series (odd-numbered stages satisfy the oscillation condition), and the second type of device in each inverter unit includes: The load resistors (denoted as R1~R3, one in series for each inverter stage) are the core resistor components of the charging and discharging circuit. They are connected in series between the driving MOSFET and the power supply / ground. Their resistance value directly affects the charging and discharging time (the larger the resistance value, the slower the charging and discharging, and the lower the output frequency of the RC ring oscillator circuit).

[0088] The driving MOSFETs (denoted as M4~M6, each stage of the inverter contains 1 NMOS) serve as the switching elements of the inverter. The gate is connected to the input signal, the drain is connected in series with the load resistor, and the source is grounded. Their driving capability when they are turned on (which determines the magnitude of the charging and discharging current) directly affects the charging and discharging speed (the stronger the driving capability, the faster the charging and discharging, and the higher the output frequency of the RC ring oscillator circuit).

[0089] The load resistors (R1~R3) in the second type of device are matched with the negative temperature resistor (R0) in the first type of device through "material consistency, temperature coefficient consistency, and fixed resistance ratio", ensuring that the two are completely synchronized in the face of temperature and process influences. R1~R3 ​​and R0 are all made of high-resistivity polycrystalline silicon material and formed through the same deposition process (such as low-pressure chemical vapor deposition), with the same doping concentration (e.g., phosphorus doping, concentration 1e18cm). -3 The film thickness (50nm) is completely consistent. This consistency ensures that the inherent resistive characteristics (such as resistivity and grain boundary structure) of both are the same, and the trend of being affected by process deviations is consistent. For example, if the local doping concentration of the wafer is too high, causing the resistance of R0 to decrease by 10%, the resistance of R1 to R3 will also decrease by 10% simultaneously.

[0090] Because the materials and processes are the same, the temperature coefficients of R1~R3 ​​are completely identical to those of R0, all exhibiting negative temperature characteristics (-2000ppm / ℃). This means that for every 1℃ increase in temperature, the resistance decreases by 0.2%; and for every 1℃ decrease in temperature, the resistance increases by 0.2%. For example, when the temperature rises from 25℃ to 125℃ (an increase of 100℃), the resistance of R0 decreases from 10kΩ to 8kΩ (a decrease of 20%), and the resistances of R1~R3 ​​also decrease from 20kΩ to 16kΩ (a decrease of 20%), with the changes occurring completely synchronously.

[0091] The resistance values ​​of R1~R3 ​​and R0 are set in a fixed ratio (2:1 in this embodiment), that is, R0 has a room temperature resistance of 10kΩ, and R1~R3 ​​have a room temperature resistance of 20kΩ. The core of this proportional design is to ensure that the absolute resistance changes of the two are proportional, so that changes in the reference voltage can accurately offset the influence of the load resistance on the frequency. For example, when the process angle is Slow, if the resistance of R0 increases by 20% due to process deviation (from 10kΩ to 12kΩ, an increase of 2kΩ), the resistance of R1~R3 ​​will increase by 20% simultaneously (from 20kΩ to 24kΩ, an increase of 4kΩ), and the ratio of their changes will still be 1:2, which can be accurately compensated by adjusting the reference voltage.

[0092] like Figure 4 As shown, the reference voltage generation module consists of a constant current source Ib (which can be set to the nA or μA level according to power consumption and minimum operating voltage requirements; the larger the current, the higher the reference supply voltage and the stronger the MOS transistor driving capability; conversely, the lower and weaker the current), a negative temperature polysilicon resistor R0 (temperature coefficient -2100ppm / ℃), and an NMOS transistor M1 (connected by a diode, with the gate and drain shorted). Ib flows through R0 and M1 to generate the reference voltage vdd_ref (the sum of the voltage across R0 and the gate-source voltage of M1). The input of the low dropout linear regulator (LDO) is the undriven vdd_ref, and the output is the equal voltage and driven vout, which supplies power to the ring oscillator. The ring oscillator consists of negative temperature polysilicon resistors R1, R2, and R3 (temperature coefficient -2100ppm / ℃, resistance N times that of R0, where N is any natural number, including decimals and integers), NMOS transistors M2, M3, and M4 (size N times that of M1), and a load capacitor C. R1 and M2, R2 and M3, and R3 and M4 form charging and discharging units, respectively. The LDO output voltage charges and discharges capacitor C through these units to achieve oscillation.

[0093] The characteristics of R0 and M1 ensure that vdd_ref is unaffected by fluctuations in the power supply voltage Vdd, resulting in a stable and synchronous LDO output vout, a constant ring oscillator supply voltage, and no frequency shift. When the temperature rises, the vgs-vth of M1~M4 would normally increase, strengthening the driving capability, and the resistance of R1~R3 ​​(negative temperature resistance resistors) would decrease with increasing temperature, accelerating the charging and discharging speed and making the frequency more likely to rise. However, the synchronous decrease in vdd_ref of R0 and M1 causes a decrease in vgs-vth of M2~M4 and a reduction in the supply voltage of R1~R3, weakening the driving capability. This negative feedback counteracts the frequency increase trend. When the temperature decreases, the vgs-vth of M2~M4 decreases, the resistance of R1~R3 ​​increases, weakening the driving capability, while the synchronous increase in vdd_ref causes an increase in vgs-vth of M2~M4 and a rise in the ring oscillator supply voltage, strengthening the driving capability. This negative feedback counteracts the frequency decrease trend, ultimately keeping the frequency almost unchanged. When the process angle slows down, the driving capability of M1~M4 and R0~R3 all weakens, and vdd_ref increases, which offsets the resulting slowdown in frequency; when the process angle speeds up, vdd_ref decreases, which offsets the resulting fastdown in frequency, and significantly reduces the range of influence of the process angle on the ring oscillation frequency.

[0094] In some embodiments, the driving MOSFETs (M4~M6) in the second type of device are matched with the MOSFETs (M0) in the first type of device through "same process type and proportional width-to-length ratio", ensuring that the two are completely synchronized under the influence of temperature and process: Firstly, they share the same manufacturing process; M4~M6 and M0 are all enhancement-mode NMOS transistors, using the same CMOS process (e.g., 180nm), with the same gate oxide thickness (3.5nm), channel length (180nm), and channel doping concentration (N-type doping, concentration 1.5e17cm). -3 The threshold voltage (Vth) and carrier mobility (μ) of both are completely consistent. This consistency ensures that the temperature characteristics and process deviations of the threshold voltage (Vth) and carrier mobility (μ) are synchronized. For example, when the temperature decreases by 100°C, the Vth of M0 increases from 0.7V to 0.9V (an increase of 0.2V), and the Vth of M4~M6 also increases synchronously from 0.7V to 0.9V; when the process angle is Fast, the μ of M0 increases by 20%, and the μ of M4~M6 also increases synchronously by 20%.

[0095] Secondly, the width-to-length ratio is predetermined. The width-to-length ratio (W / L) of M4~M6 to M0 is set to a fixed ratio (5:1 in this embodiment), that is, the W / L of M0 is 10μm / 1μm (width 10μm, length 1μm), and the W / L of M4~M6 is 50μm / 1μm (width 50μm, length 1μm). This proportional design ensures that the changes in the driving capability (proportional to W / L) of both are synchronized. For example, when the temperature rises and causes the driving capability of M0 to increase by 15%, the driving capability of M4~M6 also increases by 15% simultaneously, enabling the reference voltage generation module to accurately sense the change in the inverter's driving capability.

[0096] In some embodiments, the matching relationship between the load resistor and the negative temperature resistor, and between the driving MOSFET and the first type of MOSFET, jointly ensures the accuracy of compensation when PVT changes. The specific collaborative process is as follows: Regarding the synergistic compensation during temperature rise, when the temperature rises from 25℃ to 125℃, the load resistors R1~R3 ​​and R0 decrease by 20% synchronously. The decrease in the resistance of R1~R3 ​​accelerates the charging and discharging speed (the frequency tends to increase). The driving MOSFETs M4~M6 and M0 synchronously have their driving capability enhanced by 15% due to the decrease in Vth and the increase in μ, further accelerating the charging and discharging speed (the frequency increases due to superposition). In the reference voltage generation module, the decrease in R0 causes the voltage V_R0 across it to decrease (from 0.2V to 0.16V), and the enhanced driving capability of M0 causes VGS0 to decrease (from 0. The reference voltage Vdd_ref = V_R0 + VGS0 drops from 0.7V to 0.61V; the supply voltage V_ro (Vdd_ref + 0.3V) of the LDO output drops from 1.0V to 0.91V simultaneously. The decrease in V_ro reduces the gate-source voltage of M4~M6, weakening the driving capability (offsetting the enhanced driving capability due to temperature rise). At the same time, the actual operating voltage of R1~R3 ​​decreases (offsetting the effect of their reduced resistance). Finally, the charging and discharging speed stabilizes, and the output frequency of the RC ring resonator circuit does not change significantly.

[0097] When the process corner is Slow, the load resistors R1~R3 ​​increase by 20% synchronously with R0. The increased resistance of R1~R3 ​​slows down the charging and discharging speed (leading to a decrease in frequency). The driving MOSFETs M4~M6 and M0 are driven by Vth increasing and μ decreasing, resulting in a 20% reduction in driving capability, further slowing down the charging and discharging speed (leading to a cumulative decrease in frequency). In the reference voltage generation module, the increase in R0 increases V_R0 (from 0.2V to 0.24V), and the weakened driving capability of M0 increases VGS0 (from 0.5V to 0.6V), while Vdd_ref increases from 0.7V to 0.84V. The LDO output V_ro increases synchronously from 1.0V to 1.14V. The increase in V_ro increases the gate-source voltage of M4~M6, enhancing the driving capability (offsetting the reduced driving capability due to the Slow process corner). At the same time, the actual operating voltage of R1~R3 ​​increases (offsetting the effect of their increased resistance). Finally, the charging and discharging speed returns to the typical level, and the output frequency of the RC ring oscillator circuit stabilizes.

[0098] In summary, by matching the load resistor and negative temperature resistor, and the driving MOSFET and the first type of MOSFET in the second type of device, the influence of PVT changes on the ring oscillator body can be accurately captured and compensated in reverse by the reference voltage generation module. This ultimately achieves low sensitivity of the ring oscillator output frequency to PVT, and eliminates the need for additional temperature and voltage monitoring circuits, significantly reducing circuit cost and complexity.

[0099] In one possible implementation, the reference voltage generation module further includes a constant temperature bias current source, which is connected in series with a negative temperature resistor and a MOSFET to provide a constant temperature current to the negative temperature resistor and the MOSFET, so that the variation of the reference voltage with temperature and process angle matches the variation of the characteristics of the second type of device.

[0100] In this embodiment, the reference voltage generation module introduces a constant-temperature bias current source to provide stable current to the negative-temperature resistor and the MOSFET (Type 1 device), ensuring that the voltage changes of both accurately reflect the effects of temperature and process angle, and perfectly match the characteristic variation patterns of the second type of devices (load resistor and driving MOSFET) in the ring oscillator, ultimately achieving PVT adaptive compensation. The following explanation details the current source configuration, connection relationships, and matching mechanism: The isothermal bias current source is designed based on a bandgap reference circuit. Its output current (denoted as I_bias, typically 20μA) is unaffected by variations in the system's main supply voltage (VDD), temperature, and process angle. Specifically, when the supply voltage fluctuates between 1.6V and 2.0V, the current change is less than 1%; when the temperature varies between -40℃ and 125℃, the current temperature coefficient is less than 50ppm / ℃; and when the process angle deviates between Fast and Slow, the current deviation is less than 3%. This stability ensures that the current flowing through the first type of device remains constant, providing a basis for accurate changes in the reference voltage. Series connection with the first type of device: The output terminal of the isothermal bias current source is connected in series with one end of a negative temperature resistor (R0). The other end of R0 is connected to the drain (gate) of a MOSFET (M0, NMOS, diode connection), and the source of M0 is grounded. Current flow: The current source draws power from VDD, and the output I_bias flows sequentially through R0 and M0, finally flowing to ground. This series structure ensures that I_bias flows through R0 and M0 simultaneously, and the voltage changes of both are determined solely by their own characteristics (resistance, threshold voltage, etc.) as a function of PVT, and are independent of VDD.

[0101] By forcing I_bias to remain constant, the variation patterns of the voltage V_R0 of the negative temperature resistor R0 and the gate-source voltage V_GS0 of the MOSFET M0 are strictly matched with the characteristic variation patterns of the second type of devices in the ring oscillator (load resistors R1~R3, driving MOSFETs M4~M6). Matching the characteristics with the load resistors (R1~R3): Load resistors R1~R3 ​​and R0 are matched negative temperature resistors (same material, temperature coefficient, resistance ratio 2:1). Due to the constant I_bias, the change in the voltage V_R0 of R0 is determined only by the change in the resistance of R0: as the temperature increases, the resistance of R0 decreases, and V_R0 decreases; at this time, the resistances of R1~R3 ​​decrease synchronously, and their effect on the charging and discharging speed (accelerating) matches the decreasing trend of V_R0; when the process angle is Slow, the resistance of R0 increases, and V_R0 increases; at this time, the resistances of R1~R3 ​​increase synchronously, and their effect on the charging and discharging speed (slowing) matches the increasing trend of V_R0. This matching ensures that changes in V_R0 can accurately reflect changes in the characteristics of R1~R3, providing the first reference for compensation.

[0102] In some embodiments, the matching compensation process for PVT changes includes: Firstly, there is the matching compensation when the temperature rises. When the temperature rises from 25℃ to 125℃: In the second type of device, the resistance of R1~R3 ​​decreases by 20% (accelerating charging and discharging), and the driving capability of M4~M6 increases by 15% (further accelerating charging and discharging). Both of these factors together cause the frequency to easily increase by 25%. In the first type of device, since I_bias is constant, the resistance of R0 decreases by 20% synchronously, and V_R0 drops from 0.2V to 0.16V; the driving capability of M0 increases by 15% synchronously, and V_GS0 drops from 0.5V to 0.45V; therefore, Vdd_ref drops from 0.7V to 0.61V, and its reduction matches the frequency increase caused by the second type of device. The LDO outputs the supply voltage (V_ro) according to Vdd_ref, and synchronously drops from 1.0V to 0.91V. The reduction of V_R0 exactly offsets the effects of the decrease in the resistance of R1~R3 ​​and the increase in the driving capability of M4~M6, and the output frequency of the RC ring resonator circuit is stable.

[0103] Secondly, the matching compensation when the process angle is Slow: When the process angle is Slow, in the second type of device, the resistance of R1~R3 ​​increases by 20% (slowing down charging and discharging), and the driving capability of M4~M6 decreases by 20% (further slowing down charging and discharging), both of which together cause the frequency to drop by 30%. In the first type of device, since I_bias is constant, the resistance of R0 increases by 20% synchronously, and V_R0 rises from 0.2V to 0.24V; the driving capability of M0 decreases by 20% synchronously, and V_GS0 rises from 0.5V to 0.6V; therefore, Vdd_ref rises from 0.7V to 0.84V, and its increase matches the frequency reduction caused by the second type of device; the V_R0 output of LDO rises synchronously from 1.0V to 1.14V, and the increase of V_R0 just offsets the effects of the increase in the resistance of R1~R3 ​​and the decrease in the driving capability of M4~M6, and the output frequency of the RC ring resonator circuit returns to the typical level.

[0104] In summary, the constant temperature bias current source ensures that the variation of the reference voltage strictly matches the characteristic variation of the ring oscillator by providing a stable current to the negative temperature resistor and MOSFET. This allows the LDO to accurately adjust the supply voltage, ultimately achieving efficient compensation for PVT variations and significantly reducing the sensitivity of the RC ring oscillator circuit's output frequency.

[0105] In one possible implementation, the RC ring oscillator circuit further includes a high-voltage MOSFET operational amplifier, which shares a reference voltage generation module with the ring oscillator body. The reference voltage generated by the reference voltage generation module is input to the bias circuit of the high-voltage MOSFET operational amplifier to adjust the gate bias voltage of the input pair of transistors. When the driving capability of the high-voltage MOSFET weakens due to PVT changes, the reference voltage increases, keeping the input pair of transistors on and operating in the saturation region. When the driving capability of the high-voltage MOSFET strengthens due to PVT changes, the reference voltage decreases, keeping the input pair of transistors on and operating in the saturation region to prevent the input pair of transistors from entering the linear region.

[0106] It should be understood that the input transistors need to operate in the saturation region when they are turned on. If the reference voltage is too low, the input transistors may not turn on; if the reference voltage is too high, the input transistors may enter the linear region. Therefore, an adaptive reference voltage is needed to ensure that the operational amplifier is turned on under PVT and operates in the saturation region, so as to prevent the input transistors from entering the linear region.

[0107] like Figure 5 As shown, the bias current source Ib provides a stable bias current for the amplifier, and the current magnitude can be flexibly set according to power consumption requirements. The input transistors M0 and M1 are both high-voltage NMOS transistors of identical size, and their gates receive the differential input signals VIN and VIP respectively, amplifying the differential signals. The load transistors M2 and M3 are both high-voltage PMOS transistors of identical size, employing a current mirror structure as active loads to convert the differential current into voltage output.

[0108] In low operating voltage scenarios (such as 1.8V power supply), analog circuits often use high-voltage MOSFETs to implement amplifiers in order to reduce leakage current and improve gain. However, the threshold voltage (Vth) of high-voltage MOSFETs is relatively high and is significantly affected by changes in PVT (process corner, temperature, voltage). When the process corner is slow and the temperature is -40℃, the Vth of high-voltage NMOS (M0, M1) and PMOS (M2, M3) increases. If the reference voltage is fixed (such as 0.9V), the input pair transistors are prone to being cut off because VGS (gate-source voltage) is less than Vth, causing the amplifier to be unable to transmit signals normally. If the reference voltage is too high, it will cause the clock module frequency to increase and the power consumption to surge.

[0109] This embodiment generates a reference voltage generation module (such as the PMOS+NMOS diode series structure mentioned above) that matches the characteristics of the amplifier's high-voltage MOSFET to generate vdd_ref that adaptively changes with PVT: when the driving capability of the high-voltage MOSFET weakens due to PVT changes (Slow process corner, low temperature), vdd_ref increases synchronously, increasing the VGS of the input pair M0 and M1, ensuring their conduction and maintaining the voltage margin of the current source Ib, thus ensuring normal amplifier bias current; when the driving capability of the high-voltage MOSFET becomes stronger (Fast process corner, high temperature), vdd_ref decreases synchronously, decreasing the VGS of the input pair, maintaining conduction while avoiding additional power consumption due to excessively high reference voltage. This adaptive mechanism enables the amplifier to operate stably over a wide PVT range, significantly enhancing robustness.

[0110] In this embodiment, the RC ring resonator circuit, based on the ring resonator body, reference voltage generation module, and low dropout linear regulator (LDO), further integrates an operational amplifier (hereinafter referred to as the high-voltage op-amp). The high-voltage op-amp and the ring resonator body share the same reference voltage generation module. Through adaptive changes in the reference voltage, both the output frequency of the RC ring resonator circuit and the PVT robustness of the high-voltage op-amp are simultaneously stabilized. The following explanation focuses on the high-voltage op-amp's structure, connection relationships, and PVT compensation mechanism: In this embodiment, the high-voltage operational amplifier adopts a five-transistor differential amplification structure, including: input transistors (M7 and M8, both high-voltage PMOS transistors with a withstand voltage ≥5V), a load current source (M9, a high-voltage NMOS transistor), an output stage buffer transistor (M10, a high-voltage PMOS transistor), and a bias circuit (composed of two voltage divider resistors R4 and R5 and a mirror current source). Among them, the input transistors M7 and M8 are key components of the operational amplifier. Their gates receive differential input signals (VIN- and VIN+), their sources are connected to the output terminal of the bias circuit (receiving the gate bias voltage Vb), and their drains are connected to the load current source. Their conduction state and driving capability directly determine the gain, input offset, and power consumption characteristics of the operational amplifier.

[0111] High-voltage MOSFETs have a high threshold voltage (Vth) due to their voltage withstand design (such as a thicker gate oxide layer), typically 1.2V~1.5V, and are significantly affected by changes in PVT. When the process corner is Slow or the temperature drops to -40℃, the Vth of the high-voltage MOSFET increases (e.g., from 1.3V to 1.6V), weakening its driving capability. If the gate bias voltage Vb is insufficient, the input pair may be cut off because VGS (gate-source voltage) is less than Vth, leading to op-amp failure. When the process corner is Fast or the temperature rises to 125℃, the Vth of the high-voltage MOSFET decreases (e.g., from 1.3V to 1.0V), strengthening its driving capability. If Vb is too high, the VGS of the input pair will be too large, causing a surge in drain current (Id) and generating additional power consumption (e.g., static power consumption increases from 100μA to 200μA).

[0112] Therefore, Vb needs to be dynamically adjusted using a reference voltage to ensure stable conduction and reasonable power consumption of the input transistors across the entire PVT range. The high-voltage operational amplifier and the ring oscillator share the same reference voltage generation module (its core consists of a type I device: a negative temperature resistor R0 and a MOSFET M0, connected in series with a constant temperature bias current source I_bias), as shown in the following connection: The output of the reference voltage generation module (reference voltage Vdd_ref) is divided into two paths: one path is input to the LDO to provide power supply voltage for the ring oscillator; the other path is input to the bias circuit of the high-voltage operational amplifier (connecting the series node of R4 and R5). The bias circuit converts Vdd_ref into the gate bias voltage Vb of the input pair transistors (Vb=Vdd_ref×R5 / (R4+R5), where R4=R5, so Vb=Vdd_ref / 2), making Vb change synchronously with Vdd_ref. When Vdd_ref increases due to changes in PVT, Vb increases synchronously; when Vdd_ref decreases, Vb decreases synchronously.

[0113] The advantages of this shared design are: no need to design a separate reference circuit for the high-voltage operational amplifier, saving chip area (reducing the reference module area by about 20%), and ensuring that the ring oscillator and the PVT compensation of the high-voltage operational amplifier are based on the same reference, resulting in better characteristic consistency.

[0114] In some embodiments, the variation of the reference voltage Vdd_ref with PVT (matching the second type of device in the ring resonator) precisely meets the bias requirements of the input pair of the high-voltage operational amplifier. The specific compensation process is as follows: Compensation for the weakened driving ability of high-voltage MOS transistors (Slow process corner / low temperature). When the process corner is Slow, the Vth of high-voltage MOS transistors (including input pair transistors M7 and M8) increases (e.g., from 1.3V to 1.6V), the carrier mobility decreases by 20%, and the driving ability is significantly weakened. If Vb remains unchanged (e.g., maintained at 0.5V), the VGS of M7 and M8 = Vb - V_source (V_source is the source voltage, approximately equal to VDD), and they may be cut off due to VGS < Vth.

[0115] At this time, in the reference voltage generation module, since the first type of device is process-matched with the high-voltage MOS transistor, the Vth of M0 increases synchronously, and the resistance value of R0 increases synchronously, resulting in Vdd_ref rising from the typical value of 1.0V to 1.2V; the Vb output by the bias circuit increases synchronously from 0.5V to 0.6V, increasing the VGS of M7 and M8 (e.g., from 0.4V to 0.5V), ensuring VGS > Vth (1.6V), keeping the input pair transistors conducting, and the operational amplifier working properly. When the temperature drops to -40°C, the Vth of the high-voltage MOS transistor increases synchronously, and the compensation process is the same as that of the Slow process corner: Vdd_ref increases → Vb increases → the input pair transistors remain conducting.

[0116] Compensation for the strengthened driving ability of high-voltage MOS transistors (Fast process corner / high temperature). When the process corner is the Fast process corner: the Vth of high-voltage MOS transistors decreases (e.g., from 1.3V to 1.0V), the carrier mobility increases by 20%, and the driving ability is too strong. If Vb remains unchanged (0.5V), the VGS of M7 and M8 = 0.5V. Due to the decrease in Vth, VGS - Vth increases (from 0.2V to 0.5V), and the drain current Id surges (e.g., from 100μA to 200μA), generating additional power consumption.

[0117] At this time, in the reference voltage generation module, the Vth of M0 decreases synchronously, and the resistance value of R0 decreases synchronously, resulting in Vdd_ref dropping from the typical value of 1.0V to 0.8V; the Vb output by the bias circuit decreases synchronously from 0.5V to 0.4V, reducing the VGS of M7 and M8 (from 0.5V to 0.4V), and VGS - Vth returns to 0.2V (when Vth = 1.0V), Id drops back to 100μA, the input pair transistors remain conducting and there is no additional power consumption. When the temperature rises to 125°C, the Vth of the high-voltage MOS transistor decreases synchronously, and the compensation process is the same as that of the Fast process corner: Vdd_ref decreases → Vb decreases → the input pair transistors conduct with low power consumption.

[0118] In this embodiment, the compensation based on PVT variations for both the ring oscillator and the high-voltage operational amplifier is based on the same reference voltage Vdd_ref, ensuring complete synchronization of their characteristic change trends (e.g., as temperature rises, the output frequency of the RC ring oscillator circuit stabilizes while the operational amplifier's power consumption decreases synchronously). Eliminating the need for a separate reference circuit for the high-voltage operational amplifier reduces chip area by approximately 15%, requires only one set of static current sources for the entire circuit, and reduces static power consumption by approximately 25%. No additional calibration circuit is required; PVT compensation for both modules is achieved through device matching and the natural variation of the reference voltage, significantly reducing circuit complexity.

[0119] In summary, by sharing the reference voltage generation module, the RC ring resonator circuit achieves frequency stability while providing an adaptive bias voltage for the operational amplifier. This resolves the contradiction between the high-voltage MOSFET's cutoff and excessive power consumption over a wide PVT range, significantly improving the overall circuit's robustness and integration.

[0120] This application provides an example of an adaptive RC ring resonator circuit PVT compensation method. Please refer to [reference needed]. Figure 6 As shown, Figure 6 A schematic flowchart of an adaptive RC ring resonator circuit PVT compensation method provided in this application is shown. This is an example and not a limitation; the method can be applied to or implemented in RC ring resonator circuits. The method includes: S601 uses a first type of device to generate a reference voltage for an RC ring resonator circuit, wherein the first type of device has a matching relationship with the inverter unit of the RC ring resonator circuit.

[0121] S602 inputs a reference voltage to a low-dropout linear regulator, enabling the low-dropout linear regulator to generate a supply voltage, which is then supplied to the RC ring oscillator circuit.

[0122] S603 enables the characteristics of the second type of device in the RC ring resonator circuit to adapt to changes in PVT by varying the reference voltage with the process angle, power supply voltage, and temperature PVT of the RC ring resonator circuit, thereby reducing the sensitivity of the RC ring resonator circuit's output frequency to PVT.

[0123] This application discloses an adaptive RC ring resonator circuit PVT compensation method, which aims to solve the problem that the output frequency of the RC ring resonator circuit is easily affected by changes in process angle, power supply voltage and temperature (PVT), resulting in a deviation. By adjusting the adaptive reference voltage, dynamic compensation for PVT changes is achieved, thereby improving the stability of the output frequency of the RC ring resonator circuit.

[0124] The following section provides a detailed explanation of each step of this method, using a specific circuit structure as an example: First, a reference voltage is generated for the RC ring resonator circuit using a first type of device, wherein the first type of device has a matching relationship with the inverter unit of the RC ring resonator circuit. It should be understood that this matching relationship means that the first type of device and the devices in the inverter unit maintain consistency or a preset ratio in electrical characteristics (such as temperature coefficient, process deviation response) and structural parameters (such as the width-to-length ratio of MOSFETs, and the material and size of resistors), ensuring that changes in the characteristics of the first type of device can accurately reflect changes in the characteristics of the inverter unit.

[0125] Specifically, the first type of device can adopt two typical structures: the first is as follows Figure 3 The first and second MOSFETs shown are matched with each other, both using diode connections (gate and drain shorted). The width-to-length ratio of the first and second MOSFETs is maintained at a preset ratio (e.g., 1:4) with the width-to-length ratio of the MOSFETs in the inverter unit of the RC ring resonator circuit (i.e., the second type of device). A reference voltage is generated by superimposing the gate-source voltages (VGS) of the first and second MOSFETs when they are turned on. The second type is as follows... Figure 4 The negative temperature resistor and MOSFET shown are matched. The material of the negative temperature resistor is the same as that of the resistor connected in series in the RC ring resonator circuit (i.e., the resistor in the second type of device) (e.g., both are polysilicon negative temperature resistors), and the resistance ratio of the two is fixed. The MOSFET is also connected in a diode manner. The reference voltage is generated by the series voltage division of the negative temperature resistor and the MOSFET.

[0126] Next, the reference voltage generated above is input to a low-dropout linear regulator (LDO), which generates a supply voltage and provides it to the RC ring oscillator circuit. Using the reference voltage as a reference, the LDO, through the adjustment of its internal error amplifier and regulating transistor, outputs a stable supply voltage that follows the changes in the reference power supply voltage. This supply voltage directly powers the inverter unit of the RC ring oscillator circuit, becoming the operating voltage of the MOSFET in the inverter.

[0127] Finally, by varying the reference voltage with the PVT of the RC ring resonator circuit, the characteristics of the second type of device in the RC ring resonator circuit are made to adapt to the changes in PVT, thereby reducing the sensitivity of the output frequency to PVT. The specific compensation mechanism is as follows: When the power supply voltage (i.e., the main power supply voltage VDD of the entire circuit system) changes, due to the special connection method of the first type of device (such as the diode-connected MOSFET with constant temperature bias current), the generated reference voltage is not affected by VDD fluctuations, thereby keeping the power supply voltage output by the LDO stable, ensuring that the operating voltage of the inverter unit of the RC ring resonator circuit remains unchanged, and avoiding frequency shift caused by power supply voltage changes.

[0128] When the temperature changes, the characteristics of the first type of device change synchronously with the temperature, causing the reference voltage to adjust adaptively: If the first type of device is a first MOSFET and a second MOSFET, an increase in temperature will increase the difference between the gate-source voltage and the threshold voltage (VGS-Vth) of the second type of device (MOSFET) in the inverter unit, enhancing its driving capability. At this time, the VGS of the first and second MOSFETs decreases, leading to a decrease in the reference voltage, which in turn lowers the supply voltage of the LDO output, further reducing the VGS of the second type of device and weakening its driving capability, thus offsetting the effect of the temperature increase on the frequency; when the temperature decreases, the opposite occurs, the reference voltage increases, offsetting the effect of the weakened driving capability. If the first type of device is a temperature-sensitive resistor and a MOSFET, an increase in temperature will decrease the resistance of the temperature-sensitive resistor, and at the same time, the resistance of the matching resistor in the inverter unit will also decrease. At this time, the reference voltage generated by the temperature-sensitive resistor and the MOSFET decreases, causing the supply voltage to decrease, and the driving capability of the second type of device (MOSFET) weakens. This weakens the driving capability of the second type of device, which cancels out the effect of the decreased resistance value, stabilizing the frequency; when the temperature decreases, the opposite occurs.

[0129] When the process corner changes, the process deviations of the first type of device and the second type of device are synchronized, and the reference voltage is adaptively adjusted with the process corner: If it is a slow process corner, the driving capability of both the first type of device and the second type of device weakens (e.g., the carrier mobility of the MOS transistor decreases and the resistance value is larger). At this time, the reference voltage generated by the first type of device increases, which increases the supply voltage of the LDO output, enhances the driving capability of the second type of device, and offsets the effect of the slowing process corner; if it is a fast process corner, the driving capability of the devices becomes stronger, the reference voltage decreases, the supply voltage decreases, the driving capability weakens, and offsets the effect of the fasting process corner.

[0130] Through the above method embodiments, the reference voltage is dynamically adjusted with the change of PVT, so that the characteristics of the second type of device in the RC ring resonator circuit are always adapted to the change of PVT, which ultimately significantly reduces the sensitivity of the output frequency to process angle, power supply voltage and temperature, and achieves a stable oscillation frequency output.

[0131] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0132] Corresponding to the adaptive RC ring resonator circuit PVT compensation method in the above embodiment, Figure 7 This is a schematic diagram of a PVT compensation device based on an adaptive RC ring resonator circuit provided in an embodiment of this application. This device can be implemented by software, hardware, or a combination of both, becoming part or all of a computer device. This computer device can be... Figure 8 The electronic device shown.

[0133] Reference Figure 7The adaptive RC ring resonator circuit PVT compensation device 700 includes: The first generation unit 701 uses a first type of device to generate a reference voltage for the RC ring resonator circuit, wherein the first type of device has a matching relationship with the inverter unit of the RC ring resonator circuit. The second generation unit 702 is used to input the reference voltage to the low dropout linear regulator, so that the low dropout linear regulator generates the supply voltage and provides the supply voltage to the RC ring circuit. The adaptive unit 703 is used to adapt the characteristics of the second type of device in the RC ring resonator circuit to the changes in PVT by changing the reference voltage with the process angle, power supply voltage and temperature PVT of the RC ring resonator circuit, so as to reduce the sensitivity of the output frequency of the RC ring resonator circuit to PVT.

[0134] It is understood that the embodiments and any implementation methods of the adaptive RC ring resonator circuit PVT compensation device correspond to the embodiments and any implementation methods of the adaptive RC ring resonator circuit PVT compensation method, respectively. The technical effects corresponding to the embodiments and any implementation methods of the adaptive RC ring resonator circuit PVT compensation device can be found in the above-mentioned technical effects corresponding to the embodiments and any implementation methods of the adaptive RC ring resonator circuit PVT compensation method, and will not be repeated here.

[0135] It should be noted that the adaptive RC ring resonator circuit PVT compensation device provided in the above embodiments is only an example of the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0136] The functional units and modules in the above embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of the embodiments of this application.

[0137] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0138] This application also provides an electronic device, which includes one or more processors and a memory; The memory is coupled to one or more processors. The memory is used to store computer program code, which includes computer instructions. One or more processors call the computer instructions to cause the electronic device to execute the aforementioned adaptive RC ring resonator circuit-based PVT compensation method.

[0139] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 700 can be a mobile phone, smart screen, tablet computer, wearable electronic device, in-vehicle electronic device, augmented reality (AR) device, virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), projector, or a communication device such as a server, storage device, or base station, or a smart car, etc. This application embodiment does not impose any limitations on the specific type of electronic device.

[0140] The memory 701 can be used to store computer software programs 702 and modules. The processor 703 executes various functional applications and data processing of the electronic device by running the software programs and modules stored in the memory 701. The memory 701 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for at least one function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the electronic device (such as audio data, telephone directory, etc.). In addition, the memory 701 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0141] The processor 703 may include one or more processors such as a central processing unit (CPU), an application processor (AP), and a baseband processor. The processor can serve as the nerve center and command center of the wireless router. The processor 703 can generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution. The memory 701 can be used to store executable program code, including instructions. The processor 703 executes various functional applications and data processing of the network device by running the instructions stored in the memory. The memory 701 may include a program storage area and a data storage area, such as storing data for audio signals to be played. For example, the memory may be Double Data Rate Synchronous Dynamic Random Access Memory (DDR) or Flash memory.

[0142] This application also provides a computer-readable storage medium storing computer instructions; when the computer-readable storage medium is used on an electronic device, it causes the electronic device to execute the aforementioned adaptive RC ring resonator circuit PVT compensation method.

[0143] The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or can include one or more data storage devices such as servers or data centers that can be integrated with media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media, or semiconductor media (e.g., solid-state disks (SSDs)).

[0144] This application also provides a computer program product containing computer instructions, which, when run on an electronic device, enables the electronic device to execute the aforementioned adaptive RC ring resonator circuit PVT compensation method.

[0145] The computer storage medium and computer program product provided in the embodiments of this application are used to execute the methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects corresponding to the methods provided above, and will not be repeated here.

[0146] In the above embodiments, implementation can also be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, Digital Subscriber Line, DSL) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc., and the storage medium can also include combinations of the above types of memory.

[0147] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0148] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments claimed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0149] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0150] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0151] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An RC ring oscillator, characterized by, The application relates to an RC ring oscillator circuit. The RC ring oscillator circuit comprises: a ring oscillator main body, which comprises a plurality of inverter units, each of the inverter units comprising a second type device; a reference voltage generation module, which comprises a first type device, has a matching relationship with the inverter units, and is used for generating a reference voltage; and a low-dropout linear voltage regulator, which is connected with an output end of the reference voltage generation module and an input end of the ring oscillator main body. The reference voltage generated by the reference voltage generation module changes with process corners, power supply voltage and temperature (PVT), the low-dropout linear voltage regulator generates a supply voltage based on the reference voltage and provides the supply voltage to the ring oscillator main body, the characteristics of the second type device adapt to the change of the PVT, and the sensitivity of an output frequency of the ring oscillator main body to the PVT is reduced. The first type device comprises a first MOS tube and a second MOS tube which are matched with each other, are connected in a diode mode, and are connected in series to form a core branch of the reference voltage generation module; and the reference voltage is the sum of a gate-source voltage of the first MOS tube and a gate-source voltage of the second MOS tube. The second type device comprises a plurality of third MOS tubes which are driving devices of the inverter units; the third MOS tubes have a predetermined ratio with the first MOS tube and the second MOS tube in terms of width-length ratio and are of the same process type.

2. The RC ring oscillator circuit of claim 1, wherein, The reference voltage generation module further comprises a constant-temperature bias current source which is connected with the first MOS tube and the second MOS tube in series and is used for providing constant-temperature current to the first MOS tube and the second MOS tube, so that the reference voltage is not affected by the change of the power supply voltage.

3. The RC ring oscillator circuit of claim 2, wherein, The first type device comprises a negative temperature resistance and a MOS tube which have a matching relationship, are connected in series to form a core branch of the reference voltage generation module; and the reference voltage is the sum of a voltage across the negative temperature resistance and a gate-source voltage of the MOS tube.

4. The RC ring oscillator circuit of claim 3, wherein, The second type device comprises a resistance matched with the negative temperature resistance and a MOS tube; the resistance is a load resistance of the inverter units, the material and temperature coefficient of the load resistance are consistent with those of the negative temperature resistance, the resistance value of the load resistance has a predetermined ratio with that of the negative temperature resistance, and the MOS tube is a driving device of the inverter units and is of the same process type with the MOS tube in the first type device and has a predetermined ratio with the MOS tube in terms of width-length ratio.

5. The RC ring oscillator circuit according to any one of claims 1 to 4, wherein The reference voltage generation module further comprises a constant-temperature bias current source which is connected with the negative temperature resistance and the MOS tube in series and is used for providing constant-temperature current to the negative temperature resistance and the MOS tube, so that the change law of the reference voltage with temperature and process corners matches the change law of the characteristics of the second type device.

6. The RC ring oscillator circuit of claim 5, wherein, The RC ring oscillator circuit further comprises a high-voltage MOS tube operational amplifier which shares the reference voltage generation module with the ring oscillator main body.

7. The RC ring oscillator circuit of claim 5, wherein, ​ 8. The RC ring oscillator circuit according to any one of claims 1 to 4, wherein ​ The reference voltage generated by the reference voltage generation module is input to a bias circuit of the high-voltage MOS operational amplifier, and is used to adjust the gate bias voltage of the input pair transistor of the high-voltage MOS operational amplifier; when the driving capability of the high-voltage MOS transistor is weakened due to PVT variation, the reference voltage is increased, so that the input pair transistor is kept on and works in the saturation region; when the driving capability of the high-voltage MOS transistor is strengthened due to PVT variation, the reference voltage is reduced, so that the input pair transistor is kept on and works in the saturation region, to prevent the input pair transistor from entering the linear region.

9. A PVT compensation method based on an adaptive RC ring oscillator circuit, characterized in that, The method comprises the steps of: generating a reference voltage for the RC ring oscillator by using a first type of device, wherein the first type of device has a matching relationship with an inverter unit of the RC ring oscillator; inputting the reference voltage to a low-dropout linear regulator, so that the low-dropout linear regulator generates a supply voltage, and providing the supply voltage to the RC ring oscillator; by changing the reference voltage with process corner, power voltage and temperature (PVT) of the RC ring oscillator, the characteristics of a second type of device in the RC ring oscillator are adapted to the change of the PVT, so as to reduce the sensitivity of the output frequency of the RC ring oscillator to the PVT.

10. A PVT compensation device based on an adaptive RC ring resonator circuit, characterized in that, The method comprises the steps of: a first generation unit is configured to generate a reference voltage for the RC ring oscillator by using a first type of device, wherein the first type of device has a matching relationship with an inverter unit of the RC ring oscillator; a second generation unit is configured to input the reference voltage to a low-dropout linear regulator, so that the low-dropout linear regulator generates a supply voltage, and provide the supply voltage to the RC ring oscillator; an adaptive unit is configured to change the reference voltage with process corner, power voltage and temperature (PVT) of the RC ring oscillator, so that the characteristics of a second type of device in the RC ring oscillator are adapted to the change of the PVT, so as to reduce the sensitivity of the output frequency of the RC ring oscillator to the PVT.

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