Reference voltage easy-to-drive analog-to-digital converter

Abstract

The invention relates to a reference voltage easy-to-drive analog-to-digital converter, and belongs to the field of integrated circuits, the analog-to-digital converter comprises a fine SAR ADC and a coarse SAR ADC, when phi SA, phi S and phi D are high levels, a top plate of a DAC bit capacitor is connected with a VCM end, a bottom plate of the DAC bit capacitor is connected with an input signal end, and phi SA and phi S are sequentially reduced to low levels to complete sampling of input signals; when the phi C is in a high level, quantizing an input signal through the coarse SAR ADC to obtain a first five-bit digital code, connecting a bit capacitor bottom plate of the passive charge redistribution DAC in the fine SAR ADC to a VREFP end or a VREFN end according to the digital code, disconnecting the connection when the phi C is reduced to a low level, and after the phi D is reduced to a low level and the phi R is increased to a high level, short-circuiting the bottom plates of part of capacitors in the passive charge redistribution DAC to obtain a second five-bit digital code; the charge is redistributed to generate a residual voltage. According to the invention, the manufacturability and practicability are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a reference voltage-driven analog-to-digital converter. Background Technology

[0002] To suppress noise kT / C (where k is Boltzmann's constant, T is absolute temperature, and C is the sampling capacitance), high-precision SAR ADCs (Successive Approximation Register Analog-to-Digital Converters) require a large sampling capacitor, thus placing high demands on reference voltage establishment. However, to suppress reference voltage establishment ripple caused by DAC (Digital-to-Analog Converter) switching, traditional solutions consume significant area and power. To reduce these overheads, the paper "A Compact Low-power 16b SAR ADC using Reservoir-Charge-Redistributed DAC and Configurable Floating-Inverter-Based Comparator" (Yuan C, Pan X, Zheng Z, et al. IEEE ASSCC, Nov. 2024) utilizes coarse SAR to quantize the first four bits, and fine SAR then uses the quantization result to adjust the capacitance of the first four bits (C). bit,1-4 ) and their respective pre-charged series of capacitors (C) required to generate residual voltage. REF,1-4 A differential connection is established in series to redistribute the charge, thereby generating the residual voltage required for the fifth quantization, while the remaining bits still use the traditional V... CM -Based switching timing is quantized in the fine SAR ADC.

[0003] However, this method has the following three limitations. First, to achieve the binary quantization step size, the first four bits of C... bit,i For the same value, and each C REF,i Both are C bit,i The different complex fractional multiples increase the manufacturing difficulty; secondly, this method was used by C REF,i Constrained by the trade-off between the magnitude of C and the noise kT / C it introduces, i.e., increasing C REF,i This will increase area overhead and decrease C. REF,i More C will be introduced REF,iThe introduced noise is kT / C; third, this method is very sensitive to the parasitic capacitance of the DAC section it applies to, which leads to ADC bit weighting error and a decrease in input dynamic range. To mitigate the effects of parasitic effects, it is necessary to adjust the capacitance of each C. REF,i The process involves complex adjustments, and this complexity increases with the number of bits in the DAC used in the scheme. Therefore, the aforementioned problems severely limit the practicality of this approach.

[0004] Therefore, providing a highly manufacturable and practical analog-to-digital converter has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a reference voltage-driven analog-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a reference voltage-driven analog-to-digital converter, including a fine SAR ADC and a coarse SAR ADC. The fine SAR ADC includes a passive charge redistribution DAC and an LSB DAC, wherein: The fine SAR ADC is used when the sampling clock signal φ SA Sampling clock signal φ S and decision clock signal φ D When the voltage is high, connect the top plate of the DAC bit capacitor of the fine SAR ADC to V. CM The base plate is connected to the input signal terminal, and the sampling clock signal φ SA First, lower the voltage level to disconnect the top plate of the DAC bit capacitor from the V. CM The connection of the terminal, the sampling clock signal φ S The voltage is then lowered to disconnect the base plate of the DAC bit capacitor from the input signal terminal, and the capacitor array of the LSB DAC is connected to V. REFP End or V REFN end; The coarse SAR ADC is used to coarsely quantize the clock signal φ. C When the input signal is high, the quantization result is obtained; The fine SAR ADC is further configured to connect the capacitor array of the passive charge redistribution DAC to the V based on the quantization result. REFP End or the V REFN Terminal, and in the coarse quantization clock signal φ C The connection is disconnected when the signal drops to a low level, and when the decision clock signal φ... D After dropping to a low level, the charge redistribution clock signal φ RThe voltage rises to a high level to short-circuit the base plate of a portion of the capacitors in the passive charge redistribution DAC, thereby redistributing the charge and generating a residual voltage.

[0006] In one embodiment of the present invention, the passive charge redistribution DAC includes n identical first capacitor switch structures and n identical second capacitor switch structures, switch S1, switch S2, switch S3, and switch S4 connected in parallel, wherein: The first capacitor switch structure includes a capacitor C L,i1 Capacitor C L,i2 Switch S L,i1 Switch S L,i2 Switch S L,i3 Switch S L,i4 Switch S L,i5 and switch S L,i6 The capacitor C L,i1 The top plate is connected to the second terminal of the switch S1, and the capacitor C L,i2 The top plate is connected to the second terminal of the switch S2, and the capacitor C L,i1 The base plate is connected to the switch S L,i1 The switch S L,i2 and the switch S L,i3 The first terminal, the capacitor C L,i2 The base plate is connected to the switch S L,i4 The switch S L,i5 and the switch S L,i6 The first end, the switch S L,i1 The second end is connected to the V REFP Terminal, the switch S L,i4 The second end is connected to the V REFP Terminal, the switch S L,i2 The second end is connected to the V REFN Terminal, the switch S L,i5 The second end is connected to the V REFN Terminal, the switch S L,i3 The second terminal is connected to the input signal V IN Terminal, the switch S L,i6 The second terminal is connected to the input signal V IP Terminal, wherein the switch S L,i1 and the switch S L,i5 Both are sampled and flipped by the P clock signal φ P,i Control, the switch S L,i2 and the switch S L,i4 All are sampled and flipped by N clock signals φ N,i Control, the switch S L,i3 and the switch S L,i6 All are derived from the sampling clock signal φS Control; when the coarse quantization clock signal φ C When the sampling toggle P clock signal φ is low, P,i and the sampled toggling N clock signal φ N,i All are low level, when the coarse quantization clock signal φ C When the signal is high, if the digital code of the i-th quantized bit is 1, then the sampling toggle N clock signal φ N,i The sampling toggle P clock signal φ is at a high level. P,i If the quantization result of the i-th bit is 0, then the sampling toggle N clock signal φ is low. N,i The sampling toggle P clock signal φ is at a low level. P,i The level is high, 1≤i≤n; The second capacitor switch structure includes a capacitor C. R,i1 Capacitor C R,i2 Switch S R,i1 Switch S R,i2 Switch S R,i3 Switch S R,i4 Switch S R,i5 Switch S R,i6 Switch S R,i7 and switch S R,i8 The capacitor C R,i1 The top plate is connected to the second terminal of the switch S3, and the capacitor C R,i2 The top plate is connected to the second terminal of the switch S4, and the capacitor C R,i1 The base plate is connected to the switch S R,i1 The switch S R,i2 The switch S R,i3 and the switch S R,i4 The first terminal, the capacitor C R,i2 The base plate is connected to the switch S R,i5 The switch S R,i6 The switch S R,i7 and the switch S R,i8 The first end, the switch S R,i1 The second end is connected to the V REFP Terminal, the switch S R,i5 The second end is connected to the V REFP Terminal, the switch S R,i2 The second end is connected to the V REFN Terminal, the switch S R,i6 The second end is connected to the V REFN Terminal, the switch S R,i3 The second end is connected to the input signal V IN Terminal, the switch S R,i7The second end is connected to the input signal V IP Terminal, the switch S R,i4 The second end is connected to the switch S R,i8 The second end, wherein the switch S R,i2 and the switch S R,i5 All are generated by the sampling and flipping of the P clock signal φ P,i Control, the switch S R,i1 and the switch S R,i6 All are generated by the sampled and toggled N clock signal φ N,i Control, the switch S R,i3 and the switch S R,i7 All are derived from the sampling clock signal φ S Control, the switch S R,i4 and the switch S R,i8 All are generated by the charge redistribution clock signal φ R control; The first terminals of both switches S1 and S2 are connected to V. CM The second terminal of the switch S1 is connected to the n capacitors C. L,i1 The top plates are interconnected at a common node, and the second terminal of the switch S2 is connected to n capacitors C. L,i2 The top plates are interconnected at a common node, and the first end of the switch S3 is connected to n capacitors C. L,i1 The top plates are interconnected at a common node, and the second terminal of the switch S3 is connected to n capacitors C. R,i1 The top plates are interconnected at a common node, and the first terminal of the switch S4 is connected to n capacitors C. L,i2 The top plates are interconnected at a common node, and the second terminal of the switch S4 is connected to n capacitors C. R,i2 The top plates are interconnected by a common node, wherein both switch S1 and switch S2 are generated by the sampling clock signal φ. SA Controlled by the decision clock signal φ, both switches S3 and S4 are controlled by the decision clock signal φ. D control.

[0007] In one embodiment of the present invention, the quantization result is an n-bit first digital code consisting of 0s and 1s.

[0008] In one embodiment of the present invention, when the first digital code in the i-th position is 0, the capacitor C L,i1 Connect the V REFP Terminal, the capacitor C L,i2 Connect the V REFN Terminal, the capacitor C R,i1 Connect the V REFN Terminal, the capacitor C R,i2 Connect the VREFP When the first digital code in the i-th bit is 1, the capacitor C L,i1 Connect the V REFN Terminal, the capacitor C L,i2 Connect the V REFP Terminal, the capacitor C R,i1 Connect the V REFP Terminal, the capacitor C R,i2 Connect the V REFN end. In one embodiment of the present invention, the LSB DAC includes m groups of third capacitor switch structures, wherein the j-th group of the third capacitor switch structures includes a first capacitor switch substructure and a second capacitor switch substructure, and the first capacitor switch substructure includes a capacitor C. P,j1 C P,j2 Switch S P,j1 Switch S P,j2 Switch S P,j3 Switch S P,j4 Switch S P,j5 Switch S P,j6 The second capacitor switch substructure includes a capacitor C. N,j1 Capacitor C N,j2 Switch S N,j1 Switch S N,j2 Switch S N,j3 Switch S N,j4 Switch S N,j5 Switch S N,j6 , 1≤j≤m, where: The capacitor C P,j1 The top plate and the capacitor C N,j1 The top plate is connected to n capacitors C R,i1 The common nodes of the interconnected top plates, the capacitor C P,j2 The top plate and the capacitor C N,j2 The top plate is connected to n capacitors C R,i2 The common nodes of the interconnected top plates, the capacitor C P,j1 The base plate is connected to the switch S P,j1 The switch S P,j2 The switch S P,j3 The first terminal, the capacitor C N,j1 The base plate is connected to the switch S N,j1 The switch S N,j2 The switch S N,j3 The first terminal, the capacitor C P,j2 The base plate is connected to the switch S P,j4 The switch S P,j5 The switch S P,j6 The first terminal, the capacitor CN,j2 The base plate is connected to the switch S N,j4 The switch S N,j5 The switch S N,j6 The first end, the switch S P,j1 and the switch S P,j4 The second end is connected to the V REFP Terminal, the switch S P,j2 and the switch S P,j5 The second end is connected to the V REFN Terminal, the switch S P,j3 The second terminal is connected to the input signal V IN Terminal, the switch S P,j6 The second terminal is connected to the input signal V IP Terminal, the switch S N,j1 and the switch S N,j4 The second end is connected to the V REFP Terminal, the switch S N,j2 and the switch S N,j5 The second end is connected to the V REFN Terminal, the switch S N,j3 The second terminal is connected to the input signal V IN Terminal, the switch S N,j6 The second terminal is connected to the input signal V IP Terminal, wherein the switch S P,j1 The switch S P,j2 The switch S P,j4 The switch S P,j5 The switch S N,j1 The switch S N,j2 The switch S N,j4 and the switch S N,j5 All are controlled by asynchronous SAR output signals, the switch S P,j3 The switch S P,j6 The switch S N,j3 and the switch S N,j6 All are derived from the sampling clock signal φ S control. In one embodiment of the present invention, the capacitor C L,i1 The capacitor C L,i2 The capacitor C R,i1 and the capacitor C R,i2 The size is: ; The capacitor C P,j1 The capacitor C N,j1 The capacitor C P,j2 and the capacitor C N,j2 The size is: ; in, For unit capacitance, C P,11 C N,11 C P,12 and C N,12 These are the capacitors when j is 1.

[0009] In one embodiment of the present invention, the value of n ranges from 1 to 7, and the value of m ranges from 1 to 15. In one embodiment of the present invention, when the decision clock signal φ D After dropping to a low level, the charge redistribution clock signal φ R The voltage rises to a high level to short-circuit the base plate of a portion of the capacitors in the passive charge redistribution DAC, thereby redistributing the charge to generate a residual voltage, including: When the decision clock signal φ D After dropping to a low level, the charge redistribution clock signal φ R When the voltage rises to a high level, the capacitor C R,i1 The base plate is connected to the capacitor C R,i2 The base plate makes the capacitor C R,i1 The base plate and the capacitor C R,i2 The base plate is shorted to redistribute the charge, generating n capacitors C. R,i1 The top plate and all the capacitors C in the third capacitor switch structure of the m groups P,j1 and the capacitor C N,j1 The residual voltage V0 of the top plate, and the generation of n capacitors C R,i2 The top plate and all the capacitors C in the third capacitor switch structure of the m groups P,j2 and the capacitor C N,j2 The residual voltage V1 of the top plate. In one embodiment of the present invention, the reference voltage easily driven analog-to-digital converter further includes: A comparator, wherein the positive input terminal of the comparator is connected to n capacitors C. R,i1 The top plate and all the capacitors C of the third capacitor switch structure of the m groups P,j1 and the capacitor C N,j1 The top plate of the comparator has n capacitors C connected to its negative input terminal. R,i2 The top plate, m groups of the third capacitor switch structure, and all the capacitors C P,j2 and the capacitor C N,j2 The top plate is used to perform the j-th comparison between the current residual voltage V0 and the current residual voltage V1, so as to output the j-th comparison result; An asynchronous SAR, connected to the output of the comparator, is used to generate the j-th bit of the m-bit second digital code based on the j-th comparison result, and to perform successive approximation quantization on the LSB DAC based on the split switching timing until the m-th bit of the second digital code is finally obtained.

[0010] In one embodiment of the present invention, the reference voltage easily driven analog-to-digital converter further includes: The digital code combination module is used to combine the n-bit first digital code and the m-bit second digital code to obtain and output the digital combination code. Compared with the prior art, the beneficial effects of the present invention are as follows: This invention employs a novel residual voltage generation scheme, which eliminates the use of C while maintaining binary weights. REF,i Therefore, C was completely solved. REF,i The present invention addresses the trade-off between area and the kT / C noise it introduces. It is insensitive to the parasitic capacitance of the DAC section to which it is applied, and does not introduce bit weighting errors or dynamic range loss, thus avoiding additional complex trimmings and facilitating expansion to more bits. Furthermore, it maintains the same bit capacitor arrangement as conventional split-switching timings, thereby improving manufacturability and practicality.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0012] Figure 1 This is a structural block diagram of a reference voltage-driven analog-to-digital converter provided by the present invention; Figure 2 This is a schematic diagram of a reference voltage-driven analog-to-digital converter provided by the present invention; Figure 3 This is a timing diagram of a reference voltage-driven analog-to-digital converter provided by the present invention; Figure 4 This is a schematic diagram of a first capacitor switch structure provided by the present invention; Figure 5 This is a schematic diagram of a second capacitor switch structure provided by the present invention; Figure 6 This is a schematic diagram of the structure of an LSB DAC provided by the present invention; Figure 7 This is a schematic diagram of another reference voltage-driven analog-to-digital converter provided by the present invention; Figure 8 This is a schematic diagram of charge redistribution with a quantization result of 10 provided by the present invention; Figure 9This is a schematic diagram of charge redistribution with a quantization result of 11 provided by the present invention; Figure 10 This is a schematic diagram of charge redistribution with a quantization result of 0 provided by the present invention. Detailed Implementation

[0013] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0014] Please see Figure 1 , Figure 2 and Figure 3 , Figure 1 This is a structural block diagram of a reference voltage-driven analog-to-digital converter provided by the present invention. Figure 2 This is a schematic diagram of a reference voltage-driven analog-to-digital converter provided by the present invention. Figure 3 This is a timing diagram of a reference voltage-driven analog-to-digital converter (ADC) provided by the present invention. The present invention provides a reference voltage-driven ADC, which includes a fine SAR ADC and a coarse SAR ADC. The fine SAR ADC includes a passive charge redistribution DAC and an LSB (Least Significant Bit) DAC, wherein: Fine SAR ADC, used when sampling clock signal φ SA Sampling clock signal φ S and decision clock signal φ D When the voltage is high, connect the top plate of the DAC bit capacitor of the fine SAR ADC to V. CM (Common-Mode Voltage) terminal, baseboard input signal terminal, sampling clock signal φ SA First, lower the voltage level to disconnect the top plate of the DAC bit capacitor from V. CM Terminal connection, sampling clock signal φ S It then drops to a low level to disconnect the base plate of the DAC bit capacitor from the input signal terminal, and connects the LSBDAC capacitor array to V. REFP (Positive reference voltage) terminal or V REFN (Negative reference voltage) terminal; Coarse SAR ADC, used for coarse quantization of clock signal φ C When the input signal is high, the quantization result is obtained; The fine SAR ADC is also used to connect the capacitor array of the passive charge redistribution DAC to V based on the quantization results. REFP End or V REFN The end, and at the coarse quantization clock signal φ C The connection is disconnected when the signal drops to a low level, and the decision clock signal φ is used to determine the connection. DAfter dropping to a low level, the charge redistribution clock signal φ R The voltage rises to a high level to short-circuit the base plate of some capacitors in the passive charge redistribution DAC, thereby redistributing the charge and generating a residual voltage.

[0015] Specifically, the sampling clock signal φ SA The externally input clock signal, sampled clock signal φ S Coarse quantization clock signal φ C Decision clock signal φ D and charge redistribution clock signal φ R These are all clock signals generated internally by the analog-to-digital converter (ADC). The DAC bit capacitance is the sum of all capacitances in the fine SAR ADC. Therefore, during the sampling phase, when the sampling clock signal φ... SA Sampling clock signal φ S and decision clock signal φ D When both rise to high level, connect the top plate of the DAC bit capacitor of the fine SAR ADC to V. CM The DAC bit capacitor's base plate is connected to the input signal terminal; when the sampling clock signal φ SA When the sampling clock signal φ drops to a low level SA The control switch is turned off to disconnect the top plate of the DAC bit capacitor from V. CM The connection at the end is then used to sample the clock signal φ. S The sampling clock signal φ drops to a low level. S The control switch is turned off to disconnect the base plate of the DAC bit capacitor from the input signal terminal. Then, the base plate of the LSB DAC capacitor array (i.e., all capacitors in the LSB DAC) is connected to V. REFP End or V REFN The voltage across the base plate of the DAC bit capacitor is set to the voltage of the input signal. The coarse SAR ADC receives the input signal and applies it to the coarse quantization clock signal φ. C The input signal is quantized when it is high to obtain the quantization result. Then, based on the quantization result, the fine SAR ADC connects the base plate of the passive charge redistribution DAC's capacitor array (i.e., all capacitors in the passive charge redistribution DAC) to V. REFP End or V REFN At the end, in the coarse quantization clock signal φ C When the voltage drops to a low level, the base plate of the capacitor array of the passive charge redistribution DAC is disconnected from V. REFP End or V REFN The connection at the end, and when the decision clock signal φ D After falling to a low level, the charge redistribution clock signal φ R When the voltage rises to a high level, it shorts the base plate of part of the capacitor array in the passive charge redistribution DAC, causing the charge to redistribute and generate a residual voltage.

[0016] In one specific embodiment, please refer to Figure 2 , Figure 4 and Figure 5 The passive charge redistribution DAC includes n identical first capacitor switch structures and n identical second capacitor switch structures, switch S1, switch S2, switch S3, and switch S4 connected in parallel, wherein: The first capacitor switch structure includes a capacitor C. L,i1 Capacitor C L,i2 Switch S L,i1 Switch S L,i2 Switch S L,i3 Switch S L,i4 Switch S L,i5 and switch S L,i6 Capacitor C L,i1 The top plate is connected to the second terminal of switch S1, and capacitor C L,i2 The top plate is connected to the second terminal of switch S2, and capacitor C L,i1 The base plate is connected to switch S L,i1 Switch S L,i2 and switch S L,i3 The first terminal, capacitor C L,i2 The base plate is connected to switch S L,i4 Switch S L,i5 and switch S L,i6 The first terminal, switch S L,i1 The second end is connected to V REFP Terminal, switch S L,i4 The second end is connected to V REFP Terminal, switch S L,i2 The second end is connected to V REFN Terminal, switch S L,i5 The second end is connected to V REFN Terminal, switch S L,i3 The second terminal is connected to the input signal V IN (Inverting input voltage) terminal, switch S L,i6 The second terminal is connected to the input signal V IP (Non-inverting input voltage) terminal, where switch S L,i1 and switch S L,i5 Both are sampled and flipped by the P clock signal φ P,i Control, switch S L,i2 and switch S L,i4 All are sampled and flipped by N clock signals φ N,i Control, switch S L,i3 and switch S L,i6 All are sampled by clock signal φ S Control, input signal V IN and input signal V IPThese are two complementary signals in a differential analog input signal pair, when the coarse quantization clock signal φ C When the signal is low, the sampling toggles the P clock signal φ. P,i and sampling toggling N clock signal φ N,i All are low level, when the coarse quantization clock signal φ C When the signal is high, if the digital code of the i-th quantized bit is 1, then the sampling toggles the N-clock signal φ. N,i It is high level, and the toggle clock signal φ is sampled simultaneously. P,i If the quantized result of the i-th bit is 0, then the sampling is toggled by the N-clock signal φ. N,i The signal is low, and the toggle clock signal φ is sampled and flipped simultaneously. P,i The level is high, 1≤i≤n; The second capacitor switch structure includes a capacitor C. R,i1 Capacitor C R,i2 Switch S R,i1 Switch S R,i2 Switch S R,i3 Switch S R,i4 Switch S R,i5 Switch S R,i6 Switch S R,i7 and switch S R,i8 Capacitor C R,i1 The top plate is connected to the second terminal of switch S3, and capacitor C R,i2 The top plate is connected to the second terminal of switch S4, and capacitor C R,i1 The base plate is connected to switch S R,i1 Switch S R,i2 Switch S R,i3 and switch S R,i4 The first terminal, capacitor C R,i2 The base plate is connected to switch S R,i5 Switch S R,i6 Switch S R,i7 and switch S R,i8 The first terminal, switch S R,i1 The second end is connected to V REFP Terminal, switch S R,i5 The second end is connected to V REFP Terminal, switch S R,i2 The second end is connected to V REFN Terminal, switch S R,i6 The second end is connected to V REFN Terminal, switch S R,i3 The second terminal is connected to the input signal V IN Terminal, switch S R,i7 The second terminal is connected to the input signal V IP Terminal, switch S R,i4 The second end is connected to switch S R,i8The second terminal, where switch S R,i2 and switch S R,i5 Both are sampled and flipped by the P clock signal φ P,i Control, switch S R,i1 and switch S R,i6 All are sampled and flipped by N clock signals φ N,i Control, switch S R,i3 and switch S R,i7 All are sampled by clock signal φ S Control, switch S R,i4 and switch S R,i8 Both are generated by charge redistribution clock signal φ R control; The first terminals of both switches S1 and S2 are connected to V. CM The second terminal of switch S1 is connected to n capacitors C. L,i1 The top plates are interconnected at a common node, and the second terminal of switch S2 is connected to n capacitors C. L,i2 The top plates are interconnected at a common node, and the first terminal of switch S3 is connected to n capacitors C. L,i1 The top plates are interconnected at a common node, and the second terminal of switch S3 is connected to n capacitors C. R,i1 The top plates are interconnected at a common node, and the first terminal of switch S4 is connected to n capacitors C. L,i2 The top plates are interconnected at a common node, and the second terminal of switch S4 is connected to n capacitors C. R,i2 The top plates are interconnected by a common node, where switches S1 and S2 are both sampled by a clock signal φ. SA Both switches S3 and S4 are controlled by a decision clock signal φ. D control.

[0017] Furthermore, the quantization result is an n-bit first digital code composed of 0s and 1s (denoted as nb).

[0018] Furthermore, when the first digit code in the i-th position is 0, the capacitor C L,i1 Connect V REFP Terminal, capacitor C L,i2 Connect V REFN Terminal, capacitor C R,i1 Connect V REFN Terminal, capacitor C R,i2 Connect V REFP When the first digit code in the i-th bit is 1, the capacitor C L,i1 Connect the V REFN Terminal, capacitor C L,i2 Connect V REFP Terminal, capacitor C R,i1 Connect V REFP Terminal, capacitor C R,i2 Connect VREFN end.

[0019] In one specific embodiment, please refer to Figure 2 and Figure 6 The LSB DAC includes m groups of third capacitor switch structures. The j-th group of third capacitor switch structures includes a first capacitor switch substructure and a second capacitor switch substructure. The first capacitor switch substructure includes a capacitor C. P,j1 C P,j2 Switch S P,j1 Switch S P,j2 Switch S P,j3 Switch S P,j4 Switch S P,j5 Switch S P,j6 The second capacitor switch substructure includes capacitor C. N,j1 Capacitor C N,j2 Switch S N,j1 Switch S N,j2 Switch S N,j3 Switch S N,j4 Switch S N,j5 Switch S N,j6 , 1≤j≤m, where: Capacitor C P,j1 The top plate and capacitor C N,j1 The top plate is connected to n capacitors C R,i1 The common nodes of the interconnected top plates, capacitor C P,j2 The top plate and capacitor C N,j2 The top plate is connected to n capacitors C R,i2 The common nodes of the interconnected top plates, capacitor C P,j1 The base plate is connected to switch S P,j1 Switch S P,j2 Switch S P,j3 The first terminal, capacitor C N,j1 The base plate is connected to switch S N,j1 Switch S N,j2 Switch S N,j3 The first terminal, capacitor C P,j2 The base plate is connected to switch S P,j4 Switch S P,j5 Switch S P,j6 The first terminal, capacitor C N,j2 The base plate is connected to switch S N,j4 Switch S N,j5 Switch S N,j6 The first terminal, switch S P,j1 and switch S P,j4 The second end is connected to V REFP Terminal, switch S P,j2 and switch S P,j5 The second end is connected to VREFN Terminal, switch S P,j3 The second terminal is connected to the input signal V IN Terminal, switch S P,j6 The second terminal is connected to the input signal V IP Terminal, switch S N,j1 and switch S N,j4 The second end is connected to V REFP Terminal, switch S N,j2 and switch S N,j5 The second end is connected to V REFN Terminal, switch S N,j3 The second terminal is connected to the input signal V IN Terminal, switch S N,j6 The second terminal is connected to the input signal V IP Terminal, of which switch S P,j1 Switch S P,j2 Switch S P,j4 Switch S P,j5 Switch S N,j1 Switch S N,j2 Switch S N,j4 and switch S N,j5 All are controlled by asynchronous SAR output signals, switch S P,j3 Switch S P,j6 Switch S N,j3 and switch S N,j6 All are sampled by clock signal φ S control.

[0020] In one specific embodiment, when the decision clock signal φ D After dropping to a low level, the charge redistribution clock signal φ R The voltage rises to a high level to short-circuit the base plate of some capacitors in the passive charge redistribution DAC, causing charge redistribution to generate a residual voltage, including: When the decision clock signal φ D After dropping to a low level, the charge redistribution clock signal φ R Rise to high level, capacitor C R,i1 Base plate connected capacitor C R,i2 The base plate makes capacitor C R,i1 The base plate and capacitor C R,i2 The base plate is short-circuited to redistribute the charge, generating n capacitors C. R,i1 The top plate and all capacitors C in the m-group third capacitor switch structure P,j1 and capacitor C N,j1 The residual voltage V0 of the top plate, and the generation of n capacitors C R,i2 The top plate and all capacitors C in the m-group third capacitor switch structure P,j2 and capacitor C N,j2The residual voltage V1 of the top plate.

[0021] Optionally, capacitor C L,i1 Capacitor C L,i2 Capacitor C R,i1 and capacitor C R,i2 The values ​​are all arranged in powers of 2, and the capacitance C L,i1 Capacitor C L,i2 Capacitor C R,i1 Capacitor C R,i2 Capacitor C P,j1 Capacitor C N,j1 Capacitor C P,j2 and capacitor C N,j2 The sizes are respectively: (1); in, For unit capacitance, C P,11 C N,11 C P,12 and C N,12 These are the capacitors when j is 1.

[0022] Furthermore, n ranges from 1 to 7, and m ranges from 1 to 15. For example, ... Figure 7 As shown, Figure 7 This is an analog-to-digital converter with n = 5 and m = 13.

[0023] In one specific embodiment, please refer to Figure 1 and Figure 2 The reference voltage-driven analog-to-digital converter also includes: A comparator, with n capacitors C connected to its positive input terminal. R,i1 The top plate and all capacitors C of the third capacitor switch structure of group m P,j1 and capacitor C N,j1 On the top plate, n capacitors C are connected to the negative input terminal of the comparator. R,i2 All capacitors C of the top plate and the m-group third capacitor switch structure P,j2 and capacitor C N,j2 The top plate is used to perform the j-th comparison between the current residual voltage V0 and the current residual voltage V1, so as to output the j-th comparison result; The asynchronous SAR is connected to the output of the comparator. It is used to generate the j-th bit of the m-bit second digital code based on the j-th comparison result, and to perform successive approximation quantization on the LSB DAC based on the split switching timing until the m-th bit of the second digital code is finally obtained. The digital code combination module connects the coarse SAR ADC and the asynchronous SAR, and is used to combine the n-bit first digital code and the m-bit second digital code to obtain and output the digital combination code.

[0024] Specifically, in this embodiment, the LSB DAC uses a split switching timing for quantization. The comparator compares the currently generated residual voltage V0 and residual voltage V1 to obtain the current comparison result and transmits the comparison result to the asynchronous SAR to generate the second digital code corresponding to the comparison result. By performing successive approximation quantization on the LSB DAC through the split switching timing, all m-bit second digital codes will be generated. The coarse SAR ADC transmits the n-bit first digital code to the digital code combination module, and the asynchronous SAR transmits the m-bit second digital code to the digital code combination module. The digital code combination module then combines the n-bit first digital code and the m-bit second digital code into an n+m-bit digital combination code and outputs the n+m-bit digital combination code.

[0025] For example, see Figure 8 n is 2, the quantization result is 10, and the capacitance C L,11 Capacitor C L,22 Capacitor C R,21 Capacitor C R,12 Connect V REFN Terminal, capacitor C L,21 Capacitor C L,12 Capacitor C R,11 Capacitor C R,22 Connect V REFP At the end, the decision clock signal φ D After dropping to a low level, the charge redistribution clock signal φ R Rise to high level, capacitor C R,11 Base plate connected capacitor C R,12 The base plate, capacitor C R,21 Base plate connected capacitor C R,22 The base plate makes capacitor C R,11 The base plate and capacitor C R,12 The base plate is short-circuited, causing capacitor C to... R,21 The base plate and capacitor C R,22 The base plate is short-circuited to redistribute the charge and generate capacitance C. R,11 Capacitor C R,21 All capacitors C in the third capacitor switch structure of group m P,j1 and capacitor C N,j1 The residual voltage V0 of the top plate generates a capacitance C. R,12 Capacitor C R,22 All capacitors C in the third capacitor switch structure of group m P,j2 and capacitor C N,j2 The residual voltage V1 of the top plate, here all the capacitors C of the m-group third capacitor switch structure. P,j1 and capacitor C N,j1 Let it be C dum1 All capacitors C of the third capacitor switch structure in group mP,j2 and capacitor C N,j2 Let it be C dum2 .

[0026] For example, please see Figure 9 If n is 2 and the quantization result is 11, then the capacitance C L,11 Capacitor C L,21 Capacitor C R,12 Capacitor C R,22 Connect V REFN Terminal, capacitor C L,12 Capacitor C L,22 Capacitor C R,11 Capacitor C R,21 Connect V REFP At the end, the decision clock signal φ D After dropping to a low level, the charge redistribution clock signal φ R Rise to high level, capacitor C R,11 Base plate connected capacitor C R,12 The base plate, capacitor C R,21 Base plate connected capacitor C R,22 The base plate makes capacitor C R,11 The base plate and capacitor C R,12 The base plate is short-circuited, causing capacitor C to... R,21 The base plate and capacitor C R,22 The base plate is short-circuited to redistribute the charge and generate capacitance C. R,11 Capacitor C R,21 All capacitors C in the third capacitor switch structure of group m P,j1 and capacitor C N,j1 The residual voltage V0 of the top plate generates a capacitance C. R,12 Capacitor C R,22 All capacitors C in the third capacitor switch structure of group m P,j2 and capacitor C N,j2 The residual voltage V1 of the top plate.

[0027] To analyze the parasitic effects of the analog-to-digital converter provided in this embodiment, an example is given where n is 1 and the quantization result is 0. Please refer to [link to relevant documentation]. Figure 10 Parasitic capacitance is considered in a 1-bit passive charge redistribution DAC, where γ1C R,11 γ2C R,12 Capacitor C R,11 and capacitor C R,12 The parasitic capacitances, γ1 and γ2 are the capacitances C and C, respectively. R,11 and capacitor C R,12 The parasitic coefficient. Under the influence of parasitic capacitance, capacitance C R,11 Voltage after differential shorting of the base plate V CM,par This can be deduced as: (2); in, , , According to formula (1), Therefore, the differential change in the voltage across the top plate of the DAC bit capacitor V n,par This can be deduced as: (3); As shown in formula (3), the differential change in the top plate voltage of the DAC capacitor is not affected by parasitic effects. Therefore, the parasitic capacitance in the passive charge redistribution DAC of this embodiment will only affect the capacitance C. R,i1 Capacitor C R,i2 Voltage after differential shorting of the base plate V CM,par An offset occurs, and V CM,par The difference is canceled out in formula (3), thus not affecting the differential change in the top plate voltage of the DAC bit capacitor. This proves that the parasitic capacitance in the passive charge redistribution DAC of this embodiment does not introduce bit weighting error and input dynamic range loss. Therefore, the solution of this embodiment avoids additional complex adjustments to the capacitor and is more practical.

[0028] Furthermore, when the base plate of the bit capacitor of the passive charge redistribution DAC in this embodiment is connected to V REFP End or V REFN When the reference voltage establishes ripple, it only changes the common-mode voltage and does not affect the sampling accuracy. This is because the midpoint capacitor C in this embodiment... R,i1 Capacitor C R,i2 The differential shorting process for charge redistribution occurs only once, thus eliminating sequence dependency error and avoiding excessive weight calibration.

[0029] In this invention, a novel residual voltage generation scheme is used, which eliminates the use of C while maintaining binary weights. REF,i Therefore, C was completely solved. REF,i The invention addresses the trade-off between area and the kT / C noise it introduces. Secondly, it is insensitive to the parasitic capacitance of the DAC section to which it is applied, and does not introduce bit weighting errors or dynamic range loss, thus avoiding additional complex trimmings and making it easier to scale to more bits. Furthermore, it maintains the same bit capacitor arrangement as conventional split-switching timings, thereby improving manufacturability and practicality.

[0030] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0031] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0032] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A reference voltage easy drive type analog-to-digital converter, characterized by, The fine SAR ADC and the coarse SAR ADC comprise a passive charge redistribution DAC and an LSB DAC, wherein: The fine SAR ADC is used when the sampling clock signal φ SA Sampling clock signal φ S and decision clock signal φ D When the voltage is high, connect the top plate of the DAC bit capacitor of the fine SAR ADC to V. CM The base plate is connected to the input signal terminal, and the sampling clock signal φ SA First, lower the voltage level to disconnect the top plate of the DAC bit capacitor from the V. CM The connection of the terminal, the sampling clock signal φ S The voltage is then lowered to disconnect the base plate of the DAC bit capacitor from the input signal terminal, and the capacitor array of the LSB DAC is connected to V. REFP End or V REFN end; The coarse SAR ADC is configured to quantize the input signal to obtain a quantization result when the coarse quantization clock signal φ C is high, quantize the input signal to obtain a quantization result; The fine SAR ADC is also configured to connect a capacitance array of the passive charge redistribution DAC to the V REFP terminal or the V REFN terminal and disconnect the connection when the coarse quantization clock signal φ C falls to a low level, and when the decision clock signal φ D falls to a low level, the charge redistribution clock signal φ R rises to a high level to short the bottom plate of part of the capacitances in the passive charge redistribution DAC to redistribute the charge to generate a residual voltage.

2. The reference voltage easy drive type analog-to-digital converter according to claim 1, characterized by, The passive charge redistribution DAC comprises n first capacitor switch structures and n second capacitor switch structures which are connected in parallel in sequence, a switch S1, a switch S2, a switch S3 and a switch S4. The first capacitor switch structure comprises a capacitor C L,i1 , a capacitor C L,i2 , a switch S L,i1 , a switch S L,i2 , a switch S L,i3 , a switch S L,i4 , a switch S L,i5 , and a switch S L,i6 The top plate of the capacitor C L,i1 is connected to the second end of the switch S1, the top plate of the capacitor C L,i2 is connected to the second end of the switch S2, the bottom plate of the capacitor C L,i1 is connected to the first end of the switch S L,i1 , the switch S L,i2 , and the switch S L,i3 The bottom plate of the capacitor C L,i2 is connected to the first end of the switch S L,i4 , the switch S L,i5 , and the switch S L,i6 The second end of the switch S L,i1 is connected to the V REFP terminal, the second end of the switch S L,i4 is connected to the V REFP terminal, the second end of the switch S L,i2 is connected to the V REFN terminal, the second end of the switch S L,i5 is connected to the V REFN terminal, the second end of the switch S L,i3 is connected to the input signal V IN terminal, the second end of the switch S L,i6 is connected to the input signal V IP terminal, wherein the switch S L,i1 and the switch S L,i5 are controlled by a sampling flip P clock signal φ P,i , the switch S L,i2 and the switch S L,i4 are controlled by a sampling flip N clock signal φ N,i , the switch S L,i3 and the switch S L,i6 are controlled by the sampling clock signal φ S When the coarse quantization clock signal φ C is low, the sampling flip P clock signal φ P,i and the sampling flip N clock signal φ N,i are low, when the coarse quantization clock signal φ C is high, if the digital code of the i-th bit quantization result is 1, the sampling flip N clock signal φ N,i is high, while the sampling inverting P clock signal φ P,i is low, if the digital code of the i-th quantization result is 0, the sampling inverting N clock signal φ N,i is low, while the sampling inverting P clock signal φ P,i is high, 1≤i≤n; The second capacitor switch structure comprises a capacitor C R,i1 , a capacitor C R,i2 , a switch S R,i1 , a switch S R,i2 , a switch S R,i3 , a switch S R,i4 , a switch S R,i5 , a switch S R,i6 , a switch S R,i7 , and a switch S R,i8 The top plate of the capacitor C R,i1 is connected to the second end of the switch S3, the top plate of the capacitor C R,i2 is connected to the second end of the switch S4, the bottom plate of the capacitor C R,i1 is connected to the first end of the switch S R,i1 , the switch S R,i2 , the switch S R,i3 , and the switch S R,i4 , the bottom plate of the capacitor C R,i2 is connected to the first end of the switch S R,i5 , the switch S R,i6 , the switch S R,i7 , and the switch S R,i8 The second end of the switch S R,i1 is connected to the V REFP terminal, the second end of the switch S R,i5 is connected to the V REFP terminal, the second end of the switch S R,i2 is connected to the V REFN terminal, the second end of the switch S R,i6 is connected to the V REFN terminal, the second end of the switch S R,i3 is connected to the input signal V IN terminal, the second end of the switch S R,i7 is connected to the input signal V IP terminal, the second end of the switch S R,i4 is connected to the second end of the switch S R,i8 , wherein the switch S R,i2 and the switch S R,i5 are controlled by the sampling flip P clock signal φ P,i , the switch S R,i1 and the switch S R,i6 are controlled by the sampling flip N clock signal φ N,i , the switch S R,i3 and the switch S R,i7 are controlled by the sampling clock signal φ S , the switch S R,i4 and the switch S R,i8 both of which are derived from the charge redistribution clock signal φ R control; The first end of the switch S1 and the first end of the switch S2 are connected to V CM The second end of the switch S1 is connected to the common node to which the top plates of the n capacitors C L,i1 are connected to each other, and the second end of the switch S2 is connected to the common node to which the top plates of the n capacitors C L,i2 are connected to each other. The first end of the switch S3 is connected to the common node to which the top plates of the n capacitors C L,i1 are connected to each other, and the second end of the switch S3 is connected to the common node to which the top plates of the n capacitors C R,i1 are connected to each other. The first end of the switch S4 is connected to the common node to which the top plates of the n capacitors C L,i2 are connected to each other, and the second end of the switch S4 is connected to the common node to which the top plates of the n capacitors C R,i2 are connected to each other. The switch S1 and the switch S2 are controlled by the sampling clock signal φ SA , and the switch S3 and the switch S4 are controlled by the decision clock signal φ D .

3. The reference voltage easy drive type analog-to-digital converter according to claim 2, characterized by, The quantization result is an n-bit first digital code composed of 0 and 1.

4. The reference voltage easy drive type analog-to-digital converter according to claim 3, characterized by When the first digital code is 0 at the i-th bit, the capacitor C L,i1 connects the V REFP terminal, the capacitor C L,i2 connects the V REFN terminal, the capacitor C R,i1 connects the V REFN terminal, the capacitor C R,i2 connects the V REFP terminal, when the first digital code is 1 at the i-th bit, the capacitor C L,i1 connects the V REFN terminal, the capacitor C L,i2 connects the V REFP terminal, the capacitor C R,i1 connects the V REFP terminal, the capacitor C R,i2 connects the V REFN terminal.

5. The reference voltage easy drive type analog-to-digital converter according to claim 3, wherein The LSB DAC includes m groups of third capacitor switch structures, the jth group of the third capacitor switch structures includes a first capacitor switch substructure and a second capacitor switch substructure, the first capacitor switch substructure includes a capacitor C P,j1 P,j2 P,j1 P,j2 P,j3 P,j4 P,j5 P,j6 The second capacitor switch substructure includes a capacitor C N,j1 N,j2 N,j1 N,j2 N,j3 N,j4 N,j5 N,j6 1≤j≤m, wherein:​​​​​​​​​​​​​​ the top plate of the capacitor C P,j1 the top plate of the capacitor C N,j1 the top plate of the capacitor C R,i1 the top plate of the capacitor C P,j2 the top plate of the capacitor C N,j2 the top plate of the capacitor C R,i2 the top plate of the capacitor C P,j1 the bottom plate of the capacitor C P,j1 the bottom plate of the capacitor C P,j2 the bottom plate of the capacitor C P,j3 the bottom plate of the capacitor C N,j1 the bottom plate of the capacitor C N,j1 the bottom plate of the capacitor C N,j2 the bottom plate of the capacitor C N,j3 the bottom plate of the capacitor C P,j2 the bottom plate of the capacitor C P,j4 the bottom plate of the capacitor C P,j5 the bottom plate of the capacitor C P,j6 the bottom plate of the capacitor C N,j2 the bottom plate of the capacitor C N,j4 the bottom plate of the capacitor C N,j5 the bottom plate of the capacitor C N,j6 the first end of the switch S P,j1 and the second end of the switch S P,j4 are connected to the V REFP terminal, the second end of the switch S P,j2 and the second end of the switch S P,j5 are connected to the V REFN terminal, the second end of the switch S P,j3 is connected to the input signal V IN terminal, the second end of the switch S P,j6 is connected to the input signal V IP terminal, the second end of the switch S N,j1 and the second end of the switch S N,j4 are connected to the V REFP terminal, the second end of the switch S N,j2 and the second end of the switch S N,j5 are connected to the V REFN terminal, the second end of the switch S N,j3 is connected to the input signal V IN terminal, the second end of the switch S N,j6 is connected to the input signal V IP terminal, wherein the switch S P,j1 , the switch S P,j2 , the switch S P,j4 , the switch S P,j5 , the switches S N,j1 , the switches S N,j2 , the switches S N,j4 , and the switches S N,j5 are controlled by the asynchronous SAR output signal, the switches S P,j3 , the switches S P,j6 , the switches S N,j3 , and the switches S N,j6 are controlled by the sampling clock signal φ S .

6. The reference voltage easy drive type analog-to-digital converter according to claim 5, wherein The capacitance C L,i1 The capacitance C L,i2 The capacitance C R,i1 The capacitance C R,i2 is of the order of: ； The capacitance C P,j1 The capacitance C N,j1 The capacitance C P,j2 The capacitance C N,j2 is of the order of ； wherein, C is the unit capacitance, P,11 C N,11 C P,12 and C N,12 are the capacitances for j = 1, respectively.

7. The reference voltage easy drive type analog-to-digital converter according to claim 6, characterized by n is in the range of 1-7, and m is in the range of 1-15.

8. The reference voltage easy drive type analog-to-digital converter according to claim 5, wherein when the decision clock signal φ D goes low, the charge redistribution clock signal φ R goes high to short the bottom plate of a portion of the capacitors in the passive charge redistribution DAC, causing charge redistribution to generate a residue voltage, comprising: When the decision clock signal φ D is lowered to the low level, the charge redistribution clock signal φ R is raised to the high level, the bottom plate of the capacitor C R,i1 is connected to the bottom plate of the capacitor C R,i2 , the bottom plate of the capacitor C R,i1 is shorted to the bottom plate of the capacitor C R,i2 , to redistribute the charges, to generate the residual voltage V0 between the top plate of the capacitor C R,i1 and the top plate of all the capacitors C P,j1 and C N,j1 in the m groups of the third capacitor switch structure, and to generate the residual voltage V1 between the top plate of the capacitor C R,i2 and the top plate of all the capacitors C P,j2 and C N,j2 in the m groups of the third capacitor switch structure.

9. The reference voltage easy drive type analog-to-digital converter according to claim 8, characterized by, Further comprising: a comparator, a positive input terminal of the comparator being connected to the top plate of n capacitors C R,i1 of the m groups of the third capacitor switch structures P,j1 and the top plate of the capacitors C N,j1 , a negative input terminal of the comparator being connected to the top plate of n capacitors C R,i2 of the m groups of the third capacitor switch structures P,j2 and the top plate of the capacitors C N,j2 , for comparing the current residual voltage V0 and the current residual voltage V1 for the jth time to output a jth comparison result. An asynchronous SAR connected to the output end of the comparator, for generating a jth bit of a m-bit second digital code according to the jth comparison result, and performing successive approximation quantization on the LSB DAC based on split switch timing until a mth bit of the second digital code is obtained.

10. The reference voltage easy drive type analog-to-digital converter according to claim 9, characterized by, Further comprising: A digital code combination module for combining the n-bit first digital code and the m-bit second digital code to obtain and output a digital combination code.

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