A phase adjustment method and serdes system

Abstract

The application provides a phase adjustment method and a Serdes system, and relates to the technical field of high-speed serial communication. First, a code to be moved in a current period and a code to be moved in a next period are acquired, and a total increment of code movement is determined; then, according to a ratio of a working clock frequency of a phase interpolator to a working clock frequency of a CDR circuit, the total increment of code movement is split into N sub-increments, and a sub-increment sequence is formed; wherein the working clock frequency of the phase interpolator is greater than the working clock frequency of the CDR circuit, and an absolute value of a difference of the sub-increment sequence is less than or equal to 1, and N is a positive integer; finally, according to a timing relationship, the sub-increment sequence is sent to the phase interpolator, so that the phase interpolator realizes phase adjustment according to the sub-increment sequence in continuous N clock periods. The application has the advantage of suppressing dynamic jitter of an output clock.

Description

Technical Field

[0001] This application relates to the field of high-speed serial communication technology, and more specifically, to a phase adjustment method and a SerDes system. Background Technology

[0002] In modern high-speed serial communication systems, such as PCI Express (PCIe) and Ethernet, serializer / deserializer (SerDes) technology is the core of high-speed data transmission. The receiver of a SerDes must accurately recover the clock signal from the received data stream for precise data sampling. This crucial function is achieved by the Clock Data Recovery (CDR) circuit. The CDR circuit dynamically adjusts the phase of the local clock to align it with the center of the eye diagram of the input data stream, thus ensuring reliable sampling. The Phase Interpolator (PI), as a key execution component in the CDR circuit loop, is responsible for shifting the phase of the local clock according to the control code calculated by the CDR circuit to track changes in the data transmitted.

[0003] In existing technologies, CDR circuits are typically implemented based on digital or mixed-signal architectures. The CDR circuit algorithm calculates a phase adjustment control code in each operating cycle and directly passes this code to the phase interpolator. Upon receiving the code, the phase interpolator completes the corresponding phase shift within one clock cycle.

[0004] However, when the difference between adjacent control codes calculated by the CDR circuit is large, the phase interpolator needs to make a large phase step adjustment, which leads to a significant increase in the dynamic jitter (DJ) of the output clock. This dynamic jitter will directly affect signal integrity and data sampling, and will also affect system function and stability.

[0005] Existing solutions often focus on optimizing the CDR circuit algorithm itself to reduce instantaneous code changes, or on increasing the phase resolution of the phase interpolator to reduce the phase shift corresponding to each minimum step size, thereby avoiding dynamic jitter in the output clock. However, these methods often face trade-offs between algorithm complexity, circuit area, power consumption, and performance improvement, and cannot fundamentally eliminate the inherent jitter caused by step phase adjustments due to large code jumps.

[0006] In summary, existing technologies suffer from the problem of difficulty in eliminating dynamic jitter in the output clock. Summary of the Invention

[0007] The purpose of this application is to provide a phase adjustment method and a Serdes system to solve the problem of the difficulty in eliminating dynamic jitter of the output clock in the prior art.

[0008] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0009] On one hand, embodiments of this application provide a phase adjustment method, the method comprising:

[0010] Obtain the code that needs to be moved in the current period and the code that needs to be moved in the next period, and determine the total increment of code movement;

[0011] Based on the ratio of the operating clock frequency of the phase interpolator to the operating clock frequency of the CDR circuit, the total code movement increment is divided into N sub-increments and formed into a sub-increment sequence; wherein, the operating clock frequency of the phase interpolator is greater than the operating clock frequency of the CDR circuit, and the absolute value of the difference between the code movement increments of any two sub-increment sequences is less than or equal to 1, and N is a positive integer;

[0012] According to the timing relationship, the sub-increment sequence is sent to the phase interpolator so that the phase interpolator can perform phase adjustment according to the sub-increment sequence over N consecutive clock cycles.

[0013] On the other hand, embodiments of this application also provide a SerDes system, which includes an ADC sampling module, a CDR circuit, a phase interpolator, and a sub-increment generation module. The ADC sampling module is connected to the CDR circuit, and the CDR circuit, the sub-increment generation module, and the phase interpolator are connected sequentially. The phase interpolator is connected to the ADC.

[0014] The sub-increment generation module is used to divide the total code movement increment into N sub-increments based on the ratio of the operating clock frequency of the phase interpolator to the operating clock frequency of the CDR circuit, and form a sub-increment sequence. The operating clock frequency of the phase interpolator is greater than the operating clock frequency of the CDR circuit, and the absolute value of the difference between the code movement increments of any two sub-increment sequences is less than or equal to 1. N is a positive integer, and the total code movement increment is determined based on the code to be moved in the current cycle and the code to be moved in the next cycle.

[0015] The sub-increment generation module is further configured to send the sub-increment sequence to the phase interpolator according to the timing relationship, so that the phase interpolator can perform phase adjustment according to the sub-increment sequence in N consecutive clock cycles.

[0016] Compared with the prior art, this application has the following advantages:

[0017] This application provides a phase adjustment method and a SerDes system. First, the code to be moved in the current cycle and the code to be moved in the next cycle are obtained, and the total code movement increment is determined. Then, based on the ratio of the operating clock frequency of the phase interpolator to the operating clock frequency of the CDR circuit, the total code movement increment is divided into N sub-increments, which form a sub-increment sequence. The operating clock frequency of the phase interpolator is greater than the operating clock frequency of the CDR circuit, and the absolute value of the difference between the code movement increments of any two sub-increment sequences is less than or equal to 1, where N is a positive integer. Finally, the sub-increment sequence is sent to the phase interpolator according to the timing relationship, so that the phase interpolator can perform phase adjustment according to the sub-increment sequence in N consecutive clock cycles.

[0018] This application fundamentally avoids the clock phase abrupt changes caused by a single large jump by dividing the large total code movement increment into N sub-increments. Each sub-increment only needs to move a small amount of code, thus changing the time domain change of the clock phase from a "step" to a "gradual change," thereby directly and significantly suppressing the dynamic jitter of the output clock. At the same time, this application can ensure that the absolute value of the difference between any two sub-increments after the division is ≤1, thus ensuring that the entire adjustment process is smooth and eliminating the additional periodic jitter caused by uneven adjustment.

[0019] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the clock waveform after normal timing and phase shift provided in an embodiment of this application.

[0022] Figure 2 An exemplary flowchart of the phase adjustment method provided in the embodiments of this application.

[0023] Figure 3 This is a schematic diagram illustrating code changes provided in an embodiment of this application.

[0024] Figure 4 A schematic diagram of the hardware implementation of the first-level decomposition is provided for the embodiments of this application.

[0025] Figure 5 This is a schematic diagram of a module of the Serdes system provided in an embodiment of this application.

[0026] Figure 6 This is a schematic diagram of another module of the Serdes system provided in an embodiment of this application.

[0027] In the picture:

[0028] 110 - ADC sampling module; 120 - CDR circuit; 130 - Sub-increment generation module; 131 - First-level distribution module; 132 - Second-level distribution module; 133 - Selector; 140 - Phase interpolator; 150 - Code conversion module; 160 - FFE; 170 - DFE. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0031] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0032] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0033] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0034] As described in the background section, in ultra-high-speed protocols such as PCIe Gen6 / Gen7, the CDR circuit may operate at a clock frequency of 1 GHz, while the phase interpolator may need to operate at a higher frequency (e.g., 8 GHz) to provide sufficient phase resolution. Each phase interpolator control code corresponds to a minimum phase shift step size (e.g., in the 8 GHz clock domain, the minimum phase shift step size for a 256-bit control code is approximately 0.488 ps). If the code difference (i.e., the phase adjustment increment) calculated by the CDR circuit algorithm in two consecutive cycles is large, the phase interpolator's shift step size will increase, resulting in significant dynamic jitter in the phase interpolator's output clock. For example, if the difference is 6-7 codes in two consecutive cycles, the phase interpolator will complete a phase jump on the order of picoseconds in a very short time window (e.g., one 8 GHz cycle, 125 ps). This discrete, non-continuous phase jump directly translates into timing jitter in the output clock, degrading the integrity of the clock signal.

[0035] For example, please see Figure 1 The diagram shows the corresponding waveform. Under normal timing, the phase of the output is fixed for each clock cycle. When a phase transition is required, triggered by the rising edge, the phase transition is completed within one clock cycle. Figure 1 The phase jump variable L. Understandably, the larger the code difference between two consecutive clock cycles, the larger the phase jump variable, meaning the longer the distance of L. However, when the distance of L is too long, it will cause timing jitter in the output clock.

[0036] This increase in jitter can have a series of negative consequences: First, it reduces the effective eye diagram margin for data sampling, increases the bit error rate (BER), and decreases the reliability of system transmission. Second, in high-speed links, accumulated jitter may violate the jitter budget specification of the protocol, leading to link training failure or performance degradation. Furthermore, large phase transitions can introduce additional electromagnetic interference (EMI) problems.

[0037] Existing solutions often focus on optimizing the CDR circuit algorithm itself (such as improving the phase detection logic or filtering algorithm) to reduce instantaneous code changes, or on reducing the phase shift corresponding to each minimum step size by increasing the phase resolution of the phase interpolator (i.e., increasing the control code bit width). However, these methods often face trade-offs between algorithm complexity, circuit area, power consumption, and performance improvement, and cannot fundamentally eliminate the inherent jitter caused by the step phase adjustment due to large code jumps.

[0038] Therefore, there is an urgent need for an innovative technology that can "smooth" the phase control code between the CDR circuit and the phase interpolator. Without changing the core algorithm of the CDR circuit and the basic structure of the phase interpolator, the large-scale phase adjustment is decomposed into distributed and small-scale progressive adjustments, thereby suppressing the dynamic jitter of the output clock of the phase interpolator from the root cause and improving the tracking performance and system stability of the entire CDR circuit loop.

[0039] In view of this, the present application provides a phase adjustment method to solve the above problems. As an implementation, please refer to Figure 2 , the method includes:

[0040] S102, obtain the code to be moved in the current cycle and the code to be moved in the next cycle, and determine the total code movement increment.

[0041] S104, according to the ratio of the operating clock frequency of the phase interpolator to the operating clock frequency of the CDR circuit, split the total code movement increment into N sub-increments and form a sub-increment sequence; wherein, the operating clock frequency of the phase interpolator is greater than the operating clock frequency of the CDR circuit, and the absolute value of the difference between the code movement increments of any two sub-increment sequences is less than or equal to 1, and N is a positive integer.

[0042] S106, send the sub-increment sequence to the phase interpolator according to the timing relationship, so that the phase interpolator realizes phase adjustment according to the sub-increment sequence within N consecutive clock cycles.

[0043] It can be understood that in the method provided by the application, on the one hand, by splitting the large total code movement increment into N sub-increments, each sub-increment only needs to move a smaller code, thereby fundamentally avoiding the clock phase mutation caused by a single large jump, and changing the time-domain change of the clock phase from "step" (in this application, step means a large phase jump amount) to "smooth change", thus directly and significantly suppressing the dynamic jitter of the output clock. On the other hand, the present application can ensure that the absolute value of the difference between any two sub-increments after splitting is ≤1, thereby ensuring that the entire adjustment process is smooth and eliminating the additional periodic jitter caused by uneven adjustment amounts.

[0044] As an optional implementation, the total code movement increment satisfies:

[0045] When A > B, C = A - B;

[0046] When A < B, C = 9’h100 - B + A;

[0047] Where A represents the code to be moved in the next cycle, B represents the code to be moved in the current cycle, C represents the total increment of code movement, and 9'h100 represents 256 in hexadecimal.

[0048] It should be noted that the total code movement increment mentioned in this application refers to the number of codes that need to be moved when jumping from the current cycle to the next cycle. Furthermore, the codes to be moved in the current cycle and the codes to be moved in the next cycle are calculated by the algorithm of the CDR circuit.

[0049] It's also important to note that "code" stands for Phase Control Code. In a CDR circuit, it refers to a digitally quantized control word used to precisely indicate how much the phase of the local sampling clock needs to be shifted by the phase interpolator. It acts as a bridge mapping phase offset to digital code. Generally, "code" is an 8-bit binary number, corresponding to a decimal range of 0 to 255. These 256 discrete values ​​correspond to 256 discrete phase points within a complete cycle (360°) of the phase interpolator's output clock phase. Furthermore, "code" corresponds to a minimum resolution shift of the phase interpolator's output clock phase. For example, if the phase interpolator's reference clock period is 125ps (8GHz) and the "code" bit width is 256, then 1 "code" ≈ 125ps / 256 ≈ 0.488ps (time), or 360° / 256 ≈ 1.406° (phase). Therefore, after sending the "code" value to the phase interpolator, the phase interpolator can determine the total phase shift required by multiplying the "code" value by the minimum step size. For example, when code equals 1, it means that the phase interpolator needs to control the current clock phase to shift by 1.406°; when code equals 2, it means that the phase interpolator needs to control the current clock phase to shift by 2.812°, and so on.

[0050] Furthermore, the code exhibits cyclicity; due to its periodic phase, it returns to its origin after rotating 360°. Therefore, as the code increases from 255 to 256, its effective value cycles around 0. For example... Figure 3 As shown, the code increases clockwise. When it increases to 255, that is, from 255 to 256, the code becomes 0.

[0051] Based on this, when determining the total increment for code movement, two cases need to be considered. One case is that the amount of code to be moved in the next cycle is greater than the amount to be moved in the current cycle. In this case, the two are simply subtracted. For example, if the amount of code to be moved in the next cycle is 50 and the amount to be moved in the current cycle is 25, then the total increment for code movement is AB = 50 - 25 = 25. That is, a total of 25 codes need to be moved from the current cycle to the next cycle.

[0052] Another scenario is that the code to be moved in the next cycle is less than the code to be moved in the current cycle. Since phase adjustment is unidirectional tracking (e.g., ...), Figure 3 (In the clockwise direction), this will manifest as a phase wrapping phenomenon, meaning the phase has completed one cycle. For the path between the code to be moved in the current cycle and the code to be moved in the next cycle, the path is B→255→0→A. Therefore, the total increment of code movement needs to be expressed as 256-B+A. For example, if the code to be moved in the next cycle is 25 and the code to be moved in the current cycle is 50, then the total increment of code movement is determined to be 256-B+A =256-50+25=231, meaning that a total of 231 codes need to be moved from the current cycle to the next cycle.

[0053] After determining the total code shift increment, it needs to be distributed, so that the output clock of the phase interpolator exhibits a small phase shift over multiple clock cycles, rather than a one-time phase shift (a large phase shift) based on the total code shift increment within a single clock cycle. This effectively avoids large output clock jitter. The terms "distribution" and "splitting" used in this application refer to distributing the change in a single clock cycle relatively evenly across multiple clock cycles, thereby replacing large abrupt changes within a single clock cycle with small step changes over multiple clock cycles.

[0054] It should be noted that the data frequency output by the ADC sampling module differs under different protocol rates. Currently, under PCIe 7.0, PCIe 6.0, PCIe 5.0, and PCIe 4.0 protocol rates, the output clock frequency of the ADC sampling module is 1 GHz. Under PCIe 3.0, PCIe 2.0, and PCIe 1.0 protocol rates, the output clock frequencies of the ADC sampling module are 500 MHz, 250 MHz, and 125 MHz, respectively. To ensure compatibility with all protocol rates, this application employs different methods to distribute the total code shift increment for different output clock frequencies.

[0055] For example, S104 includes:

[0056] When the operating clock frequency of the CDR circuit is equal to 1G, the total code shift increment is divided into N sub-increments based on the ratio of the operating clock frequency of the phase interpolator to the 1G clock frequency.

[0057] When the operating clock frequency of the CDR circuit is less than 1G, the total code shift increment is distributed to the 1G clock frequency to obtain M intermediate sub-increments; each intermediate sub-increment is divided into P sub-increments according to the ratio of the operating clock frequency of the phase interpolator to the 1G clock frequency; and N = M × P.

[0058] In this application, for scenarios where the ADC output clock frequency is 1 GHz, the total code shift increment is directly distributed to the operating clock frequency of the phase interpolator. For scenarios where the ADC output clock frequency is less than 1 GHz (500 MHz / 250 MHz / 125 MHz), the total code shift increment needs to be distributed in two stages: the first stage distributes the code from 500 MHz / 250 MHz / 125 MHz to 1 GHz, and the second stage distributes the code from 1 GHz to the operating clock frequency of the phase interpolator.

[0059] Specifically, when the operating clock frequency of the CDR circuit is less than 1 GHz, the steps for distributing the total code shift increment to a 1 GHz clock frequency include:

[0060] First, the intermediate sub-increment M is determined based on the ratio of the 1G clock frequency to the operating clock frequency of the CDR circuit. Next, the total code shift increment is right-shifted by log2(M) bits, and the integer part and remainder part are taken. Finally, the integer part is assigned to each intermediate sub-increment, and the remainder part is evenly distributed among the M intermediate sub-increments, with the value of each intermediate sub-increment equal to the integer part plus the remainder part.

[0061] In the first stage of the decomposition process, it is necessary to first determine the number of intermediate sub-increments M. The number of intermediate sub-increments M represents how many parameters need to be broken down into when the operating clock frequency of the CDR circuit is decomposed to 1GHz, that is, how many parts it needs to be decomposed into. For example, when the operating clock frequency of the CDR circuit is 500MHz, the number of intermediate sub-increments M is 1GHz / 500MHz = 2, that is, the intermediate sub-increment is 2; when the operating clock frequency of the CDR circuit is 250MHz, the number of intermediate sub-increments M is 1GHz / 250MHz = 4, that is, the intermediate sub-increment is 4; when the operating clock frequency of the CDR circuit is 125MHz, the number of intermediate sub-increments M is 1GHz / 125MHz = 8, that is, the intermediate sub-increment is 8.

[0062] Based on this, during the first-level shuffling process, when the CDR circuit's operating clock frequency is 500MHz, two intermediate sub-increments are generated. The total code shift increment is shifted right by 1 bit, and the integer part and remainder part are taken. The integer part is allocated to the two intermediate sub-increments, and the remainder part is allocated to one of the intermediate sub-increments. When the CDR circuit's operating clock frequency is 250MHz, four intermediate sub-increments are generated. The total code shift increment is shifted right by 2 bits, and the integer part and remainder part are taken. The integer part is allocated to the four intermediate sub-increments, and the remainder part is evenly distributed among the four intermediate sub-increments. When the CDR circuit's operating clock frequency is 125MHz, eight intermediate sub-increments are generated. The total code shift increment is shifted right by 3 bits, and the integer part and remainder part are taken. The integer part is allocated to the eight intermediate sub-increments, and the remainder part is evenly distributed among the eight intermediate sub-increments.

[0063] The following section uses a CDR circuit with an operating clock frequency of 125MHz as an example to explain the first-stage breakup process in detail:

[0064] When the CDR circuit operates at a clock frequency of 125MHz (PCIe 1.0), the intermediate sub-increment M is determined to be 8 (1G / 125M=8). The total code movement increment is shifted right by 3 bits, and then the integer part and remainder part are distributed among the 8 intermediate sub-increments. For example, if the total code movement increment is 10, its binary representation is 00001010. Shifting 00001010 right by 3 bits yields an integer part of binary 00001 and a remainder part of binary 010. In decimal, the integer part is 1 and the remainder part is 2. The integer part is then distributed among the 8 intermediate sub-increments, and the remainder part is evenly distributed among them. Thus, the intermediate sub-increments not allocated a remainder part have a value of 1, and the intermediate sub-increments allocated a remainder part have a value of 2.

[0065] As one implementation method, for a CDR circuit operating at a clock frequency of 125MHz, the corresponding lookup table is set as follows:

[0066] C_shift0=C>>3

[0067] A[7:0]= C[2:0]==1 ? 8'b00000001:

[0068] C[2:0]==2 ? 8'b00010001:

[0069] C[2:0]==3 ? 8'b10010001:

[0070] C[2:0]==4 ? 8'b01010101:

[0071] C[2:0]==5? 8'b11010101:

[0072] C[2:0]==6? 8'b11011101:

[0073] C[2:0]==7? 8'b11111101;

[0074] C0=C_shift0+A[0]; C1=C_shift0+A[1]; C2=C_shift0+A[2]; C3=C_shift0+A[3];

[0075] C4=C_shift0+A[4]; C5=C_shift0+A[5]; C6=C_shift0+A[6]; C7=C_shift0+A[7].

[0076] Here, C>>3 indicates that the total increment of the code is shifted to the right by 3. A[7:0] represents a vector, which corresponds to 8 intermediate sub-increments (C0~C7). When A[x] = 1, the corresponding intermediate sub-increment Cx needs to be increased by 1 based on the base value C_shift0 (integer part). When A[x] = 0, the corresponding intermediate sub-increment Cx only takes the base value C_shift0. C[2:0] represents the remainder, which ranges from 000 to 111, and also indicates the number of "1"s that need to be allocated.

[0077] As can be seen from the lookup table, after determining the remainder, the corresponding remainder allocation method can be determined. For example, when the remainder is 1, the corresponding item "C[2:0]==1 ? 8'b00000001:" can be found. In this item, 1 is allocated to the last intermediate sub-increment, and 0 is allocated to the other intermediate sub-increments. Therefore, only the value of the last intermediate sub-increment is C7=C_shift0+1, and the value of the other intermediate sub-increments is C_shift0.

[0078] Similarly, when the remainder is 3, we can find the corresponding item "C[2:0]==3 ? 8'b10010001:". In this item, the three 1s are assigned to the first, fourth, and eighth intermediate sub-increments, respectively, and the remaining intermediate sub-increments are assigned 0. Therefore, the corresponding output is C0=C_shift0+1; C1=C_shift0; C2=C_shift0; C3=C_shift0+1; C4=C_shift0; C5=C_shift0; C6=C_shift0; C7=C_shift0+1.

[0079] In a practical example, if the total increment of code movement is 10, then C_shift0=1 with a remainder of 2. Using the corresponding lookup table, we can determine that "C[2:0]==2 ? 8'b00010001:" means the value of the fourth intermediate sub-increment is increased by 1, and the value of the eighth intermediate sub-increment is increased by 1. The corresponding final output is C0=1; C1=1; C2=1; C3=2; C4=1; C5=1; C6=1; C7=2.

[0080] Of course, there is no single way to set up the lookup table. The above is just an example. For example, for the case where the remainder is 2, the lookup table can also be set to "C[2:0]==2 ? 8'b10001000". In this case, if the total increment of code movement is 10, the corresponding final output is C0=2; C1=1; C2=1; C3=1; C4=2; C5=1; C6=1; C7=1.

[0081] It should be noted that, in the above-mentioned first-level shuffling process, in terms of hardware implementation, the values ​​of intermediate sub-increments can be output separately using selectors. Please refer to [link / reference]. Figure 4 In terms of hardware, selectors and counters can be configured. The counter increments by 1 for each intermediate sub-increment value output. Taking C0=1; C1=1; C2=1; C3=2; C4=1; C5=1; C6=1; C7=2 as an example, after the first-level shuffling, the intermediate sub-increments are sent sequentially to the second-level shuffling module via the selector. First, the selector will choose cnt0=0 for output, i.e., output C0. After C0 is output, cnt0 increments by 1, becoming cnt0=1, at which point C1 is output; after C1 is output, cnt0 increments by 1, becoming cnt0=2, at which point C2 is output, and so on, until all 8 intermediate sub-increments are output.

[0082] After the first-stage scattering, a second-stage scattering is required to distribute the intermediate sub-increments of the 1G clock domain to the clock domain of the phase interpolator. It should be noted that this application does not limit the operating clock frequency of the phase interpolator; for example, it can be 4G, 8G, or 16G, as long as the operating clock frequency of the phase interpolator is greater than the operating clock frequency of the CDR circuit. For ease of explanation, the following example uses an 8G operating clock frequency for the phase interpolator.

[0083] Understandably, for a CDR circuit operating at a clock frequency of 1GHz, the total code shift increment can be directly distributed to the 8GHz clock domain via a two-stage distribution process. However, for a CDR circuit operating at a clock frequency of 1GHz, the total code shift increment needs to be distributed to the 1GHz clock domain first, and then... Figure 4The output shown is C_mux[7:0]. Then, the C_mux[7:0] in the 1G clock domain is distributed to the 8G clock domain.

[0084] When the operating clock frequency of the CDR circuit is equal to 1 GHz, the step of dividing the total code shift increment into N sub-increments based on the ratio of the operating clock frequency of the phase interpolator to the 1 GHz clock frequency includes:

[0085] The number N of sub-increments is determined by the ratio of the operating clock frequency of the phase interpolator to the 1G clock frequency;

[0086] Shift the total increment of the code to the right by log2(N) bits and take the integer part and the remainder;

[0087] The integer part is assigned to each sub-increment, and the remainder part is evenly distributed among the N sub-increments, with the value of each sub-increment equal to the integer part plus the remainder part.

[0088] The corresponding lookup table is represented as follows:

[0089] C_shift1=C_mux[7:0]>>3;

[0090] A1[7:0]= C_mux[2:0]==1 ? 8'b00000001:

[0091] C_mux[2:0]==2? 8'b00010001:

[0092] C_mux [2:0]==3 ? 8'b10010001:

[0093] C_mux [2:0]==4 ? 8'b01010101:

[0094] C_mux [2:0]==5? 8'b11010101:

[0095] C_mux [2:0]==6? 8'b11011101:

[0096] C_mux [2:0]==7? 8'b11111101:

[0097] F0=C_shift1+A1[0]; F1=C_shift1+A1[1]; F2=C_shift1+A1[2]; F3=C_shift1+A1[3]; F4=C_shift1+A1[4]; F5=C_shift1+A1[5]; F6=C_shift1+A1[6]; F7=C_shift1+A1[7].

[0098] Where shift1 represents the "right shift" operation in the second-level shuffling, C_shift1 represents the integer part after the right shift, and C_mux[7:0] represents the intermediate sub-increment output after the first-level shuffling. If the operating clock frequency of the CDR circuit is equal to 1GHz, then there is no C_mux[7:0]. A1[7:0] represents a vector, which corresponds to 8 sub-increments (F0~F7). When A1[x] = 1, the corresponding sub-increment Fx needs to be added 1 to the base value C_shift1 (integer part). When A1[x] = 0, the corresponding sub-increment Fx only takes the base value C_shift1. C_mux[2:0] represents the remainder, which ranges from 000 to 111, and also represents the number of "1"s that need to be allocated.

[0099] Based on this, for the case where the operating clock frequency of the CDR circuit is equal to 1G, it is only necessary to determine the corresponding sub-increment value by moving the total code increment according to the above lookup table, and then output the 8-bit sub-increment sequence.

[0100] For example, if the total increment of code movement is 20, then C_shift0=2, with a remainder of 4. Using the corresponding lookup table, we can determine that "C_mux [2:0]==4 ? 8'b01010101:" means the values ​​of the second, fourth, sixth, and eighth sub-increments are incremented by 1. The corresponding sub-increments are F0=2; F1=3; F2=2; F3=3; F4=2; F5=3; F6=2; F7=3. After the sub-increment sequence (23232323) is sent to the phase interpolator, the phase interpolator can adjust the phase over the next 8 clock cycles based on the sub-increment sequence. Specifically, the first clock cycle is shifted by 2 codes, the second clock cycle by 3 codes, the third clock cycle by 2 codes, the fourth clock cycle by 3 codes, the fifth clock cycle by 2 codes, the sixth clock cycle by 3 codes, the seventh clock cycle by 2 codes, and the eighth clock cycle by 3 codes. This avoids shifting 20 codes at once in a single cycle, making the phase adjustment smoother and significantly reducing the dynamic jitter of the output clock.

[0101] Of course, there is no single way to set up the lookup table. The above is just an example. For example, for the case where the remainder is 4, the lookup table can also be set to "C_mux [2:0]==4 ? 8'b10101010:". In this case, if the total increment of code movement is 20, the corresponding final output will be F0=3; F1=2; F2=3; F3=2; F4=3; F5=2; F6=3; F7=2.

[0102] For the case where the operating clock frequency of the CDR circuit is less than 1GHz, it first undergoes a first-stage shuffling process to obtain M intermediate sub-increments. Then, each intermediate sub-increment is processed according to the above-mentioned second-stage shuffling method, and each intermediate sub-increment is further divided into P sub-increments. Therefore, the sub-increment N = M × P.

[0103] As can be seen, when the CDR circuit operates at a clock frequency of 1 GHz, the total code shift increment is divided into 8 sub-increments, allowing the phase interpolator to perform phase adjustment according to the sub-increment sequence over 8 consecutive clock cycles. However, when the CDR circuit operates at a clock frequency less than 1 GHz, the total code shift increment is first divided into M intermediate sub-increments, and then each intermediate sub-increment is further divided into 8 sub-increments, resulting in more than 8 sub-increments. For example, if the CDR circuit operates at a clock frequency of 500 MHz, the total code shift increment is first divided into 2 intermediate sub-increments, and then each intermediate sub-increment is further divided into 8 sub-increments. Therefore, the total number of sub-increments is 16, and the phase interpolator needs to perform phase adjustment according to the sub-increment sequence over 16 consecutive clock cycles.

[0104] Taking a total code movement increment of 50 as an example, if the operating clock frequency of the CDR circuit is 1G, then according to the above lookup table, the values ​​of the 8 sub-increments can be determined as "6 / 6 / 6 / 7 / 6 / 6 / 6 / 7". After the sub-increment sequence is sent to the phase interpolator, the phase interpolator performs phase adjustment according to the sub-increment sequence within 8 consecutive clock cycles. If the total code shift increment is still equal to 50, but the CDR circuit's operating clock frequency is 250MHz, then a first-stage shuffling is required. Using the lookup table mentioned above, the values ​​of the four intermediate sub-increments are determined to be "12 / 13 / 12 / 13". Then, each intermediate sub-increment is shuffled a second time. Using the lookup table again, the values ​​of the eight sub-increments after shuffling the first, second, and third intermediate sub-increments are determined to be "1 / 2 / 1 / 2 / 1 / 2 / 1 / 2", "2 / 2 / 1 / 2 / 1 / 2 / 1 / 2", "1 / 2 / 1 / 2 / 1 / 2", and "2 / 2 / 1 / 2 / 1 / 2 / 1 / 2". The four sets of sub-increment sequences are then sent sequentially to the phase interpolator, enabling the phase interpolator to adjust the phase according to the sub-increment sequence over 32 consecutive clock cycles.

[0105] Understandably, this application significantly reduces the dynamic jitter of the phase interpolator's output clock by distributing the total increment of the CDR circuit's code movement. In a practical application scenario, for high-speed PCIe Gen6 / Gen7, one CDR operating clock cycle (1GHz) will have approximately 6.55 code transitions. The phase interpolator's code width is 256 bits, and the phase interpolator moves at 8GHz. The phase delay for each code transition is 125ps / 256 = 0.488ps. Without distributing the code, the phase delay for each transition is approximately 6 * 0.488 = 2.9ps (6 represents 6.55 rounded down). After distributing the code, the phase delay for each transition is one code, i.e., 0.488ps, significantly reducing dynamic jitter and improving the CDR loop tracking performance.

[0106] Furthermore, to further enhance the system's processing capabilities, this application, after determining the sub-increment sequence, can convert the sub-increment sequence into thermometer code before sending it to the phase interpolator. Based on this, one implementation method is as follows:

[0107] The steps of sending the sub-increment sequence to the phase interpolator include:

[0108] Each binary code sub-increment is converted into the corresponding thermometer code in real time; the thermometer code is divided into 4 equal-length blocks, one of which is a target block that changes dynamically according to the sub-increment, and the thermometer codes of the other three blocks are all 0 or all 1; and the target block is cyclically switched among the 4 equal-length blocks.

[0109] The thermometer code containing the target block but not the other three blocks is sent to the phase interpolator.

[0110] Thermometer code, also known as unit distance code or thermal code, is a special binary encoding method. Its name comes from its encoding characteristics, which resemble the mercury column of a thermometer: as the value increases, the number of "1"s in the code monotonically increases, and the "1"s always appear consecutively starting from one end. Thermometer code possesses the characteristics of monotonicity, continuity, and unit distance. Monotonicity means the number of "1"s in the code is strictly proportional to the represented value; continuity means all "1"s are arranged consecutively in the code without any gaps of "0"s; and unit distance means that the codes for adjacent values ​​differ by only one bit.

[0111] In phase interpolators, using thermometer code enables continuously adjustable phase (high resolution) and smooth transitions, reducing glitches. Compared to using binary code, using thermometer code offers at least the following advantages:

[0112] 1. Achieve true analog linear control: When the temperature code value changes, the number of switches changes linearly, and the output changes smoothly, which is close to analog control.

[0113] 2. Ensure monotonicity and avoid nonlinear errors: In actual circuits, each switch / current source has a process deviation (mismatch), while all bits of the thermometer code have equal weights, thus averaging the mismatch error and resulting in better overall linearity.

[0114] 3. Reduce glitches and instantaneous current spikes: When the thermometer code changes, only one bit changes each time. For example, when the thermometer code changes from 4 to 5, it is represented by changing from 00001111 to 00011111. Therefore, there are no intermediate glitches and the current change is smooth.

[0115] 4. Simplified decoding logic and improved speed: The thermometer code requires no complex decoding; each bit directly controls one physical unit. Furthermore, the thermometer code can operate in parallel, with all bits taking effect simultaneously, resulting in high speed. In addition, the timing of the thermometer code is simple, with consistent setup / hold time requirements.

[0116] 5. Supports zone control: The continuous "1" or continuous "0" zone characteristics of the thermometer code are naturally suitable for zone control, and this zoning is a perfect match with the spatial continuity of the thermometer code.

[0117] Therefore, in this application, the sub-increments of the binary code can be converted into the corresponding thermometer code in real time, and then the thermometer code can be sent to the phase interpolator. To reduce the data processing load of the phase interpolator, a partitioning method can be used to send only a portion of the thermometer code to the phase interpolator.

[0118] Specifically, the thermometer code is divided into four equal-length blocks, each with 32 bits, totaling 128 bits. One target block dynamically changes based on the sub-increment, while the other three blocks contain either all 0s or all 1s (a characteristic of thermometer codes). The target block cycles through the four equal-length blocks, ensuring that each block has a chance to become the target block within multiple consecutive adjustment cycles, thus collectively covering the complete phase adjustment range. In other words, the target block represents the sub-increment, while the other three blocks contain either all 0s or all 1s. Therefore, when sending the thermometer code, only the thermometer code containing the target block but not the other three blocks needs to be sent to the phase interpolator. This implementation significantly reduces the data processing load of the phase interpolator.

[0119] As one implementation, when each block has 32 bits, Bn[39:0] is sent to the phase interpolator; where n is an integer from 0 to N. In Bn[39:0], Bn[31:0] represents the thermometer code of the target block, Bn[35:32] indicates whether the basic codeword of the phase interpolator's working clock domain is flipped, and Bn[39:36] indicates whether the basic codeword of the phase interpolator's working clock domain is replaced by the incremental codeword. That is, when sending the thermometer code to the phase interpolator, it is only necessary to synchronously send which block the current target block is and the status of the remaining blocks. The "whether the basic codeword of the phase interpolator's working clock domain is flipped" mentioned in this application means that the four bits of Bn[35:32] are the basic code flipping control bits, which are used to indicate whether the current thermometer code update adopts forward (increasing the number of "1"s) or reverse (decreasing the number of "1"s) encoding logic to adapt to the basic code status of the phase interpolator, so as to determine the status of the remaining blocks. The "whether the working clock domain base codeword of the phase interpolator is replaced by the incremental codeword" mentioned in this application indicates that Bn[39:36] is the target block selection bit. It is used to indicate which block is the target block. For example, 0001 represents block 0, 0010 represents block 1, 0100 represents block 2, and 1000 represents block 3.

[0120] This method reduces the amount of data sent to the phase interpolator from 128 bits to only 40 bits. When the phase interpolator receives these 40 bits, Bn[31:0] (bits 1 to 32) represents the sub-increment, Bn[35:32] (bits 33 to 36) represents the remaining blocks, and Bn[39:36] (bits 37 to 40) represents the current target block number. This method allows the phase interpolator to process only 40 bits of data, significantly reducing its processing load to 40 / 128*100% = 31.25% compared to processing 128 bits, thus facilitating high-speed communication.

[0121] Based on the above implementation, this application also provides a SerDes system. Please refer to [link / reference]. Figure 5The SerDes system includes an ADC sampling module 110, a CDR circuit 120, a phase interpolator 140, and a sub-increment generation module 130. The ADC sampling module 110 is connected to the CDR circuit 120, and the CDR circuit 120, sub-increment generation module 130, and phase interpolator 140 are connected sequentially. The phase interpolator 140 is connected to the ADC. The sub-increment generation module 130 is used to divide the total code movement increment into N sub-increments based on the ratio of the operating clock frequency of the phase interpolator 140 to the operating clock frequency of the CDR circuit 120, and form a sub-increment sequence. The operating clock frequency of the phase interpolator 140 is greater than the operating clock frequency of the CDR circuit 120, and the absolute value of the difference between the code movement increments of any two sub-increment sequences is less than or equal to 1. N is a positive integer, and the total code movement increment is determined based on the code to be moved in the current cycle and the code to be moved in the next cycle.

[0122] The sub-increment generation module 130 is also used to send the sub-increment sequence to the phase interpolator 140 according to the timing relationship, so that the phase interpolator 140 can perform phase adjustment according to the sub-increment sequence in N consecutive clock cycles.

[0123] Please see Figure 6 The sub-increment generation module 130 includes a first-level distribution module 131, a second-level distribution module 132, and a selector 133. The first input terminal of the selector 133 and the input terminal of the first-level distribution module 131 are both connected to the CDR circuit 120. The output terminal of the first-level distribution module 131 is connected to the second input terminal of the selector 133. The output terminal of the selector 133 is connected to the second-level distribution module 132. The output terminal of the second-level distribution module 132 is connected to the phase interpolator 140.

[0124] Furthermore, in one implementation, the SerDes system also includes a code conversion module 150, an FFE 160, and a DFE 170. The output of the secondary distribution module 132 is connected to the code conversion module 150, which is connected to the phase interpolator 140. The code conversion module 150 converts binary code into thermometer code. The ADC sampling modules 110, FFE 160, and DFE 170 are connected sequentially, so that the analog signal Rx is sampled by the ADC sampling module 110 and sent to the CDR circuit 120. Simultaneously, the sampled value from the ADC sampling module 110 is also sent to the data channel composed of FFE 160 and DFE 170, and after processing by FFE 160 and DFE 170, the processed data rx_data is output. Figure 6In this context, PLL CLK represents the phase-locked loop clock, ADC CLK represents the clock output from phase interpolator 140 to ADC sampling module 110, FFE represents the feed-forward equalizer, a linear equalizer that compensates for inter-symbol interference (ISI) introduced by the channel by weighted summation of input sample values ​​from the current and previous times. DFE represents the decision feedback equalizer, a non-linear equalizer that uses decided data to cancel interference from previous symbols received by the current symbol.

[0125] In summary, this application provides a phase adjustment method and a SerDes system. First, the code to be moved in the current cycle and the code to be moved in the next cycle are obtained, and the total code movement increment is determined. Then, based on the ratio of the operating clock frequency of the phase interpolator to the operating clock frequency of the CDR circuit, the total code movement increment is divided into N sub-increments, which form a sub-increment sequence. The operating clock frequency of the phase interpolator is greater than the operating clock frequency of the CDR circuit, and the absolute value of the difference between the code movement increments of any two sub-increment sequences is less than or equal to 1, where N is a positive integer. Finally, according to the timing relationship, the sub-increment sequence is sent to the phase interpolator so that the phase interpolator can perform phase adjustment according to the sub-increment sequence within N consecutive clock cycles.

[0126] This application fundamentally avoids the clock phase abrupt changes caused by a single large jump by dividing the large total code movement increment into N sub-increments. Each sub-increment only needs to move a small amount of code, thus changing the time domain change of the clock phase from a "step" to a "gradual change," thereby directly and significantly suppressing the dynamic jitter of the output clock. At the same time, this application can ensure that the absolute value of the difference between any two sub-increments after the division is ≤1, thus ensuring that the entire adjustment process is smooth and eliminating the additional periodic jitter caused by uneven adjustment.

[0127] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0128] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method of phase adjustment, characterized by, The method includes: Obtain the code to be moved in the current cycle and the code to be moved in the next cycle, and determine the total code movement increment; According to the ratio of the operating clock frequency of the phase interpolator to the operating clock frequency of the CDR circuit, split the total code movement increment into N sub-increments and form a sub-increment sequence; wherein, the operating clock frequency of the phase interpolator is greater than the operating clock frequency of the CDR circuit, and the absolute value of the difference between the code movement increments of any two sub-increment sequences is less than or equal to 1, and N is a positive integer; Send the sub-increment sequence to the phase interpolator according to the timing relationship, so that the phase interpolator realizes phase adjustment according to the sub-increment sequence within N consecutive clock cycles; The step of splitting the total code movement increment into N sub-increments according to the ratio of the operating clock frequency of the phase interpolator to the operating clock frequency of the CDR circuit includes: When the operating clock frequency of the CDR circuit is equal to 1G, split the total code movement increment into N sub-increments according to the ratio of the operating clock frequency of the phase interpolator to the 1G clock frequency; When the operating clock frequency of the CDR circuit is less than 1G, distribute the total code movement increment to the 1G clock frequency to obtain M intermediate sub-increments; split each intermediate sub-increment into P sub-increments according to the ratio of the operating clock frequency of the phase interpolator to the 1G clock frequency; and N = M × P.

2. The phase adjustment method of claim 1, wherein, The total code movement increment satisfies: When A > B, C = A - B; When A < B, C = 9’h100 - B + A; Wherein, A represents the code to be moved in the next cycle, B represents the code to be moved in the current cycle, C represents the total code movement increment, and 9’h100 represents 256 in hexadecimal.

3. The phase adjustment method of claim 1, wherein, When the operating clock frequency of the CDR circuit is less than 1G, the step of distributing the total code movement increment to the 1G clock frequency includes: Determine the number M of intermediate sub-increments according to the ratio of the 1G clock frequency to the operating clock frequency of the CDR circuit; Shift the total code movement increment to the right by log2(M) bits to obtain the integer part and the remainder part; Allocate the integer part to each intermediate sub-increment, and evenly allocate the remainder part to M intermediate sub-increments, and the value of each intermediate sub-increment is equal to the integer part + the remainder part.

4. The phase adjustment method of claim 3, wherein, When the operating clock frequency of the CDR circuit is less than 1G, the step of distributing the total code movement increment to the 1G clock frequency includes: When the operating clock frequency of the CDR circuit is 500M, generate 2 intermediate sub-increments, shift the total code movement increment to the right by 1 bit to obtain the integer part and the remainder part; allocate the integer part to 2 intermediate sub-increments, and allocate the remainder part to one of the intermediate sub-increments; When the operating clock frequency of the CDR circuit is 250M, generate 4 intermediate sub-increments, shift the total code movement increment to the right by 2 bits to obtain the integer part and the remainder part; allocate the integer part to 4 intermediate sub-increments, and evenly allocate the remainder part to 4 intermediate sub-increments; When the operating clock frequency of the CDR circuit is 125MHz, eight intermediate sub-increments are generated. The total increment of the code shift is shifted three bits to the right, and the integer part and the remainder part are taken. The integer part is distributed to the eight intermediate sub-increments, and the remainder part is evenly distributed to the eight intermediate sub-increments.

5. The phase adjustment method of claim 1, wherein, When the operating clock frequency of the CDR circuit is equal to 1GHz, the step of dividing the total code shift increment into N sub-increments based on the ratio of the operating clock frequency of the phase interpolator to the 1GHz clock frequency includes: The number N of sub-increments is determined by the ratio of the operating clock frequency of the phase interpolator to the 1G clock frequency; Shift the total increment of the code movement right by log2(N) bits and take the integer part and the remainder; The integer part is assigned to each sub-increment, and the remainder part is evenly distributed among the N sub-increments, with the value of each sub-increment equal to the integer part plus the remainder part.

6. The phase adjustment method of claim 1, wherein, The step of sending the sub-increment sequence to the phase interpolator according to the timing relationship includes: Each binary code sub-increment is converted into a corresponding thermometer code in real time; wherein, the thermometer code is divided into 4 equal-length blocks, one of which is a target block that changes dynamically according to the sub-increment, and the thermometer codes of the other three blocks are all 0 or all 1; and the target block is cyclically switched among the 4 equal-length blocks; The thermometer code containing the target block but not the other three blocks is sent to the phase interpolator.

7. The phase adjustment method of claim 6, wherein, The step of sending the thermometer code containing the target block but not the other three blocks to the phase interpolator includes: When each block has 32 bits, Bn[39:0] is sent to the phase interpolator; where n is an integer from 0 to N, Bn[31:0] represents the thermometer code of the target block, Bn[35:32] represents whether the working clock domain base codeword of the phase interpolator is flipped, and Bn[39:36] represents whether the working clock domain base codeword of the phase interpolator is replaced by the incremental codeword.

8. A Serdes system characterized by, The SerDes system includes an ADC sampling module, a CDR circuit, a phase interpolator, and a sub-increment generation module. The ADC sampling module is connected to the CDR circuit, and the CDR circuit, the sub-increment generation module, and the phase interpolator are connected sequentially. The phase interpolator is connected to the ADC. The sub-increment generation module is used to divide the total code movement increment into N sub-increments based on the ratio of the operating clock frequency of the phase interpolator to the operating clock frequency of the CDR circuit, and form a sub-increment sequence. The operating clock frequency of the phase interpolator is greater than the operating clock frequency of the CDR circuit, and the absolute value of the difference between the code movement increments of any two sub-increment sequences is less than or equal to 1. N is a positive integer, and the total code movement increment is determined based on the code to be moved in the current cycle and the code to be moved in the next cycle. When the operating clock frequency of the CDR circuit is equal to 1G, the total code movement increment is divided into N sub-increments based on the ratio of the operating clock frequency of the phase interpolator to the 1G clock frequency. When the operating clock frequency of the CDR circuit is less than 1G, the total code shift increment is distributed to the 1G clock frequency to obtain M intermediate sub-increments; each intermediate sub-increment is divided into P sub-increments according to the ratio of the operating clock frequency of the phase interpolator to the 1G clock frequency; and N = M × P. The sub-increment generation module is further configured to send the sub-increment sequence to the phase interpolator according to the timing relationship, so that the phase interpolator can perform phase adjustment according to the sub-increment sequence in N consecutive clock cycles.

9. The Serdes system of claim 8, wherein, The sub-increment generation module includes a first-level distribution module, a second-level distribution module, and a selector. The first input terminal of the selector and the input terminal of the first-level distribution module are both connected to the CDR circuit. The output terminal of the first-level distribution module is connected to the second input terminal of the selector. The output terminal of the selector is connected to the second-level distribution module. The output terminal of the second-level distribution module is connected to the phase interpolator.

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