Packaging structure and method for on-chip ultrasonic module

Abstract

The invention provides a packaging structure and method for an on-chip ultrasonic module. The packaging structure comprises a CMOS bare chip; the packaging layer is used for packaging the CMOS bare chip; the metal columns used for fan-out of the CMOS bare chip are arranged on the packaging layer in a penetrating manner; the first redistribution layer is formed on the packaging layer on the front surface of the CMOS bare chip and is used for connecting a bonding pad of the CMOS bare chip to the metal column; and the second redistribution layer is formed on the packaging layer on the back surface of the CMOS bare chip and is used for connecting the metal columns to a welding piece for connecting an external substrate. And the piezoelectric ceramic transducer array is arranged on the first redistribution layer and is connected with the CMOS bare chip through an electric connection column arranged in the first redistribution layer in a penetrating manner. According to the invention, the ultrasonic chip can be conveniently connected with the circuit board, the processing requirement on the circuit board is reduced, and the signal delay of the ultrasonic chip is reduced.

Description

Technical Field

[0001] This invention relates to ultrasonic chips, and more specifically, to a packaging structure and method for on-chip ultrasonic modules. Background Technology

[0002] Piezoelectric ceramic transducers operate on the principle of the direct and inverse piezoelectric effects of piezoelectric materials. They achieve efficient transmission and reception of ultrasonic signals through the periodic vibration of the piezoelectric layer. When used as a transmitter, the transducer essentially converts electrical signals into mechanical vibration energy. Under the influence of a driving voltage, the piezoelectric layer deforms due to the inverse piezoelectric effect, radiating ultrasonic waves into the medium. When used as a receiver, it becomes a sensor that captures mechanical vibration energy. External ultrasonic waves cause the piezoelectric layer to vibrate, converting the acoustic signal into an electrical signal through the direct piezoelectric effect for subsequent processing.

[0003] Complementary Metal Oxide Semiconductor (CMOS) technology, as a core technology in the semiconductor field, is widely used in integrated circuit manufacturing and many other fields. It can integrate a large number of transistors onto a small chip, continuously developing in accordance with Moore's Law, and driving the evolution of semiconductors towards miniaturization and high performance.

[0004] In ultrasound imaging systems, CMOS integrated circuits at the transmitting end precisely control the excitation signal of the ultrasound transducer. For example, they can generate electrical pulse signals with specific frequencies, pulse widths, and amplitudes to drive the ultrasound transducer to emit ultrasonic waves. In some medical ultrasound diagnostic devices, CMOS integrated circuits optimize the emitted waveform, improving the emission efficiency and directivity of ultrasound waves, thereby enhancing the resolution and clarity of the imaging. At the receiving end, CMOS integrated circuits are responsible for receiving the echo signals received by the ultrasound transducer and performing preprocessing such as pre-amplification and filtering. CMOS integrated circuits can integrate high-performance, low-noise amplifiers to reduce noise interference in the received signal, while simultaneously processing echo signals of different frequencies and amplitudes quickly and accurately, providing high-quality data for subsequent signal processing and image reconstruction.

[0005] 2.5D packaging technology is an advanced semiconductor packaging technology that combines the characteristics of 2D (planar) and 3D (stereoscopic) packaging. It has significant advantages in improving chip performance, integration, and functional density. How to package PZT-CMOS ultrasonic chips using 2.5D packaging technology is an urgent problem to be solved. Summary of the Invention

[0006] To address the problems in the prior art, the purpose of this invention is to provide a packaging structure and method for on-chip ultrasonic modules.

[0007] The packaging structure for an on-chip ultrasonic module provided by the present invention includes:

[0008] CMOS die;

[0009] A packaging layer is used to encapsulate the CMOS die; a metal pillar for fanning out the CMOS die is disposed through the packaging layer.

[0010] A first redistribution layer is formed on the packaging layer on the front side of the CMOS die, and is used to connect the pads of the CMOS die to the metal pillars;

[0011] A second redistribution layer is formed on the packaging layer on the back side of the CMOS die, for connecting the metal pillars to a solder joint for connecting to an external substrate;

[0012] A piezoelectric ceramic transducer array is disposed on the first redistribution layer and connected to the CMOS die through an electrical connection post disposed throughout the first redistribution layer.

[0013] Preferably, the first redistribution layer comprises a first front insulating layer and a first front metal wiring layer formed sequentially;

[0014] The first front-side metal wiring layer connects to the metal pillar;

[0015] The electrical connection post is disposed through the first front insulating layer.

[0016] Preferably, the second redistribution layer comprises a first back insulating layer and a first back metal wiring layer formed sequentially;

[0017] The first back metal wiring layer is connected to the metal pillar on one side and to the weldment on the other.

[0018] Preferably, a passive device is mounted on the first redistribution layer; the passive device is electrically connected to the front metal wiring layer in the first redistribution layer.

[0019] Preferably, one end of the electrical connection post is connected to a pad on the CMOS die for connecting the transducer, and the other end is connected to the electrode of the piezoelectric ceramic transducer through a connection structure. The connection structure is used to realize the electrical connection and mechanical support between the electrical connection post and the piezoelectric ceramic transducer.

[0020] Preferably, the connection structure comprises multiple metal layers or a single metal layer.

[0021] The packaging structure for an on-chip ultrasonic module provided by the present invention includes:

[0022] CMOS die;

[0023] A packaging layer is used to encapsulate the CMOS die; a metal pillar for fanning out the CMOS die is disposed through the packaging layer.

[0024] A first redistribution layer is formed on the packaging layer on the front side of the CMOS die, for connecting the pads of the CMOS die to the metal pillars, and the metal pillars are connected to the solder joints for connecting to an external substrate;

[0025] A piezoelectric ceramic transducer array is disposed on the first redistribution layer and connected to the CMOS die through an electrical connection post disposed throughout the first redistribution layer.

[0026] Preferably, the first redistribution layer comprises a first front insulating layer and a first front metal wiring layer formed sequentially;

[0027] The first front-side metal wiring layer connects to the metal pillar;

[0028] The electrical connection post is disposed through the first front insulating layer.

[0029] Preferably, a passive device is mounted on the first redistribution layer; the passive device is electrically connected to the front metal wiring layer in the first redistribution layer.

[0030] Preferably, one end of the electrical connection post is connected to a pad on the CMOS die for connecting the transducer, and the other end is connected to the electrode of the piezoelectric ceramic transducer through a connection structure. The connection structure is used to realize the electrical connection and mechanical support between the electrical connection post and the piezoelectric ceramic transducer.

[0031] Preferably, the connection structure comprises multiple metal layers or a single metal layer.

[0033] The packaging method for an on-chip ultrasonic module provided by the present invention includes the following steps:

[0034] Step S1: Package the CMOS die to form a packaging layer, wherein the packaging layer forms metal pillars for fan-out reconstruction around the periphery of the CMOS die;

[0035] Step S2: Construct a first redistribution layer on the packaging layer on the front side of the CMOS die to connect the pads of the CMOS die to the metal pillars, etch the first redistribution layer to form interlayer vias and form electrical connection pillars in the interlayer vias;

[0036] Step S3: Construct a second redistribution layer on the packaging layer on the back side of the CMOS die to connect the metal pillar to the solder joint for connecting to the external substrate;

[0037] Step S4: Install a piezoelectric ceramic transducer and a passive device on the front side of the CMOS die, and bond the piezoelectric ceramic transducer to the electrical connection post.

[0038] Preferably, step S1 includes the following steps:

[0039] Step S101: Fabricate a metal pillar on the surface of the first temporary support sheet, and then encapsulate the metal pillar;

[0040] Step S102: Mount the CMOS die onto the first temporary support sheet and encapsulate it again to form an encapsulation layer;

[0041] Step S103: Bond the encapsulation layer on the back of the CMOS die to the second temporary support sheet, debond and remove the first temporary support sheet, and release the encapsulation layer.

[0042] Preferably, step S2 includes the following steps:

[0043] Step S201: Sequentially fabricate a first front insulating layer and a first front metal wiring layer on the packaging layer on the front side of the CMOS die;

[0044] Step S202: Etch the first front metal wiring layer and the first front insulating layer to form interlayer vias, and electroplate the interlayer vias to form the electrical connection pillars;

[0045] Step S203: Bond the packaging layer on the front side of the CMOS die to the first temporary support sheet to prepare for back side processing;

[0046] Step S204: Remove the second temporary support sheet from the back of the CMOS die by laser debonding to expose the metal pillar.

[0047] Preferably, step S3 includes the following steps:

[0048] Step S301: Sequentially fabricate a first back insulating layer, a first back metal wiring layer, a second back insulating layer, a second back metal wiring layer, and a bottom metal layer on the packaging layer on the back side of the CMOS die, wherein a solder joint is disposed on the bottom metal layer;

[0049] Step S302: Apply dicing tape to the bottom metal layer;

[0050] Step S303: Remove the first temporary support sheet by laser debonding on the front side of the CMOS die to expose the first redistribution layer.

[0051] Preferably, step S4 includes the following steps:

[0052] Step S401: Install a piezoelectric ceramic transducer and a passive device on the front side of the CMOS die, wherein the passive device is electrically connected to the first redistribution layer;

[0053] Step S402: Cut the piezoelectric ceramic transducer into multiple individual piezoelectric ceramic transducers, and bond the electrodes of the individual piezoelectric ceramic transducers to the electrical connection post;

[0054] Step S403: The package after installing the piezoelectric ceramic transducer is diced and cut into individual chips. Each individual chip is tested and qualified individual chips are selected.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] In this invention, when packaging a CMOS die and a piezoelectric ceramic transducer array, a metal pillar for fanning out the CMOS die is provided through the packaging layer. A first redistribution layer is formed on the packaging layer on the front side of the CMOS die to connect the pads of the CMOS die to the metal pillar. The piezoelectric ceramic transducer array is connected to the CMOS die through an electrical connection pillar provided through the first redistribution layer. A second redistribution layer is formed on the packaging layer on the back side of the CMOS die to connect the metal pillar to a solder piece for connecting an external substrate. This makes it easier for the ultrasonic chip to connect to the circuit board, reduces the process requirements of the circuit board, and reduces the signal delay of the ultrasonic chip. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0058] Figure 1 This is a schematic diagram illustrating the application scenario of the on-chip ultrasonic chip in an embodiment of the present invention;

[0059] Figure 2 This is a schematic diagram illustrating the working principle of the on-chip ultrasonic chip in an embodiment of the present invention;

[0060] Figure 3 This is a schematic diagram of a CMOS die with a piezoelectric ceramic transducer installed in an embodiment of the present invention;

[0061] Figure 4This is a schematic diagram of the packaging structure for an on-chip ultrasonic module in an embodiment of the present invention;

[0062] Figure 5 This is a specific example diagram of the packaging structure used for the on-chip ultrasonic module in an embodiment of the present invention;

[0063] Figure 6 This is a schematic diagram showing the connection between the piezoelectric ceramic transducer and the CMOS die in an embodiment of the present invention;

[0064] Figure 7 This is a schematic diagram of the connection structure in an embodiment of the present invention;

[0065] Figure 8 This is a flowchart illustrating the steps of a packaging method for an on-chip ultrasonic module in an embodiment of the present invention.

[0066] Figure 9 This is a schematic diagram of the encapsulation layer formed in an embodiment of the present invention;

[0067] Figure 10 This is a schematic diagram illustrating the construction of the first redistribution layer in an embodiment of the present invention;

[0068] Figure 11 This is a schematic diagram illustrating the construction of the second redistribution layer in an embodiment of the present invention; and

[0069] Figure 12 This is a schematic diagram of mounting passive components in an embodiment of the present invention.

[0070] In the picture:

[0071] 100 is a probe; 200 is an interventional catheter; 101 is a CMOS die; 102 is a piezoelectric ceramic transducer array; 103 is a pad; 104 is an encapsulation layer; 105 is a metal pillar; 106 is a first redistribution layer; 1061 is a first front insulating layer; 1062 is a first front metal wiring layer; 1063 is a second front insulating layer; 1064 is a second front metal wiring layer; 1065 is a third front insulating layer; 1066 is a fifth metal wiring layer; 1067 is a fourth front insulating layer; 107 is a second redistribution layer; 1071 is a first back insulating layer; 1072 is a first back metal wiring layer; 1073 is a second back insulating layer; 1074 is a second back metal wiring layer; 108 is a solder joint; 109 is a passive device; 110 is a first temporary support sheet; 111 is a heat-release tape; 112 is a second temporary support sheet. Detailed Implementation

[0072] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0073] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0074] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0075] The technical solutions of the present invention and how they solve the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0076] Figure 1 This is a schematic diagram illustrating the application scenario of the on-chip ultrasound chip in an embodiment of the present invention, such as... Figure 1As shown, during intracardiac ultrasound, a transceiver probe 100 is placed inside the heart via a blood vessel to perform real-time, high-quality imaging or hemodynamic measurements of the heart and adjacent tissues. It is primarily used in interventional cardiac procedures such as atrial fibrillation radiofrequency ablation, mitral valve repair, left atrial appendage closure, and closure of atrial septal defects and patent foramen ovale. It enables real-time monitoring of catheter position and surgical outcomes, assessment of cardiac structure and function, guidance of surgical procedures, and reduction of surgical risks. The probe 100 has a diameter of approximately 3-10F (1-3.3 mm) and is positioned at the tip of the interventional catheter 200, inserted into the heart chamber via a vascular pathway (such as the femoral vein). The probe frequency is typically 5-20 MHz, offering extremely high resolution, but with limited penetration depth, covering only local structures within the heart chambers. Given that the heart rate is approximately 60-100 beats per minute and the valve opening and closing cycle is only a few hundred milliseconds, a high imaging frame rate, such as a 4D imaging rate of 50 volumes / s, is required.

[0077] Figure 2 This is a schematic diagram illustrating the working principle of the on-chip ultrasonic chip in an embodiment of the present invention, as shown below. Figure 2 As shown, when ultrasound is transmitted via the on-chip ultrasound chip provided by this invention, the transmitting beamformer delays and adjusts the phase of the electrical pulse to direct the synthesized beam towards the target area. The pulse generator generates a high-voltage pulse based on the delay and phase of the electrical pulse, which triggers the piezoelectric ceramic transducer to vibrate and transmit ultrasound. During ultrasound reception, the ultrasound waves are reflected by tissue and act on the piezoelectric ceramic transducer, generating a signal-to-noise ratio through the positive piezoelectric effect. The low-noise amplifier (LNA) amplifies and reduces the noise of the weak electrical signal output by the piezoelectric ceramic transducer, improving the signal-to-noise ratio. The receiving beamformer performs phase compensation on the electrical signals received by each array element, superimposing and enhancing the target echo. The target echo is transmitted to the ultrasound control console through the output channel, thereby realizing image reconstruction and real-time display.

[0078] Figure 3 This is a schematic diagram of a CMOS die with a piezoelectric ceramic transducer installed in an embodiment of the present invention, as shown below. Figure 3 As shown, a piezoelectric ceramic transducer array is mounted on the CMOS die, with pads 103 arrayed on both sides of the CMOS die. The piezoelectric ceramic transducer array 102 is used to convert received pulse electrical signals into ultrasonic waves and transmit them, or to convert received ultrasonic echoes into echo electrical signals. An ultrasonic control circuit is formed on the CMOS die, including a pulse transmitting circuit and an echo receiving circuit. The pulse transmitting circuit includes a transmitting beamformer and a pulse generator to generate pulse electrical signals to drive the piezoelectric ceramic transducer array 102 to transmit ultrasonic waves. The echo receiving circuit includes a low-noise amplifier and a receiving beamformer to receive and process the echo electrical signals. The CMOS die has a length between 10 and 15 mm and a width between 2 and 3 mm.

[0079] Figure 4 This is a schematic diagram of the packaging structure for an on-chip ultrasonic module in one embodiment of the present invention, as shown below. Figure 4 As shown, the packaging structure for an on-chip ultrasonic module provided by the present invention includes:

[0080] CMOS die 101;

[0081] The encapsulation layer 104 is used to encapsulate the CMOS die; the encapsulation layer 104 is provided with metal pillars 105 for fanning out the CMOS die.

[0082] A first redistribution layer 106 is formed on the packaging layer 104 on the front side of the CMOS die 101, and is used to connect the pads 103 of the CMOS die to the metal pillars 105.

[0083] The second redistribution layer 107 is formed on the encapsulation layer 104 on the back side of the CMOS die 101 and is used to connect the metal pillar 105 to the solder joint 108 for connecting to an external substrate.

[0084] The piezoelectric ceramic transducer array 102 is disposed on the first redistribution layer 106 and connected to the CMOS die 101 through an electrical connection post disposed through the first redistribution layer 106.

[0085] In one embodiment of the present invention, epoxy molding compound (EMC), silicone rubber, polyimide, silicon wafer and glass substrate are used in the encapsulation process, wherein epoxy molding compound (EMC) is preferred.

[0086] In one embodiment of the present invention, an interlayer via is formed by etching the first redistribution layer and an electrical connection post is formed by electroplating the interlayer via.

[0087] In an optional embodiment of the present invention, a redistribution layer is formed again on the plane where the other end of the electrical connection post is located, and the installation and connection of the piezoelectric ceramic transducer is realized through the redistribution layer.

[0088] In one embodiment of the present invention, the piezoelectric ceramic transducer may be made of PZT-based piezoelectric ceramics, PMN-PZT modified piezoelectric ceramics, BaTiO3-based piezoelectric ceramics, lead-free piezoelectric ceramics, composite piezoelectric ceramics, or piezoelectric single crystal materials.

[0089] In one embodiment of the present invention, the front side of the CMOS die is a side with a piezoelectric ceramic transducer array, and the back side is encapsulated in the encapsulation layer 104.

[0090] The plurality of metal pillars 105 form two metal pillar arrays, with the CMOS die located between the two metal pillar arrays 1.

[0091] The first redistribution layer 106 redistributes the pads of the CMOS die to adapt to packaging interconnect requirements.

[0092] The metal pillar 105 is made of materials such as copper, tin, tin alloy, nickel, and gold, with copper being the preferred material.

[0093] In one embodiment of the present invention, epoxy molding compound (EMC), silicone rubber and polyimide are used in the molding process, with epoxy molding compound (EMC) being preferred.

[0094] Figure 5 This is a specific example diagram of the packaging structure for an on-chip ultrasonic module in an embodiment of the present invention, such as... Figure 5 As shown, in one embodiment of the present invention, the first redistribution layer 106 includes a first front insulating layer 1061, a first front metal wiring layer 1062, a second front insulating layer 1063 and a second front metal wiring layer 1064 formed sequentially.

[0095] The second front metal wiring layer 1064 is connected to the metal pillar 105 through the first front metal wiring layer 1062.

[0096] A passive device 109 is mounted on the second front insulating layer 1063; the passive device 109 is electrically connected to the second front metal wiring layer 1064.

[0097] In one embodiment of the present invention, a third front insulating layer 1065, a fifth metal wiring layer 1066, and a fourth front insulating layer 1067 are sequentially formed on the second front metal wiring layer 1064.

[0098] The second front metal wiring layer 1064 is connected to the metal pillar 105 through the first front metal wiring layer 1062;

[0099] The fifth metal wiring layer 1066 is connected to the second front metal wiring layer 1064 on one hand, and electrically connected to the passive device 109 mounted on the fourth front insulating layer 1067 on the other hand.

[0100] A passive device 109 is mounted on the fourth front insulating layer 1067; the passive device 109 is electrically connected to the fifth metal wiring layer 1066.

[0101] The electrical connection post is disposed through the first front insulating layer 1061, the second front insulating layer 1063, the third front insulating layer 1065, and the fourth front insulating layer 1067.

[0102] In one embodiment of the present invention, the second redistribution layer 107 includes a first back insulating layer 1071, a first back metal wiring layer 1072, a second back insulating layer 1073, and a second back metal wiring layer 1074 formed sequentially.

[0103] The first back metal wiring layer 1072 is connected to the metal pillar 105 on one hand, and to the weldment 108 through the second back metal wiring layer 1074 on the other hand.

[0104] In one embodiment of the present invention, a bottom metal layer is formed on the second back metal wiring layer 1074, and a solder joint 108 is disposed on the bottom metal layer.

[0105] In one embodiment of the present invention, the soldering component 108 uses solder balls. When mounting the passive device 109, silicon-based passive device 109 (IPD) components can be used, or surface-mount components (SMD) can be used. The passive device 109 is a capacitor, which can be capacitors of different capacitance values, such as a first group of capacitors with a capacitance of 20nF and a second group of capacitors with a capacitance of 40nF.

[0106] The first front insulating layer 1061, the second front insulating layer 1063, the first back insulating layer 1071, the second back insulating layer 1073, the third front insulating layer 1065, and the fourth front insulating layer 1067 are made of polyimide insulating layers.

[0107] In one embodiment of the present invention, a protective layer is formed on the front side of the piezoelectric ceramic transducer array 102. This protective layer can be made of PDMS (polydimethylsiloxane), a polymer material based on the parylene series, or synthetic rubber. The acoustic impedance of the PDMS layer is well-matched to common media such as biological tissues. When the piezoelectric ceramic transducer is used in biomedical detection and other fields, it helps to better transmit ultrasonic signals between the device and the external medium, reducing reflections and energy losses caused by acoustic impedance mismatch. For example, in ultrasonic imaging, it can make the transmitted and received ultrasonic signals clearer, improving image quality. The PDMS layer has good chemical stability and flexibility, protecting the piezoelectric ceramic transducer from the influence of the external environment, such as preventing water vapor, dust, and other contaminants from corroding the device. It can also buffer external mechanical stress, reducing damage to the piezoelectric ceramic transducer caused by vibration and impact, thus improving the reliability and service life of the device. Parylene series (such as F-VT4, C, N) can also be used as acoustic impedance matching layers to reduce acoustic energy reflection and improve transducer sensitivity and imaging quality; with excellent film properties, they can isolate external erosion and ensure the service life of transducers in complex environments; at the same time, they have good biocompatibility and are suitable for medical scenarios such as in vivo ultrasound detection and wearable ultrasound patches.

[0108] Figure 6 This is a schematic diagram illustrating the connection between the piezoelectric ceramic transducer and the CMOS die in an embodiment of the present invention, as shown below. Figure 6 As shown, one end of the electrical connection post 113 is connected to a pad on the CMOS die for connecting a transducer, and the other end is provided with a connection structure 114 to connect to the electrode of the piezoelectric ceramic transducer, thereby realizing the electrical connection between the CMOS die and the piezoelectric ceramic transducer. The connection structure 114 is used to realize the electrical connection and mechanical support between the electrical connection post and the piezoelectric ceramic transducer, and the connection structure 114 includes, but is not limited to, bumps, copper pillars, conductive pillars, etc.

[0109] The electrical connection post is made of a metal material, such as copper, gold, or silver, with copper being the preferred material.

[0110] Figure 7 This is a schematic diagram of the connection structure in an embodiment of the present invention, such as... Figure 7 As shown, the connection structure includes multiple metal layers or a single metal layer; for example, a multi-layer structure consisting of copper layer 1141, nickel layer 1142 and gold layer 1143 in sequence, or a multi-layer structure consisting of copper layer 1141, nickel layer 1142 and tin-silver alloy layer in sequence, or a single gold layer, silver layer and copper layer, etc.

[0111] In a variation of the present invention, the connection structure may also be made of any conductive material.

[0112] Figure 8 This is a flowchart illustrating the steps of a packaging method for an on-chip ultrasonic module in an embodiment of the present invention, as follows: Figure 8 As shown, the packaging method for an on-chip ultrasonic module provided by the present invention includes the following steps:

[0113] Step S1: Molding the CMOS die 101 to form an encapsulation layer 104, wherein the encapsulation layer 104 contains metal pillars 105 for fan-out reconstruction around the CMOS die 101.

[0114] In one embodiment of the present invention, a protective layer is formed on the front side of the piezoelectric ceramic transducer array 102. The protective layer may be made of PDMS (polydimethylsiloxane), a poly(p-xylene) series polymer material, or synthetic rubber.

[0115] Figure 9 This is a schematic diagram of the encapsulation layer formed in an embodiment of the present invention, such as... Figure 9 As shown, step S1 includes the following steps:

[0116] Step S101: Fabricate a metal pillar 105 on the surface of the first temporary support sheet 110, and then encapsulate the metal pillar 105.

[0117] Step S102: The CMOS die is mounted onto the first temporary support sheet 110 and then encapsulated again to form the encapsulation layer 104;

[0118] Step S103: Bond the encapsulation layer 104 on the back of the CMOS die to the second temporary support sheet 112, unbond and remove the first temporary support sheet 110, and release the encapsulation layer 104.

[0119] In one embodiment of the present invention, a thermal release tape 111 is attached to the first temporary support sheet 110, and the plurality of metal pillars 105 form two metal pillar arrays. The CMOS die is attached to the first temporary support sheet 110 through the thermal release tape 111 and is located between the two metal pillar arrays, so that the first temporary support sheet 110 can be removed by heating.

[0120] The metal pillar 105 is made of materials such as copper, tin, tin alloy, nickel, and gold, with copper being the preferred material.

[0121] Materials such as epoxy molding compound (EMC), silicone rubber, and polyimide are used in the molding process, with epoxy molding compound (EMC) being the preferred choice.

[0122] Step S2: Construct a first redistribution layer 106 on the packaging layer 104 on the front side of the CMOS die to connect the pads 103 of the CMOS die to the metal pillars 105. Etch the first redistribution layer 106 to form interlayer vias and form electrical connection pillars in the interlayer vias.

[0123] In one embodiment of the present invention, the first redistribution layer 106 is used to redistribute the pads of the CMOS die to adapt to packaging interconnect requirements.

[0124] Figure 10 This is a schematic diagram of constructing the first redistribution layer in an embodiment of the present invention, as shown below. Figure 10 As shown, step S2 includes the following steps:

[0125] Step S201: Sequentially fabricate a first polyimide insulating layer 1061, a first front-side metal wiring layer 1062, a second polyimide insulating layer 1063, and a second front-side metal wiring layer 1064 on the packaging layer on the front side of the CMOS die.

[0126] Step S202: Etch the first front metal wiring layer and the first front insulating layer to form interlayer vias, and electroplate the interlayer vias to form the electrical connection pillars;

[0127] Step S203: Bond the packaging layer 104 on the front side of the CMOS die to the first temporary support sheet 110 through LTHC coating to prepare for back side processing;

[0128] Step S204: Remove the second temporary support sheet 112 from the packaging layer 104 on the back of the CMOS die by laser debonding to expose the metal pillar.

[0129] In one embodiment of the present invention, one end of the electrical connection post is connected to a transducer pad on the CMOS die, and the other end forms a connection pad to connect to an electrode of the piezoelectric ceramic transducer. The electrode of the piezoelectric ceramic transducer and the connection pad are connected by wire bonding.

[0130] In one embodiment of the present invention, the metal pillar is exposed by grinding the encapsulation layer 104.

[0131] In one embodiment of the present invention, the first polyimide insulating layer 1061 and the second polyimide insulating layer 1063 are formed by spin coating or chemical vapor deposition (CVD) to serve as the basis for the redistribution layer, providing electrical isolation and supporting the metal wiring. Then, photoresist is coated, and after exposure and development, the designed wiring pattern is transferred onto the photoresist, exposing the areas where metal deposition is required. The first front-side metal wiring layer 1062 and the second front-side metal wiring layer 1064 are formed by physical vapor deposition (PVD) to sputter or evaporate metals such as titanium (Ti) and copper (Cu) onto the insulating layer, creating a "seed layer." Based on the seed layer, copper is rapidly thickened in the photoresist window area through electroplating (e.g., copper sulfate plating solution), forming a thick metal wiring. After electroplating, the photoresist is removed, and then dry etching (e.g., plasma etching) or wet etching is used to remove excess metal, retaining the wiring pattern defined by the photolithography, forming the complete metal circuit of the redistribution layer.

[0132] In one embodiment of the invention, an LTHC coating is applied to the surface of a glass support sheet. A solid UV adhesive with selectable temperature resistance and bonding strength is then applied to the chip and the glass support sheet, bonding them together via light or heat. This provides temporary fixation between the chip and the glass support sheet, supporting subsequent semiconductor manufacturing processes such as lithography, etching, thin film deposition, and electroplating. During debonding, a laser debonding process is used, where a laser beam passes through the glass substrate and irradiates the LTHC coating. The LTHC coating absorbs photon energy and converts it into heat, causing high-temperature debonding at the bonding interface. This debonding is released at room temperature with very low levels of cleaning adhesive, achieving stress-free and easy separation between the glass substrate and the chip. The glass substrate remains intact after separation for reuse and recycling.

[0133] In a modified embodiment of the present invention, in step S201, a first polyimide insulating layer 1061, a first front metal wiring layer 1062, a second polyimide insulating layer 1063, a second front metal wiring layer 1064, a third front insulating layer 1065, a fifth metal wiring layer 1066, and a fourth front insulating layer 1067 can be sequentially fabricated on the packaging layer on the front side of the CMOS die.

[0134] The second front metal wiring layer 1064 is connected to the metal pillar 105 through the first front metal wiring layer 1062;

[0135] The fifth metal wiring layer 1066 is connected to the second front metal wiring layer 1064 on one hand, and electrically connected to the passive device 109 mounted on the fourth front insulating layer 1067 on the other hand.

[0136] Step S3: Construct a second redistribution layer 107 on the packaging layer 104 on the back side of the CMOS die to connect the metal pillar 105 to the solder joint 108 for connecting to the external substrate.

[0137] Figure 11 This is a schematic diagram illustrating the construction of the second redistribution layer in an embodiment of the present invention, as shown below. Figure 11 As shown, step S3 includes the following steps:

[0138] Step S301: Sequentially fabricate a third polyimide insulating layer 1071, a first back metal wiring layer 1072, a fourth polyimide insulating layer 1074, a second back metal wiring layer 1074, and a bottom metal layer on the packaging layer 104 on the back side of the CMOS die. A solder joint 108 is provided on the bottom metal layer.

[0139] Step S302: Apply dicing tape to the bottom metal layer;

[0140] Step S303: Remove the first temporary support sheet 110 by laser debonding on the front side of the CMOS die to expose the first redistribution layer 106.

[0141] In one embodiment of the present invention, the third polyimide insulating layer 1071 and the fourth polyimide insulating layer 1074 are formed by spin coating or chemical vapor deposition (CVD). The insulating layer serves as the base of the redistribution layer, providing electrical isolation and supporting the metal wiring. Then, photoresist is coated, and after exposure and development, the designed wiring pattern is transferred onto the photoresist, exposing the areas where metal deposition is required. The first back metal wiring layer 1072 and the second back metal wiring layer 1074 are formed by physical vapor deposition (PVD) to sputter or evaporate metals such as titanium (Ti) and copper (Cu) onto the insulating layer, creating a "seed layer." Based on the seed layer, copper is rapidly thickened in the photoresist window area through electroplating (e.g., copper sulfate plating solution), forming a thick metal wiring. After electroplating, the photoresist is removed, and then dry etching (e.g., plasma etching) or wet etching is used to remove excess metal, retaining the wiring pattern defined by the photolithography, forming the complete metal circuit of the redistribution layer.

[0142] In one embodiment of the present invention, the welded component 108 is a welding ball.

[0143] Step S4: Install the piezoelectric ceramic transducer 102 and the passive device 109 (IPD) on the front side of the chip, and bond the piezoelectric ceramic transducer 102 to the electrical connection post.

[0144] Figure 12 This is a schematic diagram of mounting passive components in an embodiment of the present invention, as shown below. Figure 12 As shown, step S4 includes the following steps:

[0145] Step S401: Install a piezoelectric ceramic transducer 102 and a passive device 109 on the front side of the CMOS die. The passive device 109 is electrically connected to the first redistribution layer 106.

[0146] Step S402: Cut the piezoelectric ceramic transducer 102 into multiple individual piezoelectric ceramic transducers, and bond the electrodes of the individual piezoelectric ceramic transducers to the electrical connection post;

[0147] Step S403: The package after installing the piezoelectric ceramic transducer 102 is diced and cut into individual chips, each individual chip is tested, and qualified individual chips are selected.

[0148] In one embodiment of the present invention, the first temporary support sheet 110 and the second temporary support sheet 112 are glass support sheets.

[0149] In one embodiment of the present invention, when mounting the passive device 109, a silicon-based passive device 109 (IPD) element can be used, or a surface-mount element with SMD as the incoming material can be used. The passive device 109 is a capacitor, which can be a capacitor with different capacitance values, such as a first group of capacitors with a capacitance value of 20nF and a second group of capacitors with a capacitance value of 40nF.

[0150] In this embodiment of the invention, when packaging a CMOS die and a piezoelectric ceramic transducer array, a metal pillar for fanning out the CMOS die is provided through the packaging layer. A first redistribution layer is formed on the packaging layer on the front side of the CMOS die to connect the pads of the CMOS die to the metal pillar. The piezoelectric ceramic transducer array is connected to the CMOS die through an electrical connection pillar provided through the first redistribution layer. A second redistribution layer is formed on the packaging layer on the back side of the CMOS die to connect the metal pillar to a solder piece for connecting an external substrate. This makes it easier for the ultrasonic chip to connect to the circuit board, reduces the process requirements of the circuit board, and reduces the signal delay of the ultrasonic chip.

[0151] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0152] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A packaging structure for an on-chip ultrasound module, characterized by, The application relates to a CMOS chip, a packaging layer for packaging the CMOS chip, a metal column through the packaging layer for fan-out of the CMOS chip, a first redistribution layer formed on the packaging layer on the front side of the CMOS chip for connecting pads of the CMOS chip to the metal column, a second redistribution layer formed on the packaging layer on the back side of the CMOS chip for connecting the metal column to a soldering part for connecting an external substrate, and a piezoelectric ceramic transducer array arranged on the first redistribution layer and connected to the CMOS chip through an electric connection column through the first redistribution layer. The first redistribution layer comprises a first front side insulating layer and a first front side metal wiring layer formed in sequence. The first front side metal wiring layer is connected to the metal column. The first front side insulating layer is provided with the electric connection column. The second redistribution layer comprises a first back side insulating layer and a first back side metal wiring layer formed in sequence. The first back side metal wiring layer is connected to the metal column and the soldering part.

2. The packaging structure for an on-chip ultrasonic module according to claim 1, wherein A passive device is attached to the first redistribution layer and electrically connected to the front side metal wiring layer in the first redistribution layer. One end of the electric connection column is connected to a pad on the CMOS chip for connecting a transducer, and the other end is connected to an electrode of the piezoelectric ceramic transducer through a connection structure for realizing electric connection and mechanical support between the electric connection column and the piezoelectric ceramic transducer. The connection structure comprises a plurality of metal layers or a single metal layer.

3. The packaging structure for an on-chip ultrasonic module according to claim 1, wherein The application relates to a CMOS chip, a packaging layer for packaging the CMOS chip, a metal column through the packaging layer for fan-out of the CMOS chip, a first redistribution layer formed on the packaging layer on the front side of the CMOS chip for connecting pads of the CMOS chip to the metal column, a second redistribution layer formed on the packaging layer on the back side of the CMOS chip for connecting the metal column to a soldering part for connecting an external substrate, and a piezoelectric ceramic transducer array arranged on the first redistribution layer and connected to the CMOS chip through an electric connection column through the first redistribution layer. The application relates to a CMOS chip, a packaging layer for packaging the CMOS chip, a metal column through the packaging layer for fan-out of the CMOS chip, a first redistribution layer formed on the packaging layer on the front side of the CMOS chip for connecting pads of the CMOS chip to the metal column, a second redistribution layer formed on the packaging layer on the back side of the CMOS chip for connecting the metal column to a soldering part for connecting an external substrate, and a piezoelectric ceramic transducer array arranged on the first redistribution layer and connected to the CMOS chip through an electric connection column through the first redistribution layer.

4. The package structure for on-chip ultrasonic module according to claim 1, wherein, The application relates to a CMOS chip, a packaging layer for packaging the CMOS chip, a metal column through the packaging layer for fan-out of the CMOS chip, a first redistribution layer formed on the packaging layer on the front side of the CMOS chip for connecting pads of the CMOS chip to the metal column, a second redistribution layer formed on the packaging layer on the back side of the CMOS chip for connecting the metal column to a soldering part for connecting an external substrate, and a piezoelectric ceramic transducer array arranged on the first redistribution layer and connected to the CMOS chip through an electric connection column through the first redistribution layer.

5. The package structure for on-chip ultrasonic module according to claim 1, wherein, The application relates to a CMOS chip, a packaging layer for packaging the CMOS chip, a metal column through the packaging layer for fan-out of the CMOS chip, a first redistribution layer formed on the packaging layer on the front side of the CMOS chip for connecting pads of the CMOS chip to the metal column, a second redistribution layer formed on the packaging layer on the back side of the CMOS chip for connecting the metal column to a soldering part for connecting an external substrate, and a piezoelectric ceramic transducer array arranged on the first redistribution layer and connected to the CMOS chip through an electric connection column through the first redistribution layer.

6. The packaging structure for an on-chip ultrasonic module according to claim 5, wherein The application relates to a CMOS chip, a packaging layer for packaging the CMOS chip, a metal column through the packaging layer for fan-out of the CMOS chip, a first redistribution layer formed on the packaging layer on the front side of the CMOS chip for connecting pads of the CMOS chip to the metal column, a second redistribution layer formed on the packaging layer on the back side of the CMOS chip for connecting the metal column to a soldering part for connecting an external substrate, and a piezoelectric ceramic transducer array arranged on the first redistribution layer and connected to the CMOS chip through an electric connection column through the first redistribution layer.

7. A packaging structure for an on-chip ultrasound module, characterized by, The application relates to a CMOS chip, a packaging layer for packaging the CMOS chip, a metal column through the packaging layer for fan-out of the CMOS chip, a first redistribution layer formed on the packaging layer on the front side of the CMOS chip for connecting pads of the CMOS chip to the metal column, a second redistribution layer formed on the packaging layer on the back side of the CMOS chip for connecting the metal column to a soldering part for connecting an external substrate, and a piezoelectric ceramic transducer array arranged on the first redistribution layer and connected to the CMOS chip through an electric connection column through the first redistribution layer. The application relates to a CMOS chip, a packaging layer for packaging the CMOS chip, a metal column through the packaging layer for fan-out of the CMOS chip, a first redistribution layer formed on the packaging layer on the front side of the CMOS chip for connecting pads of the CMOS chip to the metal column, a second redistribution layer formed on the packaging layer on the back side of the CMOS chip for connecting the metal column to a soldering part for connecting an external substrate, and a piezoelectric ceramic transducer array arranged on the first redistribution layer and connected to the CMOS chip through an electric connection column through the first redistribution layer. ​ ​ ​ 8. A packaging method for an on-chip ultrasound module, characterized by, ​ ​ ​ ​ ​ 9. The packaging method for an on-chip ultrasonic module according to claim 8, wherein ​ Step S101: making a metal column on the surface of the first temporary support sheet, and then packaging the metal column; Step S102: mounting the CMOS die on the first temporary support sheet, and packaging again to form a packaging layer; Step S103: bonding the packaging layer on the back surface of the CMOS die to the second temporary support sheet, and removing the first temporary support sheet by debonding, to release the packaging layer.

10. The packaging method for an on-chip ultrasonic module according to claim 8, wherein The step S2 comprises the following steps: Step S201: sequentially making a first front surface insulating layer and a first front surface metal wiring layer on the packaging layer on the front surface of the CMOS die; Step S202: etching the first front surface metal wiring layer and the first front surface insulating layer to form an interlayer via, and electroplating filling the interlayer via to form the electrically connecting column; Step S203: bonding the packaging layer on the front surface of the CMOS die to the first temporary support sheet, to prepare for back surface processing; Step S204: removing the second temporary support sheet by laser debonding the packaging layer on the back surface of the CMOS die, to expose the metal column.

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