Semiconductor process method and semiconductor structure

Abstract

The invention provides a semiconductor process method and a semiconductor structure. The method comprises the steps that a cutting groove with the depth smaller than that of a cutting channel is formed in the back cutting channel of the semiconductor structure; arranging a back gold layer to cover the packaging unit and the exposed surface of the cutting groove; the cutting groove is filled with an isolation protection layer not lower than the back gold layer; and cutting the semiconductor structure at the position of the isolation protection layer to obtain separated packaging units, wherein the isolation protection layer covers the back gold layer on the side wall of the cutting groove. According to the invention, the isolation protection layer is arranged in the cutting groove, so that the isolation protection layer covers the back gold layer on the side wall of the cutting groove after the packaging unit is cut, the back gold layer is prevented from being peeled off due to corrosion during back-section packaging cleaning, and the structural reliability of the packaging unit is improved; meanwhile, the thickness of the isolation protection layer on the two sides of the cutting position is set, and the cut isolation protection layer covers the back gold layer on the side wall of the cutting groove; in addition, the isolation protection layer is arranged to ensure the protection effect on the back gold layer; and finally, a boss of the heat dissipation cover is arranged, so that the isolation protection layer is not influenced by the structural stress of the heat dissipation cover.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a semiconductor process method and semiconductor structure. Background Technology

[0002] In existing technology, after a back gold layer is applied to the back of an uncutterd wafer, the wafer is diced and separated. Then, the separated packaging units are subjected to a substrate packaging process. Since flux is used in the substrate packaging process, a flux removal (deflux) process is required after the substrate packaging process to avoid the flux affecting the packaging units.

[0003] However, because the chemical solution used to remove flux is corrosive to the back gold layer, after the package unit is cut and separated, part of the back gold layer will be exposed on the sidewall where the package unit was cut. This exposed part of the back gold layer is easily corroded by the flux removal solution, resulting in peeling of the back gold layer. Peeling of the back gold layer will affect the overall heat dissipation performance and electrical reliability of the package unit.

[0004] Therefore, there is an urgent need for a process that can prevent the back gold layer of the packaging unit from being corroded and peeled off.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor process method and semiconductor structure to solve the problem that the back gold layer of the packaging unit is easily corroded and thus peeled off in the prior art.

[0007] To achieve the above objectives, the present invention provides a semiconductor process method, the semiconductor process method comprising:

[0008] An uncut semiconductor structure is provided, the semiconductor structure including a front side and a back side disposed opposite to each other; the semiconductor structure includes n packaging units, where n is an integer greater than or equal to 1; the front side of each packaging unit corresponds to the front side of the semiconductor structure, the back side of each packaging unit corresponds to the back side of the semiconductor structure, and each packaging unit has a cutting channel on its edge;

[0009] A dicing groove is provided on the back side of the semiconductor structure at a position corresponding to the dicing track, and the depth of the dicing groove is less than the depth of the dicing track;

[0010] A back gold layer is provided on the back side of the semiconductor structure, and the back gold layer covers the back side of the packaging unit and the surface of the sidewalls and bottom surface exposed by the dicing groove;

[0011] An isolation protective layer is filled in the dicing groove covered with the back gold layer, and the surface height of the isolation protective layer is not lower than the surface height of the back gold layer on the back side of the packaging unit;

[0012] The semiconductor structure is cut at the location where the isolation protective layer is provided in the dicing groove, and the thickness of the isolation protective layer on both sides of the dicing location is greater than 0; after dicing, n independent packaging units are obtained, and the back gold layer of each packaging unit is covered by the isolation protective layer on the sidewall of the dicing groove.

[0013] Optionally, the semiconductor process method further includes:

[0014] After cutting, the front sides of each separate packaging unit are electrically connected to the substrate, and a heat dissipation cover is set to cover the back side of the packaging unit and fixedly connected to the edge of the substrate to obtain the packaging structure.

[0015] The encapsulation structure is subjected to a flux removal process.

[0016] Optionally, the heat sink cover has a protrusion at a position corresponding to the exposed surface of the back gold layer of the packaging unit, the height difference between the surface height of the isolation protective layer and the surface height of the back gold layer on the back of the packaging unit is Δx, and the thickness of the protrusion is not less than Δx.

[0017] Optionally, the thickness of the protective layer on both sides of the cutting location is equal.

[0018] Alternatively, the cutting groove can be set by laser or mechanical cutting.

[0019] Optionally, the surface height of the isolation protective layer filled in the cutting groove is higher than the surface height of the back gold layer on the back side of the packaging unit.

[0020] Optionally, the method for filling the isolation protective layer is photolithography or hard mask etching.

[0021] Optionally, the material of the isolation and protective layer is an insulating material.

[0022] Optionally, the material of the isolation and protective layer is a photosensitive organic adhesive material or an inorganic medium material.

[0023] The present invention also provides a semiconductor structure, wherein the semiconductor structure is processed using any of the semiconductor process methods described above.

[0024] As described above, the semiconductor process method and semiconductor structure of the present invention have the following beneficial effects:

[0025] This invention improves the structural reliability of the packaging unit by setting an isolation and protective layer in the cutting groove, so that the isolation and protective layer covers the back gold layer on the side wall of the cutting groove after the packaging unit is cut, thus preventing the back gold layer from being corroded and peeled off during the subsequent packaging and cleaning.

[0026] This invention ensures that the protective layer covers the back gold layer on the side wall of the cutting groove after cutting by setting the thickness of the protective layer on both sides of the cutting position.

[0027] This invention ensures the protection of the back gold layer by setting the height of the isolation protective layer higher than that of the back gold layer;

[0028] This invention provides protection for the back gold layer by setting protrusions on the heat dissipation cover, thus preventing the isolation and protective layer from being affected by the structural stress of the heat dissipation cover. Attached Figure Description

[0029] Figure 1 The diagram shown is a side cross-sectional view of the semiconductor structure presented in step 1 of the semiconductor process method of the present invention.

[0030] Figure 2 The diagram shown is a side cross-sectional view of the structure of the dicing groove formed in step 2 of the semiconductor process method of the present invention.

[0031] Figure 3 The diagram shown is a side cross-sectional view of the structure of the back gold layer being set in step 3 of the semiconductor process method of the present invention.

[0032] Figure 4 The diagram shown is a side cross-sectional view of the structure of step 4 of the semiconductor process method of the present invention, in which an isolation protective layer is set.

[0033] Figure 5 The diagram shown is a side cross-sectional view of the semiconductor structure cut in step 5 of the semiconductor process method of the present invention.

[0034] Figure 6 The diagram shown is a top view of the semiconductor structure cut in step 5 of the semiconductor process method of the present invention.

[0035] Figure 7 This is a schematic diagram of the structure of a packaging unit after it has been cut and separated, and a back gold layer has been set.

[0036] Figure 8 This diagram illustrates the structural process of substrate packaging after the packaging unit is cut and separated to set the back gold layer in the prior art.

[0037] Figure 9 The diagram shown is a side cross-sectional view of the structure of step 5 of the semiconductor process method of the present invention, which illustrates the arrangement of the substrate and the heat sink.

[0038] Component designation explanation

[0039] 1. Packaging unit; 2. Cutting channel; 3. Cutting groove; 4. Back gold layer; 5. Isolation protective layer; 6. Heat sink cover; 61. Boss;

[0040] 7. Substrate; 8. Electrical connection structure; 9. Solder ball array. Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0043] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0044] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] This invention provides a semiconductor process method, the semiconductor process method comprising:

[0047] Step 1: Provide an uncut semiconductor structure, the semiconductor structure including a front side and a back side arranged opposite to each other; the semiconductor structure includes n packaging units, where n is an integer greater than or equal to 1; the front side of each packaging unit corresponds to the front side of the semiconductor structure, the back side of each packaging unit corresponds to the back side of the semiconductor structure, and each packaging unit has a cutting channel on its edge;

[0048] Step 2: A dicing groove is formed on the back side of the semiconductor structure corresponding to the dicing track, wherein the depth of the dicing groove is less than the depth of the dicing track;

[0049] Step 3: A back gold layer is formed on the back side of the semiconductor structure, the back gold layer covering the back side of the packaging unit and the surface of the sidewalls and bottom exposed by the dicing groove;

[0050] Step 4: Fill the cutting groove covered with the back gold layer with an isolation protective layer, the surface height of the isolation protective layer being no less than the surface height of the back gold layer on the back side of the packaging unit;

[0051] Step 5: The semiconductor structure is cut at the location where the isolation protective layer is set in the dicing groove, and the thickness of the isolation protective layer on both sides of the dicing location is greater than 0; after cutting, n independent packaging units are obtained, and the back gold layer of each packaging unit is covered by the isolation protective layer on the side wall of the dicing groove.

[0052] The semiconductor process method of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the semiconductor process method protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0053] First, proceed with step 1, as follows: Figure 1 As shown, an uncut semiconductor structure is provided, the semiconductor structure including a front side and a back side arranged opposite to each other; the semiconductor structure includes n packaging units 1, where n is an integer greater than or equal to 1; the front side of each packaging unit 1 corresponds to the front side of the semiconductor structure, the back side of each packaging unit 1 corresponds to the back side of the semiconductor structure, and each packaging unit 1 has a cutting channel 2 on its edge.

[0054] Specifically, when n equals 1, the cutting channel 2 exists only on the edge of this one packaging unit 1; when n is greater than 1, the cutting channel 2 also exists on both edges between two adjacent packaging units 1.

[0055] Specifically, each of the packaging units may include one or more dies as needed.

[0056] Then, proceed to step 2, as follows: Figure 2As shown, a cutting groove 3 is provided on the back side of the semiconductor structure at a position corresponding to the cutting channel 2, and the depth of the cutting groove 3 is less than the depth of the cutting channel 2.

[0057] The present invention sets the depth of the cutting groove 3 to be less than the depth of the cutting channel 2, so that the cutting groove 3 is a groove instead of a through groove, which facilitates the subsequent process of setting the isolation protective layer 5 on the back gold layer 4, and also helps to ensure the protective effect of the isolation protective layer 5 on the surface of the back gold layer 4.

[0058] In one embodiment, such as Figure 2 As shown, the depth of the cutting groove 3 is half the depth of the cutting channel 2. Specifically, the depth ratio of the cutting groove 3 to the cutting channel 2 can also be adjusted as needed, all of which are within the protection scope of this invention.

[0059] In one embodiment, the cutting groove 3 is formed by laser or mechanical cutting. Specifically, other suitable methods can also be used to form the cutting groove 3, all of which are within the scope of protection of this invention.

[0060] Next, proceed to step 3, as follows: Figure 3 As shown, a back gold layer 4 is provided on the back side of the semiconductor structure, and the back gold layer 4 covers the back side of the packaging unit 1 and the surface of the sidewalls and bottom exposed by the dicing groove 3.

[0061] In one embodiment, the back gold layer 4 is made of aluminum. Specifically, the back gold layer 4 can also be made of other suitable back gold materials.

[0062] Then, proceed to step 4, as follows: Figure 4 As shown, an isolation protective layer 5 is filled in the cutting groove 3, which is covered with the back gold layer 4, and the surface height of the isolation protective layer 5 is not lower than the surface height of the back gold layer 4 on the back side of the packaging unit 1.

[0063] In one embodiment, such as Figure 4 As shown, the surface height of the isolation protective layer 5 filled in the cutting groove 3 is higher than the surface height of the back gold layer 4 on the back of the packaging unit 1.

[0064] The present invention ensures that the surface height of the isolation protective layer 5 filled in the cutting groove 3 is higher than the surface height of the back gold layer 4 on the back of the packaging unit 1, so that the isolation protective layer 5 can completely cover the back gold layer 4 on the side wall of the cutting groove 3, avoiding the back gold layer 4 from being exposed on the side wall of the cutting groove 3 after cutting. This ensures that the back gold layer 4 is not corroded by the cleaning solution in the subsequent packaging process, thus ensuring the performance reliability of the packaging unit 1.

[0065] In one embodiment, the method for filling the isolation protective layer 5 is photolithography or hard mask etching.

[0066] In one embodiment, the method of filling the isolation protective layer 5 by photolithography is as follows: photoresist is disposed on the back side of the semiconductor structure on which the back gold layer 4 is disposed; the photoresist is patterned and exposed; the exposed photoresist is developed; after development, the photoresist is retained only in the dicing groove 3, and the retained photoresist serves as the isolation protective layer 5.

[0067] This invention uses photoresist directly as the isolation and protective layer 5, which can reduce the steps of subsequently setting the isolation and protective layer 5 and removing the photoresist, thereby improving process efficiency and reducing process costs. However, since it is difficult to ensure that the surface height of the photoresist after development is not lower than the surface height of the back gold layer 4 during the development process, there is a possibility that a small part of the back gold layer 4 may not be covered by the isolation and protective layer 5. The choice of this process method can be determined based on the product yield in actual application.

[0068] In one embodiment, the method of filling the isolation protective layer 5 by photolithography is as follows: a photoresist is disposed on the back side of the semiconductor structure on which the back gold layer 4 is disposed; the photoresist is patterned and exposed; the exposed photoresist is developed; the dicing groove 3 is exposed after development; an isolation protective layer 5 is disposed on the developed photoresist and the exposed dicing groove 3, wherein there is a high etching selectivity between the isolation protective layer 5 and the photoresist; the remaining photoresist and the isolation protective layer 5 on the photoresist are removed to obtain an isolation protective layer 5 that is only in the dicing groove 3.

[0069] This invention uses the material set after photoresist development as the isolation protective layer 5, which can control the height of the isolation protective layer 5 to a certain extent. This ensures that the isolation protective layer 5 can completely cover the back gold layer 4 on the side wall of the dicing groove 3, thereby preventing the back gold layer 4 from being corroded by the cleaning solution in the subsequent packaging process and ensuring the performance reliability of the packaging unit 1. However, this method increases the subsequent steps of setting the isolation protective layer 5 and removing the photoresist, resulting in lower process efficiency and higher process cost. The choice of this process method can be determined based on the product yield in the actual application.

[0070] In one embodiment, the method of filling the isolation protective layer 5 by hard mask etching is as follows: a patterned hard mask is provided on the back side of the semiconductor structure on which the back gold layer 4 is provided; an isolation protective layer 5 is provided on the hard mask to expose the dicing groove 3, and there is a high etching selectivity between the isolation protective layer 5 and the hard mask; the hard mask and the isolation protective layer 5 on the hard mask are removed to obtain an isolation protective layer 5 only in the dicing groove 3.

[0071] This invention uses the material set within a patterned hard mask as an isolation and protective layer 5, which can control the height of the isolation and protective layer 5 to a certain extent. This ensures that the isolation and protective layer 5 can completely cover the back gold layer 4 on the sidewall of the cut groove 3, thereby preventing the back gold layer 4 from being corroded by the cleaning solution in the subsequent packaging process and ensuring the performance reliability of the packaging unit 1. Moreover, the hard mask can be reused, which helps to reduce process costs. However, this method increases the steps of setting and removing the hard mask, and the step of removing the hard mask is prone to causing damage to the isolation and protective layer 5, which poses a certain risk. The choice of this process method can be determined based on the product yield in the actual application.

[0072] Specifically, the isolation and protection layer 5 can also be set by other methods, all of which are within the protection scope of this invention.

[0073] In one embodiment, the material of the isolation protective layer 5 is an insulating material.

[0074] In one embodiment, the material of the isolation and protective layer 5 is a photosensitive organic adhesive material or an inorganic medium material.

[0075] Specifically, the isolation and protective layer 5 can also be other suitable materials that can protect the back gold layer 4 from corrosion, all of which are within the protection scope of this invention.

[0076] Finally, proceed to step 5, as follows: Figures 5-6 As shown, where Figure 6 for Figure 5 The top view shows that the semiconductor structure is cut at the location where the isolation protection layer 5 is provided in the cutting groove 2. The thickness of the isolation protection layer 5 on both sides of the cutting location is greater than 0. After cutting, n independent packaging units 1 are obtained. The back gold layer 4 of each packaging unit 1 on the side wall of the cutting groove 3 is covered by the isolation protection layer 5.

[0077] In the prior art, after a back gold layer 4 is formed on the back side of the uncut packaging unit 1 wafer, the packaging unit 1 wafer is cut and separated, and then the separated packaging unit 1 undergoes a substrate packaging process. Since flux is used in the substrate packaging process, a flux removal process is required after the substrate packaging process to avoid the flux affecting the packaging unit 1. However, the chemical solution used to remove the flux is corrosive to the back gold layer 4, and the cutting path 2 used to cut the packaging unit 1 becomes corrosive after the packaging unit 1 is cut and separated. Figures 7-8 As shown, part of the back gold layer 4 will be exposed on the sidewall, which makes this exposed part of the back gold layer 4 easy to be corroded by the flux removal solution, resulting in the peeling of the back gold layer 4. The peeling of the back gold layer 4 will affect the overall heat dissipation performance and electrical reliability of the package unit 1.

[0078] This invention, by setting a cutting groove 3 with a depth less than the cutting channel 2 before cutting, provides an isolation protective layer 5 on the surface of the back gold layer 4 within the cutting groove 3. This allows cutting to proceed from the position of the isolation protective layer 5, exposing the isolation protective layer 5 rather than the back gold layer 4 on the sidewall after cutting. This prevents the back gold layer 4 from being corroded by various cleaning solutions, including flux removal solutions, in the subsequent packaging process, thus ensuring the bonding strength between the back gold layer 4 and the packaging unit 1 and guaranteeing the performance reliability of the packaging unit 1 after the packaging process.

[0079] Specifically, although the inventive concept of this invention mainly comes from the corrosion of the back gold layer 4 by the solution used to remove flux in the back packaging process, it can also be used to prevent corrosion of the back gold layer 4 by other solutions or processes after the formation of the back gold layer 4 and cutting, and all of these are within the protection scope of this invention.

[0080] In one embodiment, such as Figures 5-6 As shown, the thickness of the isolation protective layer 5 on both sides of the cutting position is equal.

[0081] By setting the length of the isolation protective layer 5 on both sides of the cutting position along the first direction to be equal, the present invention further ensures that the thickness of the isolation protective layer 5 on the side wall of the package unit 1 after cutting is the same, so that the isolation protective layer 5 provides the same protection effect to the back gold layer 4. This prevents the package unit 1 on one side from having a thicker isolation protective layer 5 while the package unit 1 on the other side has a thinner isolation protective layer 5, thus avoiding the problem that the side with a thinner isolation protective layer 5 provides poor protection for the back gold layer 4.

[0082] In one embodiment, the semiconductor process method further includes:

[0083] After cutting, as Figure 9 As shown, the front sides of each separate packaging unit 1 are electrically connected to the substrate 7, and a heat dissipation cover 6 is provided to cover the back side of the packaging unit 1 and fixedly connected to the edge of the substrate 7 to obtain the packaging structure.

[0084] The encapsulation structure is subjected to a flux removal process.

[0085] In one embodiment, the front side of the packaging unit 1 is electrically connected to the substrate 7 via an electrical connection structure 8.

[0086] In one embodiment, the surface of the substrate 7 away from the front of the packaging unit 1 is provided with a solder ball array 9 for electrical connection lead-out.

[0087] In one embodiment, such as Figure 9As shown, the heat dissipation cover 6 has a protrusion 61 at the position corresponding to the exposed surface of the back gold layer 4 of the packaging unit 1. The height difference between the surface height of the isolation protective layer 5 and the surface height of the back gold layer 4 on the back of the packaging unit 1 is Δx, and the thickness of the protrusion 61 is not less than Δx.

[0088] The present invention ensures that the thickness of the protrusion 61 of the heat dissipation cover 6 is not less than Δx, so that the position of the heat dissipation cover 6 near the isolation protection layer 5 will not generate stress on the isolation protection layer 5, thereby avoiding the isolation protection layer 5 from being deformed, displaced or falling off due to the pressure of the heat dissipation cover, and ensuring the protective effect of the isolation protection layer 5 on the back gold layer 4.

[0089] The present invention also provides a semiconductor structure, wherein the semiconductor structure is processed using any of the semiconductor process methods described above.

[0090] Specifically, the semiconductor structure can be any semiconductor structure that has a packaging unit 1 structure on the wafer but no back gold layer 4 and is not cut.

[0091] In summary, the semiconductor process method and semiconductor structure of the present invention can improve the reliability of the packaging unit structure by setting an isolation protective layer in the dicing groove, so that the isolation protective layer covers the back gold layer on the side wall of the dicing groove after the packaging unit is diced, thus preventing the back gold layer from being corroded and peeled off during the subsequent packaging cleaning. At the same time, by setting the thickness of the isolation protective layer on both sides of the dicing position, it is ensured that the isolation protective layer covers the back gold layer on the side wall of the dicing groove after dicing. In addition, by setting the height of the isolation protective layer higher than the back gold layer, the protection effect on the back gold layer is ensured. Finally, by setting the protrusion of the heat sink, the isolation protective layer is not affected by the stress of the heat sink structure, thus ensuring the protection effect of the isolation protective layer on the back gold layer.

[0092] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0093] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of semiconductor processing, characterized by, The semiconductor process method comprises: providing a semiconductor structure without cutting, the semiconductor structure comprising a front surface and a back surface arranged oppositely; the semiconductor structure comprising n packaging units, n being an integer greater than or equal to 1; the front surface of each packaging unit corresponding to the front surface of the semiconductor structure, the back surface of each packaging unit corresponding to the back surface of the semiconductor structure, and a cutting groove being present at the edge of each packaging unit; providing a cutting groove at the position of the back surface of the semiconductor structure corresponding to the cutting groove, the depth of the cutting groove being less than the depth of the cutting groove; providing a back gold layer on the back surface of the semiconductor structure, the back gold layer covering the back surface of the packaging unit and the surface of the sidewall and bottom surface of the cutting groove exposed; filling an isolation protective layer in the cutting groove covered with the back gold layer, the surface height of the isolation protective layer being not less than the surface height of the back gold layer of the back surface of the packaging unit; cutting the semiconductor structure at the position provided with the isolation protective layer in the cutting groove, the thickness of the isolation protective layer on both sides of the cutting position being greater than 0; and obtaining n independent packaging units after cutting, the back gold layer of the semiconductor structure at the sidewall of the cutting groove being covered by the isolation protective layer.

2. The semiconductor process method of claim 1, wherein, The semiconductor process method further comprises: electrically connecting the front surface of each packaging unit separated from each other after cutting to a substrate, covering the back surface of the packaging unit with a heat dissipation cover and fixedly connecting the edge of the heat dissipation cover to the substrate to obtain a packaging structure; performing a flux removal process on the packaging structure.

3. The semiconductor process method of claim 2, wherein, The heat dissipation cover is provided with a boss at the position corresponding to the surface of the back gold layer exposed, the height difference between the surface height of the isolation protective layer and the surface height of the back gold layer of the back surface of the packaging unit is Δx, and the thickness of the boss is not less than Δx.

4. The semiconductor process method of any of claims 1-3, wherein, The thickness of the isolation protective layer on both sides of the cutting position is equal.

5. The semiconductor process method of any one of claims 1-3, wherein, The cutting groove is provided by laser or mechanical cutting.

6. The semiconductor process method of any one of claims 1-3, wherein, The surface height of the isolation protective layer filled in the cutting groove is higher than the surface height of the back gold layer of the back surface of the packaging unit.

7. The semiconductor process method of any one of claims 1-3, wherein, The method for filling the isolation protective layer is photolithography or hard mask etching.

8. The semiconductor process method of any one of claims 1-3, wherein, The material of the isolation protective layer is an insulating material.

9. The semiconductor process method of any one of claims 1-3, wherein, The material of the isolation protective layer is a photosensitive organic glue material or an inorganic medium material.

10. A semiconductor structure, characterized by The semiconductor structure is processed by the semiconductor process method according to any one of claims 1-9.

Images