Semiconductor structure and manufacturing method thereof
By forming a second trench in the substrate structure and filling it with a buried oxide layer, the problems of ion implantation damage and unsuitable thickness in existing SOI substrates are solved, and high-quality and reliable SOI substrates are achieved.
Patent Information
- Application Number
- CN202411178202.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2026-03-06
AI Technical Summary
SOI substrates manufactured using existing technologies suffer from ion implantation damage or inappropriate thicknesses of the top silicon layer or buried oxide layer.
By forming a second trench in the substrate structure, etching away the buffer layer to form a cavity between the back substrate and the top silicon layer, and filling the cavity with a buried oxide layer to form an SOI substrate, the ion implantation process is avoided, and the thickness of the top silicon layer and the buried oxide layer is controlled.
An SOI substrate with ideal thickness was achieved, avoiding ion implantation damage and improving the quality and reliability of the SOI substrate.
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Figure CN121620180A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology
[0002] SOI (Silicon-On-Insulator) technology introduces a buried oxide layer between the top silicon layer and the back substrate. SOI substrates can achieve dielectric isolation of components in integrated circuits, completely eliminating the parasitic latch-up effect found in bulk silicon CMOS circuits. Integrated circuits fabricated using SOI substrates also offer advantages such as low parasitic capacitance, high integration density, high speed, simple fabrication process, low short-channel effect, and particular suitability for low-voltage, low-power circuits. SOI technology has the potential to become the mainstream technology for deep submicron low-voltage, low-power integrated circuits.
[0003] However, SOI substrates manufactured using existing technologies suffer from problems such as ion implantation damage or inappropriate thickness of the top silicon layer or buried oxide layer. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor structure and its manufacturing method to solve the problems of ion implantation damage or unsuitable thickness of top silicon layer and buried oxide layer in SOI substrates manufactured by existing technologies.
[0005] To address the aforementioned technical problems, the present invention provides a method for manufacturing a semiconductor structure, the method comprising:
[0006] A substrate structure is provided, the substrate structure comprising a back substrate, a buffer layer and a top silicon layer stacked sequentially;
[0007] The substrate structure is etched to form a first trench in the substrate structure, the first trench having a first extension direction in the extension direction of the substrate structure; in the thickness direction of the substrate structure, the first trench extends at least from the surface of the top silicon layer to the surface of the back substrate.
[0008] The first trench is filled to form a support structure in the first trench;
[0009] The substrate structure is etched to form a second trench in the substrate structure, the second trench having a second extending direction and penetrating the support structure in the extending direction of the substrate structure; in the thickness direction of the substrate structure, the second trench extends at least from the surface of the top silicon layer to the surface of the back substrate.
[0010] The buffer layer is removed by the second trench etching to form a cavity between the back substrate and the top silicon layer; and...
[0011] The cavity and the second trench are filled to form a buried oxide layer in the cavity and an isolation sidewall in the second trench.
[0012] Optionally, in the method for manufacturing the semiconductor structure, the method further includes:
[0013] Etching removes the support structure to expose the first trench; and,
[0014] The first trench is filled to form an isolation structure within the first trench.
[0015] Optionally, in the method for manufacturing the semiconductor structure, after forming the isolation structure in the first trench, the method further includes:
[0016] A gate structure is formed on the top silicon layer; and,
[0017] Source and drain regions are formed in the top silicon layers on both sides of the gate structure.
[0018] Optionally, in the semiconductor structure manufacturing method, the buffer layer is made of germanium-silicon and is removed by a wet etching process.
[0019] Optionally, in the method for manufacturing the semiconductor structure, the etching solution in the wet etching process includes oxalic acid.
[0020] Optionally, in the semiconductor structure manufacturing method, the substrate structure includes a plurality of device regions, and two first trenches are formed in the substrate structure of each device region, with each first trench located at the edge of the device region.
[0021] Optionally, in the semiconductor structure manufacturing method, two second trenches are formed in the substrate structure of each of the device regions, and each second trench is located at the edge of the device region.
[0022] Optionally, in the semiconductor structure manufacturing method, the cavity and the second trench are filled by an atomic layer deposition process to form the buried oxide layer and the isolation sidewall.
[0023] Optionally, in the method for manufacturing the semiconductor structure, the thickness of the buffer layer is between 200 nm and 1000 nm.
[0024] The present invention also provides a semiconductor structure, the semiconductor structure comprising:
[0025] The back substrate, buried oxide layer, and top silicon layer are stacked in sequence.
[0026] A first trench that penetrates at least the top silicon layer, the first trench having a first extending direction in the extending direction of the top silicon layer;
[0027] A second trench that penetrates at least through the top silicon layer, the second trench having a second extending direction in the extending direction of the top silicon layer;
[0028] The support structure filling the first trench; and,
[0029] Isolation sidewalls filled in the second trench.
[0030] In the semiconductor structure and manufacturing method provided by the present invention, a substrate structure is provided, comprising a back substrate, a buffer layer, and a top silicon layer stacked sequentially; a second trench is formed in the substrate structure, and the buffer layer is removed by etching through the second trench to form a cavity between the back substrate and the top silicon layer; a buried oxide layer is filled in the cavity to form an SOI substrate. This allows for control of the thickness of the top silicon layer and the buried oxide layer to obtain an SOI substrate with ideal thickness, while also avoiding the formation of the SOI substrate through ion implantation. Consequently, ion implantation damage is avoided, improving the quality and reliability of the formed SOI substrate. Attached Figure Description
[0031] Figures 1 to 17 This is a cross-sectional schematic diagram of the structure formed by the semiconductor structure manufacturing method of the present invention.
[0032] Figures 18 to 31 This is a top view schematic diagram of the structure formed by the semiconductor structure manufacturing method of the present invention embodiment.
[0033] The reference numerals in the attached figures are explained as follows:
[0034] 100 - Substrate structure; 101 - Back substrate; 102 - Buffer layer; 103 - Top silicon layer; 104 - Buried oxide layer; 110 - First patterned photoresist layer; 111 - First opening; 120 - First trench; 130 - Support structure; 140 - Second patterned photoresist layer; 141 - Second opening; 150 - Second trench; 160 - Cavity; 170 - Isolation sidewall; 180 - Third patterned photoresist layer; 181 - Third opening; 190 - Isolation structure; 200 - Gate structure; 210 - Sidewall structure; 220 - Source region; 221 - Drain region; 230 - Interlayer dielectric layer; 240 - First conductive plug; 241 - Second conductive plug; 242 - Third conductive plug; 1000 - Silicon oxide layer; 1100 - Isolation material layer. Detailed Implementation
[0035] The semiconductor structure and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0036] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined in this application, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. "A plurality" or "several" indicates two or more. Unless otherwise indicated, terms such as "upper / upper layer," "lower / lower layer," and similar terms are for ease of description only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed following "comprising" or "including" and its equivalents, and does not exclude other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0037] The core idea of this invention is to provide a semiconductor structure and its manufacturing method. By providing a substrate structure, the substrate structure includes a back substrate, a buffer layer, and a top silicon layer stacked sequentially; a second trench is formed in the substrate structure, and the buffer layer is removed by etching through the second trench to form a cavity between the back substrate and the top silicon layer; a buried oxide layer is filled in the cavity to form an SOI substrate. Thus, the thickness of the top silicon layer and the buried oxide layer can be controlled to obtain an SOI substrate with ideal thickness, and the formation of the SOI substrate by ion implantation process is avoided. Correspondingly, ion implantation damage is avoided, and the quality and reliability of the formed SOI substrate are improved.
[0038] For details, please refer to Figures 1 to 31 ,in, Figures 1 to 17This is a schematic cross-sectional view of the structure formed by the semiconductor structure manufacturing method according to the embodiments of the present invention; Figures 18 to 31 This is a top view schematic diagram of the structure formed by the semiconductor structure manufacturing method of the present invention embodiment.
[0039] like Figure 1 , Figure 2 , Figure 18 and Figure 19 As shown, a substrate structure 100 is first provided, which includes a back substrate 101, a buffer layer 102, and a top silicon layer 103 stacked sequentially. Here, only a portion of the substrate structure 100 is schematically shown, which includes a device region (not shown in the figure). Specifically, the substrate structure 100 may have a larger chip area and may include more device regions.
[0040] like Figure 1 and Figure 18 As shown, in this embodiment of the application, a back substrate 101 is first provided, the material of which is silicon; then, as... Figure 2 and Figure 19 As shown, a buffer layer 102 is formed on the back substrate 101, wherein the buffer layer 102 is made of germanium-silicon (Si). x Ge y The buffer layer 102 can be formed by an epitaxial growth process. Further, a top silicon layer 103 is formed on the buffer layer 102, which can also be formed by an epitaxial growth process. The thicknesses of the buffer layer 102 and the top silicon layer 103 can be determined as needed, specifically by controlling parameters such as the growth rate and process time of the epitaxial growth process. Preferably, the thickness of the buffer layer 102 is between 200nm and 1000nm, for example, 300nm, 380nm, 450nm, 520nm, 760nm, or 880nm; the thickness of the top silicon layer 103 is between 300nm and 800nm, for example, 360nm, 480nm, 550nm, or 720nm.
[0041] like Figure 3 and Figure 20 As shown, in this embodiment of the application, a first patterned photoresist layer 110 is then formed on the substrate structure 100, specifically on the top silicon layer 103. A first opening 111 is formed in the first patterned photoresist layer 110, exposing a portion of the top silicon layer 103. For example... Figure 20As shown, in the extension direction of the substrate structure 100, that is, in the extension direction of the top silicon layer 103, the first opening 111 has a first extension direction. Further, in this embodiment, two first openings 111 are formed in the first patterned photoresist layer 110 corresponding to a device region. Both first openings 111 have a first extension direction, that is, the two first openings 111 are arranged in parallel. Here, the two first openings 111 respectively correspond to the edge positions of the device region, that is, the positions where the isolation structure between the device regions will be formed.
[0042] Next, as Figure 4 and Figure 21 As shown, using the first patterned photoresist layer 110 as a mask, the substrate structure 100 is etched to form a first trench 120 in the substrate structure 100. Next, the first patterned photoresist layer 110 is removed; specifically, the first patterned photoresist layer 110 can be removed by an ashing process.
[0043] Accordingly, in the extension direction of the substrate structure 100, that is, in the extension direction of the top silicon layer 103, the first trench 120 has a first extension direction; and two first trenches 120 are formed in the substrate structure 100 of each device region, each first trench 120 being located at the edge of the device region. Please continue to refer to Figure 4 In the thickness direction of the substrate structure 100, the first trench 120 extends from the surface of the top silicon layer 103 to at least the surface of the back substrate 101, that is, the first trench 120 penetrates the top silicon layer 103 and the buffer layer 102.
[0044] Please refer to Figure 5 and Figure 22 Next, the first trench 120 is filled to form a support structure 130 within the first trench 120. Specifically, a support material layer (not shown in the figure) can be filled into the first trench 120 by a deposition process, and the support material layer can also extend to cover the surface of the top silicon layer 103; then, the support material layer on the surface of the top silicon layer 103 can be removed by a chemical mechanical polishing process to form the support structure 130 within the first trench 120. In this embodiment, the support structure 130 is made of silicon nitride.
[0045] Next, please refer to Figure 6 and Figure 23A second patterned photoresist layer 140 is formed on the substrate structure 100, and a second opening 141 is formed in the second patterned photoresist layer 140, the second opening 141 exposing a portion of the top silicon layer 103 and a portion of the support structure 130 located in the first trench 120.
[0046] like Figure 23 As shown, in the extending direction of the substrate structure 100, the second opening 141 has a second extending direction. Here, the second extending direction intersects with the first extending direction, and more specifically, the second extending direction is perpendicular to the first extending direction. Further, in this embodiment, two second openings 141 are formed in the second patterned photoresist layer 140 corresponding to a device region, and both second openings 141 have a second extending direction, that is, the two second openings 141 are arranged in parallel. Here, the two second openings 141 respectively correspond to the edge positions of the device region, that is, the positions where the isolation structure between the device regions will be formed.
[0047] Next, as Figure 7 and Figure 24 As shown, using the second patterned photoresist layer 140 as a mask, the substrate structure 100 is etched to form a second trench 150 in the substrate structure 100. Next, the second patterned photoresist layer 140 is removed; specifically, the second patterned photoresist layer 140 can be removed by an ashing process.
[0048] Accordingly, in the extending direction of the substrate structure 100, the second trench 150 has a second extending direction, whereby the second trench 150 also penetrates the support structure 130, that is, the second trench 150 intersects with the first trench 120; and two second trenches 150 are formed in the substrate structure 100 of each device region, each second trench 150 being located at the edge of the device region. Please continue to refer to Figure 7 and Figure 24 In the thickness direction of the substrate structure 100, the second trench 150 extends from the surface of the top silicon layer 103 to at least the surface of the back substrate 101, that is, the second trench 150 penetrates the top silicon layer 103 and the buffer layer 102, exposing a portion of the back substrate 101.
[0049] Next, please refer to Figure 8 and Figure 25The buffer layer 102 is removed by etching through the second trench 150 to form a cavity 160 between the back substrate 101 and the top silicon layer 103. In this embodiment, the buffer layer 102 is removed by a wet etching process, wherein the wet etching process has an etching selectivity ratio of germanium-silicon to silicon greater than or equal to 20:1, thereby avoiding damage to the top silicon layer 103 and the back substrate 101 while removing the buffer layer 102. Preferably, the etching solution of the wet etching process includes oxalic acid, which can further improve the etching selectivity ratio of germanium-silicon to silicon and avoid damage to the top silicon layer 103 and the back substrate 101. In one embodiment of this application, the etching solution of the wet etching process includes nitric acid, hydrofluoric acid and oxalic acid, and its etching selectivity ratio of germanium-silicon to silicon can be greater than 200:1.
[0050] Next, as Figure 9 , Figure 10 , Figure 26 and Figure 27 As shown, the cavity 160 and the second trench 150 are filled to form a buried oxide layer 104 in the cavity 160 and an isolation sidewall 170 in the second trench 150. Preferably, the cavity 160 and the second trench 150 are filled by an atomic layer deposition process to form the buried oxide layer 104 and the isolation sidewall 170, thereby improving the quality of the formed buried oxide layer 104 and isolation sidewall 170.
[0051] In this embodiment, the buried oxide layer 104 and the isolation sidewall 170 are made of silicon oxide. Specifically, an atomic layer deposition process can be used to fill the cavity 160 and the second trench 150 with a silicon oxide layer 1000, which can also extend to cover the surface of the top silicon layer 103. Then, a chemical mechanical polishing process can be used to remove the silicon oxide layer 1000 from the surface of the top silicon layer 103 to form the buried oxide layer 104 and the isolation sidewall 170 in the cavity 160 and the second trench 150, respectively.
[0052] The SOI substrate can be obtained through the above process. The SOI substrate includes a back substrate 101, a buried oxide layer 104 and a top silicon layer 103 stacked in sequence. Thus, the thickness of the top silicon layer 103 and the buried oxide layer 104 can be controlled to obtain an SOI substrate with ideal thickness. At the same time, the formation of SOI substrate through ion implantation process is avoided. Correspondingly, ion implantation damage is avoided, and the quality and reliability of the formed SOI substrate are improved.
[0053] Furthermore, this application also provides a semiconductor structure, please refer to the following embodiments. Figure 10 and Figure 27The semiconductor structure includes: a back substrate 101, a buried oxide layer 104, and a top silicon layer 103 stacked sequentially; a first trench 120 extending at least through the top silicon layer 103, the first trench 120 having a first extending direction in the extending direction of the top silicon layer 103; a second trench 150 extending at least through the top silicon layer 103, the second trench 150 having a second extending direction in the extending direction of the top silicon layer 103; a support structure 130 filling the first trench 120; and isolation sidewalls 170 filling the second trench 150. This forms an SOI substrate with ideal thickness and high reliability.
[0054] To further improve the quality of the formed semiconductor structure, such as Figures 11 to 14 as well as Figures 28 to 31 As shown in this embodiment, a third patterned photoresist layer 180 is further formed on the substrate structure 100. The third patterned photoresist layer 180 can be formed using the same photomask as the first patterned photoresist layer 110. Specifically, a third opening 181 is formed in the third patterned photoresist layer 180, and the third opening 181 has a first extending direction. Here, the third opening 181 exposes the support structure 130.
[0055] Next, as Figure 12 and Figure 29 As shown, using the third patterned photoresist layer 180 as a mask, the support structure 130 is etched away to expose the first trench 120.
[0056] Next, as Figure 13 , Figure 14 , Figure 30 and Figure 31 As shown, the first trench 120 is filled to form an isolation structure 190 within it. Specifically, an isolation material layer 1100 can be filled into the first trench 120 using a deposition process, the isolation material layer 1100 extending to cover the surface of the top silicon layer 103; subsequently, the isolation material layer 1100 on the surface of the top silicon layer 103 can be removed using a chemical mechanical polishing process to form the isolation structure 190 within the first trench 120. In this embodiment, the isolation structure 190 is made of silicon oxide. In this embodiment, the isolation structure 190 and the isolation sidewall 170 achieve separation between different device regions.
[0057] Please refer to Figures 15 to 17Furthermore, the method for manufacturing the semiconductor structure further includes: forming a gate structure 200 on the top silicon layer 100 and covering the sidewalls of the gate structure 200 with sidewall structures 210; forming a source region 220 and a drain region 221 in the top silicon layer 100 on both sides of the gate structure 200. Further, an interlayer dielectric layer 230 is formed on the top silicon layer 100, the interlayer dielectric layer 230 covering the gate structure 200; and a first conductive plug 240 connecting the gate structure 200, a second conductive plug 241 connecting the source region 220, and a third conductive plug 242 connecting the drain region 221 are formed in the interlayer dielectric layer 230. The transistor thus formed avoids parasitic latch-up effects and has better electrical performance.
[0058] In this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment or at least some embodiments of this application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same or the same embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.
[0059] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The embodiments of this application can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.
Claims
1. A method of manufacturing a semiconductor structure, characterized by, The method for manufacturing the semiconductor structure comprises: providing a base structure comprising a back substrate, a buffer layer and a top silicon layer stacked in sequence; etching the base structure to form a first trench in the base structure, the first trench having a first extension direction in the extension direction of the base structure, and extending from the surface of the top silicon layer to at least the surface of the back substrate in the thickness direction of the base structure; filling the first trench to form a support structure in the first trench; etching the base structure to form a second trench in the base structure, the second trench having a second extension direction in the extension direction of the base structure and penetrating the support structure, and extending from the surface of the top silicon layer to at least the surface of the back substrate in the thickness direction of the base structure; removing the buffer layer by etching through the second trench to form a cavity between the back substrate and the top silicon layer; and filling the cavity and the second trench to form a buried oxide layer in the cavity and an isolation side wall in the second trench.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein The method for manufacturing the semiconductor structure further comprises: removing the support structure by etching to expose the first trench; and filling the first trench to form an isolation structure in the first trench.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein After forming the isolation structure in the first trench, the method for manufacturing the semiconductor structure further comprises: forming a gate structure on the top silicon layer; and forming a source region and a drain region in the top silicon layer on both sides of the gate structure.
4. The method of manufacturing a semiconductor structure according to one of claims 1 to 3, wherein The material of the buffer layer is germanium-silicon, and the buffer layer is removed by a wet etching process.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein The etching solution of the wet etching process comprises oxalic acid.
6. The method of manufacturing a semiconductor structure according to one of claims 1 to 3, wherein The base structure comprises a plurality of device regions, two first trenches are formed in the base structure of each device region, and each first trench is located at an edge position of the device region.
7. The method of manufacturing a semiconductor structure according to claim 6, wherein Two second trenches are formed in the base structure of each device region, and each second trench is located at an edge position of the device region.
8. The method of manufacturing a semiconductor structure according to one of claims 1 to 3, wherein The cavity and the second trench are filled by an atomic layer deposition process to form the buried oxide layer and the isolation side wall.
9. The method of manufacturing a semiconductor structure according to one of claims 1 to 3, wherein The thickness of the buffer layer is between 200 nm and 1000 nm.
10. A semiconductor structure, characterized by The semiconductor structure comprises: a back substrate, a buried oxide layer and a top silicon layer stacked in sequence; a first trench penetrating at least the top silicon layer, the first trench having a first extension direction in the extension direction of the top silicon layer; a second trench penetrating at least the top silicon layer, the second trench having a second extension direction in the extension direction of the top silicon layer; a support structure filled in the first trench; and an isolation side wall filled in the second trench.